Overall: 2072/2419 fields covered

ADC

0x40012400: Analog to digital converter

75/80 fields covered. Toggle Registers.

STAT

status register

Offset: 0x0, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRC
rw 		STIC
rw 		EOIC
rw 		EOC
rw 		WDE
rw
Toggle Fields.

WDE

Bit 0: Analog watchdog event flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC

Bit 1: End of group conversion flag.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

EOIC

Bit 2: End of inserted group conversion flag.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

STIC

Bit 3: Start flag of inserted channel group.

Allowed values:
0: NotStarted: No inserted channel group conversion started
1: Started: Inserted channel group conversion has started

STRC

Bit 4: Start flag of regular channel group.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

CTL0

control register 0

Offset: 0x4, reset: 0x00000000, access: read-write

12/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DRES
rw 		RWDEN
rw 		IWDEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISNUM
rw 		DISIC
rw 		DISRC
rw 		ICA
rw 		WDSC
rw 		SM
rw 		EOICIE
rw 		WDEIE
rw 		EOCIE
rw 		WDCHSEL
rw
Toggle Fields.

WDCHSEL

Bits 0-4: Analog watchdog channel select.

Allowed values: 0-18

EOCIE

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set

WDEIE

Bit 6: Interrupt enable for WDE.

Allowed values:
0: Disabled: WDE interrupt disabled
1: Enabled: WDE interrupt enabled. An interrupt is generated when the WDE bit is set

EOICIE

Bit 7: Interrupt enable for EOIC.

Allowed values:
0: Disabled: EOIC interrupt disabled
1: Enabled: EOIC interrupt enabled. An interrupt is generated when the EOIC bit is set

SM

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

WDSC

Bit 9: When in scan mode, analog watchdog is effective on a single channel.

Allowed values:
0: All: Analog watchdog enabled on all channels
1: Single: Analog watchdog enabled on a single channel

ICA

Bit 10: Inserted channel group convert automatically.

Allowed values:
0: Disabled: Automatic inserted group conversion disabled
1: Enabled: Automatic inserted group conversion enabled

DISRC

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

DISIC

Bit 12: Discontinuous mode on injected channels.

Allowed values:
0: Disabled: Discontinuous mode on inserted channels disabled
1: Enabled: Discontinuous mode on inserted channels enabled

DISNUM

Bits 13-15: Number of conversions in discontinuous mode.

Allowed values: 0-7

IWDEN

Bit 22: Inserted channel analog watchdog enable.

Allowed values:
0: Disabled: Analog watchdog disabled on inserted channels
1: Enabled: Analog watchdog enabled on inserted channels

RWDEN

Bit 23: Regular channel analog watchdog enable.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

DRES

Bits 24-25: ADC resolution.

CTL1

control register 1

Offset: 0x8, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSVREN
rw 		SWRCST
rw 		SWICST
rw 		ETERC
rw 		ETSRC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETEIC
rw 		ETSIC
rw 		DAL
rw 		DMA
rw 		RSTCLB
rw 		CLB
rw 		CTN
rw 		ADCON
rw
Toggle Fields.

ADCON

Bit 0: ADC ON.

Allowed values:
0: Disabled: Disable ADC conversion/calibration and go to power down mode
1: Enabled: Enable ADC and to start conversion

CTN

Bit 1: Continuous mode.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

CLB

Bit 2: ADC calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

RSTCLB

Bit 3: Reset calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

DMA

Bit 8: DMA request enable.

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

DAL

Bit 11: Data alignment.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

ETSIC

Bits 12-14: External trigger select for inserted channel.

Allowed values:
0: Timer0Trgo: Timer 0 TRGO event
1: Timer0Ch3: Timer 0 channel 3 event
2: Timer1Trgo: Timer 1 TRGO event
3: Timer1Ch0: Timer 1 channel 0 event
4: Timer2Ch2: Timer 2 channel 3 event
5: Timer14Trgo: Timer 14 TRGO event
6: Exti15: EXTI line 15
7: Swicst: SWICST

ETEIC

Bit 15: External trigger enable for inserted channels.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

ETSRC

Bits 17-19: External trigger select for regular channel.

Allowed values:
0: Timer0Ch0: Timer 0 channel 0 event
1: Timer0Ch1: Timer 0 channel 1 event
2: Timer0Ch2: Timer 0 channel 2 event
3: Timer1Ch1: Timer 1 channel 1 event
4: Timer2Trgo: Timer 2 TRGO event
5: Timer14Ch0: Timer 14 channel 0 event
6: Exti11: EXTI line 11
7: Swrcst: SWRCST

ETERC

Bit 20: External trigger enable for regular channel.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

SWICST

Bit 21: Start on inserted channel.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of inserted channels

SWRCST

Bit 22: Start on regular channel.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of regular channels

TSVREN

Bit 23: Channel 16 and 17 enable of ADC.

Allowed values:
0: Disabled: Channel 16 and 17 disabled
1: Enabled: Channel 16 and 17 enabled

SAMPT0

Sampling time register 0

Offset: 0xC, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT17
rw 		SPT16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

SPT16

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT17

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SAMPT1

Sampling time register 1

Offset: 0x10, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT9
rw 		SPT8
rw 		SPT7
rw 		SPT6
rw 		SPT5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT5
rw 		SPT4
rw 		SPT3
rw 		SPT2
rw 		SPT1
rw 		SPT0
rw
Toggle Fields.

SPT0

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT1

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT2

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT3

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT4

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT5

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT6

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT7

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT8

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT9

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

IOFF0

Inserted channel data offset register 0

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for injected channel x.

Allowed values: 0-4095

IOFF1

Inserted channel data offset register 1

Offset: 0x18, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for injected channel x.

Allowed values: 0-4095

IOFF2

Inserted channel data offset register 2

Offset: 0x1C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for injected channel x.

Allowed values: 0-4095

IOFF3

Inserted channel data offset register 3

Offset: 0x20, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for injected channel x.

Allowed values: 0-4095

WDHT

watchdog higher threshold register

Offset: 0x24, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDHT
rw
Toggle Fields.

WDHT

Bits 0-11: Analog watchdog high threshold.

Allowed values: 0-4095

WDLT

watchdog low threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDLT
rw
Toggle Fields.

WDLT

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0-4095

RSQ0

regular sequence register 0

Offset: 0x2C, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RL
rw 		RSQ15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ15
rw 		RSQ14
rw 		RSQ13
rw 		RSQ12
rw
Toggle Fields.

RSQ12

Bits 0-4: 12th conversion in regular sequence.

Allowed values: 0-18

RSQ13

Bits 5-9: 13th conversion in regular sequence.

Allowed values: 0-18

RSQ14

Bits 10-14: 14th conversion in regular sequence.

Allowed values: 0-18

RSQ15

Bits 15-19: 15th conversion in regular sequence.

Allowed values: 0-18

RL

Bits 20-23: Regular channel sequence length.

Allowed values: 0-15

RSQ1

regular sequence register 1

Offset: 0x30, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ11
rw 		RSQ10
rw 		RSQ9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ9
rw 		RSQ8
rw 		RSQ7
rw 		RSQ6
rw
Toggle Fields.

RSQ6

Bits 0-4: 6th conversion in regular sequence.

Allowed values: 0-18

RSQ7

Bits 5-9: 7th conversion in regular sequence.

Allowed values: 0-18

RSQ8

Bits 10-14: 8th conversion in regular sequence.

Allowed values: 0-18

RSQ9

Bits 15-19: 9th conversion in regular sequence.

Allowed values: 0-18

RSQ10

Bits 20-24: 10th conversion in regular sequence.

Allowed values: 0-18

RSQ11

Bits 25-29: 11th conversion in regular sequence.

Allowed values: 0-18

RSQ2

regular sequence register 2

Offset: 0x34, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ5
rw 		RSQ4
rw 		RSQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ3
rw 		RSQ2
rw 		RSQ1
rw 		RSQ0
rw
Toggle Fields.

RSQ0

Bits 0-4: conversion in regular sequence.

Allowed values: 0-18

RSQ1

Bits 5-9: 1st conversion in regular sequence.

Allowed values: 0-18

RSQ2

Bits 10-14: 2nd conversion in regular sequence.

Allowed values: 0-18

RSQ3

Bits 15-19: 3rd conversion in regular sequence.

Allowed values: 0-18

RSQ4

Bits 20-24: 4th conversion in regular sequence.

Allowed values: 0-18

RSQ5

Bits 25-29: 5th conversion in regular sequence.

Allowed values: 0-18

ISQ

injected sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IL
rw 		ISQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISQ3
rw 		ISQ2
rw 		ISQ1
rw 		ISQ0
rw
Toggle Fields.

ISQ0

Bits 0-4: conversion in injected sequence.

Allowed values: 0-18

ISQ1

Bits 5-9: 1st conversion in injected sequence.

Allowed values: 0-18

ISQ2

Bits 10-14: 2nd conversion in injected sequence.

Allowed values: 0-18

ISQ3

Bits 15-19: 3rd conversion in injected sequence.

Allowed values: 0-18

IL

Bits 20-21: Injected sequence length.

Allowed values: 0-3

IDATA0

injected data register 0

Offset: 0x3C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Injected data.

Allowed values: 0-65535

IDATA1

injected data register 1

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Injected data.

Allowed values: 0-65535

IDATA2

injected data register 2

Offset: 0x44, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Injected data.

Allowed values: 0-65535

IDATA3

injected data register 3

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Injected data.

Allowed values: 0-65535

RDATA

regular data register

Offset: 0x4C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle Fields.

RDATA

Bits 0-15: Regular data.

Allowed values: 0-65535

OVSAMPCTL

ADC oversample control register

Offset: 0x80, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOVS
rw 		OVSS
rw 		OVSR
rw 		OVSEN
rw
Toggle Fields.

OVSEN

Bit 0: Oversampler Enable.

OVSR

Bits 2-4: Oversampling ratio.

OVSS

Bits 5-8: Oversampling shift.

TOVS

Bit 9: Triggered Oversampling.

CMP

0x4001001C: Comparator

9/9 fields covered. Toggle Registers.

CS

control and status register

Offset: 0x0, reset: 0x00000000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPLK
rw 		CMPO
r 		CMPHST
rw 		CMPPL
rw 		CMPOSEL
rw 		CMPMSEL
rw 		CMPM
rw 		CMPSW
rw 		CMPEN
rw
Toggle Fields.

CMPEN

Bit 0: Comparator enable.

Allowed values:
0: Disabled: Comparator disabled
1: Enabled: Comparator enabled

CMPSW

Bit 1: Comparator switch .

Allowed values:
0: Open: Switch open
1: Closed: Switch closed

CMPM

Bits 2-3: Comparator mode.

Allowed values:
0: HighSpeed: High speed / full power
1: MediumSpeed: Medium speed / medium power
2: LowSpeed: Low speed / low power
3: VeryLowSpeed: Very-low speed / ultra-low power

CMPMSEL

Bits 4-6: Comparator input selection.

Allowed values:
0: OneQuarterVRef: 1/4 of VRefint
1: OneHalfVRef: 1/2 of VRefint
2: ThreeQuarterVRef: 3/4 of VRefint
3: VRef: VRefint
4: PA4: PA4 (DAC0
5: PA5: PA5
6: PA0: PA0

CMPOSEL

Bits 8-10: Comparator output selection.

Allowed values:
0: NoSelection: No selection
1: Timer0BreakInput: Timer 0 break input
2: Timer0InputCapture0: Timer 0 Input capture 0
3: Timer0OCPREClearInput: Timer 0 OCPRE_CLR input
4: Timer1InputCapture3: Timer 1 input capture 3
5: Timer1OCPREClearInput: Timer 1 OCPRE_CLR input
6: Timer2InputCapture0: Timer 2 input capture 0
7: Timer2OCPREClearInput: Timer 2 OCPRE_CLR input

CMPPL

Bit 11: Polarity of comparator output.

Allowed values:
0: NotInverted: Output is not inverted
1: Inverted: Output is inverted

CMPHST

Bits 12-13: Comparator hysteresis.

Allowed values:
0: NoHysteresis: No hysteresis
1: LowHysteresis: Low hysteresis
2: MediumHysteresis: Medium hysteresis
3: HighHysteresis: High hysteresis

CMPO

Bit 14: Comparator 0 output.

Allowed values:
0: Low: Non-inverting input below inverting input
1: High: Non-inverting input above inverting input

CMPLK

Bit 15: Comparator 0 lock.

Allowed values:
0: ReadWrite: Control bits are read-write
1: ReadOnly: Control bits are read-only

CRC

0x40023000: cyclic redundancy check calculation unit

6/8 fields covered. Toggle Registers.

DATA

Data register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: CRC calculation result bits.

Allowed values: 0-4294967295

FDATA

Free data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDATA
rw
Toggle Fields.

FDATA

Bits 0-7: General-purpose 8-bit data register bits.

Allowed values: 0-255

CTL

Control register

Offset: 0x8, reset: 0x00000000, access: read-write

3/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_O
rw 		REV_I
rw 		PS
rw 		RST
rw
Toggle Fields.

RST

Bit 0: reset bit.

Allowed values:
1: Reset: Resets the DATA register to IDATA, with no effect on FDATA

PS

Bits 3-4: Size of polynomial.

REV_I

Bits 5-6: Reverse input data.

Allowed values:
0: Normal: Bit order not affected
1: Byte: Bit reversal done by byte
2: HalfWord: Bit reversal done by half-word
3: Word: Bit reversal done by word

REV_O

Bit 7: Reverse output data.

Allowed values:
0: Normal: Bit order not affected
1: Reversed: Bit reversed output

IDATA

Initialization Data Register

Offset: 0x10, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATA
rw
Toggle Fields.

IDATA

Bits 0-31: CRC calculation initial value.

Allowed values: 0-4294967295

POLY

Polynomial register

Offset: 0x14, reset: 0x04C11DB7, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
POLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POLY
rw
Toggle Fields.

POLY

Bits 0-31: User configurable polynomial value.

DBG

0x40015800: Debug support

16/16 fields covered. Toggle Registers.

ID

MCU Device ID Code Register

Offset: 0x0, reset: 0x0, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID_CODE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID_CODE
r
Toggle Fields.

ID_CODE

Bits 0-31: DBG ID code register.

Allowed values: 0-4294967295

CTL0

Debug Control Register 0

Offset: 0x4, reset: 0x0, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIMER13_HOLD
rw 		TIMER5_HOLD
rw 		I2C1_HOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C0_HOLD
rw 		TIMER2_HOLD
rw 		TIMER0_HOLD
rw 		WWDGT_HOLD
rw 		FWDGT_HOLD
rw 		STB_HOLD
rw 		DSLP_HOLD
rw 		SLP_HOLD
rw
Toggle Fields.

SLP_HOLD

Bit 0: Sleep mode hold register.

Allowed values:
0: Disabled: No effect
1: Enabled: In sleep mode the AHB clock is on

DSLP_HOLD

Bit 1: DEEPSLEEP mode hold Mode.

Allowed values:
0: Disabled: No effect
1: Enabled: In deep-sleep mode the AHB clock and system clock are provided by IRC8M

STB_HOLD

Bit 2: Standby mode hold Mode.

Allowed values:
0: Disabled: No effect
1: Enabled: In standby mode the AHB clock and system clock are provided by IRC8M

FWDGT_HOLD

Bit 8: FWDGT hold register.

Allowed values:
0: Continue: Continue running the watchdog timer as usual
1: Stop: Hold the watchdog timer for debug when the core is halted

WWDGT_HOLD

Bit 9: WWDGT hold register.

Allowed values:
0: Continue: Continue running the watchdog timer as usual
1: Stop: Hold the watchdog timer for debug when the core is halted

TIMER0_HOLD

Bit 10: Timer 0 hold register.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER2_HOLD

Bit 12: Timer 2 hold register.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

I2C0_HOLD

Bit 15: I2C0 hold register.

Allowed values:
0: Continue: Continue running I2C as usual
1: Stop: Hold the I2C timeout for debug when the core is halted

I2C1_HOLD

Bit 16: I2C1 hold register.

Allowed values:
0: Continue: Continue running I2C as usual
1: Stop: Hold the I2C timeout for debug when the core is halted

TIMER5_HOLD

Bit 19: Timer 5 hold register.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER13_HOLD

Bit 27: Timer 13 hold register.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

CTL1

Debug Control Register 1

Offset: 0x8, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIMER16_HOLD
rw 		TIMER15_HOLD
rw 		TIMER14_HOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTC_HOLD
rw
Toggle Fields.

RTC_HOLD

Bit 10: RTC hold register.

Allowed values:
0: Continue: Continue running the RTC as usual
1: Stop: Hold the RTC for debug when the core is halted

TIMER14_HOLD

Bit 16: Timer 14 hold register.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER15_HOLD

Bit 17: Timer 15 hold register.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER16_HOLD

Bit 18: Timer 16 hold register.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

DMA

0x40020000: DMA controller

105/115 fields covered. Toggle Registers.

INTF

DMA interrupt flag register (DMA_INTF)

Offset: 0x0, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERRIF4
r 		HTFIF4
r 		FTFIF4
r 		GIF4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIF3
r 		HTFIF3
r 		FTFIF3
r 		GIF3
r 		ERRIF2
r 		HTFIF2
r 		FTFIF2
r 		GIF2
r 		ERRIF1
r 		HTFIF1
r 		FTFIF1
r 		GIF1
r 		ERRIF0
r 		HTFIF0
r 		FTFIF0
r 		GIF0
r
Toggle Fields.

GIF0

Bit 0: Channel 0 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF0

Bit 1: Channel 0 Full Transfer Finish flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF0

Bit 2: Channel 0 Half Transfer Finish flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF0

Bit 3: Channel 0 Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF1

Bit 4: Channel 1 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF1

Bit 5: Channel 1 Full Transfer Finish flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF1

Bit 6: Channel 1 Half Transfer Finish flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF1

Bit 7: Channel 1 Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF2

Bit 8: Channel 2 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF2

Bit 9: Channel 2 Full Transfer Finish flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF2

Bit 10: Channel 2 Half Transfer Finish flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF2

Bit 11: Channel 2 Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF3

Bit 12: Channel 3 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF3

Bit 13: Channel 3 Full Transfer Finish flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF3

Bit 14: Channel 3 Half Transfer Finish flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF3

Bit 15: Channel 3 Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF4

Bit 16: Channel 4 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF4

Bit 17: Channel 4 Full Transfer Finish flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF4

Bit 18: Channel 4 Half Transfer Finish flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF4

Bit 19: Channel 4 Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

INTC

DMA interrupt flag clear register (DMA_INTC)

Offset: 0x4, reset: 0x00000000, access: write-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERRIFC4
w 		HTFIFC4
w 		FTFIFC4
w 		GIFC4
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIFC3
w 		HTFIFC3
w 		FTFIFC3
w 		GIFC3
w 		ERRIFC2
w 		HTFIFC2
w 		FTFIFC2
w 		GIFC2
w 		ERRIFC1
w 		HTFIFC1
w 		FTFIFC1
w 		GIFC1
w 		ERRIFC0
w 		HTFIFC0
w 		FTFIFC0
w 		GIFC0
w
Toggle Fields.

GIFC0

Bit 0: Channel 0 Global interrupt flag clear.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC0

Bit 1: Channel 0 Full Transfer Finish clear.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC0

Bit 2: Channel 0 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC0

Bit 3: Channel 0 Error clear.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC1

Bit 4: Channel 1 Global interrupt flag clear.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC1

Bit 5: Channel 1 Full Transfer Finish clear.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC1

Bit 6: Channel 1 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC1

Bit 7: Channel 1 Error clear.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC2

Bit 8: Channel 2 Global interrupt flag clear.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC2

Bit 9: Channel 2 Full Transfer Finish clear.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC2

Bit 10: Channel 2 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC2

Bit 11: Channel 2 Error clear.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC3

Bit 12: Channel 3 Global interrupt flag clear.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC3

Bit 13: Channel 3 Full Transfer Finish clear.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC3

Bit 14: Channel 3 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC3

Bit 15: Channel 3 Error clear.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC4

Bit 16: Channel 4 Global interrupt flag clear.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC4

Bit 17: Channel 4 Full Transfer Finish clear.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC4

Bit 18: Channel 4 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC4

Bit 19: Channel 4 Error clear.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

CH0CTL

DMA channel configuration register (DMA_CH0CTL)

Offset: 0x8, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Full Transfer Finish interrupt enable.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Half Transfer Finish interrupt enable.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Transfer access error interrupt enable.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority Level of this channel.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH0CNT

DMA channel 0 counter register

Offset: 0xC, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH0PADDR

DMA channel 0 peripheral base address register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH0MADDR

DMA channel 0 memory base address register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory address.

CH1CTL

DMA channel configuration register (DMA_CH1CTL)

Offset: 0x1C, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Full Transfer Finish interrupt enable.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Half Transfer Finish interrupt enable.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Error interrupt enable.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority Level of this channel.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH1CNT

DMA channel 1 counter register

Offset: 0x20, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH1PADDR

DMA channel 1 peripheral base address register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH1MADDR

DMA channel 1 memory base address register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory address.

CH2CTL

DMA channel configuration register (DMA_CH2CTL)

Offset: 0x30, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Full Transfer Finish interrupt enable.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Half Transfer Finish interrupt enable.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Error interrupt enable.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority Level of this channel.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH2CNT

DMA channel 2 counter register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH2PADDR

DMA channel 2 peripheral base address register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH2MADDR

DMA channel 2 memory base address register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory address.

CH3CTL

DMA channel configuration register (DMA_CH3CTL)

Offset: 0x44, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Full Transfer Finish interrupt enable.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Half Transfer Finish interrupt enable.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Error interrupt enable.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority Level of this channel.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH3CNT

DMA channel 3 counter register

Offset: 0x48, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH3PADDR

DMA channel 3 peripheral base address register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH3MADDR

DMA channel 3 memory base address register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory address.

CH4CTL

DMA channel configuration register (DMA_CH4CTL)

Offset: 0x58, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Full Transfer Finish interrupt enable.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Half Transfer Finish interrupt enable.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Error interrupt enable.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority Level of this channel.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH4CNT

DMA channel 4 counter register

Offset: 0x5C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH4PADDR

DMA channel 4 peripheral base address register

Offset: 0x60, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH4MADDR

DMA channel 4 memory base address register

Offset: 0x64, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory address.

EXTI

0x40010400: External interrupt/event controller

136/136 fields covered. Toggle Registers.

INTEN

Interrupt enable register (EXTI_INTEN)

Offset: 0x0, reset: 0x0F940000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INTEN27
rw 		INTEN26
rw 		INTEN25
rw 		INTEN24
rw 		INTEN23
rw 		INTEN22
rw 		INTEN21
rw 		INTEN20
rw 		INTEN19
rw 		INTEN18
rw 		INTEN17
rw 		INTEN16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTEN15
rw 		INTEN14
rw 		INTEN13
rw 		INTEN12
rw 		INTEN11
rw 		INTEN10
rw 		INTEN9
rw 		INTEN8
rw 		INTEN7
rw 		INTEN6
rw 		INTEN5
rw 		INTEN4
rw 		INTEN3
rw 		INTEN2
rw 		INTEN1
rw 		INTEN0
rw
Toggle Fields.

INTEN0

Bit 0: Enable Interrupt on line 0.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN1

Bit 1: Enable Interrupt on line 1.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN2

Bit 2: Enable Interrupt on line 2.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN3

Bit 3: Enable Interrupt on line 3.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN4

Bit 4: Enable Interrupt on line 4.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN5

Bit 5: Enable Interrupt on line 5.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN6

Bit 6: Enable Interrupt on line 6.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN7

Bit 7: Enable Interrupt on line 7.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN8

Bit 8: Enable Interrupt on line 8.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN9

Bit 9: Enable Interrupt on line 9.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN10

Bit 10: Enable Interrupt on line 10.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN11

Bit 11: Enable Interrupt on line 11.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN12

Bit 12: Enable Interrupt on line 12.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN13

Bit 13: Enable Interrupt on line 13.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN14

Bit 14: Enable Interrupt on line 14.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN15

Bit 15: Enable Interrupt on line 15.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN16

Bit 16: Enable Interrupt on line 16.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN17

Bit 17: Enable Interrupt on line 17.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN18

Bit 18: Enable Interrupt on line 18.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN19

Bit 19: Enable Interrupt on line 19.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN20

Bit 20: Enable Interrupt on line 20.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN21

Bit 21: Enable Interrupt on line 21.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN22

Bit 22: Enable Interrupt on line 22.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN23

Bit 23: Enable Interrupt on line 23.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN24

Bit 24: Enable Interrupt on line 24.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN25

Bit 25: Enable Interrupt on line 25.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN26

Bit 26: Enable Interrupt on line 26.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN27

Bit 27: Enable Interrupt on line 27.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

EVEN

Event enable register (EXTI_EVEN)

Offset: 0x4, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EVEN27
rw 		EVEN26
rw 		EVEN25
rw 		EVEN24
rw 		EVEN23
rw 		EVEN22
rw 		EVEN21
rw 		EVEN20
rw 		EVEN19
rw 		EVEN18
rw 		EVEN17
rw 		EVEN16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EVEN15
rw 		EVEN14
rw 		EVEN13
rw 		EVEN12
rw 		EVEN11
rw 		EVEN10
rw 		EVEN9
rw 		EVEN8
rw 		EVEN7
rw 		EVEN6
rw 		EVEN5
rw 		EVEN4
rw 		EVEN3
rw 		EVEN2
rw 		EVEN1
rw 		EVEN0
rw
Toggle Fields.

EVEN0

Bit 0: Enable Event on line 0.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN1

Bit 1: Enable Event on line 1.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN2

Bit 2: Enable Event on line 2.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN3

Bit 3: Enable Event on line 3.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN4

Bit 4: Enable Event on line 4.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN5

Bit 5: Enable Event on line 5.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN6

Bit 6: Enable Event on line 6.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN7

Bit 7: Enable Event on line 7.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN8

Bit 8: Enable Event on line 8.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN9

Bit 9: Enable Event on line 9.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN10

Bit 10: Enable Event on line 10.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN11

Bit 11: Enable Event on line 11.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN12

Bit 12: Enable Event on line 12.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN13

Bit 13: Enable Event on line 13.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN14

Bit 14: Enable Event on line 14.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN15

Bit 15: Enable Event on line 15.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN16

Bit 16: Enable Event on line 16.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN17

Bit 17: Enable Event on line 17.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN18

Bit 18: Enable Event on line 18.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN19

Bit 19: Enable Event on line 19.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN20

Bit 20: Enable Event on line 20.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN21

Bit 21: Enable Event on line 21.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN22

Bit 22: Enable Event on line 22.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN23

Bit 23: Enable Event on line 23.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN24

Bit 24: Enable Event on line 24.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN25

Bit 25: Enable Event on line 25.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN26

Bit 26: Enable Event on line 26.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN27

Bit 27: Enable Event on line 27.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

RTEN

Rising Edge Trigger Enable register (EXTI_RTEN)

Offset: 0x8, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTEN21
rw 		RTEN19
rw 		RTEN17
rw 		RTEN16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTEN15
rw 		RTEN14
rw 		RTEN13
rw 		RTEN12
rw 		RTEN11
rw 		RTEN10
rw 		RTEN9
rw 		RTEN8
rw 		RTEN7
rw 		RTEN6
rw 		RTEN5
rw 		RTEN4
rw 		RTEN3
rw 		RTEN2
rw 		RTEN1
rw 		RTEN0
rw
Toggle Fields.

RTEN0

Bit 0: Rising trigger event configuration of line 0.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN1

Bit 1: Rising trigger event configuration of line 1.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN2

Bit 2: Rising trigger event configuration of line 2.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN3

Bit 3: Rising trigger event configuration of line 3.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN4

Bit 4: Rising trigger event configuration of line 4.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN5

Bit 5: Rising trigger event configuration of line 5.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN6

Bit 6: Rising trigger event configuration of line 6.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN7

Bit 7: Rising trigger event configuration of line 7.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN8

Bit 8: Rising trigger event configuration of line 8.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN9

Bit 9: Rising trigger event configuration of line 9.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN10

Bit 10: Rising trigger event configuration of line 10.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN11

Bit 11: Rising trigger event configuration of line 11.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN12

Bit 12: Rising trigger event configuration of line 12.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN13

Bit 13: Rising trigger event configuration of line 13.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN14

Bit 14: Rising trigger event configuration of line 14.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN15

Bit 15: Rising trigger event configuration of line 15.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN16

Bit 16: Rising trigger event configuration of line 16.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN17

Bit 17: Rising trigger event configuration of line 17.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN19

Bit 19: Rising trigger event configuration of line 19.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN21

Bit 21: Rising trigger event configuration of line 21.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTEN

Falling Egde Trigger Enable register (EXTI_FTEN)

Offset: 0xC, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTEN21
rw 		FTEN19
rw 		FTEN17
rw 		FTEN16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTEN15
rw 		FTEN14
rw 		FTEN13
rw 		FTEN12
rw 		FTEN11
rw 		FTEN10
rw 		FTEN9
rw 		FTEN8
rw 		FTEN7
rw 		FTEN6
rw 		FTEN5
rw 		FTEN4
rw 		FTEN3
rw 		FTEN2
rw 		FTEN1
rw 		FTEN0
rw
Toggle Fields.

FTEN0

Bit 0: Falling trigger event configuration of line 0.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN1

Bit 1: Falling trigger event configuration of line 1.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN2

Bit 2: Falling trigger event configuration of line 2.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN3

Bit 3: Falling trigger event configuration of line 3.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN4

Bit 4: Falling trigger event configuration of line 4.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN5

Bit 5: Falling trigger event configuration of line 5.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN6

Bit 6: Falling trigger event configuration of line 6.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN7

Bit 7: Falling trigger event configuration of line 7.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN8

Bit 8: Falling trigger event configuration of line 8.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN9

Bit 9: Falling trigger event configuration of line 9.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN10

Bit 10: Falling trigger event configuration of line 10.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN11

Bit 11: Falling trigger event configuration of line 11.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN12

Bit 12: Falling trigger event configuration of line 12.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN13

Bit 13: Falling trigger event configuration of line 13.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN14

Bit 14: Falling trigger event configuration of line 14.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN15

Bit 15: Falling trigger event configuration of line 15.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN16

Bit 16: Falling trigger event configuration of line 16.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN17

Bit 17: Falling trigger event configuration of line 17.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN19

Bit 19: Falling trigger event configuration of line 19.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN21

Bit 21: Falling trigger event configuration of line 21.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIEV

Software interrupt event register (EXTI_SWIEV)

Offset: 0x10, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWIEV21
rw 		SWIEV19
rw 		SWIEV17
rw 		SWIEV16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWIEV15
rw 		SWIEV14
rw 		SWIEV13
rw 		SWIEV12
rw 		SWIEV11
rw 		SWIEV10
rw 		SWIEV9
rw 		SWIEV8
rw 		SWIEV7
rw 		SWIEV6
rw 		SWIEV5
rw 		SWIEV4
rw 		SWIEV3
rw 		SWIEV2
rw 		SWIEV1
rw 		SWIEV0
rw
Toggle Fields.

SWIEV0

Bit 0: Software Interrupt on line 0.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV1

Bit 1: Software Interrupt on line 1.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV2

Bit 2: Software Interrupt on line 2.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV3

Bit 3: Software Interrupt on line 3.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV4

Bit 4: Software Interrupt on line 4.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV5

Bit 5: Software Interrupt on line 5.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV6

Bit 6: Software Interrupt on line 6.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV7

Bit 7: Software Interrupt on line 7.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV8

Bit 8: Software Interrupt on line 8.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV9

Bit 9: Software Interrupt on line 9.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV10

Bit 10: Software Interrupt on line 10.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV11

Bit 11: Software Interrupt on line 11.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV12

Bit 12: Software Interrupt on line 12.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV13

Bit 13: Software Interrupt on line 13.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV14

Bit 14: Software Interrupt on line 14.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV15

Bit 15: Software Interrupt on line 15.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV16

Bit 16: Software Interrupt on line 16.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV17

Bit 17: Software Interrupt on line 17.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV19

Bit 19: Software Interrupt on line 19.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV21

Bit 21: Software Interrupt on line 21.

Allowed values:
1: Pend: Generates an interrupt request

PD

Pending register (EXTI_PD)

Offset: 0x14, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PD21
rw 		PD19
rw 		PD17
rw 		PD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle Fields.

PD0

Bit 0: Pending bit 0.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD1

Bit 1: Pending bit 1.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD2

Bit 2: Pending bit 2.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD3

Bit 3: Pending bit 3.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD4

Bit 4: Pending bit 4.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD5

Bit 5: Pending bit 5.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD6

Bit 6: Pending bit 6.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD7

Bit 7: Pending bit 7.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD8

Bit 8: Pending bit 8.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD9

Bit 9: Pending bit 9.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD10

Bit 10: Pending bit 10.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD11

Bit 11: Pending bit 11.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD12

Bit 12: Pending bit 12.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD13

Bit 13: Pending bit 13.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD14

Bit 14: Pending bit 14.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD15

Bit 15: Pending bit 15.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD16

Bit 16: Pending bit 16.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD17

Bit 17: Pending bit 17.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD19

Bit 19: Pending bit 19.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD21

Bit 21: Pending bit 21.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FMC

0x40022000: FMC

25/28 fields covered. Toggle Registers.

WS

wait state register

Offset: 0x0, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PGW
rw 		PFEN
rw 		WSCNT
rw
Toggle Fields.

WSCNT

Bits 0-2: wait state counter register.

Allowed values:
0: WS0: 0 wait states added
1: WS1: 1 wait state added
2: WS2: 2 wait states added

PFEN

Bit 4: Pre-fetch enable.

PGW

Bit 15: Program width to flash memory.

KEY

Unlock key register

Offset: 0x4, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-31: FMC_CTL unlock register.

Allowed values: 0-4294967295

OBKEY

Option byte unlock key register

Offset: 0x8, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OBKEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OBKEY
w
Toggle Fields.

OBKEY

Bits 0-31: FMC_ CTL option bytes operation unlock register.

Allowed values: 0-4294967295

STAT

Status register

Offset: 0xC, reset: 0x00000000, access: Unspecified

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENDF
rw 		WPERR
rw 		PGAERR
rw 		PGERR
rw 		BUSY
r
Toggle Fields.

BUSY

Bit 0: The flash is busy bit.

Allowed values:
0: Inactive: No operation is in progress
1: Active: An operation is in progress

PGERR

Bit 2: Program error flag bit.

Allowed values:
0: NoError: There was no error
1: Error: There was an error programming flash

PGAERR

Bit 3: Program alignment error flag bit.

WPERR

Bit 4: Erase/Program protection error flag bit.

Allowed values:
0: NoError: There was no error
1: Error: There was an error erasing/programming protected pages

ENDF

Bit 5: End of operation flag bit.

Allowed values:
0: NoEvent: No end of operation occurred
1: Event: An end of operation event occurred

CTL

Control register

Offset: 0x10, reset: 0x00000080, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OBRLD
rw 		ENDIE
rw 		ERRIE
rw 		OBWEN
rw 		LK
rw 		START
rw 		OBER
rw 		OBPG
rw 		MER
rw 		PER
rw 		PG
rw
Toggle Fields.

PG

Bit 0: Main flash program for bank0 command bit.

Allowed values:
1: Program: Flash programming activated

PER

Bit 1: Main flash page erase for bank0 command bit.

Allowed values:
1: PageErase: Erase activated for selected page

MER

Bit 2: Main flash mass erase for bank0 command bit.

Allowed values:
1: MassErase: Erase activated for all user sectors

OBPG

Bit 4: Option bytes program command bit.

Allowed values:
1: OptionByteProgramming: Program option byte activated

OBER

Bit 5: Option bytes erase command bit.

Allowed values:
1: OptionByteErase: Erase option byte activated

START

Bit 6: Send erase command to FMC bit.

Allowed values:
1: Start: Trigger an erase operation

LK

Bit 7: FMC_CTL lock bit.

Allowed values:
0: Unlocked: CTL register is unlocked
1: Locked: CTL register is locked

OBWEN

Bit 9: Option byte erase/program enable bit.

Allowed values:
0: Disabled: Option byte write disabled
1: Enabled: Option byte write enabled

ERRIE

Bit 10: Error interrupt enable bit.

Allowed values:
0: Disabled: Error interrupt generation disabled
1: Enabled: Error interrupt generation enabled

ENDIE

Bit 12: End of operation interrupt enable bit.

Allowed values:
0: Disabled: End of operation interrupt disabled
1: Enabled: End of operation interrupt enabled

OBRLD

Bit 13: Option byte reload bit.

Allowed values:
1: Reload: Force option bytes reload and reset

ADDR

Address register

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
rw
Toggle Fields.

ADDR

Bits 0-31: Flash erase/program command address bits.

Allowed values: 0-4294967295

OBSTAT

Option byte control register

Offset: 0x1C, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OB_DATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OB_USER
r 		PLEVEL
r 		OBERR
r
Toggle Fields.

OBERR

Bit 0: Option bytes read error bit.

Allowed values:
0: NoError: No error with option bytes
1: Error: Option bytes and complement bytes do not match

PLEVEL

Bits 1-2: Option bytes security protection level.

Allowed values:
0: None: No protection level
1: Low: Low protection level
3: High: High protection level

OB_USER

Bits 8-15: Store USER of option bytes block after system reset.

Allowed values: 0-255

OB_DATA

Bits 16-31: Store DATA[15:0] of option bytes block after system reset.

Allowed values: 0-65535

WP

Erase/Program Protection register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OB_WP
r
Toggle Fields.

OB_WP

Bits 0-15: Store WP[15:0] of option bytes block after system reset.

Allowed values: 0-65535

PID

Product ID register

Offset: 0x100, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PID
r
Toggle Fields.

PID

Bits 0-31: Product reserved ID code register.

Allowed values: 0-4294967295

FWDGT

0x40003000: free watchdog timer

7/7 fields covered. Toggle Registers.

CTL

Control register

Offset: 0x0, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMD
w
Toggle Fields.

CMD

Bits 0-15: Key value.

Allowed values:
21845: Enable: Enable access to PR, RLR and WINR registers (0x5555)
43690: Reset: Reset the watchdog value (0xAAAA)
52428: Start: Start the watchdog (0xCCCC)

PSC

Prescaler register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-2: Prescaler divider.

Allowed values:
0: DivideBy4: Divider /4
1: DivideBy8: Divider /8
2: DivideBy16: Divider /16
3: DivideBy32: Divider /32
4: DivideBy64: Divider /64
5: DivideBy128: Divider /128
6: DivideBy256: Divider /256
7: DivideBy256bis: Divider /256

RLD

Reload register

Offset: 0x8, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RLD
rw
Toggle Fields.

RLD

Bits 0-11: Watchdog counter reload value.

Allowed values: 0-4095

STAT

Status register

Offset: 0xC, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUD
r 		RUD
r 		PUD
r
Toggle Fields.

PUD

Bit 0: Watchdog prescaler value update.

Allowed values:
0: Valid: The value read from the PSC register is valid
1: Ongoing: A write operation to to the PSC register is ongoing, so the value read is invalid

RUD

Bit 1: Watchdog counter reload value update.

Allowed values:
0: Valid: The value read from the RLD register is valid
1: Ongoing: A write operation to to the RLD register is ongoing, so the value read is invalid

WUD

Bit 2: Watchdog counter window value update.

Allowed values:
0: Valid: The value read from the WND register is valid
1: Ongoing: A write operation to to the WND register is ongoing, so the value read is invalid

WND

Window register

Offset: 0x10, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WND
rw
Toggle Fields.

WND

Bits 0-11: Watchdog counter window value.

Allowed values: 0-4095

GPIOA

0x48000000: General-purpose I/Os

193/193 fields covered. Toggle Registers.

CTL

GPIO port control register

Offset: 0x0, reset: 0x28000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		CTL14
rw 		CTL13
rw 		CTL12
rw 		CTL11
rw 		CTL10
rw 		CTL9
rw 		CTL8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL7
rw 		CTL6
rw 		CTL5
rw 		CTL4
rw 		CTL3
rw 		CTL2
rw 		CTL1
rw 		CTL0
rw
Toggle Fields.

CTL0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OMODE

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OM15
rw 		OM14
rw 		OM13
rw 		OM12
rw 		OM11
rw 		OM10
rw 		OM9
rw 		OM8
rw 		OM7
rw 		OM6
rw 		OM5
rw 		OM4
rw 		OM3
rw 		OM2
rw 		OM1
rw 		OM0
rw
Toggle Fields.

OM0

Bit 0: Port x configuration bit 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM1

Bit 1: Port x configuration bit 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM2

Bit 2: Port x configuration bit 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM3

Bit 3: Port x configuration bit 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM4

Bit 4: Port x configuration bit 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM5

Bit 5: Port x configuration bit 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM6

Bit 6: Port x configuration bit 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM7

Bit 7: Port x configuration bit 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM8

Bit 8: Port x configuration bit 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM9

Bit 9: Port x configuration bit 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM10

Bit 10: Port x configuration bit 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM11

Bit 11: Port x configuration bit 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM12

Bit 12: Port x configuration bit 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM13

Bit 13: Port x configuration bit 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM14

Bit 14: Port x configuration bit 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM15

Bit 15: Port x configuration bit 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPD

GPIO port output speed register

Offset: 0x8, reset: 0x0C000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPD15
rw 		OSPD14
rw 		OSPD13
rw 		OSPD12
rw 		OSPD11
rw 		OSPD10
rw 		OSPD9
rw 		OSPD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPD7
rw 		OSPD6
rw 		OSPD5
rw 		OSPD4
rw 		OSPD3
rw 		OSPD2
rw 		OSPD1
rw 		OSPD0
rw
Toggle Fields.

OSPD0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

PUD

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x24000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUD15
rw 		PUD14
rw 		PUD13
rw 		PUD12
rw 		PUD11
rw 		PUD10
rw 		PUD9
rw 		PUD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUD7
rw 		PUD6
rw 		PUD5
rw 		PUD4
rw 		PUD3
rw 		PUD2
rw 		PUD1
rw 		PUD0
rw
Toggle Fields.

PUD0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

ISTAT

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port x reset bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LKK

Bit 16: Port x lock bit y .

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFSEL0

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL7
rw 		SEL6
rw 		SEL5
rw 		SEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL3
rw 		SEL2
rw 		SEL1
rw 		SEL0
rw
Toggle Fields.

SEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

AFSEL1

GPIO alternate function register 1

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL15
rw 		SEL14
rw 		SEL13
rw 		SEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL11
rw 		SEL10
rw 		SEL9
rw 		SEL8
rw
Toggle Fields.

SEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

BC

Port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

TG

Port bit toggle register

Offset: 0x2C, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG15
w 		TG14
w 		TG13
w 		TG12
w 		TG11
w 		TG10
w 		TG9
w 		TG8
w 		TG7
w 		TG6
w 		TG5
w 		TG4
w 		TG3
w 		TG2
w 		TG1
w 		TG0
w
Toggle Fields.

TG0

Bit 0: Port toggle bit .

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG1

Bit 1: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG2

Bit 2: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG3

Bit 3: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG4

Bit 4: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG5

Bit 5: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG6

Bit 6: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG7

Bit 7: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG8

Bit 8: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG9

Bit 9: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG10

Bit 10: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG11

Bit 11: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG12

Bit 12: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG13

Bit 13: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG14

Bit 14: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG15

Bit 15: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

GPIOB

0x48000400: General-purpose I/Os

193/193 fields covered. Toggle Registers.

CTL

GPIO port control register

Offset: 0x0, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		CTL14
rw 		CTL13
rw 		CTL12
rw 		CTL11
rw 		CTL10
rw 		CTL9
rw 		CTL8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL7
rw 		CTL6
rw 		CTL5
rw 		CTL4
rw 		CTL3
rw 		CTL2
rw 		CTL1
rw 		CTL0
rw
Toggle Fields.

CTL0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OMODE

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OM15
rw 		OM14
rw 		OM13
rw 		OM12
rw 		OM11
rw 		OM10
rw 		OM9
rw 		OM8
rw 		OM7
rw 		OM6
rw 		OM5
rw 		OM4
rw 		OM3
rw 		OM2
rw 		OM1
rw 		OM0
rw
Toggle Fields.

OM0

Bit 0: Port x configuration bit 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM1

Bit 1: Port x configuration bit 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM2

Bit 2: Port x configuration bit 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM3

Bit 3: Port x configuration bit 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM4

Bit 4: Port x configuration bit 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM5

Bit 5: Port x configuration bit 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM6

Bit 6: Port x configuration bit 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM7

Bit 7: Port x configuration bit 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM8

Bit 8: Port x configuration bit 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM9

Bit 9: Port x configuration bit 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM10

Bit 10: Port x configuration bit 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM11

Bit 11: Port x configuration bit 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM12

Bit 12: Port x configuration bit 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM13

Bit 13: Port x configuration bit 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM14

Bit 14: Port x configuration bit 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM15

Bit 15: Port x configuration bit 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPD

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPD15
rw 		OSPD14
rw 		OSPD13
rw 		OSPD12
rw 		OSPD11
rw 		OSPD10
rw 		OSPD9
rw 		OSPD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPD7
rw 		OSPD6
rw 		OSPD5
rw 		OSPD4
rw 		OSPD3
rw 		OSPD2
rw 		OSPD1
rw 		OSPD0
rw
Toggle Fields.

OSPD0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

PUD

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUD15
rw 		PUD14
rw 		PUD13
rw 		PUD12
rw 		PUD11
rw 		PUD10
rw 		PUD9
rw 		PUD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUD7
rw 		PUD6
rw 		PUD5
rw 		PUD4
rw 		PUD3
rw 		PUD2
rw 		PUD1
rw 		PUD0
rw
Toggle Fields.

PUD0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

ISTAT

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port x reset bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LKK

Bit 16: Port x lock bit y .

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFSEL0

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL7
rw 		SEL6
rw 		SEL5
rw 		SEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL3
rw 		SEL2
rw 		SEL1
rw 		SEL0
rw
Toggle Fields.

SEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

AFSEL1

GPIO alternate function register 1

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL15
rw 		SEL14
rw 		SEL13
rw 		SEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL11
rw 		SEL10
rw 		SEL9
rw 		SEL8
rw
Toggle Fields.

SEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

BC

Port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

TG

Port bit toggle register

Offset: 0x2C, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG15
w 		TG14
w 		TG13
w 		TG12
w 		TG11
w 		TG10
w 		TG9
w 		TG8
w 		TG7
w 		TG6
w 		TG5
w 		TG4
w 		TG3
w 		TG2
w 		TG1
w 		TG0
w
Toggle Fields.

TG0

Bit 0: Port toggle bit .

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG1

Bit 1: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG2

Bit 2: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG3

Bit 3: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG4

Bit 4: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG5

Bit 5: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG6

Bit 6: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG7

Bit 7: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG8

Bit 8: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG9

Bit 9: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG10

Bit 10: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG11

Bit 11: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG12

Bit 12: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG13

Bit 13: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG14

Bit 14: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG15

Bit 15: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

GPIOC

0x48000800: General-purpose I/Os

176/176 fields covered. Toggle Registers.

CTL

GPIO port control register

Offset: 0x0, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		CTL14
rw 		CTL13
rw 		CTL12
rw 		CTL11
rw 		CTL10
rw 		CTL9
rw 		CTL8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL7
rw 		CTL6
rw 		CTL5
rw 		CTL4
rw 		CTL3
rw 		CTL2
rw 		CTL1
rw 		CTL0
rw
Toggle Fields.

CTL0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OMODE

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OM15
rw 		OM14
rw 		OM13
rw 		OM12
rw 		OM11
rw 		OM10
rw 		OM9
rw 		OM8
rw 		OM7
rw 		OM6
rw 		OM5
rw 		OM4
rw 		OM3
rw 		OM2
rw 		OM1
rw 		OM0
rw
Toggle Fields.

OM0

Bit 0: Port x configuration bit 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM1

Bit 1: Port x configuration bit 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM2

Bit 2: Port x configuration bit 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM3

Bit 3: Port x configuration bit 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM4

Bit 4: Port x configuration bit 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM5

Bit 5: Port x configuration bit 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM6

Bit 6: Port x configuration bit 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM7

Bit 7: Port x configuration bit 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM8

Bit 8: Port x configuration bit 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM9

Bit 9: Port x configuration bit 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM10

Bit 10: Port x configuration bit 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM11

Bit 11: Port x configuration bit 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM12

Bit 12: Port x configuration bit 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM13

Bit 13: Port x configuration bit 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM14

Bit 14: Port x configuration bit 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM15

Bit 15: Port x configuration bit 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPD

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPD15
rw 		OSPD14
rw 		OSPD13
rw 		OSPD12
rw 		OSPD11
rw 		OSPD10
rw 		OSPD9
rw 		OSPD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPD7
rw 		OSPD6
rw 		OSPD5
rw 		OSPD4
rw 		OSPD3
rw 		OSPD2
rw 		OSPD1
rw 		OSPD0
rw
Toggle Fields.

OSPD0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

PUD

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUD15
rw 		PUD14
rw 		PUD13
rw 		PUD12
rw 		PUD11
rw 		PUD10
rw 		PUD9
rw 		PUD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUD7
rw 		PUD6
rw 		PUD5
rw 		PUD4
rw 		PUD3
rw 		PUD2
rw 		PUD1
rw 		PUD0
rw
Toggle Fields.

PUD0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

ISTAT

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port x reset bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

AFSEL0

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL7
rw 		SEL6
rw 		SEL5
rw 		SEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL3
rw 		SEL2
rw 		SEL1
rw 		SEL0
rw
Toggle Fields.

SEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

AFSEL1

GPIO alternate function register 1

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL15
rw 		SEL14
rw 		SEL13
rw 		SEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL11
rw 		SEL10
rw 		SEL9
rw 		SEL8
rw
Toggle Fields.

SEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

SEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
9: AF9: AF9
11: AF11: AF11

BC

Port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port cleat bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

TG

Port bit toggle register

Offset: 0x2C, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG15
w 		TG14
w 		TG13
w 		TG12
w 		TG11
w 		TG10
w 		TG9
w 		TG8
w 		TG7
w 		TG6
w 		TG5
w 		TG4
w 		TG3
w 		TG2
w 		TG1
w 		TG0
w
Toggle Fields.

TG0

Bit 0: Port toggle bit .

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG1

Bit 1: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG2

Bit 2: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG3

Bit 3: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG4

Bit 4: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG5

Bit 5: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG6

Bit 6: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG7

Bit 7: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG8

Bit 8: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG9

Bit 9: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG10

Bit 10: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG11

Bit 11: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG12

Bit 12: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG13

Bit 13: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG14

Bit 14: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG15

Bit 15: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

GPIOF

0x48001400: General-purpose I/Os

160/160 fields covered. Toggle Registers.

CTL

GPIOF port control register

Offset: 0x0, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		CTL14
rw 		CTL13
rw 		CTL12
rw 		CTL11
rw 		CTL10
rw 		CTL9
rw 		CTL8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL7
rw 		CTL6
rw 		CTL5
rw 		CTL4
rw 		CTL3
rw 		CTL2
rw 		CTL1
rw 		CTL0
rw
Toggle Fields.

CTL0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

CTL15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OMODE

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OM15
rw 		OM14
rw 		OM13
rw 		OM12
rw 		OM11
rw 		OM10
rw 		OM9
rw 		OM8
rw 		OM7
rw 		OM6
rw 		OM5
rw 		OM4
rw 		OM3
rw 		OM2
rw 		OM1
rw 		OM0
rw
Toggle Fields.

OM0

Bit 0: Port x configuration bit 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM1

Bit 1: Port x configuration bit 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM2

Bit 2: Port x configuration bit 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM3

Bit 3: Port x configuration bit 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM4

Bit 4: Port x configuration bit 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM5

Bit 5: Port x configuration bit 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM6

Bit 6: Port x configuration bit 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM7

Bit 7: Port x configuration bit 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM8

Bit 8: Port x configuration bit 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM9

Bit 9: Port x configuration bit 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM10

Bit 10: Port x configuration bit 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM11

Bit 11: Port x configuration bit 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM12

Bit 12: Port x configuration bit 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM13

Bit 13: Port x configuration bit 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM14

Bit 14: Port x configuration bit 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OM15

Bit 15: Port x configuration bit 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPD

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPD15
rw 		OSPD14
rw 		OSPD13
rw 		OSPD12
rw 		OSPD11
rw 		OSPD10
rw 		OSPD9
rw 		OSPD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPD7
rw 		OSPD6
rw 		OSPD5
rw 		OSPD4
rw 		OSPD3
rw 		OSPD2
rw 		OSPD1
rw 		OSPD0
rw
Toggle Fields.

OSPD0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

OSPD15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Speed2M: Max output speed 2 MHz
1: Speed10M: Max output speed 10 MHz
3: Speed50M: Max output speed 50 MHz

PUD

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUD15
rw 		PUD14
rw 		PUD13
rw 		PUD12
rw 		PUD11
rw 		PUD10
rw 		PUD9
rw 		PUD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUD7
rw 		PUD6
rw 		PUD5
rw 		PUD4
rw 		PUD3
rw 		PUD2
rw 		PUD1
rw 		PUD0
rw
Toggle Fields.

PUD0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

PUD15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down (reset state)
1: PullUp: Pull-up
2: PullDown: Pull-down

ISTAT

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input data (y = 0..15).

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output data (y = 0..15).

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port x Reset bit y.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port x Reset bit y.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port x Reset bit y.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port x Reset bit y.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port x Reset bit y.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port x Reset bit y.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port x Reset bit y.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port x Reset bit y.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port x Reset bit y.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port x Reset bit y.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port x Reset bit y.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port x Reset bit y.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port x Reset bit y.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port x Reset bit y.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port x Reset bit y.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port x Reset bit y.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

TG

Port bit toggle register

Offset: 0x2C, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG15
w 		TG14
w 		TG13
w 		TG12
w 		TG11
w 		TG10
w 		TG9
w 		TG8
w 		TG7
w 		TG6
w 		TG5
w 		TG4
w 		TG3
w 		TG2
w 		TG1
w 		TG0
w
Toggle Fields.

TG0

Bit 0: Port toggle bit .

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG1

Bit 1: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG2

Bit 2: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG3

Bit 3: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG4

Bit 4: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG5

Bit 5: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG6

Bit 6: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG7

Bit 7: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG8

Bit 8: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG9

Bit 9: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG10

Bit 10: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG11

Bit 11: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG12

Bit 12: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG13

Bit 13: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG14

Bit 14: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

TG15

Bit 15: Port toggle bit.

Allowed values:
1: Toggle: Toggles the corresponding OCTLx bit

I2C0

0x40005400: Inter integrated circuit

57/64 fields covered. Toggle Registers.

CTL0

Control register 0

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRESET
rw 		SALT
rw 		PECTRANS
rw 		POAP
rw 		ACKEN
rw 		STOP
rw 		START
rw 		SS
rw 		GCEN
rw 		PECEN
rw 		ARPEN
rw 		SMBSEL
rw 		SMBEN
rw 		I2CEN
rw
Toggle Fields.

I2CEN

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

SMBEN

Bit 1: SMBus mode.

Allowed values:
0: I2C: I2C Mode
1: SMBus: SMBus

SMBSEL

Bit 3: SMBus type.

Allowed values:
0: Device: SMBus Device
1: Host: SMBus Host

ARPEN

Bit 4: ARP enable.

Allowed values:
0: Disabled: ARP disabled
1: Enabled: ARP enabled

PECEN

Bit 5: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

GCEN

Bit 6: General call enable.

Allowed values:
0: NotRespond: Slave won't respond to General Call
1: Respond: Slave will respond to General Call

SS

Bit 7: SCL Stretching(Slave mode).

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

START

Bit 8: Start generation.

Allowed values:
0: NoStart: START will not be sent
1: Start: START will be sent

STOP

Bit 9: Stop condition.

Allowed values:
0: NoStop: STOP will not be sent
1: Stop: STOP will be sent

ACKEN

Bit 10: Acknowledge enable.

Allowed values:
0: NAK: No acknowledge returned
1: ACK: Acknowledge returned after a byte is received

POAP

Bit 11: Acknowledge/PEC Position (for data reception).

Allowed values:
0: Current: ACK bit controls the (N)ACK of the current byte being received
1: Next: ACK bit controls the (N)ACK of the next byte to be received

PECTRANS

Bit 12: Packet error checking.

Allowed values:
0: Disabled: No PEC transfer
1: Enabled: PEC transfer

SALT

Bit 13: SMBus alert.

Allowed values:
0: Release: SMBA pin released high
1: Drive: SMBA pin driven low

SRESET

Bit 15: Software reset.

Allowed values:
0: NotReset: I2C peripheral not under reset
1: Reset: I2C peripheral under reset

CTL1

Control register 1

Offset: 0x4, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMALST
rw 		DMAON
rw 		BUFIE
rw 		EVIE
rw 		ERRIE
rw 		I2CCLK
rw
Toggle Fields.

I2CCLK

Bits 0-6: Peripheral clock frequency.

Allowed values: 2-72

ERRIE

Bit 8: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

EVIE

Bit 9: Event interrupt enable.

Allowed values:
0: Disabled: Event interrupt disabled
1: Enabled: Event interrupt enabled

BUFIE

Bit 10: Buffer interrupt enable.

Allowed values:
0: Disabled: TBE=1 or RBNE=1 does not generate any interrupt
1: Enabled: TBE=1 or RBNE=1 generates Event interrupt

DMAON

Bit 11: DMA mode switch.

Allowed values:
0: Disabled: DMA requests disabled
1: Enabled: DMA requests enabled

DMALST

Bit 12: Flag indicating DMA last transfer.

Allowed values:
0: NotLast: Next DMA EOT is not the last transfer
1: Last: Next DMA EOT is the last transfer

SADDR0

Own address register 0

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDFORMAT
rw 		ADDRESS
rw
Toggle Fields.

ADDRESS

Bits 0-9: Interface address.

Allowed values: 0-1023

ADDFORMAT

Bit 15: Addressing mode (slave mode).

Allowed values:
0: Add7: 7-bit slave address (note that you'll need to shift the address by 1b)
1: Add10: 10-bit slave address

SADDR1

Own address register 1

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS2
rw 		DUADEN
rw
Toggle Fields.

DUADEN

Bit 0: Dual addressing mode enable.

Allowed values:
0: Single: Single addressing mode
1: Dual: Dual addressing mode

ADDRESS2

Bits 1-7: Interface address.

Allowed values: 0-127

DATA

Data register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRB
rw
Toggle Fields.

TRB

Bits 0-7: Transmission or reception data buffer.

Allowed values: 0-255

STAT0

Transfer status register 0

Offset: 0x14, reset: 0x0000, access: Unspecified

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALT
rw 		SMBTO
rw 		PECERR
rw 		OUERR
rw 		AERR
rw 		LOSTARB
rw 		BERR
rw 		TBE
r 		RBNE
r 		STPDET
r 		ADD10SEND
r 		BTC
r 		ADDSEND
r 		SBSEND
r
Toggle Fields.

SBSEND

Bit 0: Start bit (Master mode).

Allowed values:
0: NoStart: No Start condition
1: Start: Start condition generated

ADDSEND

Bit 1: Address sent (master mode)/matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

BTC

Bit 2: Byte transmission completed.

Allowed values:
0: NotFinished: Data byte transfer not done
1: Finished: Data byte transfer successful

ADD10SEND

Bit 3: Header of 10-bit address is sent in master mode.

Allowed values:
0: NoHeader: No header of 10-bit address is sent
1: Header: Header of 10-bit address is sent

STPDET

Bit 4: Stop detection (slave mode).

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

RBNE

Bit 6: I2C_DATA is not Empty during receiving.

Allowed values:
0: Empty: Data register empty
1: NotEmpty: Data register not empty, software can read

TBE

Bit 7: I2C_DATA is Empty during transmitting.

Allowed values:
0: NotEmpty: Data register not empty
1: Empty: Data register empty, software can write

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No misplaced Start or Stop condition
1: Error: Misplaced Start or Stop condition

LOSTARB

Bit 9: Arbitration lost (master mode).

Allowed values:
0: NoLost: No Arbitration Lost detected
1: Lost: Arbitration Lost detected

AERR

Bit 10: Acknowledge error.

Allowed values:
0: NoError: No acknowledge error
1: Error: Acknowledge error

OUERR

Bit 11: Overrun/Underrun occurs in slave mode.

Allowed values:
0: NoOverrun: No overrun/underrun occured
1: Overrun: Overrun/underrun occured

PECERR

Bit 12: PEC error when receiving data.

Allowed values:
0: NoError: No PEC error
1: Error: PEC error

SMBTO

Bit 14: Timeout signal in SMBus mode.

Allowed values:
0: NoTimeout: No Timeout error
1: Timeout: SCL remained low for 25 ms

SMBALT

Bit 15: SMBus alert.

Allowed values:
0: NoAlert: SMBA not pulled down or no alert occured
1: Alert: SMBA pulled down or alert occurred

STAT1

Transfer status register 1

Offset: 0x18, reset: 0x0000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PECV
r 		DUMODF
r 		HSTSMB
r 		DEFSMB
r 		RXGC
r 		TR
r 		I2CBSY
r 		MASTER
r
Toggle Fields.

MASTER

Bit 0: Master/slave.

Allowed values:
0: Slave: Slave mode
1: Master: Master mode

I2CBSY

Bit 1: Bus busy.

Allowed values:
0: NotBusy: No I2C communication
1: Busy: I2C communication active

TR

Bit 2: Transmitter/receiver.

Allowed values:
0: Receiver: Receiver
1: Transmitter: Transmitter

RXGC

Bit 4: General call address (Slave mode).

Allowed values:
0: NotReceived: No general call address received
1: Received: General call address received

DEFSMB

Bit 5: SMBus device default address (Slave mode).

Allowed values:
0: NotReceived: Default address has not been received
1: Received: Default address has been received

HSTSMB

Bit 6: SMBus host header (Slave mode).

Allowed values:
0: NoHeader: No SMBus host header detected
1: Header: SMBus host header detected

DUMODF

Bit 7: Dual flag (Slave mode).

Allowed values:
0: SADDR0: The address matches SADDR0
1: SADDR1: The address matches SADDR1

PECV

Bits 8-15: Packet error checking register.

Allowed values: 0-127

CKCFG

Clock configure register

Offset: 0x1C, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAST
rw 		DTCY
rw 		CLKC
rw
Toggle Fields.

CLKC

Bits 0-11: Clock control register in Fast/Standard mode (Master mode).

Allowed values: 0-4095

DTCY

Bit 14: Fast mode duty cycle.

Allowed values:
0: Duty2: Duty cycle t_low/t_high = 2
1: Duty16_9: Duty cycle t_low/t_high = 16/9

FAST

Bit 15: I2C master mode selection.

Allowed values:
0: Standard: Standard mode I2C
1: Fast: Fast mode I2C

RT

Rise time register

Offset: 0x20, reset: 0x0002, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RISETIME
rw
Toggle Fields.

RISETIME

Bits 0-6: Maximum rise time in master mode.

Allowed values: 0-127

SAMCS

SAM control and status register

Offset: 0x80, reset: 0x0000, access: read-write

6/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFR
rw 		RFF
rw 		TFR
rw 		TFF
rw 		RXF
rw 		TXF
rw 		RFRIE
rw 		RFFIE
rw 		TFRIE
rw 		TFFIE
rw 		STOEN
rw 		SAMEN
rw
Toggle Fields.

SAMEN

Bit 0: SAM_V interface enable.

Allowed values:
0: Disabled: SAM_V interface disabled
1: Enabled: SAM_V interface enabled

STOEN

Bit 1: SAM_V interface timeout detect enable.

Allowed values:
0: Disabled: SAM_V interface timeout detect disabled
1: Enabled: SAM_V interface timeout detect enabled

TFFIE

Bit 4: Tx frame fall interrupt enable.

Allowed values:
0: Disabled: Txframe fall interrupt disabled
1: Enabled: Txframe fall interrupt enabled

TFRIE

Bit 5: Tx frame rise interrupt enable.

Allowed values:
0: Disabled: Txframe rise interrupt disabled
1: Enabled: Txframe rise interrupt enabled

RFFIE

Bit 6: Rx frame fall interrupt enable.

Allowed values:
0: Disabled: Rxframe fall interrupt disabled
1: Enabled: Rxframe fall interrupt enabled

RFRIE

Bit 7: Rx frame rise interrupt enable.

Allowed values:
0: Disabled: Rxframe rise interrupt disabled
1: Enabled: Rxframe rise interrupt enabled

TXF

Bit 8: level of tx frame signal.

RXF

Bit 9: level of rx frame signal.

TFF

Bit 12: Txframe fall flag.

TFR

Bit 13: Txframe rise flag.

RFF

Bit 14: Rxframe fall flag.

RFR

Bit 15: Rxframe rise flag.

FMPCFG

Fast-mode-plus configure register

Offset: 0x90, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMPEN
rw
Toggle Fields.

FMPEN

Bit 0: Fast-mode-plus enable.

I2C1

0x40005800: Inter integrated circuit

57/64 fields covered. Toggle Registers.

CTL0

Control register 0

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRESET
rw 		SALT
rw 		PECTRANS
rw 		POAP
rw 		ACKEN
rw 		STOP
rw 		START
rw 		SS
rw 		GCEN
rw 		PECEN
rw 		ARPEN
rw 		SMBSEL
rw 		SMBEN
rw 		I2CEN
rw
Toggle Fields.

I2CEN

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

SMBEN

Bit 1: SMBus mode.

Allowed values:
0: I2C: I2C Mode
1: SMBus: SMBus

SMBSEL

Bit 3: SMBus type.

Allowed values:
0: Device: SMBus Device
1: Host: SMBus Host

ARPEN

Bit 4: ARP enable.

Allowed values:
0: Disabled: ARP disabled
1: Enabled: ARP enabled

PECEN

Bit 5: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

GCEN

Bit 6: General call enable.

Allowed values:
0: NotRespond: Slave won't respond to General Call
1: Respond: Slave will respond to General Call

SS

Bit 7: SCL Stretching(Slave mode).

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

START

Bit 8: Start generation.

Allowed values:
0: NoStart: START will not be sent
1: Start: START will be sent

STOP

Bit 9: Stop condition.

Allowed values:
0: NoStop: STOP will not be sent
1: Stop: STOP will be sent

ACKEN

Bit 10: Acknowledge enable.

Allowed values:
0: NAK: No acknowledge returned
1: ACK: Acknowledge returned after a byte is received

POAP

Bit 11: Acknowledge/PEC Position (for data reception).

Allowed values:
0: Current: ACK bit controls the (N)ACK of the current byte being received
1: Next: ACK bit controls the (N)ACK of the next byte to be received

PECTRANS

Bit 12: Packet error checking.

Allowed values:
0: Disabled: No PEC transfer
1: Enabled: PEC transfer

SALT

Bit 13: SMBus alert.

Allowed values:
0: Release: SMBA pin released high
1: Drive: SMBA pin driven low

SRESET

Bit 15: Software reset.

Allowed values:
0: NotReset: I2C peripheral not under reset
1: Reset: I2C peripheral under reset

CTL1

Control register 1

Offset: 0x4, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMALST
rw 		DMAON
rw 		BUFIE
rw 		EVIE
rw 		ERRIE
rw 		I2CCLK
rw
Toggle Fields.

I2CCLK

Bits 0-6: Peripheral clock frequency.

Allowed values: 2-72

ERRIE

Bit 8: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

EVIE

Bit 9: Event interrupt enable.

Allowed values:
0: Disabled: Event interrupt disabled
1: Enabled: Event interrupt enabled

BUFIE

Bit 10: Buffer interrupt enable.

Allowed values:
0: Disabled: TBE=1 or RBNE=1 does not generate any interrupt
1: Enabled: TBE=1 or RBNE=1 generates Event interrupt

DMAON

Bit 11: DMA mode switch.

Allowed values:
0: Disabled: DMA requests disabled
1: Enabled: DMA requests enabled

DMALST

Bit 12: Flag indicating DMA last transfer.

Allowed values:
0: NotLast: Next DMA EOT is not the last transfer
1: Last: Next DMA EOT is the last transfer

SADDR0

Own address register 0

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDFORMAT
rw 		ADDRESS
rw
Toggle Fields.

ADDRESS

Bits 0-9: Interface address.

Allowed values: 0-1023

ADDFORMAT

Bit 15: Addressing mode (slave mode).

Allowed values:
0: Add7: 7-bit slave address (note that you'll need to shift the address by 1b)
1: Add10: 10-bit slave address

SADDR1

Own address register 1

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS2
rw 		DUADEN
rw
Toggle Fields.

DUADEN

Bit 0: Dual addressing mode enable.

Allowed values:
0: Single: Single addressing mode
1: Dual: Dual addressing mode

ADDRESS2

Bits 1-7: Interface address.

Allowed values: 0-127

DATA

Data register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRB
rw
Toggle Fields.

TRB

Bits 0-7: Transmission or reception data buffer.

Allowed values: 0-255

STAT0

Transfer status register 0

Offset: 0x14, reset: 0x0000, access: Unspecified

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALT
rw 		SMBTO
rw 		PECERR
rw 		OUERR
rw 		AERR
rw 		LOSTARB
rw 		BERR
rw 		TBE
r 		RBNE
r 		STPDET
r 		ADD10SEND
r 		BTC
r 		ADDSEND
r 		SBSEND
r
Toggle Fields.

SBSEND

Bit 0: Start bit (Master mode).

Allowed values:
0: NoStart: No Start condition
1: Start: Start condition generated

ADDSEND

Bit 1: Address sent (master mode)/matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

BTC

Bit 2: Byte transmission completed.

Allowed values:
0: NotFinished: Data byte transfer not done
1: Finished: Data byte transfer successful

ADD10SEND

Bit 3: Header of 10-bit address is sent in master mode.

Allowed values:
0: NoHeader: No header of 10-bit address is sent
1: Header: Header of 10-bit address is sent

STPDET

Bit 4: Stop detection (slave mode).

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

RBNE

Bit 6: I2C_DATA is not Empty during receiving.

Allowed values:
0: Empty: Data register empty
1: NotEmpty: Data register not empty, software can read

TBE

Bit 7: I2C_DATA is Empty during transmitting.

Allowed values:
0: NotEmpty: Data register not empty
1: Empty: Data register empty, software can write

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No misplaced Start or Stop condition
1: Error: Misplaced Start or Stop condition

LOSTARB

Bit 9: Arbitration lost (master mode).

Allowed values:
0: NoLost: No Arbitration Lost detected
1: Lost: Arbitration Lost detected

AERR

Bit 10: Acknowledge error.

Allowed values:
0: NoError: No acknowledge error
1: Error: Acknowledge error

OUERR

Bit 11: Overrun/Underrun occurs in slave mode.

Allowed values:
0: NoOverrun: No overrun/underrun occured
1: Overrun: Overrun/underrun occured

PECERR

Bit 12: PEC error when receiving data.

Allowed values:
0: NoError: No PEC error
1: Error: PEC error

SMBTO

Bit 14: Timeout signal in SMBus mode.

Allowed values:
0: NoTimeout: No Timeout error
1: Timeout: SCL remained low for 25 ms

SMBALT

Bit 15: SMBus alert.

Allowed values:
0: NoAlert: SMBA not pulled down or no alert occured
1: Alert: SMBA pulled down or alert occurred

STAT1

Transfer status register 1

Offset: 0x18, reset: 0x0000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PECV
r 		DUMODF
r 		HSTSMB
r 		DEFSMB
r 		RXGC
r 		TR
r 		I2CBSY
r 		MASTER
r
Toggle Fields.

MASTER

Bit 0: Master/slave.

Allowed values:
0: Slave: Slave mode
1: Master: Master mode

I2CBSY

Bit 1: Bus busy.

Allowed values:
0: NotBusy: No I2C communication
1: Busy: I2C communication active

TR

Bit 2: Transmitter/receiver.

Allowed values:
0: Receiver: Receiver
1: Transmitter: Transmitter

RXGC

Bit 4: General call address (Slave mode).

Allowed values:
0: NotReceived: No general call address received
1: Received: General call address received

DEFSMB

Bit 5: SMBus device default address (Slave mode).

Allowed values:
0: NotReceived: Default address has not been received
1: Received: Default address has been received

HSTSMB

Bit 6: SMBus host header (Slave mode).

Allowed values:
0: NoHeader: No SMBus host header detected
1: Header: SMBus host header detected

DUMODF

Bit 7: Dual flag (Slave mode).

Allowed values:
0: SADDR0: The address matches SADDR0
1: SADDR1: The address matches SADDR1

PECV

Bits 8-15: Packet error checking register.

Allowed values: 0-127

CKCFG

Clock configure register

Offset: 0x1C, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAST
rw 		DTCY
rw 		CLKC
rw
Toggle Fields.

CLKC

Bits 0-11: Clock control register in Fast/Standard mode (Master mode).

Allowed values: 0-4095

DTCY

Bit 14: Fast mode duty cycle.

Allowed values:
0: Duty2: Duty cycle t_low/t_high = 2
1: Duty16_9: Duty cycle t_low/t_high = 16/9

FAST

Bit 15: I2C master mode selection.

Allowed values:
0: Standard: Standard mode I2C
1: Fast: Fast mode I2C

RT

Rise time register

Offset: 0x20, reset: 0x0002, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RISETIME
rw
Toggle Fields.

RISETIME

Bits 0-6: Maximum rise time in master mode.

Allowed values: 0-127

SAMCS

SAM control and status register

Offset: 0x80, reset: 0x0000, access: read-write

6/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFR
rw 		RFF
rw 		TFR
rw 		TFF
rw 		RXF
rw 		TXF
rw 		RFRIE
rw 		RFFIE
rw 		TFRIE
rw 		TFFIE
rw 		STOEN
rw 		SAMEN
rw
Toggle Fields.

SAMEN

Bit 0: SAM_V interface enable.

Allowed values:
0: Disabled: SAM_V interface disabled
1: Enabled: SAM_V interface enabled

STOEN

Bit 1: SAM_V interface timeout detect enable.

Allowed values:
0: Disabled: SAM_V interface timeout detect disabled
1: Enabled: SAM_V interface timeout detect enabled

TFFIE

Bit 4: Tx frame fall interrupt enable.

Allowed values:
0: Disabled: Txframe fall interrupt disabled
1: Enabled: Txframe fall interrupt enabled

TFRIE

Bit 5: Tx frame rise interrupt enable.

Allowed values:
0: Disabled: Txframe rise interrupt disabled
1: Enabled: Txframe rise interrupt enabled

RFFIE

Bit 6: Rx frame fall interrupt enable.

Allowed values:
0: Disabled: Rxframe fall interrupt disabled
1: Enabled: Rxframe fall interrupt enabled

RFRIE

Bit 7: Rx frame rise interrupt enable.

Allowed values:
0: Disabled: Rxframe rise interrupt disabled
1: Enabled: Rxframe rise interrupt enabled

TXF

Bit 8: level of tx frame signal.

RXF

Bit 9: level of rx frame signal.

TFF

Bit 12: Txframe fall flag.

TFR

Bit 13: Txframe rise flag.

RFF

Bit 14: Rxframe fall flag.

RFR

Bit 15: Rxframe rise flag.

FMPCFG

Fast-mode-plus configure register

Offset: 0x90, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMPEN
rw
Toggle Fields.

FMPEN

Bit 0: Fast-mode-plus enable.

NVIC

0xE000E100: Nested Vectored Interrupt Controller

0/128 fields covered. Toggle Registers.

ISER0

Interrupt Set Enable Register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER1

Interrupt Set Enable Register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER2

Interrupt Set Enable Register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER3

Interrupt Set Enable Register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER4

Interrupt Set Enable Register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER5

Interrupt Set Enable Register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER6

Interrupt Set Enable Register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER7

Interrupt Set Enable Register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER8

Interrupt Set Enable Register

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER9

Interrupt Set Enable Register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER10

Interrupt Set Enable Register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER11

Interrupt Set Enable Register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER12

Interrupt Set Enable Register

Offset: 0x30, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER13

Interrupt Set Enable Register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER14

Interrupt Set Enable Register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER15

Interrupt Set Enable Register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ICER0

Interrupt Clear Enable Register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER1

Interrupt Clear Enable Register

Offset: 0x84, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER2

Interrupt Clear Enable Register

Offset: 0x8C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER3

Interrupt Clear Enable Register

Offset: 0x90, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER4

Interrupt Clear Enable Register

Offset: 0x94, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER5

Interrupt Clear Enable Register

Offset: 0x98, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER6

Interrupt Clear Enable Register

Offset: 0x9C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER7

Interrupt Clear Enable Register

Offset: 0xA0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER8

Interrupt Clear Enable Register

Offset: 0xA4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER9

Interrupt Clear Enable Register

Offset: 0xA8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER10

Interrupt Clear Enable Register

Offset: 0xAC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER11

Interrupt Clear Enable Register

Offset: 0xB0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER12

Interrupt Clear Enable Register

Offset: 0xB4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER13

Interrupt Clear Enable Register

Offset: 0xB8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER14

Interrupt Clear Enable Register

Offset: 0xBC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER15

Interrupt Clear Enable Register

Offset: 0xC0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ISPR0

Interrupt Set-Pending Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR1

Interrupt Set-Pending Register

Offset: 0x104, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR2

Interrupt Set-Pending Register

Offset: 0x108, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR3

Interrupt Set-Pending Register

Offset: 0x10C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR4

Interrupt Set-Pending Register

Offset: 0x110, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR5

Interrupt Set-Pending Register

Offset: 0x114, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR6

Interrupt Set-Pending Register

Offset: 0x118, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR7

Interrupt Set-Pending Register

Offset: 0x11C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR8

Interrupt Set-Pending Register

Offset: 0x120, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR9

Interrupt Set-Pending Register

Offset: 0x124, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR10

Interrupt Set-Pending Register

Offset: 0x128, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR11

Interrupt Set-Pending Register

Offset: 0x12C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR12

Interrupt Set-Pending Register

Offset: 0x130, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR13

Interrupt Set-Pending Register

Offset: 0x134, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR14

Interrupt Set-Pending Register

Offset: 0x138, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR15

Interrupt Set-Pending Register

Offset: 0x13C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ICPR0

Interrupt Clear-Pending Register

Offset: 0x180, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR1

Interrupt Clear-Pending Register

Offset: 0x184, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR2

Interrupt Clear-Pending Register

Offset: 0x188, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR3

Interrupt Clear-Pending Register

Offset: 0x18C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR4

Interrupt Clear-Pending Register

Offset: 0x190, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR5

Interrupt Clear-Pending Register

Offset: 0x194, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR6

Interrupt Clear-Pending Register

Offset: 0x198, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR7

Interrupt Clear-Pending Register

Offset: 0x19C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR8

Interrupt Clear-Pending Register

Offset: 0x1A0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR9

Interrupt Clear-Pending Register

Offset: 0x1A4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR10

Interrupt Clear-Pending Register

Offset: 0x1A8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR11

Interrupt Clear-Pending Register

Offset: 0x1AC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR12

Interrupt Clear-Pending Register

Offset: 0x1B0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR13

Interrupt Clear-Pending Register

Offset: 0x1B4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR14

Interrupt Clear-Pending Register

Offset: 0x1B8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR15

Interrupt Clear-Pending Register

Offset: 0x1BC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

IABR0

Interrupt Active bit Register

Offset: 0x200, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IABR
rw
Toggle Fields.

IABR

Bits 0-31: IABR.

IABR1

Interrupt Active bit Register

Offset: 0x204, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IABR
rw
Toggle Fields.

IABR

Bits 0-31: IABR.

IABR2

Interrupt Active bit Register

Offset: 0x208, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IABR
rw
Toggle Fields.

IABR

Bits 0-31: IABR.

IABR3

Interrupt Active bit Register

Offset: 0x20C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IABR
rw
Toggle Fields.

IABR

Bits 0-31: IABR.

IABR4

Interrupt Active bit Register

Offset: 0x210, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IABR
rw
Toggle Fields.

IABR

Bits 0-31: IABR.

IABR5

Interrupt Active bit Register

Offset: 0x214, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IABR
rw
Toggle Fields.

IABR

Bits 0-31: IABR.

IABR6

Interrupt Active bit Register

Offset: 0x218, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IABR
rw
Toggle Fields.

IABR

Bits 0-31: IABR.

IABR7

Interrupt Active bit Register

Offset: 0x21C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IABR
rw
Toggle Fields.

IABR

Bits 0-31: IABR.

IABR8

Interrupt Active bit Register

Offset: 0x220, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IABR
rw
Toggle Fields.

IABR

Bits 0-31: IABR.

IABR9

Interrupt Active bit Register

Offset: 0x224, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IABR
rw
Toggle Fields.

IABR

Bits 0-31: IABR.

IABR10

Interrupt Active bit Register

Offset: 0x228, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IABR
rw
Toggle Fields.

IABR

Bits 0-31: IABR.

IABR11

Interrupt Active bit Register

Offset: 0x22C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IABR
rw
Toggle Fields.

IABR

Bits 0-31: IABR.

IABR12

Interrupt Active bit Register

Offset: 0x230, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IABR
rw
Toggle Fields.

IABR

Bits 0-31: IABR.

IABR13

Interrupt Active bit Register

Offset: 0x234, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IABR
rw
Toggle Fields.

IABR

Bits 0-31: IABR.

IABR14

Interrupt Active bit Register

Offset: 0x238, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IABR
rw
Toggle Fields.

IABR

Bits 0-31: IABR.

IABR15

Interrupt Active bit Register

Offset: 0x23C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IABR
rw
Toggle Fields.

IABR

Bits 0-31: IABR.

ITNS0

Interrupt Active bit Register

Offset: 0x280, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITNS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITNS
rw
Toggle Fields.

ITNS

Bits 0-31: ITNS.

ITNS1

Interrupt Active bit Register

Offset: 0x284, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITNS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITNS
rw
Toggle Fields.

ITNS

Bits 0-31: ITNS.

ITNS2

Interrupt Active bit Register

Offset: 0x288, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITNS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITNS
rw
Toggle Fields.

ITNS

Bits 0-31: ITNS.

ITNS3

Interrupt Active bit Register

Offset: 0x28C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITNS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITNS
rw
Toggle Fields.

ITNS

Bits 0-31: ITNS.

ITNS4

Interrupt Active bit Register

Offset: 0x290, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITNS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITNS
rw
Toggle Fields.

ITNS

Bits 0-31: ITNS.

ITNS5

Interrupt Active bit Register

Offset: 0x294, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITNS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITNS
rw
Toggle Fields.

ITNS

Bits 0-31: ITNS.

ITNS6

Interrupt Active bit Register

Offset: 0x298, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITNS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITNS
rw
Toggle Fields.

ITNS

Bits 0-31: ITNS.

ITNS7

Interrupt Active bit Register

Offset: 0x29C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITNS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITNS
rw
Toggle Fields.

ITNS

Bits 0-31: ITNS.

ITNS8

Interrupt Active bit Register

Offset: 0x2A0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITNS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITNS
rw
Toggle Fields.

ITNS

Bits 0-31: ITNS.

ITNS9

Interrupt Active bit Register

Offset: 0x2A4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITNS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITNS
rw
Toggle Fields.

ITNS

Bits 0-31: ITNS.

ITNS10

Interrupt Active bit Register

Offset: 0x2A8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITNS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITNS
rw
Toggle Fields.

ITNS

Bits 0-31: ITNS.

ITNS11

Interrupt Active bit Register

Offset: 0x2AC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITNS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITNS
rw
Toggle Fields.

ITNS

Bits 0-31: ITNS.

ITNS12

Interrupt Active bit Register

Offset: 0x2B0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITNS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITNS
rw
Toggle Fields.

ITNS

Bits 0-31: ITNS.

ITNS13

Interrupt Active bit Register

Offset: 0x2B4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITNS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITNS
rw
Toggle Fields.

ITNS

Bits 0-31: ITNS.

ITNS14

Interrupt Active bit Register

Offset: 0x2B8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITNS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITNS
rw
Toggle Fields.

ITNS

Bits 0-31: ITNS.

ITNS15

Interrupt Active bit Register

Offset: 0x2BC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITNS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITNS
rw
Toggle Fields.

ITNS

Bits 0-31: ITNS.

IPR0

Interrupt Priority Register 0

Offset: 0x300, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_00
rw
Toggle Fields.

PRI_00

Bits 0-7: PRI_00.

IPR1

Interrupt Priority Register 1

Offset: 0x301, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_01
rw
Toggle Fields.

PRI_01

Bits 0-7: PRI_01.

IPR2

Interrupt Priority Register 2

Offset: 0x302, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_02
rw
Toggle Fields.

PRI_02

Bits 0-7: PRI_02.

IPR3

Interrupt Priority Register 3

Offset: 0x303, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_03
rw
Toggle Fields.

PRI_03

Bits 0-7: PRI_03.

IPR4

Interrupt Priority Register 4

Offset: 0x304, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_04
rw
Toggle Fields.

PRI_04

Bits 0-7: PRI_04.

IPR5

Interrupt Priority Register 5

Offset: 0x305, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_05
rw
Toggle Fields.

PRI_05

Bits 0-7: PRI_05.

IPR6

Interrupt Priority Register 6

Offset: 0x306, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_06
rw
Toggle Fields.

PRI_06

Bits 0-7: PRI_06.

IPR7

Interrupt Priority Register 7

Offset: 0x307, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_07
rw
Toggle Fields.

PRI_07

Bits 0-7: PRI_07.

IPR8

Interrupt Priority Register 8

Offset: 0x308, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_08
rw
Toggle Fields.

PRI_08

Bits 0-7: PRI_08.

IPR9

Interrupt Priority Register 9

Offset: 0x309, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_09
rw
Toggle Fields.

PRI_09

Bits 0-7: PRI_09.

IPR10

Interrupt Priority Register 10

Offset: 0x30A, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_10
rw
Toggle Fields.

PRI_10

Bits 0-7: PRI_10.

IPR11

Interrupt Priority Register 11

Offset: 0x30B, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_11
rw
Toggle Fields.

PRI_11

Bits 0-7: PRI_11.

IPR12

Interrupt Priority Register 12

Offset: 0x30C, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_12
rw
Toggle Fields.

PRI_12

Bits 0-7: PRI_12.

IPR13

Interrupt Priority Register 13

Offset: 0x30D, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_13
rw
Toggle Fields.

PRI_13

Bits 0-7: PRI_13.

IPR14

Interrupt Priority Register 14

Offset: 0x30E, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_14
rw
Toggle Fields.

PRI_14

Bits 0-7: PRI_14.

IPR15

Interrupt Priority Register 15

Offset: 0x30F, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_15
rw
Toggle Fields.

PRI_15

Bits 0-7: PRI_15.

IPR16

Interrupt Priority Register 16

Offset: 0x310, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_16
rw
Toggle Fields.

PRI_16

Bits 0-7: PRI_16.

IPR17

Interrupt Priority Register 17

Offset: 0x311, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_17
rw
Toggle Fields.

PRI_17

Bits 0-7: PRI_17.

IPR18

Interrupt Priority Register 18

Offset: 0x312, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_18
rw
Toggle Fields.

PRI_18

Bits 0-7: PRI_18.

IPR19

Interrupt Priority Register 19

Offset: 0x313, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_19
rw
Toggle Fields.

PRI_19

Bits 0-7: PRI_19.

IPR20

Interrupt Priority Register 20

Offset: 0x314, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_20
rw
Toggle Fields.

PRI_20

Bits 0-7: PRI_20.

IPR21

Interrupt Priority Register 21

Offset: 0x315, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_21
rw
Toggle Fields.

PRI_21

Bits 0-7: PRI_21.

IPR22

Interrupt Priority Register 22

Offset: 0x316, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_22
rw
Toggle Fields.

PRI_22

Bits 0-7: PRI_22.

IPR23

Interrupt Priority Register 23

Offset: 0x317, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_23
rw
Toggle Fields.

PRI_23

Bits 0-7: PRI_23.

IPR24

Interrupt Priority Register 24

Offset: 0x318, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_24
rw
Toggle Fields.

PRI_24

Bits 0-7: PRI_24.

IPR25

Interrupt Priority Register 25

Offset: 0x319, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_25
rw
Toggle Fields.

PRI_25

Bits 0-7: PRI_25.

IPR26

Interrupt Priority Register 26

Offset: 0x31A, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_26
rw
Toggle Fields.

PRI_26

Bits 0-7: PRI_26.

IPR27

Interrupt Priority Register 27

Offset: 0x31B, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_27
rw
Toggle Fields.

PRI_27

Bits 0-7: PRI_27.

IPR28

Interrupt Priority Register 28

Offset: 0x31C, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_28
rw
Toggle Fields.

PRI_28

Bits 0-7: PRI_28.

IPR29

Interrupt Priority Register 29

Offset: 0x31D, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_29
rw
Toggle Fields.

PRI_29

Bits 0-7: PRI_29.

IPR30

Interrupt Priority Register 30

Offset: 0x31E, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_30
rw
Toggle Fields.

PRI_30

Bits 0-7: PRI_30.

IPR31

Interrupt Priority Register 31

Offset: 0x31F, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_31
rw
Toggle Fields.

PRI_31

Bits 0-7: PRI_31.

PMU

0x40007000: Power management unit

11/14 fields covered. Toggle Registers.

CTL

power control register

Offset: 0x0, reset: 0x00004000, access: read-write

7/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDOVS
rw 		BKPWEN
rw 		LVDT
rw 		LVDEN
rw 		STBRST
rw 		WURST
rw 		STBMOD
rw 		LDOLP
rw
Toggle Fields.

LDOLP

Bit 0: LDO Low Power Mode.

Allowed values:
0: Normal: LDO operates normally during Deepsleep mode
1: LowPower: LDO in low-power mode during Deepsleep mode

STBMOD

Bit 1: Standby Mode.

Allowed values:
0: DeepSleep: Enter Deep-sleep mode when the CPU enters deepsleep
1: Standby: Enter Standby mode when the CPU enters deepsleep

WURST

Bit 2: Wakeup Flag Reset.

Allowed values:
1: Clear: Clear the wakeup flag

STBRST

Bit 3: Standby Flag Reset.

Allowed values:
1: Clear: Clear the standby flag

LVDEN

Bit 4: Low Voltage Detector Enable.

Allowed values:
0: Disabled: Low voltage detector disabled
1: Enabled: Low voltage detector enabled

LVDT

Bits 5-7: Low Voltage Detector Threshold.

Allowed values:
0: V2_2: 2.2 V
1: V2_3: 2.3 V
2: V2_4: 2.4 V
3: V2_5: 2.5 V
4: V2_6: 2.6 V
5: V2_7: 2.7 V
6: V2_8: 2.8 V
7: V2_9: 2.9 V

BKPWEN

Bit 8: Backup Domain Write Enable.

Allowed values:
0: Disabled: Access to backup domain registers disabled
1: Enabled: Access to backup domain registers enabled

LDOVS

Bits 14-15: LDO output voltage select.

CS

power control/status register

Offset: 0x4, reset: 0x00000000, access: Unspecified

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUPEN6
rw 		WUPEN5
rw 		WUPEN0
rw 		LVDF
r 		STBF
r 		WUF
r
Toggle Fields.

WUF

Bit 0: Wakeup flag.

Allowed values:
0: NoWakeupEvent: No wakeup event occurred
1: WakeupEvent: A wakeup event was received from the WKUP pin or from the RTC wakeup event (RTC Tamper event, RTC TimeStamp event or RTC alarm)

STBF

Bit 1: Standby flag.

Allowed values:
0: NoStandbyEvent: Device has not been in Standby mode
1: StandbyEvent: Device has been in Standby mode

LVDF

Bit 2: Low Voltage Detector Status Flag.

Allowed values:
0: AboveThreshold: VDD is higher than the LVD threshold
1: BelowThreshold: VDD is lower than or equal to the LVD threshold

WUPEN0

Bit 8: WKUP pin0 Enable.

Allowed values:
0: Disabled: WKUP pin 0 is used for general purpose I/Os. An event on the WKUP pin 0 does not wakeup the device from Standby mode
1: Enabled: WKUP pin 0 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 0 wakes-up the system from Standby mode)

WUPEN5

Bit 13: WKUP pin5 Enable.

WUPEN6

Bit 14: WKUP pin6 Enable.

RCU

0x40021000: Reset and clock unit

116/119 fields covered. Toggle Registers.

CTL0

Control register 0

Offset: 0x0, reset: 0x00000083, access: Unspecified

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSTB
r 		PLLEN
rw 		CKMEN
rw 		HXTALBPS
rw 		HXTALSTB
r 		HXTALEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRC8MCALIB
r 		IRC8MADJ
rw 		IRC8MSTB
r 		IRC8MEN
rw
Toggle Fields.

IRC8MEN

Bit 0: Internal High Speed oscillator Enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

IRC8MSTB

Bit 1: IRC8M High Speed Internal Oscillator stabilization Flag.

Allowed values:
0: NotReady: IRC8M is not stable
1: Ready: IRC8M is stable

IRC8MADJ

Bits 3-7: High Speed Internal Oscillator clock trim adjust value.

Allowed values: 0-31

IRC8MCALIB

Bits 8-15: High Speed Internal Oscillator calibration value register.

Allowed values: 0-255

HXTALEN

Bit 16: External High Speed oscillator Enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

HXTALSTB

Bit 17: External crystal oscillator (HXTAL) clock stabilization flag.

Allowed values:
0: NotReady: HXTAL is not stable
1: Ready: HXTAL is stable

HXTALBPS

Bit 18: External crystal oscillator (HXTAL) clock bypass mode enable.

Allowed values:
0: NotBypassed: HXTAL crystal oscillator not bypassed
1: Bypassed: HXTAL crystal oscillator bypassed with external clock

CKMEN

Bit 19: HXTAL Clock Monitor Enable.

Allowed values:
0: Off: Clock monitor disabled
1: On: Clock monitor enabled

PLLEN

Bit 24: PLL enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

PLLSTB

Bit 25: PLL Clock Stabilization Flag.

Allowed values:
0: NotReady: PLL is not stable
1: Ready: PLL is stable

CFG0

Clock configuration register 0 (RCU_CFG0)

Offset: 0x4, reset: 0x00000000, access: Unspecified

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLDV
rw 		CKOUTDIV
rw 		PLLMF_MSB
rw 		CKOUTSEL
rw 		PLLMF
rw 		PLLPREDV
rw 		PLLSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCPSC
rw 		APB2PSC
rw 		APB1PSC
rw 		AHBPSC
rw 		SCSS
r 		SCS
rw
Toggle Fields.

SCS

Bits 0-1: System clock switch.

Allowed values:
0: IRC8M: IRC8M used as system clock
1: HXTAL: HXTAL used as system clock
2: PLL: PLL used as system clock

SCSS

Bits 2-3: System clock switch status.

Allowed values:
0: IRC8M: IRC8M used as system clock
1: HXTAL: HXTAL used as system clock
2: PLL: PLL used as system clock

AHBPSC

Bits 4-7: AHB prescaler selection.

Allowed values:
0: Div1: CK_SYS
8: Div2: CK_SYS divided by 2
9: Div4: CK_SYS divided by 4
10: Div8: CK_SYS divided by 8
11: Div16: CK_SYS divided by 16
12: Div64: CK_SYS divided by 64
13: Div128: CK_SYS divided by 128
14: Div256: CK_SYS divided by 256
15: Div512: CK_SYS divided by 512

APB1PSC

Bits 8-10: APB1 prescaler selection.

Allowed values:
0: Div1: CK_AHB
4: Div2: CK_AHB divided by 2
5: Div4: CK_AHB divided by 4
6: Div8: CK_AHB divided by 8
7: Div16: CK_AHB divided by 16

APB2PSC

Bits 11-13: APB2 prescaler selection.

Allowed values:
0: Div1: CK_AHB
4: Div2: CK_AHB divided by 2
5: Div4: CK_AHB divided by 4
6: Div8: CK_AHB divided by 8
7: Div16: CK_AHB divided by 16

ADCPSC

Bits 14-15: ADC clock prescaler selection.

Allowed values:
0: Div2: CK_APB2 divided by 2
1: Div4: CK_APB2 divided by 4
2: Div6: CK_APB2 divided by 6
3: Div8: CK_APB2 divided by 8

PLLSEL

Bit 16: PLL Clock Source Selection.

Allowed values:
0: IRC8M_2: IRC8M / 2 selected as PLL source clock
1: HXTAL: HXTAL selected as PLL source clock

PLLPREDV

Bit 17: HXTAL divider for PLL source clock selection..

Allowed values:
0: Div1: HXTAL clock not divided
1: Div2: HXTAL clock divided by 2

PLLMF

Bits 18-21: PLL multiply factor.

Allowed values:
0: Mul2: PLL input clock x2
1: Mul3: PLL input clock x3
2: Mul4: PLL input clock x4
3: Mul5: PLL input clock x5
4: Mul6: PLL input clock x6
5: Mul7: PLL input clock x7
6: Mul8: PLL input clock x8
7: Mul9: PLL input clock x9
8: Mul10: PLL input clock x10
9: Mul11: PLL input clock x11
10: Mul12: PLL input clock x12
11: Mul13: PLL input clock x13
12: Mul14: PLL input clock x14
13: Mul15: PLL input clock x15
14: Mul16: PLL input clock x16
15: Mul16x: PLL input clock x16

CKOUTSEL

Bits 24-26: CK_OUT Clock Source Selection.

Allowed values:
0: None: No clock selected
1: IRC14M: Internal 14 MHz RC oscillator clock selected
2: LSI40K: Internal 40 kHz RC oscillator clock selected
3: LXTAL: External low speed oscillator clock selected
4: SYSCLK: System clock selected
5: IRC8M: Internal RC 8 MHz (HSI) oscillator clock selected
6: HXTAL: External 4-32 MHz (HSE) oscillator clock selected
7: PLL: PLL clock selected (divided by 1 or 2, depending on PLLDV)

PLLMF_MSB

Bit 27: Bit 4 of PLLMF register.

Allowed values:
0: None: Value of PLLMF is as set
1: Plus15: Add 15 to the value of PLLMF

CKOUTDIV

Bits 28-30: The CK_OUT divider which the CK_OUT frequency can be reduced.

Allowed values:
0: Div1: CK_OUT is divided by 1
1: Div2: CK_OUT is divided by 2
2: Div4: CK_OUT is divided by 4
3: Div8: CK_OUT is divided by 8
4: Div16: CK_OUT is divided by 16
5: Div32: CK_OUT is divided by 32
6: Div64: CK_OUT is divided by 64
7: Div128: CK_OUT is divided by 128

PLLDV

Bit 31: The CK_PLL divide by 1 or 2 for CK_OUT .

Allowed values:
0: Div2: PLL is divided by 2 for CK_OUT
1: Div1: PLL is not divided for CK_OUT

INT

Clock interrupt register (RCU_INT)

Offset: 0x8, reset: 0x00000000, access: Unspecified

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKMIC
w 		IRC28MSTBIC
w 		PLLSTBIC
w 		HXTALSTBIC
w 		IRC8MSTBIC
w 		LXTALSTBIC
w 		IRC40KSTBIC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRC28MSTBIE
rw 		PLLSTBIE
rw 		HXTALSTBIE
rw 		IRC8MSTBIE
rw 		LXTALSTBIE
rw 		IRC40KSTBIE
rw 		CKMIF
r 		IRC28MSTBIF
r 		PLLSTBIF
r 		HXTALSTBIF
r 		IRC8MSTBIF
r 		LXTALSTBIF
r 		IRC40KSTBIF
r
Toggle Fields.

IRC40KSTBIF

Bit 0: IRC40K stabilization interrupt flag.

Allowed values:
0: NotInterrupted: No interrupt generated
1: Interrupted: IRC40K stabilisation interrupt generated

LXTALSTBIF

Bit 1: LXTAL stabilization interrupt flag.

Allowed values:
0: NotInterrupted: No interrupt generated
1: Interrupted: LXTAL stabilisation interrupt generated

IRC8MSTBIF

Bit 2: IRC8M stabilization interrupt flag.

Allowed values:
0: NotInterrupted: No interrupt generated
1: Interrupted: IRC8M stabilisation interrupt generated

HXTALSTBIF

Bit 3: HXTAL stabilization interrupt flag.

Allowed values:
0: NotInterrupted: No interrupt generated
1: Interrupted: HXTAL stabilisation interrupt generated

PLLSTBIF

Bit 4: PLL stabilization interrupt flag.

Allowed values:
0: NotInterrupted: No interrupt generated
1: Interrupted: PLL stabilisation interrupt generated

IRC28MSTBIF

Bit 5: IRC28M stabilization interrupt flag.

Allowed values:
0: NotInterrupted: No interrupt generated
1: Interrupted: IRC14M stabilisation interrupt generated

CKMIF

Bit 7: HXTAL Clock Stuck Interrupt Flag.

Allowed values:
0: NotInterrupted: Clock operating normally
1: Interrupted: HXTAL clock stuck

IRC40KSTBIE

Bit 8: IRC40K Stabilization interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

LXTALSTBIE

Bit 9: LXTAL Stabilization Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

IRC8MSTBIE

Bit 10: IRC8M Stabilization Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HXTALSTBIE

Bit 11: HXTAL Stabilization Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

PLLSTBIE

Bit 12: PLL Stabilization Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

IRC28MSTBIE

Bit 13: IRC28M Stabilization Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

IRC40KSTBIC

Bit 16: IRC40K Stabilization Interrupt Clear.

Allowed values:
1: Clear: Clear IRC40KSTBIF flag

LXTALSTBIC

Bit 17: LXTAL Stabilization Interrupt Clear.

Allowed values:
1: Clear: Clear LXTALSTBIF flag

IRC8MSTBIC

Bit 18: IRC8M Stabilization Interrupt Clear.

Allowed values:
1: Clear: Clear IRC8MSTBIF flag

HXTALSTBIC

Bit 19: HXTAL Stabilization Interrupt Clear.

Allowed values:
1: Clear: Clear HXTALSTBIF flag

PLLSTBIC

Bit 20: PLL stabilization Interrupt Clear.

Allowed values:
1: Clear: Clear PLLSTBIF flag

IRC28MSTBIC

Bit 21: IRC28M stabilization Interrupt Clear.

Allowed values:
1: Clear: Clear IRC28MSTBIF flag

CKMIC

Bit 23: HXTAL Clock Stuck Interrupt Clear.

Allowed values:
1: Clear: Clear CKMIF flag

APB2RST

APB2 reset register (RCU_APB2RST)

Offset: 0xC, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIMER16RST
rw 		TIMER15RST
rw 		TIMER14RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART0RST
rw 		SPI0RST
rw 		TIMER0RST
rw 		ADCRST
rw 		CFGCMPRST
rw
Toggle Fields.

CFGCMPRST

Bit 0: System configuration and comparator reset.

Allowed values:
1: Reset: Reset the selected module

ADCRST

Bit 9: ADC reset.

Allowed values:
1: Reset: Reset the selected module

TIMER0RST

Bit 11: TIMER0 reset.

Allowed values:
1: Reset: Reset the selected module

SPI0RST

Bit 12: SPI0 Reset.

Allowed values:
1: Reset: Reset the selected module

USART0RST

Bit 14: USART0 Reset.

Allowed values:
1: Reset: Reset the selected module

TIMER14RST

Bit 16: TIMER14 reset.

Allowed values:
1: Reset: Reset the selected module

TIMER15RST

Bit 17: TIMER15 reset.

Allowed values:
1: Reset: Reset the selected module

TIMER16RST

Bit 18: TIMER16 reset.

Allowed values:
1: Reset: Reset the selected module

APB1RST

APB1 reset register (RCU_APB1RST)

Offset: 0x10, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PMURST
rw 		I2C1RST
rw 		I2C0RST
rw 		USART1RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI1RST
rw 		WWDGTRST
rw 		TIMER13RST
rw 		TIMER5RST
rw 		TIMER2RST
rw
Toggle Fields.

TIMER2RST

Bit 1: TIMER2 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIMER5RST

Bit 4: TIMER5 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIMER13RST

Bit 8: TIMER13 timer reset.

Allowed values:
1: Reset: Reset the selected module

WWDGTRST

Bit 11: Window watchdog timer reset.

Allowed values:
1: Reset: Reset the selected module

SPI1RST

Bit 14: SPI1 reset.

Allowed values:
1: Reset: Reset the selected module

USART1RST

Bit 17: USART1 reset.

Allowed values:
1: Reset: Reset the selected module

I2C0RST

Bit 21: I2C0 reset.

Allowed values:
1: Reset: Reset the selected module

I2C1RST

Bit 22: I2C1 reset.

Allowed values:
1: Reset: Reset the selected module

PMURST

Bit 28: Power control reset.

Allowed values:
1: Reset: Reset the selected module

AHBEN

AHB enable register (RCU_AHBEN)

Offset: 0x14, reset: 0x00000014, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PFEN
rw 		PCEN
rw 		PBEN
rw 		PAEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCEN
rw 		FMCSPEN
rw 		SRAMSPEN
rw 		DMAEN
rw
Toggle Fields.

DMAEN

Bit 0: DMA clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SRAMSPEN

Bit 2: SRAM interface clock during sleep mode enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

FMCSPEN

Bit 4: FMC clock during sleep mode enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CRCEN

Bit 6: CRC clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PAEN

Bit 17: GPIO port A clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PBEN

Bit 18: GPIO port B clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PCEN

Bit 19: GPIO port C clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PFEN

Bit 22: GPIO port F clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB2EN

APB2 enable register (RCU_APB2EN)

Offset: 0x18, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBGMCUEN
rw 		TIMER16EN
rw 		TIMER15EN
rw 		TIMER14EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART0EN
rw 		SPI0EN
rw 		TIMER0EN
rw 		ADCEN
rw 		CFGCMPEN
rw
Toggle Fields.

CFGCMPEN

Bit 0: System configuration and comparator clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ADCEN

Bit 9: ADC interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIMER0EN

Bit 11: TIMER0 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI0EN

Bit 12: SPI0 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART0EN

Bit 14: USART0 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIMER14EN

Bit 16: TIMER14 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIMER15EN

Bit 17: TIMER15 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIMER16EN

Bit 18: TIMER16 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DBGMCUEN

Bit 22: DBGMCU clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB1EN

APB1 enable register (RCU_APB1EN)

Offset: 0x1C, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PMUEN
rw 		I2C1EN
rw 		I2C0EN
rw 		USART1EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI1EN
rw 		WWDGTEN
rw 		TIMER13EN
rw 		TIMER5EN
rw 		TIMER2EN
rw
Toggle Fields.

TIMER2EN

Bit 1: TIMER2 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIMER5EN

Bit 4: TIMER5 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIMER13EN

Bit 8: TIMER13 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

WWDGTEN

Bit 11: Window watchdog timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI1EN

Bit 14: SPI1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART1EN

Bit 17: USART1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C0EN

Bit 21: I2C0 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C1EN

Bit 22: I2C1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PMUEN

Bit 28: Power interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

BDCTL

Backup domain control register (RCU_BDCTL)

Offset: 0x20, reset: 0x00000018, access: Unspecified

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKPRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCEN
rw 		RTCSRC
rw 		LXTALDRI
rw 		LXTALBPS
rw 		LXTALSTB
r 		LXTALEN
rw
Toggle Fields.

LXTALEN

Bit 0: LXTAL enable.

Allowed values:
0: Off: LXTAL oscillator Off
1: On: LXTAL oscillator On

LXTALSTB

Bit 1: External low-speed oscillator stabilization.

Allowed values:
0: NotReady: LXTAL oscillator not ready
1: Ready: LXTAL oscillator ready

LXTALBPS

Bit 2: LXTAL bypass mode enable.

Allowed values:
0: NotBypassed: LXTAL crystal oscillator not bypassed
1: Bypassed: LXTAL crystal oscillator bypassed with external clock

LXTALDRI

Bits 3-4: LXTAL drive capability.

Allowed values:
0: Low: Low driving capability
1: MediumLow: Medium low driving capability
2: MediumHigh: Medium high driving capability
3: High: High driving capability (reset value)

RTCSRC

Bits 8-9: RTC clock entry selection.

Allowed values:
0: NoClock: No clock
1: LXTAL: LXTAL oscillator clock used as RTC clock
2: IRC40K: IRC40K oscillator clock used as RTC clock
3: HXTAL: HXTAL oscillator / 32 used as RTC clock

RTCEN

Bit 15: RTC clock enable.

Allowed values:
0: Disabled: RTC clock disabled
1: Enabled: RTC clock enabled

BKPRST

Bit 16: Backup domain reset.

Allowed values:
0: NoReset: Reset not activated
1: Reset: Reset the entire RTC domain

RSTSCK

Reset source /clock register (RCU_RSTSCK)

Offset: 0x24, reset: 0x0C000000, access: Unspecified

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPRSTF
rw 		WWDGTRSTF
rw 		FWDGTRSTF
rw 		SWRSTF
rw 		PORRSTF
rw 		EPRSTF
rw 		OBLRSTF
rw 		RSTFC
rw 		V12RSTF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRC40KSTB
r 		IRC40KEN
rw
Toggle Fields.

IRC40KEN

Bit 0: IRC40K enable.

Allowed values:
0: Off: IRC40K oscillator disabled
1: On: IRC40K oscillator enabled

IRC40KSTB

Bit 1: IRC40K stabilization.

Allowed values:
0: NotReady: IRC40K oscillator is not stable
1: Ready: IRC40K oscillator is stable

V12RSTF

Bit 23: V12 domain Power reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

RSTFC

Bit 24: Reset flag clear.

Allowed values:
1: Clear: Clears reset flags

OBLRSTF

Bit 25: Option byte loader reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

EPRSTF

Bit 26: External PIN reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

PORRSTF

Bit 27: Power reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

SWRSTF

Bit 28: Software reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

FWDGTRSTF

Bit 29: Free Watchdog timer reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

WWDGTRSTF

Bit 30: Window watchdog timer reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

LPRSTF

Bit 31: Low-power reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

AHBRST

AHB reset register

Offset: 0x28, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PFRST
rw 		PCRST
rw 		PBRST
rw 		PARST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PARST

Bit 17: GPIO port A reset.

Allowed values:
1: Reset: Reset the selected module

PBRST

Bit 18: GPIO port B reset.

Allowed values:
1: Reset: Reset the selected module

PCRST

Bit 19: GPIO port C reset.

Allowed values:
1: Reset: Reset the selected module

PFRST

Bit 22: GPIO port F reset.

Allowed values:
1: Reset: Reset the selected module

CFG1

Configuration register 1

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HXTALPREDV
rw
Toggle Fields.

HXTALPREDV

Bits 0-3: CK_HXTAL or CK_IRC48M divider previous PLL.

Allowed values:
0: Div1: HXTAL input to PLL not divided
1: Div2: HXTAL input to PLL divided by 2
2: Div3: HXTAL input to PLL divided by 3
3: Div4: HXTAL input to PLL divided by 4
4: Div5: HXTAL input to PLL divided by 5
5: Div6: HXTAL input to PLL divided by 6
6: Div7: HXTAL input to PLL divided by 7
7: Div8: HXTAL input to PLL divided by 8
8: Div9: HXTAL input to PLL divided by 9
9: Div10: HXTAL input to PLL divided by 10
10: Div11: HXTAL input to PLL divided by 11
11: Div12: HXTAL input to PLL divided by 12
12: Div13: HXTAL input to PLL divided by 13
13: Div14: HXTAL input to PLL divided by 14
14: Div15: HXTAL input to PLL divided by 15
15: Div16: HXTAL input to PLL divided by 16

CFG2

Configuration register 2

Offset: 0x30, reset: 0x00000000, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCPSC
rw 		IRC28MDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCSEL
rw 		USART0SEL
rw
Toggle Fields.

USART0SEL

Bits 0-1: CK_USART0 clock source selection.

Allowed values:
0: APB2: APB2 selected as USART0 clock source
1: SYS: SYS selected as USART0 clock source
2: LXTAL: LXTAL selected as USART0 clock source
3: IRC8M: IRC8M selected as USART0 clock source

ADCSEL

Bit 8: CK_ADC clock source selection.

IRC28MDIV

Bit 16: CK_IRC28M divider 2 or not.

ADCPSC

Bit 31: Bit 2 of ADCPSC.

CTL1

Control register 1

Offset: 0x34, reset: 0x00000080, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRC28MCALIB
r 		IRC28MADJ
rw 		IRC28MSTB
r 		IRC28MEN
rw
Toggle Fields.

IRC28MEN

Bit 0: IRC28M Internal 28M RC oscillator Enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

IRC28MSTB

Bit 1: IRC28M Internal 28M RC Oscillator stabilization Flag.

Allowed values:
0: NotReady: IRC14M is not stable
1: Ready: IRC14M is stable

IRC28MADJ

Bits 3-7: Internal 28M RC Oscillator clock trim adjust value.

Allowed values: 0-31

IRC28MCALIB

Bits 8-15: Internal 28M RC Oscillator calibration value register.

Allowed values: 0-255

VKEY

Voltage key register

Offset: 0x100, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-31: The key of RCU_DSV register.

Allowed values:
439041101: Enable: Allow PDVSEL and DSV to be written

DSV

Deep-sleep mode voltage register

Offset: 0x134, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSLPVS
rw
Toggle Fields.

DSLPVS

Bits 0-1: Deep-sleep mode voltage select.

Allowed values:
0: V1_0: The core voltage is 1.0 V in deep-sleep mode
1: V0_9: The core voltage is 0.9 V in deep-sleep mode
2: V0_8: The core voltage is 0.8 V in deep-sleep mode
3: V1_2: The core voltage is 1.2 V in deep-sleep mode

RTC

0x40002800: Real-time clock

19/86 fields covered. Toggle Registers.

TIME

time register

Offset: 0x0, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw 		HRT
rw 		HRU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw 		MNU
rw 		SCT
rw 		SCU
rw
Toggle Fields.

SCU

Bits 0-3: Second units in BCD code.

SCT

Bits 4-6: Second tens in BCD code.

MNU

Bits 8-11: Minute units in BCD code.

MNT

Bits 12-14: Minute tens in BCD code.

HRU

Bits 16-19: Hour units in BCD format.

HRT

Bits 20-21: Hour tens in BCD code.

PM

Bit 22: AM/PM mark.

DATE

date register

Offset: 0x4, reset: 0x00002101, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YRT
rw 		YRU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOW
rw 		MONT
rw 		MONU
rw 		DAYT
rw 		DAYU
rw
Toggle Fields.

DAYU

Bits 0-3: Date units in BCD code.

DAYT

Bits 4-5: Date tens in BCD code.

MONU

Bits 8-11: Month units in BCD code.

MONT

Bit 12: Month tens in BCD code.

DOW

Bits 13-15: Days of the week.

YRU

Bits 16-19: Year units in BCD code.

YRT

Bits 20-23: Year tens in BCD code.

CTL

control register

Offset: 0x8, reset: 0x00000000, access: Unspecified

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSM
rw 		S1H
w 		A1H
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALRM0IE
rw 		ALRM0EN
rw 		CS
rw 		BPSHAD
rw 		REFEN
rw
Toggle Fields.

REFEN

Bit 4: RTC_REFIN reference clock detection enable (50 or 60 Hz).

BPSHAD

Bit 5: Bypass the shadow registers.

CS

Bit 6: Hour format.

ALRM0EN

Bit 8: Alarm A enable.

ALRM0IE

Bit 12: Alarm A interrupt enable.

A1H

Bit 16: Add 1 hour (summer time change).

S1H

Bit 17: Subtract 1 hour (winter time change).

DSM

Bit 18: Backup.

STAT

initialization and status register

Offset: 0xC, reset: 0x00000007, access: Unspecified

5/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCPF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TP1F
rw 		ALRM0F
rw 		INITM
rw 		INITF
r 		RSYNF
rw 		YCM
r 		SOPF
r 		ALRM0WF
r
Toggle Fields.

ALRM0WF

Bit 0: Alarm A write flag.

SOPF

Bit 3: Shift operation pending.

YCM

Bit 4: Initialization status flag.

RSYNF

Bit 5: Registers synchronization flag.

INITF

Bit 6: Initialization flag.

INITM

Bit 7: Initialization mode.

ALRM0F

Bit 8: Alarm A flag.

TP1F

Bit 14: RTC_TAMP1 detection flag.

SCPF

Bit 16: Recalibration pending Flag.

PSC

prescaler register

Offset: 0x10, reset: 0x007F00FF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FACTOR_A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FACTOR_S
rw
Toggle Fields.

FACTOR_S

Bits 0-14: Synchronous prescaler factor.

FACTOR_A

Bits 16-22: Asynchronous prescaler factor.

ALRM0TD

alarm A register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSKD
rw 		DOWS
rw 		DAYT
rw 		DAYU
rw 		MSKH
rw 		PM
rw 		HRT
rw 		HRU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSKM
rw 		MNT
rw 		MNU
rw 		MSKS
rw 		SCT
rw 		SCU
rw
Toggle Fields.

SCU

Bits 0-3: Second units in BCD format..

SCT

Bits 4-6: Second tens in BCD format..

MSKS

Bit 7: Alarm seconds mask.

MNU

Bits 8-11: Minute units in BCD format..

MNT

Bits 12-14: Minute tens in BCD format..

MSKM

Bit 15: Alarm minutes mask.

HRU

Bits 16-19: Hour units in BCD format..

HRT

Bits 20-21: Hour tens in BCD format..

PM

Bit 22: AM/PM notation.

MSKH

Bit 23: Alarm hours mask.

DAYU

Bits 24-27: Date units or day in BCD format..

DAYT

Bits 28-29: Date tens in BCD format..

DOWS

Bit 30: Week day selection.

MSKD

Bit 31: Alarm date mask.

WPK

write protection register

Offset: 0x24, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPK
w
Toggle Fields.

WPK

Bits 0-7: Write protection key.

SS

sub second register

Offset: 0x28, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSC
r
Toggle Fields.

SSC

Bits 0-15: Sub second value.

SHIFTCTL

shift control register

Offset: 0x2C, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A1S
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SFS
w
Toggle Fields.

SFS

Bits 0-14: Subtract a fraction of a second.

A1S

Bit 31: One second add.

TTS

timestamp time register

Offset: 0x30, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
r 		HRT
r 		HRU
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
r 		MNU
r 		SCT
r 		SCU
r
Toggle Fields.

SCU

Bits 0-3: Second units in BCD code.

SCT

Bits 4-6: Second tens in BCD code.

MNU

Bits 8-11: Minute units in BCD code.

MNT

Bits 12-14: Minute tens in BCD code.

HRU

Bits 16-19: Hour units in BCD code.

HRT

Bits 20-21: Hour tens in BCD code.

PM

Bit 22: AM/PM mark.

DTS

Date of time stamp register

Offset: 0x34, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOW
r 		MONT
r 		MONU
r 		DAYT
r 		DAYU
r
Toggle Fields.

DAYU

Bits 0-4: Date units in BCD code.

DAYT

Bits 5-6: Date tens in BCD code.

MONU

Bits 8-11: Month units in BCD code.

MONT

Bit 12: Month tens in BCD code.

DOW

Bits 13-15: Week day units.

SSTS

time-stamp sub second register

Offset: 0x38, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSC
r
Toggle Fields.

SSC

Bits 0-15: Sub second value.

HRFC

High resolution frequency compensation register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FREQI
rw 		CWND8
rw 		CWND16
rw 		CMSK
rw
Toggle Fields.

CMSK

Bits 0-8: Calibration mask number.

CWND16

Bit 13: Frequency compensation window 16 second selected.

CWND8

Bit 14: Frequency compensation window 8 second selected.

FREQI

Bit 15: Increase RTC frequency by 488.5PPM.

TAMP

tamper and alternate function configuration register

Offset: 0x40, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PC15MDE
rw 		PC15VAL
rw 		PC14MDE
rw 		PC14VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISPU
rw 		PRCH
rw 		FLT
rw 		FREQ
rw 		TP1EG
rw 		TP1EN
rw 		TPIE
rw
Toggle Fields.

TPIE

Bit 2: Tamper detection interrupt enable.

TP1EN

Bit 3: Tamper 1 detection enable.

TP1EG

Bit 4: Tamper 1 event trigger edge.

FREQ

Bits 8-10: Tamper sampling frequency.

FLT

Bits 11-12: RTC_TAMPx filter count.

PRCH

Bits 13-14: RTC_TAMPx precharge duration.

DISPU

Bit 15: RTC_TAMPx pull-up disable.

PC14VAL

Bit 20: PC14 value.

PC14MDE

Bit 21: PC14 mode.

PC15VAL

Bit 22: PC15 value.

PC15MDE

Bit 23: PC15 mode.

ALRM0SS

alarm 0 sub second register

Offset: 0x44, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSKSSC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSC
rw
Toggle Fields.

SSC

Bits 0-14: Alarm sub second value.

MSKSSC

Bits 24-27: Mask control bit of SSC.

BKP0

backup register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: BKP data.

BKP1

backup register

Offset: 0x54, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: BKP data.

BKP2

backup register

Offset: 0x58, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: BKP data.

BKP3

backup register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: BKP data.

BKP4

backup register

Offset: 0x60, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: BKP data.

SPI0

0x40013000: Serial peripheral interface

9/46 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDEN
rw 		BDOEN
rw 		CRCEN
rw 		CRCNT
rw 		FF16
rw 		RO
rw 		SWNSSEN
rw 		SWNSS
rw 		LF
rw 		SPIEN
rw 		PSC
rw 		MSTMOD
rw 		CKPL
rw 		CKPH
rw
Toggle Fields.

CKPH

Bit 0: Clock Phase Selection.

CKPL

Bit 1: Clock Polarity Selection.

MSTMOD

Bit 2: Master Mode Enable.

PSC

Bits 3-5: Master Clock Prescaler Selection.

SPIEN

Bit 6: SPI enable.

LF

Bit 7: LSB First Mode.

SWNSS

Bit 8: NSS Pin Selection In NSS Software Mode.

SWNSSEN

Bit 9: NSS Software Mode Selection.

RO

Bit 10: Receive only.

FF16

Bit 11: Data frame format.

CRCNT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BDOEN

Bit 14: Bidirectional Transmit output enable.

BDEN

Bit 15: Bidirectional enable.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBEIE
rw 		RBNEIE
rw 		ERRIE
rw 		TMOD
rw 		NSSP
rw 		NSSDRV
rw 		DMATEN
rw 		DMAREN
rw
Toggle Fields.

DMAREN

Bit 0: Rx buffer DMA enable.

DMATEN

Bit 1: Tx buffer DMA enable.

NSSDRV

Bit 2: NSS output enable.

NSSP

Bit 3: SPI NSS Pulse Mode Enable.

TMOD

Bit 4: SPI TI Mode Enable.

ERRIE

Bit 5: Error interrupt enable.

RBNEIE

Bit 6: Receive Buffer Not Empty Interrupt Enable.

TBEIE

Bit 7: Transmit Buffer Empty Interrupt Enable.

STAT

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

7/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FERR
rw 		TRANS
r 		RXORERR
r 		CONFERR
r 		CRCERR
rw 		TXURERR
r 		I2SCH
r 		TBE
r 		RBNE
r
Toggle Fields.

RBNE

Bit 0: Receive Buffer Not Empty.

TBE

Bit 1: Transmit Buffer Empty.

I2SCH

Bit 2: I2S channel side.

TXURERR

Bit 3: Transmission underrun error bit.

CRCERR

Bit 4: SPI CRC Error Bit.

CONFERR

Bit 5: SPI Configuration error.

RXORERR

Bit 6: Reception Overrun Error Bit.

TRANS

Bit 7: Transmitting On-going Bit.

FERR

Bit 8: Format Error.

DATA

data register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Data register.

CRCPOLY

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

RCRC

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCRC
r
Toggle Fields.

RCRC

Bits 0-15: RX RCR register.

TCRC

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRC
r
Toggle Fields.

TCRC

Bits 0-15: Tx CRC register.

I2SCTL

I2S configuration register

Offset: 0x1C, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SSEL
rw 		I2SEN
rw 		I2SOPMOD
rw 		PCMSMOD
rw 		I2SSTD
rw 		CKPL
rw 		DTLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

DTLEN

Bits 1-2: Data length to be transferred.

CKPL

Bit 3: Idle state clock polarity.

I2SSTD

Bits 4-5: I2S standard selection.

PCMSMOD

Bit 7: PCM frame synchronization.

I2SOPMOD

Bits 8-9: I2S configuration mode.

I2SEN

Bit 10: I2S Enable.

I2SSEL

Bit 11: I2S mode selection.

I2SPSC

I2S prescaler register

Offset: 0x20, reset: 0x0002, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOEN
rw 		OF
rw 		DIV
rw
Toggle Fields.

DIV

Bits 0-7: Dividing factor for the prescaler.

OF

Bit 8: Odd factor for the prescaler.

MCKOEN

Bit 9: I2S_MCK output enable.

SPI1

0x40003800: Serial Peripheral Interface 1

9/53 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDEN
rw 		BDOEN
rw 		CRCEN
rw 		CRCNT
rw 		CRCL
rw 		RO
rw 		SWNSSEN
rw 		SWNSS
rw 		LF
rw 		SPIEN
rw 		PSC
rw 		MSTMOD
rw 		CKPL
rw 		CKPH
rw
Toggle Fields.

CKPH

Bit 0: Clock Phase Selection.

CKPL

Bit 1: Clock Polarity Selection.

MSTMOD

Bit 2: Master Mode Enable.

PSC

Bits 3-5: Master Clock Prescaler Selection.

SPIEN

Bit 6: SPI enable.

LF

Bit 7: LSB First Mode.

SWNSS

Bit 8: NSS Pin Selection In NSS Software Mode.

SWNSSEN

Bit 9: NSS Software Mode Selection.

RO

Bit 10: Receive only.

CRCL

Bit 11: CRC length.

CRCNT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BDOEN

Bit 14: Bidirectional Transmit output enable.

BDEN

Bit 15: Bidirectional enable.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDMA_ODD
rw 		RXDMA_ODD
rw 		BYTEN
rw 		DZ
rw 		TBEIE
rw 		RBNEIE
rw 		ERRIE
rw 		TMOD
rw 		NSSP
rw 		NSSDRV
rw 		DMATEN
rw 		DMAREN
rw
Toggle Fields.

DMAREN

Bit 0: Rx buffer DMA enable.

DMATEN

Bit 1: Tx buffer DMA enable.

NSSDRV

Bit 2: NSS output enable.

NSSP

Bit 3: SPI NSS Pulse Mode Enable.

TMOD

Bit 4: SPI TI Mode Enable.

ERRIE

Bit 5: Error interrupt enable.

RBNEIE

Bit 6: Receive Buffer Not Empty Interrupt Enable.

TBEIE

Bit 7: Transmit Buffer Empty Interrupt Enable.

DZ

Bits 8-11: Date size.

BYTEN

Bit 12: Byte access enable.

RXDMA_ODD

Bit 13: Odd bytes in RX DMA channel.

TXDMA_ODD

Bit 14: Odd bytes in TX DMA channel.

STAT

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

7/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXLVL
r 		RXLVL
r 		FERR
rw 		TRANS
r 		RXORERR
r 		CONFERR
r 		CRCERR
rw 		TBE
r 		RBNE
r
Toggle Fields.

RBNE

Bit 0: Receive Buffer Not Empty.

TBE

Bit 1: Transmit Buffer Empty.

CRCERR

Bit 4: SPI CRC Error Bit.

CONFERR

Bit 5: SPI Configuration error.

RXORERR

Bit 6: Reception Overrun Error Bit.

TRANS

Bit 7: Transmitting On-going Bit.

FERR

Bit 8: Format Error.

RXLVL

Bits 9-10: Rx FIFO level.

TXLVL

Bits 11-12: Tx FIFO level.

DATA

data register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Data register.

CRCPOLY

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

RCRC

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCRC
r
Toggle Fields.

RCRC

Bits 0-15: RX RCR register.

TCRC

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRC
r
Toggle Fields.

TCRC

Bits 0-15: Tx CRC register.

I2SCTL

I2S configuration register

Offset: 0x1C, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SSEL
rw 		I2SEN
rw 		I2SOPMOD
rw 		PCMSMOD
rw 		I2SSTD
rw 		CKPL
rw 		DTLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

DTLEN

Bits 1-2: Data length to be transferred.

CKPL

Bit 3: Idle state clock polarity.

I2SSTD

Bits 4-5: I2S standard selection.

PCMSMOD

Bit 7: PCM frame synchronization.

I2SOPMOD

Bits 8-9: I2S configuration mode.

I2SEN

Bit 10: I2S Enable.

I2SSEL

Bit 11: I2S mode selection.

I2SPSC

I2S prescaler register

Offset: 0x20, reset: 0x0002, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOEN
rw 		OF
rw 		DIV
rw
Toggle Fields.

DIV

Bits 0-7: Dividing factor for the prescaler.

OF

Bit 8: Odd factor for the prescaler.

MCKOEN

Bit 9: I2S_MCK output enable.

QCTL

SPI quad wird control register

Offset: 0x80, reset: 0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IO23_DRV
rw 		QRD
rw 		QMOD
rw
Toggle Fields.

QMOD

Bit 0: Quad wire mode enable.

QRD

Bit 1: Quad wire read select.

IO23_DRV

Bit 2: Drive IO2 and IO3 enable.

SYSCFG

0x40010000: System configuration controller

26/28 fields covered. Toggle Registers.

CFG0

System configuration register 0

Offset: 0x0, reset: 0x00000000, access: read-write

6/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMER16_DMA_RMP
rw 		TIMER15_DMA_RMP
rw 		USART0_RX_DMA_RMP
rw 		USART0_TX_DMA_RMP
rw 		ADC_DMA_RMP
rw 		PA11_PA12_RMP
rw 		BOOT_MODE
r
Toggle Fields.

BOOT_MODE

Bits 0-1: Boot mode.

Allowed values:
0: Flash: Boot from main flash
1: SystemMemory: Boot from system memory
3: SRAM: Boot from embedded SRAM

PA11_PA12_RMP

Bit 4: PA11 and PA12 remapping bit for small packages.

ADC_DMA_RMP

Bit 8: ADC DMA request remapping enable.

Allowed values:
0: Channel0: ADC DMA requests are mapped to DMA channel 0
1: Channel1: ADC DMA requests are remapped to DMA channel 1

USART0_TX_DMA_RMP

Bit 9: USART0_TX DMA request remapping enable.

Allowed values:
0: Channel1: USART0 TX DMA requests are mapped to DMA channel 1
1: Channel3: USART0 TX DMA requests are remapped to DMA channel 3

USART0_RX_DMA_RMP

Bit 10: USART0_RX DMA request remapping enable.

Allowed values:
0: Channel2: USART0 RX DMA requests are mapped to DMA channel 2
1: Channel4: USART0 RX DMA requests are remapped to DMA channel 4

TIMER15_DMA_RMP

Bit 11: Timer 15 DMA request remapping enable.

Allowed values:
0: Channel2: Timer 15 DMA requests are mapped to DMA channel 2
1: Channel3: Timer 15 DMA requests are remapped to DMA channel 3

TIMER16_DMA_RMP

Bit 12: Timer 16 DMA request remapping enable.

Allowed values:
0: Channel0: Timer 16 DMA requests are mapped to DMA channel 0
1: Channel1: Timer 16 DMA requests are remapped to DMA channel 1

EXTISS0

EXTI sources selection register 0

Offset: 0x8, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3_SS
rw 		EXTI2_SS
rw 		EXTI1_SS
rw 		EXTI0_SS
rw
Toggle Fields.

EXTI0_SS

Bits 0-3: EXTI 0 sources selection.

Allowed values:
0: PA0: PA0 pin
1: PB0: PB0 pin
2: PC0: PC0 pin
5: PF0: PF0 pin

EXTI1_SS

Bits 4-7: EXTI 1 sources selection.

Allowed values:
0: PA1: PA1 pin
1: PB1: PB1 pin
2: PC1: PC1 pin
5: PF1: PF1 pin

EXTI2_SS

Bits 8-11: EXTI 2 sources selection.

Allowed values:
0: PA2: PA2 pin
1: PB2: PB2 pin
2: PC2: PC2 pin
3: PD2: PD2 pin

EXTI3_SS

Bits 12-15: EXTI 3 sources selection.

Allowed values:
0: PA3: PA3 pin
1: PB3: PB3 pin
2: PC3: PC3 pin

EXTISS1

EXTI sources selection register 1

Offset: 0xC, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7_SS
rw 		EXTI6_SS
rw 		EXTI5_SS
rw 		EXTI4_SS
rw
Toggle Fields.

EXTI4_SS

Bits 0-3: EXTI 4 sources selection.

Allowed values:
0: PA4: PA4 pin
1: PB4: PB4 pin
2: PC4: PC4 pin
5: PF4: PF4 pin

EXTI5_SS

Bits 4-7: EXTI 5 sources selection.

Allowed values:
0: PA5: PA5 pin
1: PB5: PB5 pin
2: PC5: PC5 pin
5: PF5: PF5 pin

EXTI6_SS

Bits 8-11: EXTI 6 sources selection.

Allowed values:
0: PA6: PA6 pin
1: PB6: PB6 pin
2: PC6: PC6 pin
5: PF6: PF6 pin

EXTI7_SS

Bits 12-15: EXTI 7 sources selection.

Allowed values:
0: PA7: PA7 pin
1: PB7: PB7 pin
2: PC7: PC7 pin
5: PF7: PF7 pin

EXTISS2

EXTI sources selection register 2

Offset: 0x10, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11_SS
rw 		EXTI10_SS
rw 		EXTI9_SS
rw 		EXTI8_SS
rw
Toggle Fields.

EXTI8_SS

Bits 0-3: EXTI 8 sources selection.

Allowed values:
0: PA8: PA8 pin
1: PB8: PB8 pin
2: PC8: PC8 pin

EXTI9_SS

Bits 4-7: EXTI 9 sources selection.

Allowed values:
0: PA9: PA9 pin
1: PB9: PB9 pin
2: PC9: PC9 pin

EXTI10_SS

Bits 8-11: EXTI 10 sources selection.

Allowed values:
0: PA10: PA10 pin
1: PB10: PB10 pin
2: PC10: PC10 pin

EXTI11_SS

Bits 12-15: EXTI 11 sources selection.

Allowed values:
0: PA11: PA11 pin
1: PB11: PB11 pin
2: PC11: PC11 pin

EXTISS3

EXTI sources selection register 3

Offset: 0x14, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15_SS
rw 		EXTI14_SS
rw 		EXTI13_SS
rw 		EXTI12_SS
rw
Toggle Fields.

EXTI12_SS

Bits 0-3: EXTI 12 sources selection.

Allowed values:
0: PA12: PA12 pin
1: PB12: PB12 pin
2: PC12: PC12 pin

EXTI13_SS

Bits 4-7: EXTI 13 sources selection.

Allowed values:
0: PA13: PA13 pin
1: PB13: PB13 pin
2: PC13: PC13 pin

EXTI14_SS

Bits 8-11: EXTI 14 sources selection.

Allowed values:
0: PA14: PA14 pin
1: PB14: PB14 pin
2: PC14: PC14 pin

EXTI15_SS

Bits 12-15: EXTI 15 sources selection.

Allowed values:
0: PA15: PA15 pin
1: PB15: PB15 pin
2: PC15: PC15 pin

CFG2

System configuration register 2

Offset: 0x18, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM_PCEF
rw 		LVD_LOCK
rw 		SRAM_PARITY_ERROR_LOCK
rw 		LOCKUP_LOCK
rw
Toggle Fields.

LOCKUP_LOCK

Bit 0: Cortex-M4 LOCKUP output lock.

Allowed values:
0: Unlocked: The Cortex-M3 LOCKUP output is disconnected from the break input
1: Locked: The Cortex-M3 LOCKUP output is connected to the break input

SRAM_PARITY_ERROR_LOCK

Bit 1: SRAM parity check error lock.

Allowed values:
0: Unlocked: The SRAM parity check error is disconnected from the break input
1: Locked: The SRAM parity check error is connected to the break input

LVD_LOCK

Bit 2: LVD lock.

Allowed values:
0: Unlocked: The LVD interrupt is disconnected from the break input
1: Locked: The LVD interrupt is connected to the break input

SRAM_PCEF

Bit 8: SRAM parity check error flag.

Allowed values:
0: NoError: No SRAM parity check error detected
1: Error: SRAM parity check error detected

CPU_IRQ_LAT

IRQ Latency register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRQ_LATENCY
rw
Toggle Fields.

IRQ_LATENCY

Bits 0-7: specifies the minimum number of cycles between an interrupt .

TIMER0

0x40012C00: Advanced-timers

128/130 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UPDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

UPS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UPG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

SPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CAM

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAlignedCountingDown: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAlignedCountingUp: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAlignedCountingUpDown: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARSE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: The shadow register for CAR is disabled
1: Enabled: The shadow register for CAR is enabled

CKDIV

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISO3
rw 		ISO2N
rw 		ISO2
rw 		ISO1N
rw 		ISO1
rw 		ISO0N
rw 		ISO0
rw 		TI0S
rw 		MMC
rw 		DMAS
rw 		CCUC
rw 		CCSE
rw
Toggle Fields.

CCSE

Bit 0: Commutation control shadow enable.

Allowed values:
0: NotPreloaded: The shadow registers for CHxEN, CHxNEN and CHxCOMCTL bits are disabled
1: Preloaded: The shadow registers for CHxEN, CHxNEN and CHxCOMCTL bits are enabled

CCUC

Bit 2: Commutation control shadow register update control.

Allowed values:
0: Default: Capture/compare are updated only by setting the CMTG bit
1: WithRisingEdge: Capture/compare are updated by setting the CMTG bit or when an rising edge occurs on TRGI

DMAS

Bit 3: DMA request source selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMC

Bits 4-6: Master mode control.

Allowed values:
0: Reset: Use UPG bit from SWEVG register
1: Enable: Use CEN bit from CTL0 register
2: Update: Use the update event
3: CaptureComparePulse: The trigger output send a positive pulse when a capture or a compare match occurred in channel 0
4: CompareO0C: O0CPRE signal is used as trigger output
5: CompareO1C: O1CPRE signal is used as trigger output
6: CompareO2C: O2CPRE signal is used as trigger output
7: CompareO3C: O3CPRE signal is used as trigger output

TI0S

Bit 7: Channel 0 trigger input selection.

Allowed values:
0: Normal: The CH0 pin input is selected as channel 0 trigger input
1: XOR: The XOR of CH0, CH1 and CH2 pins are selected as channel 0 trigger input

ISO0

Bit 8: Idle state of channel 0 output.

Allowed values:
0: Low: CHn_O=0 (after a dead-time if CHn_ON is implemented) when POEN=0
1: High: CHn_O=1 (after a dead-time if CHn_ON is implemented) when POEN=0

ISO0N

Bit 9: Idle state of channel 0 complementary output.

Allowed values:
0: Low: CHn_ON=0 when POEN=0
1: High: CHn_ON=1 when POEN=0

ISO1

Bit 10: Idle state of channel 1 output.

Allowed values:

ISO1N

Bit 11: Idle state of channel 1 complementary output.

Allowed values:
0: Low: CHn_ON=0 when POEN=0
1: High: CHn_ON=1 when POEN=0

ISO2

Bit 12: Idle state of channel 2 output.

Allowed values:
0: Low: CHn_O=0 (after a dead-time if CHn_ON is implemented) when POEN=0
1: High: CHn_O=1 (after a dead-time if CHn_ON is implemented) when POEN=0

ISO2N

Bit 13: Idle state of channel 2 complementary output.

Allowed values:
0: Low: CHn_ON=0 when POEN=0
1: High: CHn_ON=1 when POEN=0

ISO3

Bit 14: Idle state of channel 3 output.

Allowed values:
0: Low: CHn_O=0 (after a dead-time if CHn_ON is implemented) when POEN=0
1: High: CHn_O=1 (after a dead-time if CHn_ON is implemented) when POEN=0

SMCFG

slave mode configuration register

Offset: 0x8, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		OCRC
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.
1: QuadratureDecoderMode0: Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.
2: QuadratureDecoderMode1: Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.
3: QuadratureDecoderMode2: Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.
4: RestartMode: Restart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: PauseMode: Pause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: EventMode: Event Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: ExternalClockMode: External Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.

OCRC

Bit 3: Trigger selection.

Allowed values:
0: Input: OCPRE_CLR_INT is connected to the OCPRE_CLR input
1: ETIF: OCPRE_CLR_INT is connected to ETIF

TRGS

Bits 4-6: Trigger selection.

Allowed values:
0: ITI0: Internal Trigger 0 (ITI0)
1: ITI1: Internal Trigger 1 (ITI1)
2: ITI2: Internal Trigger 2 (ITI2)
4: CI0F_ED: CI0 Edge Detector (CI0F_ED)
5: CI0FE0: Filtered Timer Input 0 (CI0FE0)
6: CI1FE1: Filtered Timer Input 1 (CI1FE1)
7: ETIFP: External Trigger input (ETIFP)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETFC

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8

ETPSC

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: External trigger prescaler disabled
1: Div2: ETI frequency divided by 2
2: Div4: ETI frequency divided by 4
3: Div8: ETI frequency divided by 8

SMC1

Bit 14: Part of SMC for enable External clock mode1.

Allowed values:
0: Disabled: External clock mode 1 disabled
1: Enabled: External clock mode 1 enabled. The counter is clocked by any active edge on the ETIF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETI is noninverted, active at high level or rising edge
1: Inverted: ETI is inverted, active at low level or falling edge

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CMTDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		BRKIE
rw 		TRGIE
rw 		CMTIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CH0IE

Bit 1: Capture/Compare 0 interrupt enable.

Allowed values:
0: Disabled: Capture/compare interrupt disabled
1: Enabled: Capture/compare interrupt enabled

CH1IE

Bit 2: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: Capture/compare interrupt disabled
1: Enabled: Capture/compare interrupt enabled

CH2IE

Bit 3: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: Capture/compare interrupt disabled
1: Enabled: Capture/compare interrupt enabled

CH3IE

Bit 4: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: Capture/compare interrupt disabled
1: Enabled: Capture/compare interrupt enabled

CMTIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: Commutation interrupt disabled
1: Enabled: Commutation interrupt enabled

TRGIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BRKIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CH0DEN

Bit 9: Capture/Compare 0 DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH1DEN

Bit 10: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH2DEN

Bit 11: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH3DEN

Bit 12: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CMTDEN

Bit 13: Reserved.

Allowed values:
0: Disabled: Commutation DMA request disabled
1: Enabled: Commutation DMA request enabled

TRGDEN

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

INTF

status register

Offset: 0x10, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		BRKIF
rw 		TRGIF
rw 		CMTIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update interrupt occurred
1: UpdatePending: Update interrupt pending.

CH0IF

Bit 1: Capture/compare 0 interrupt flag.

Allowed values:
0: Clear: No capture or compare interrupt occurred
1: CaptureCompare: A capture or compare event occurred

CH1IF

Bit 2: Capture/Compare 1 interrupt flag.

Allowed values:
0: Clear: No capture or compare interrupt occurred
1: CaptureCompare: A capture or compare event occurred

CH2IF

Bit 3: Capture/Compare 2 interrupt flag.

Allowed values:
0: Clear: No capture or compare interrupt occurred
1: CaptureCompare: A capture or compare event occurred

CH3IF

Bit 4: Capture/Compare 3 interrupt flag.

Allowed values:
0: Clear: No capture or compare interrupt occurred
1: CaptureCompare: A capture or compare event occurred

CMTIF

Bit 5: COM interrupt flag.

Allowed values:
0: Clear: No channel commutation event occured
1: Commutation: Channel commutation event occurred

TRGIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: Clear: No trigger event occured
1: Triggered: Trigger event occurred

BRKIF

Bit 7: Break interrupt flag.

Allowed values:
0: Clear: No active level break detected
1: Break: Active level detected

CH0OF

Bit 9: Channel 0 over capture flag.

Allowed values:
0: Clear: No over capture occurred
1: OverCapture: A capture event occured while CHnIF was already set

CH1OF

Bit 10: Channel 1 over capture flag.

Allowed values:
0: Clear: No over capture occurred
1: OverCapture: A capture event occured while CHnIF was already set

CH2OF

Bit 11: Channel 2 over capture flag.

Allowed values:
0: Clear: No over capture occurred
1: OverCapture: A capture event occured while CHnIF was already set

CH3OF

Bit 12: Channel 3 over capture flag.

Allowed values:
0: Clear: No over capture occurred
1: OverCapture: A capture event occured while CHnIF was already set

SWEVG

Software event generation register

Offset: 0x14, reset: 0x0000, access: write-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRKG
w 		TRGG
w 		CMTG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update event generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CH0G

Bit 1: Channel 0's capture or compare event generation.

Allowed values:
1: CaptureCompare: Generate a capture or compare event

CH1G

Bit 2: Channel 1's capture or compare event generation.

Allowed values:
1: CaptureCompare: Generate a capture or compare event

CH2G

Bit 3: Channel 2's capture or compare event generation.

Allowed values:
1: CaptureCompare: Generate a capture or compare event

CH3G

Bit 4: Channel 3's capture or compare event generation.

Allowed values:
1: CaptureCompare: Generate a capture or compare event

CMTG

Bit 5: Channel commutation event generation.

Allowed values:
1: Update: Generate a channel commutation event, updating capture/compare control registers based on the value of CCSE

TRGG

Bit 6: Trigger event generation.

Allowed values:
1: Trigger: Generate a trigger event

BRKG

Bit 7: Break event generation.

Allowed values:
1: Break: Generate a break event

CHCTL0_Input

capture/compare mode register 0 (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

Allowed values:
0: Output: Channel is configured as output
1: CI0: Channel is configured as input, ISx is connected to CI0FEx
2: CI1: Channel is configured as input, ISx is connected to CI1FEx
3: ITS: Channel is configured as input, ISx is connected to ITS

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

Allowed values:
0: Div1: Prescaler disabled, capture on every edge
1: Div2: Capture every 2 edges
2: Div4: Capture every 4 edges
3: Div8: Capture every 8 edges

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8

CH1MS

Bits 8-9: Channel 1 mode selection.

Allowed values:

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

Allowed values:

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

Allowed values:

CHCTL1_Input

capture/compare mode register 1 (input mode)

Offset: 0x1C, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Capture/compare 2 selection.

Allowed values:

CH2CAPPSC

Bits 2-3: Input capture 2 prescaler.

Allowed values:

CH2CAPFLT

Bits 4-7: Input capture 2 filter.

Allowed values:

CH3MS

Bits 8-9: Channel 3 mode selection.

Allowed values:

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

Allowed values:

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

Allowed values:

CHCTL2

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2NEN
rw 		CH2P
rw 		CH2EN
rw 		CH1NP
rw 		CH1NEN
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0NEN
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Channel output is disabled
1: Enabled: Channel output is enabled

CH0P

Bit 1: Capture/Compare 0 output Polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH0NEN

Bit 2: Capture/Compare 0 complementary output enable.

Allowed values:

CH0NP

Bit 3: Capture/Compare 0 output Polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH1EN

Bit 4: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Channel output is disabled
1: Enabled: Channel output is enabled

CH1P

Bit 5: Capture/Compare 1 output Polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH1NEN

Bit 6: Capture/Compare 1 complementary output enable.

Allowed values:

CH1NP

Bit 7: Capture/Compare 1 output Polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH2EN

Bit 8: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Channel output is disabled
1: Enabled: Channel output is enabled

CH2P

Bit 9: Capture/Compare 2 output Polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH2NEN

Bit 10: Capture/Compare 2 complementary output enable.

Allowed values:

CH2NP

Bit 11: Capture/Compare 2 output Polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH3EN

Bit 12: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Channel output is disabled
1: Enabled: Channel output is enabled

CH3P

Bit 13: Capture/Compare 3 output Polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CNT

counter

Offset: 0x24, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

CAR

auto-reload register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CREP

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CREP
rw
Toggle Fields.

CREP

Bits 0-7: Repetition counter value.

Allowed values: 0-255

CH0CV

capture/compare register 0

Offset: 0x34, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture/Compare 0 value.

Allowed values: 0-65535

CH1CV

capture/compare register 1

Offset: 0x38, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture/Compare 1 value.

Allowed values: 0-65535

CH2CV

capture/compare register 2

Offset: 0x3C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: Capture/Compare 2 value.

Allowed values: 0-65535

CH3CV

capture/compare register 3

Offset: 0x40, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: Capture/Compare 3 value.

Allowed values: 0-65535

CCHP

channel complementary protection register

Offset: 0x44, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POEN
rw 		OAEN
rw 		BRKP
rw 		BRKEN
rw 		ROS
rw 		IOS
rw 		PROT
rw 		DTCFG
rw
Toggle Fields.

DTCFG

Bits 0-7: Dead-time generator setup.

Allowed values: 0-255

PROT

Bits 8-9: Lock configuration.

Allowed values:
0: Disabled: Write protection disabled
1: Mode0: Protection mode 0
2: Mode1: Protection mode 1
3: Mode2: Protection mode 2

IOS

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: Disabled: When POEN is reset, the channel output signals are disabled
1: Enabled: When POEN is reset, the channel output signals are enabled

ROS

Bit 11: Off-state selection for Run mode.

Allowed values:
0: Disabled: When POEN is set, the channel output signals are disabled
1: Enabled: When POEN is set, the channel output signals are enabled

BRKEN

Bit 12: Break enable.

Allowed values:
0: Disabled: Break inputs disabled
1: Enabled: Break inputs enabled

BRKP

Bit 13: Break polarity.

Allowed values:
0: Inverted: BRKIN is active low
1: NotInverted: BRKIN is active high

OAEN

Bit 14: Automatic output enable.

Allowed values:
0: Manual: POEN cannot be set by hardware
1: Automatic: POEN can be set by hardware automatically at the next update event

POEN

Bit 15: Main output enable.

Allowed values:
0: Disabled: Channel outputs are disabled
1: Enabled: Channel outputs are enabled

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

Allowed values: 0-31

DMATC

Bits 8-12: DMA transfer count.

Allowed values: 0-31

DMATB

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA register for burst accesses.

Allowed values: 0-65535

CFG

Configuration register

Offset: 0xFC, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw 		OUTSEL
rw
Toggle Fields.

OUTSEL

Bit 0: The output value selection.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER13

0x40002000: General-purpose-timers

27/28 fields covered. Toggle Registers.

CTL0

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update request source.

Allowed values:

ARSE

Bit 7: Auto-reload preload enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

Allowed values:

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Capture/Compare 0 interrupt enable.

Allowed values:

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0OF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Capture/compare 0 interrupt flag.

Allowed values:

CH0OF

Bit 9: Capture/Compare 0 overcapture flag.

Allowed values:

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Capture/compare 0 generation.

Allowed values:

CHCTL0_Input

capture/compare mode register (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Capture/Compare 0 selection.

Allowed values:

CH0CAPPSC

Bits 2-3: Input capture 0 prescaler.

Allowed values:

CH0CAPFLT

Bits 4-7: Input capture 0 filter.

Allowed values:

CHCTL2

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Capture/Compare 1 output enable.

Allowed values:

CH0P

Bit 1: Capture/Compare 0 output Polarity.

Allowed values:

CH0NP

Bit 3: Capture/Compare 0 output Polarity.

Allowed values:

CNT

counter

Offset: 0x24, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

CAR

auto-reload register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Auto-reload value.

Allowed values: 0-65535

CH0CV

capture/compare register 0

Offset: 0x34, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture/Compare 1 value.

Allowed values: 0-65535

IRMP

channel input remap register

Offset: 0x50, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CI0_RMP
rw
Toggle Fields.

CI0_RMP

Bits 0-1: Timer input 0 remap.

Allowed values:
0: GPIO: Channel 0 input is connected to GPIO
1: RTCCLK: Channel 0 input is connected to RTCCLK
2: HXTAL_32: Channel 0 input is connected to HXTAL / 32
3: CKOUTSEL: Channel 0 input is connected to CKOUTSEL

CFG

configuration register

Offset: 0xFC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER14

0x40014000: General-purpose-timers

78/81 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update request source.

Allowed values:

SPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARSE

Bit 7: Auto-reload preload enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

Allowed values:

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISO1
rw 		ISO0N
rw 		ISO0
rw 		MMC
rw 		DMAS
rw 		CCUC
rw 		CCSE
rw
Toggle Fields.

CCSE

Bit 0: Capture/compare preloaded control.

Allowed values:

CCUC

Bit 2: Capture/compare control update selection.

Allowed values:

DMAS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMC

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UPG bit from SWEVG register
1: Enable: Use CEN bit from CTL0 register
2: Update: Use the update event

ISO0

Bit 8: Output Idle state 0.

Allowed values:

ISO0N

Bit 9: Output Idle state 0.

Allowed values:

ISO1

Bit 10: Output Idle state 1.

Allowed values:

SMCFG

slave mode configuration register

Offset: 0x8, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.
4: RestartMode: Restart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: PauseMode: Pause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: EventMode: Event Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: ExternalClockMode: External Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.

TRGS

Bits 4-6: Trigger selection.

Allowed values:
0: ITI0: Internal Trigger 0 (ITI0)
1: ITI1: Internal Trigger 1 (ITI1)
4: CI0F_ED: CI0 Edge Detector (CI0F_ED)
5: CI0FE0: Filtered Timer Input 0 (CI0FE0)
6: CI1FE1: Filtered Timer Input 1 (CI1FE1)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

10/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CMTDEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		BRKIE
rw 		TRGIE
rw 		CMTIE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:

CH1IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:

CMTIE

Bit 5: COM interrupt enable.

Allowed values:

TRGIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BRKIE

Bit 7: Break interrupt enable.

Allowed values:

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CH0DEN

Bit 9: Capture/Compare 0 DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH1DEN

Bit 10: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CMTDEN

Bit 13: Commutation DMA request enable.

TRGDEN

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1OF
rw 		CH0OF
rw 		BRKIF
rw 		TRGIF
rw 		CMTIF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Capture/compare 0 interrupt flag.

Allowed values:

CH1IF

Bit 2: Capture/Compare 1 interrupt flag.

Allowed values:

CMTIF

Bit 5: COM interrupt flag.

Allowed values:

TRGIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: Clear: No trigger event occured
1: Triggered: Trigger event occurred

BRKIF

Bit 7: Break interrupt flag.

Allowed values:

CH0OF

Bit 9: Capture/Compare 0 overcapture flag.

Allowed values:

CH1OF

Bit 10: Capture/compare 1 overcapture flag.

Allowed values:

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRKG
w 		TRGG
w 		CMTG
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Capture/compare 0 generation.

Allowed values:

CH1G

Bit 2: Capture/compare 1 generation.

Allowed values:

CMTG

Bit 5: Capture/Compare control update generation.

Allowed values:

TRGG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: Generate a trigger event

BRKG

Bit 7: Break generation.

Allowed values:

CHCTL0_Input

capture/compare mode register 0 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Capture/Compare 0 selection.

Allowed values:

CH0CAPPSC

Bits 2-3: Input capture 0 prescaler.

Allowed values:

CH0CAPFLT

Bits 4-7: Input capture 0 filter.

Allowed values:

CH1MS

Bits 8-9: Capture/Compare 1 selection.

Allowed values:

CH1CAPPSC

Bits 10-11: Input capture 1 prescaler.

Allowed values:

CH1CAPFLT

Bits 12-15: Input capture 1 filter.

Allowed values:

CHCTL2

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1NP
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0NEN
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Capture/Compare 0 output enable.

Allowed values:

CH0P

Bit 1: Capture/Compare 0 output Polarity.

Allowed values:

CH0NEN

Bit 2: Capture/Compare 0 complementary output enable.

Allowed values:

CH0NP

Bit 3: Capture/Compare 0 output Polarity.

Allowed values:

CH1EN

Bit 4: Capture/Compare 1 output enable.

Allowed values:

CH1P

Bit 5: Capture/Compare 1 output Polarity.

Allowed values:

CH1NP

Bit 7: Capture/Compare 1 output Polarity.

Allowed values:

CNT

counter

Offset: 0x24, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

CAR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Auto-reload value.

Allowed values: 0-65535

CREP

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CREP
rw
Toggle Fields.

CREP

Bits 0-7: Repetition counter value.

Allowed values: 0-255

CH0CV

capture/compare register 0

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture/Compare 0 value.

Allowed values: 0-65535

CH1CV

capture/compare register 1

Offset: 0x38, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture/Compare 1 value.

Allowed values: 0-65535

CCHP

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POEN
rw 		OAEN
rw 		BRKP
rw 		BRKEN
rw 		ROS
rw 		IOS
rw 		PROT
rw 		DTCFG
rw
Toggle Fields.

DTCFG

Bits 0-7: Dead-time generator configure.

Allowed values: 0-255

PROT

Bits 8-9: complementary register protect control.

Allowed values:

IOS

Bit 10: Off-state selection for Idle mode.

Allowed values:

ROS

Bit 11: Off-state selection for Run mode.

Allowed values:

BRKEN

Bit 12: Break enable.

Allowed values:

BRKP

Bit 13: Break polarity.

Allowed values:

OAEN

Bit 14: Automatic output enable.

Allowed values:

POEN

Bit 15: Main output enable.

Allowed values:

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA base address.

Allowed values: 0-31

DMATC

Bits 8-12: DMA burst length.

Allowed values: 0-31

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA register for burst accesses.

Allowed values: 0-65535

CFG

configuration register

Offset: 0xFC, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw 		OUTSEL
rw
Toggle Fields.

OUTSEL

Bit 0: The output value selection.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER15

0x40014400: General-purpose-timers

53/55 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update request source.

Allowed values:

SPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARSE

Bit 7: Auto-reload preload enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

Allowed values:

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISO0N
rw 		ISO0
rw 		DMAS
rw 		CCUC
rw 		CCSE
rw
Toggle Fields.

CCSE

Bit 0: Capture/compare preloaded control.

Allowed values:

CCUC

Bit 2: Capture/compare control update selection.

Allowed values:

DMAS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

ISO0

Bit 8: Output Idle state 0.

Allowed values:

ISO0N

Bit 9: Output Idle state 0.

Allowed values:

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0DEN
rw 		UPDEN
rw 		BRKIE
rw 		CMTIE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Capture/Compare 0 interrupt enable.

Allowed values:

CMTIE

Bit 5: COM interrupt enable.

Allowed values:

BRKIE

Bit 7: Break interrupt enable.

Allowed values:

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CH0DEN

Bit 9: Capture/Compare 0 DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0OF
rw 		BRKIF
rw 		CMTIF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Capture/compare 0 interrupt flag.

Allowed values:

CMTIF

Bit 5: COM interrupt flag.

Allowed values:

BRKIF

Bit 7: Break interrupt flag.

Allowed values:

CH0OF

Bit 9: Capture/Compare 0 overcapture flag.

Allowed values:

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRKG
w 		CMTG
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Capture/compare 0 generation.

Allowed values:

CMTG

Bit 5: Capture/Compare control update generation.

Allowed values:

BRKG

Bit 7: Break generation.

Allowed values:

CHCTL0_Input

capture/compare mode register 0 (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Capture/Compare 0 selection.

Allowed values:

CH0CAPPSC

Bits 2-3: Input capture 0 prescaler.

Allowed values:

CH0CAPFLT

Bits 4-7: Input capture 0 filter.

Allowed values:

CHCTL2

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0NP
rw 		CH0NEN
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Capture/Compare 0 output enable.

Allowed values:

CH0P

Bit 1: Capture/Compare 0 output Polarity.

Allowed values:

CH0NEN

Bit 2: Capture/Compare 0 complementary output enable.

Allowed values:

CH0NP

Bit 3: Capture/Compare 0 output Polarity.

Allowed values:

CNT

counter

Offset: 0x24, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

CAR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Auto-reload value.

Allowed values: 0-65535

CREP

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CREP
rw
Toggle Fields.

CREP

Bits 0-7: Repetition counter value.

Allowed values: 0-255

CH0CV

capture/compare register 0

Offset: 0x34, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture/Compare 0 value.

Allowed values: 0-65535

CCHP

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POEN
rw 		OAEN
rw 		BRKP
rw 		BRKEN
rw 		ROS
rw 		IOS
rw 		PROT
rw 		DTCFG
rw
Toggle Fields.

DTCFG

Bits 0-7: Dead-time generator setup.

Allowed values: 0-255

PROT

Bits 8-9: complementary register protect control.

Allowed values:

IOS

Bit 10: Off-state selection for Idle mode.

Allowed values:

ROS

Bit 11: Off-state selection for Run mode.

Allowed values:

BRKEN

Bit 12: Break enable.

Allowed values:

BRKP

Bit 13: Break polarity.

Allowed values:

OAEN

Bit 14: Automatic output enable.

Allowed values:

POEN

Bit 15: Main output enable.

Allowed values:

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

Allowed values: 0-31

DMATC

Bits 8-12: DMA transfer count.

Allowed values: 0-31

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA register for burst accesses.

Allowed values: 0-65535

CFG

configuration register

Offset: 0xFC, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw 		OUTSEL
rw
Toggle Fields.

OUTSEL

Bit 0: The output value selection.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER16

0x40014800: General-purpose-timers

53/55 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update request source.

Allowed values:

SPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARSE

Bit 7: Auto-reload preload enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

Allowed values:

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISO0N
rw 		ISO0
rw 		DMAS
rw 		CCUC
rw 		CCSE
rw
Toggle Fields.

CCSE

Bit 0: Capture/compare preloaded control.

Allowed values:

CCUC

Bit 2: Capture/compare control update selection.

Allowed values:

DMAS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

ISO0

Bit 8: Output Idle state 0.

Allowed values:

ISO0N

Bit 9: Output Idle state 0.

Allowed values:

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0DEN
rw 		UPDEN
rw 		BRKIE
rw 		CMTIE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Capture/Compare 0 interrupt enable.

Allowed values:

CMTIE

Bit 5: COM interrupt enable.

Allowed values:

BRKIE

Bit 7: Break interrupt enable.

Allowed values:

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CH0DEN

Bit 9: Capture/Compare 0 DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0OF
rw 		BRKIF
rw 		CMTIF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Capture/compare 0 interrupt flag.

Allowed values:

CMTIF

Bit 5: COM interrupt flag.

Allowed values:

BRKIF

Bit 7: Break interrupt flag.

Allowed values:

CH0OF

Bit 9: Capture/Compare 0 overcapture flag.

Allowed values:

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRKG
w 		CMTG
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Capture/compare 0 generation.

Allowed values:

CMTG

Bit 5: Capture/Compare control update generation.

Allowed values:

BRKG

Bit 7: Break generation.

Allowed values:

CHCTL0_Input

capture/compare mode register 0 (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Capture/Compare 0 selection.

Allowed values:

CH0CAPPSC

Bits 2-3: Input capture 0 prescaler.

Allowed values:

CH0CAPFLT

Bits 4-7: Input capture 0 filter.

Allowed values:

CHCTL2

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0NP
rw 		CH0NEN
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Capture/Compare 0 output enable.

Allowed values:

CH0P

Bit 1: Capture/Compare 0 output Polarity.

Allowed values:

CH0NEN

Bit 2: Capture/Compare 0 complementary output enable.

Allowed values:

CH0NP

Bit 3: Capture/Compare 0 output Polarity.

Allowed values:

CNT

counter

Offset: 0x24, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

CAR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Auto-reload value.

Allowed values: 0-65535

CREP

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CREP
rw
Toggle Fields.

CREP

Bits 0-7: Repetition counter value.

Allowed values: 0-255

CH0CV

capture/compare register 0

Offset: 0x34, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture/Compare 0 value.

Allowed values: 0-65535

CCHP

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POEN
rw 		OAEN
rw 		BRKP
rw 		BRKEN
rw 		ROS
rw 		IOS
rw 		PROT
rw 		DTCFG
rw
Toggle Fields.

DTCFG

Bits 0-7: Dead-time generator setup.

Allowed values: 0-255

PROT

Bits 8-9: complementary register protect control.

Allowed values:

IOS

Bit 10: Off-state selection for Idle mode.

Allowed values:

ROS

Bit 11: Off-state selection for Run mode.

Allowed values:

BRKEN

Bit 12: Break enable.

Allowed values:

BRKP

Bit 13: Break polarity.

Allowed values:

OAEN

Bit 14: Automatic output enable.

Allowed values:

POEN

Bit 15: Main output enable.

Allowed values:

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

Allowed values: 0-31

DMATC

Bits 8-12: DMA transfer count.

Allowed values: 0-31

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA register for burst accesses.

Allowed values: 0-65535

CFG

configuration register

Offset: 0xFC, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw 		OUTSEL
rw
Toggle Fields.

OUTSEL

Bit 0: The output value selection.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER2

0x40000400: General-purpose-timers

95/102 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update request source.

Allowed values:

SPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:

CAM

Bits 5-6: Center-aligned mode selection.

Allowed values:

ARSE

Bit 7: Auto-reload preload enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

Allowed values:

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI0S
rw 		MMC
rw 		DMAS
rw
Toggle Fields.

DMAS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMC

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UPG bit from SWEVG register
1: Enable: Use CEN bit from CTL0 register
2: Update: Use the update event

TI0S

Bit 7: TI0 selection.

Allowed values:
0: Normal: The CH0 pin input is selected as channel 0 trigger input
1: XOR: The XOR of CH0, CH1 and CH2 pins are selected as channel 0 trigger input

SMCFG

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		OCRC
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.
1: QuadratureDecoderMode0: Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.
2: QuadratureDecoderMode1: Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.
3: QuadratureDecoderMode2: Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.
4: RestartMode: Restart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: PauseMode: Pause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: EventMode: Event Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: ExternalClockMode: External Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.

OCRC

Bit 3: OCREF clear source selection .

Allowed values:
0: Input: OCPRE_CLR_INT is connected to the OCPRE_CLR input
1: ETIF: OCPRE_CLR_INT is connected to ETIF

TRGS

Bits 4-6: Trigger selection.

Allowed values:
0: ITI0: Internal Trigger 0 (ITI0)
1: ITI1: Internal Trigger 1 (ITI1)
2: ITI2: Internal Trigger 2 (ITI2)
4: CI0F_ED: CI0 Edge Detector (CI0F_ED)
5: CI0FE0: Filtered Timer Input 0 (CI0FE0)
6: CI1FE1: Filtered Timer Input 1 (CI1FE1)
7: ETIFP: External Trigger input (ETIFP)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETFC

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8

ETPSC

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: External trigger prescaler disabled
1: Div2: ETI frequency divided by 2
2: Div4: ETI frequency divided by 4
3: Div8: ETI frequency divided by 8

SMC1

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 1 disabled
1: Enabled: External clock mode 1 enabled. The counter is clocked by any active edge on the ETIF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETI is noninverted, active at high level or rising edge
1: Inverted: ETI is inverted, active at low level or falling edge

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		TRGIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Capture/Compare 0 interrupt enable.

Allowed values:

CH1IE

Bit 2: Capture/Compare 1 interrupt enable.

Allowed values:

CH2IE

Bit 3: Capture/Compare 2 interrupt enable.

Allowed values:

CH3IE

Bit 4: Capture/Compare 3 interrupt enable.

Allowed values:

TRGIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CH0DEN

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH1DEN

Bit 10: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH2DEN

Bit 11: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH3DEN

Bit 12: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

TRGDEN

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Capture/compare 0 interrupt flag.

Allowed values:

CH1IF

Bit 2: Capture/Compare 1 interrupt flag.

Allowed values:

CH2IF

Bit 3: Capture/Compare 2 interrupt flag.

Allowed values:

CH3IF

Bit 4: Capture/Compare 3 interrupt flag.

Allowed values:

TRGIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: Clear: No trigger event occured
1: Triggered: Trigger event occurred

CH0OF

Bit 9: Capture/Compare 0 overcapture flag.

Allowed values:

CH1OF

Bit 10: Capture/compare 1 overcapture flag.

Allowed values:

CH2OF

Bit 11: Capture/Compare 2 overcapture flag.

Allowed values:

CH3OF

Bit 12: Capture/Compare 3 overcapture flag.

Allowed values:

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Capture/compare 0 generation.

Allowed values:

CH1G

Bit 2: Capture/compare 1 generation.

Allowed values:

CH2G

Bit 3: Capture/compare 2 generation.

Allowed values:

CH3G

Bit 4: Capture/compare 3 generation.

Allowed values:

TRGG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: Generate a trigger event

CHCTL0_Input

capture/compare mode register 0 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Capture/Compare 0 selection.

Allowed values:

CH0CAPPSC

Bits 2-3: Input capture 0 prescaler.

Allowed values:

CH0CAPFLT

Bits 4-7: Input capture 0 filter.

Allowed values:

CH1MS

Bits 8-9: Capture/compare 1 selection.

Allowed values:

CH1CAPPSC

Bits 10-11: Input capture 1 prescaler.

Allowed values:

CH1CAPFLT

Bits 12-15: Input capture 1 filter.

Allowed values:

CHCTL1_Input

capture/compare mode register 1 (input mode)

Offset: 0x1C, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Capture/Compare 2 selection.

Allowed values:

CH2CAPPSC

Bits 2-3: Input capture 2 prescaler.

Allowed values:

CH2CAPFLT

Bits 4-7: Input capture 2 filter.

Allowed values:

CH3MS

Bits 8-9: Capture/Compare 3 selection.

Allowed values:

CH3CAPPSC

Bits 10-11: Input capture 3 prescaler.

Allowed values:

CH3CAPFLT

Bits 12-15: Input capture 3 filter.

Allowed values:

CHCTL2

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3NP
rw 		CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2P
rw 		CH2EN
rw 		CH1NP
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Capture/Compare 0 output enable.

Allowed values:

CH0P

Bit 1: Capture/Compare 0 output Polarity.

Allowed values:

CH0NP

Bit 3: Capture/Compare 0 output Polarity.

Allowed values:

CH1EN

Bit 4: Capture/Compare 1 output enable.

Allowed values:

CH1P

Bit 5: Capture/Compare 1 output Polarity.

Allowed values:

CH1NP

Bit 7: Capture/Compare 1 output Polarity.

Allowed values:

CH2EN

Bit 8: Capture/Compare 2 output enable.

Allowed values:

CH2P

Bit 9: Capture/Compare 2 output Polarity.

Allowed values:

CH2NP

Bit 11: Capture/Compare 2 output Polarity.

Allowed values:

CH3EN

Bit 12: Capture/Compare 3 output enable.

Allowed values:

CH3P

Bit 13: Capture/Compare 3 output Polarity.

Allowed values:

CH3NP

Bit 15: Capture/Compare 3 output Polarity.

Allowed values:

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

CAR

auto-reload register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Low Auto-reload value.

CH0CV

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Low Capture/Compare 1 value.

CH1CV

capture/compare register 2

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Low Capture/Compare 2 value.

CH2CV

capture/compare register 2

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: High Capture/Compare value (TIM2 only).

CH3CV

capture/compare register 3

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: High Capture/Compare value (TIM2 only).

DMACFG

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA base address.

Allowed values: 0-31

DMATC

Bits 8-12: DMA burst length.

Allowed values: 0-31

DMATB

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA register for burst accesses.

Allowed values: 0-65535

CFG

Configuration

Offset: 0xFC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER5

0x40001000: Basic-timers

13/13 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARSE
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update request source.

Allowed values:

SPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARSE

Bit 7: Auto-reload preload enable.

Allowed values:

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMC
rw
Toggle Fields.

MMC

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UPG bit from SWEVG register
1: Enable: Use CEN bit from CTL0 register
2: Update: Use the update event

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPDEN
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

INTF

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Low counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

CAR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Low Auto-reload value.

Allowed values: 0-65535

USART0

0x40013800: Universal synchronous asynchronous receiver transmitter

107/113 fields covered. Toggle Registers.

CTL0

Control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EBIE
rw 		RTIE
rw 		DEA
rw 		DED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVSMOD
rw 		AMIE
rw 		MEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		UESM
rw 		UEN
rw
Toggle Fields.

UEN

Bit 0: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART prescaler and outputs enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake the MCU from deep-sleep mode
1: Enabled: USART is able to wake the MCU from deep-sleep mode, as long as the clock source for the USART is IRC8M or LXTAL

REN

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TEN

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Idle line detected interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLEF=1 in the STAT register

RBNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Read data buffer not empty and overrrun error interrupts are disabled
1: Enabled: Interrupt is generated whenever ORERR=1 or RBNE=1 in the STAT register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Transmission complete interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the STAT register

TBEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Transmission register empty interrupt is disabled
1: Enabled: Interrupt is generated whenever TBE=1 in the STAT register

PERRIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Parity error interrupt is disabled
1: Enabled: Interrupt is generated whenever PERR=1 in the STAT register

PM

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCEN

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WM

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

WL

Bit 12: Word length.

Allowed values:
0: Bit8: 8 data bits
1: Bit9: 9 data bits

MEN

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

AMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Address match interrupt is disabled
1: Enabled: Address match interrupt is enabled

OVSMOD

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DED

Bits 16-20: Driver Enable deassertion time.

Allowed values: 0-31

DEA

Bits 21-25: Driver Enable assertion time.

Allowed values: 0-31

RTIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Receiver timeout interrupt is disabled
1: Enabled: Receiver timeout interrupt is enabled

EBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: End of block interrupt is disabled
1: Enabled: End of block interrupt is enabled

CTL1

Control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
rw 		RTEN
rw 		ABDM
rw 		ABDEN
rw 		MSBF
rw 		DINV
rw 		TINV
rw 		RINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRP
rw 		LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDM
rw
Toggle Fields.

ADDM

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Full: Full-bit address detection

LBLEN

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: An interrupt is generated whenever LBDF=1 in the STAT register

CLEN

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPH

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPL

Bit 10: Clock polarity.

Allowed values:
0: NotInverted: Steady low value on CK pin outside tranmission window
1: Inverted: Steady high value on CK pin outside tranmission window

CKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STB

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LMEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

STRP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBF

Bit 19: Most significant bit first.

Allowed values:
0: LSB: Data is transmitted/received with data bit 0 first, following the start bit
1: MSB: Data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABDEN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABDM

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement

RTEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADDR

Bits 24-31: Address of the USART node.

Allowed values: 0-255

CTL2

Control register 2

Offset: 0x8, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUIE
rw 		WUM
rw 		SCRTNUM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRD
rw 		OSB
rw 		CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt is disabled
1: Enabled: An interrupt is generated when FERR=1 or ORERR=1 or NERR=1 in the STAT register

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDEN

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NKEN

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DENR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DENT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSEN

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSEN

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: An interrupt is generated whenever CTS=1 in the STAT register

OSB

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRD

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDATA register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCRTNUM

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0-7

WUM

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WUF active on start bit detection
3: RXNE: WUF active on RBNE

WUIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Wake-up from deep-sleep mode interrupt is disabled
1: Enabled: Wake-up from deep-sleep mode interrupt is generated whenever WUF=1 in the STAT register

BAUD

Baud rate register

Offset: 0xC, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: integer of baud-rate divider.

Allowed values: 0-15

INTDIV

Bits 4-15: integer of baud-rate divider.

Allowed values: 0-4095

GP

Guard time and prescaler register

Offset: 0x10, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

Allowed values: 0-255

GUAT

Bits 8-15: Guard time value.

Allowed values: 0-255

RT

Receiver timeout register

Offset: 0x14, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BL
rw 		RT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT
rw
Toggle Fields.

RT

Bits 0-23: Receiver timeout value.

Allowed values: 0-16777215

BL

Bits 24-31: Block Length.

Allowed values: 0-255

CMD

Request register

Offset: 0x18, reset: 0x00000000, access: write-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFCMD
w 		RXFCMD
w 		MMCMD
w 		SBKCMD
w 		ABDCMD
w
Toggle Fields.

ABDCMD

Bit 0: Auto baud rate request.

Allowed values:
1: Request: Resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKCMD

Bit 1: Send break request.

Allowed values:
1: Break: Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMCMD

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFCMD

Bit 3: Receive data flush request.

Allowed values:
1: Discard: Clears the RBNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFCMD

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TBE flag. This allows to discard the transmit data

STAT

Interrupt & status register

Offset: 0x1C, reset: 0x000000C0, access: read-only

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REA
r 		TEA
r 		WUF
r 		RWU
r 		SBF
r 		AMF
r 		BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABDF
r 		ABDE
r 		EBF
r 		RTF
r 		CTS
r 		CTSF
r 		LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error.

FERR

Bit 1: Framing error.

NERR

Bit 2: Noise detected flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: Idle line detected.

RBNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data register empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS interrupt flag.

CTS

Bit 10: CTS flag.

RTF

Bit 11: Receiver timeout.

EBF

Bit 12: End of block flag.

ABDE

Bit 14: Auto baud rate error.

ABDF

Bit 15: Auto baud rate flag.

BSY

Bit 16: Busy flag.

AMF

Bit 17: character match flag.

SBF

Bit 18: Send break flag.

RWU

Bit 19: Receiver wakeup from Mute mode.

WUF

Bit 20: Wakeup from Stop mode flag.

TEA

Bit 21: Transmit enable acknowledge flag.

REA

Bit 22: Receive enable acknowledge flag.

INTC

Interrupt flag clear register

Offset: 0x20, reset: 0x00000000, access: write-only

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUC
w 		AMC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBC
w 		RTC
w 		CTSC
w 		LBDC
w 		TCC
w 		IDLEC
w 		OREC
w 		NEC
w 		FEC
w 		PEC
w
Toggle Fields.

PEC

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PERR bit in the STAT register

FEC

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FERR bit in the STAT register

NEC

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NERR bit in the STAT register

OREC

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORERR bit in the STAT register

IDLEC

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLEF flag in the STAT register

TCC

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC bit in the STAT register

LBDC

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the STAT register

CTSC

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSF flag in the STAT register

RTC

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RCF flag in the STAT register

EBC

Bit 12: End of timeout clear flag.

Allowed values:
1: Clear: Clears the EBF flag in the STAT register

AMC

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the AMF flag in the STAT register

WUC

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the STAT register

RDATA

Receive data register

Offset: 0x24, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle Fields.

RDATA

Bits 0-8: Receive data value.

Allowed values: 0-511

TDATA

Transmit data register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDATA
rw
Toggle Fields.

TDATA

Bits 0-8: Transmit data value.

Allowed values: 0-255

CHC

coherence control register

Offset: 0xC0, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPERR
rw 		HCM
rw
Toggle Fields.

HCM

Bit 0: Hardware flow control coherence mode.

EPERR

Bit 8: Early parity error flag.

RFCS

USART receive FIFO control and status register

Offset: 0xD0, reset: 0x00000400, access: Unspecified

3/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFFINT
rw 		RFCNT
r 		RFF
r 		RFE
r 		RFFIE
rw 		RFEN
rw 		ELNACK
rw
Toggle Fields.

ELNACK

Bit 0: Early NKEN when smartcard mode is selected.

RFEN

Bit 8: Receive FIFO enable.

RFFIE

Bit 9: Receive FIFO full interrupt enable.

RFE

Bit 10: Receive FIFO empty flag.

RFF

Bit 11: Receive FIFO full flag.

RFCNT

Bits 12-14: Receive FIFO count number.

RFFINT

Bit 15: Receive FIFO full interrupt flag.

USART1

0x40004400: Universal synchronous asynchronous receiver transmitter

107/113 fields covered. Toggle Registers.

CTL0

Control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EBIE
rw 		RTIE
rw 		DEA
rw 		DED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVSMOD
rw 		AMIE
rw 		MEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		UESM
rw 		UEN
rw
Toggle Fields.

UEN

Bit 0: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART prescaler and outputs enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake the MCU from deep-sleep mode
1: Enabled: USART is able to wake the MCU from deep-sleep mode, as long as the clock source for the USART is IRC8M or LXTAL

REN

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TEN

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Idle line detected interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLEF=1 in the STAT register

RBNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Read data buffer not empty and overrrun error interrupts are disabled
1: Enabled: Interrupt is generated whenever ORERR=1 or RBNE=1 in the STAT register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Transmission complete interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the STAT register

TBEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Transmission register empty interrupt is disabled
1: Enabled: Interrupt is generated whenever TBE=1 in the STAT register

PERRIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Parity error interrupt is disabled
1: Enabled: Interrupt is generated whenever PERR=1 in the STAT register

PM

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCEN

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WM

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

WL

Bit 12: Word length.

Allowed values:
0: Bit8: 8 data bits
1: Bit9: 9 data bits

MEN

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

AMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Address match interrupt is disabled
1: Enabled: Address match interrupt is enabled

OVSMOD

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DED

Bits 16-20: Driver Enable deassertion time.

Allowed values: 0-31

DEA

Bits 21-25: Driver Enable assertion time.

Allowed values: 0-31

RTIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Receiver timeout interrupt is disabled
1: Enabled: Receiver timeout interrupt is enabled

EBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: End of block interrupt is disabled
1: Enabled: End of block interrupt is enabled

CTL1

Control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
rw 		RTEN
rw 		ABDM
rw 		ABDEN
rw 		MSBF
rw 		DINV
rw 		TINV
rw 		RINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRP
rw 		LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDM
rw
Toggle Fields.

ADDM

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Full: Full-bit address detection

LBLEN

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: An interrupt is generated whenever LBDF=1 in the STAT register

CLEN

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPH

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPL

Bit 10: Clock polarity.

Allowed values:
0: NotInverted: Steady low value on CK pin outside tranmission window
1: Inverted: Steady high value on CK pin outside tranmission window

CKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STB

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LMEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

STRP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBF

Bit 19: Most significant bit first.

Allowed values:
0: LSB: Data is transmitted/received with data bit 0 first, following the start bit
1: MSB: Data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABDEN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABDM

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement

RTEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADDR

Bits 24-31: Address of the USART node.

Allowed values: 0-255

CTL2

Control register 2

Offset: 0x8, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUIE
rw 		WUM
rw 		SCRTNUM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRD
rw 		OSB
rw 		CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt is disabled
1: Enabled: An interrupt is generated when FERR=1 or ORERR=1 or NERR=1 in the STAT register

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDEN

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NKEN

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DENR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DENT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSEN

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSEN

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: An interrupt is generated whenever CTS=1 in the STAT register

OSB

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRD

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDATA register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCRTNUM

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0-7

WUM

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WUF active on start bit detection
3: RXNE: WUF active on RBNE

WUIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Wake-up from deep-sleep mode interrupt is disabled
1: Enabled: Wake-up from deep-sleep mode interrupt is generated whenever WUF=1 in the STAT register

BAUD

Baud rate register

Offset: 0xC, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: integer of baud-rate divider.

Allowed values: 0-15

INTDIV

Bits 4-15: integer of baud-rate divider.

Allowed values: 0-4095

GP

Guard time and prescaler register

Offset: 0x10, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

Allowed values: 0-255

GUAT

Bits 8-15: Guard time value.

Allowed values: 0-255

RT

Receiver timeout register

Offset: 0x14, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BL
rw 		RT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT
rw
Toggle Fields.

RT

Bits 0-23: Receiver timeout value.

Allowed values: 0-16777215

BL

Bits 24-31: Block Length.

Allowed values: 0-255

CMD

Request register

Offset: 0x18, reset: 0x00000000, access: write-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFCMD
w 		RXFCMD
w 		MMCMD
w 		SBKCMD
w 		ABDCMD
w
Toggle Fields.

ABDCMD

Bit 0: Auto baud rate request.

Allowed values:
1: Request: Resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKCMD

Bit 1: Send break request.

Allowed values:
1: Break: Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMCMD

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFCMD

Bit 3: Receive data flush request.

Allowed values:
1: Discard: Clears the RBNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFCMD

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TBE flag. This allows to discard the transmit data

STAT

Interrupt & status register

Offset: 0x1C, reset: 0x000000C0, access: read-only

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REA
r 		TEA
r 		WUF
r 		RWU
r 		SBF
r 		AMF
r 		BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABDF
r 		ABDE
r 		EBF
r 		RTF
r 		CTS
r 		CTSF
r 		LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error.

FERR

Bit 1: Framing error.

NERR

Bit 2: Noise detected flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: Idle line detected.

RBNE

Bit 5: Read data register not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data register empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS interrupt flag.

CTS

Bit 10: CTS flag.

RTF

Bit 11: Receiver timeout.

EBF

Bit 12: End of block flag.

ABDE

Bit 14: Auto baud rate error.

ABDF

Bit 15: Auto baud rate flag.

BSY

Bit 16: Busy flag.

AMF

Bit 17: character match flag.

SBF

Bit 18: Send break flag.

RWU

Bit 19: Receiver wakeup from Mute mode.

WUF

Bit 20: Wakeup from Stop mode flag.

TEA

Bit 21: Transmit enable acknowledge flag.

REA

Bit 22: Receive enable acknowledge flag.

INTC

Interrupt flag clear register

Offset: 0x20, reset: 0x00000000, access: write-only

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUC
w 		AMC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBC
w 		RTC
w 		CTSC
w 		LBDC
w 		TCC
w 		IDLEC
w 		OREC
w 		NEC
w 		FEC
w 		PEC
w
Toggle Fields.

PEC

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PERR bit in the STAT register

FEC

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FERR bit in the STAT register

NEC

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NERR bit in the STAT register

OREC

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORERR bit in the STAT register

IDLEC

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLEF flag in the STAT register

TCC

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC bit in the STAT register

LBDC

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the STAT register

CTSC

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSF flag in the STAT register

RTC

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RCF flag in the STAT register

EBC

Bit 12: End of timeout clear flag.

Allowed values:
1: Clear: Clears the EBF flag in the STAT register

AMC

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the AMF flag in the STAT register

WUC

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the STAT register

RDATA

Receive data register

Offset: 0x24, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle Fields.

RDATA

Bits 0-8: Receive data value.

Allowed values: 0-511

TDATA

Transmit data register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDATA
rw
Toggle Fields.

TDATA

Bits 0-8: Transmit data value.

Allowed values: 0-255

CHC

coherence control register

Offset: 0xC0, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPERR
rw 		HCM
rw
Toggle Fields.

HCM

Bit 0: Hardware flow control coherence mode.

EPERR

Bit 8: Early parity error flag.

RFCS

USART receive FIFO control and status register

Offset: 0xD0, reset: 0x00000400, access: Unspecified

3/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFFINT
rw 		RFCNT
r 		RFF
r 		RFE
r 		RFFIE
rw 		RFEN
rw 		ELNACK
rw
Toggle Fields.

ELNACK

Bit 0: Early NKEN when smartcard mode is selected.

RFEN

Bit 8: Receive FIFO enable.

RFFIE

Bit 9: Receive FIFO full interrupt enable.

RFE

Bit 10: Receive FIFO empty flag.

RFF

Bit 11: Receive FIFO full flag.

RFCNT

Bits 12-14: Receive FIFO count number.

RFFINT

Bit 15: Receive FIFO full interrupt flag.

WWDGT

0x40002C00: Window watchdog timer

6/6 fields covered. Toggle Registers.

CTL

Control register

Offset: 0x0, reset: 0x0000007F, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGTEN
rw 		CNT
rw
Toggle Fields.

CNT

Bits 0-6: 7-bit counter.

Allowed values: 0-127

WDGTEN

Bit 7: Activation bit.

Allowed values:
0: Disabled: Watchdog disabled
1: Enabled: Watchdog enabled

CFG

Configuration register

Offset: 0x4, reset: 0x0000007F, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIE
rw 		PSC
rw 		WIN
rw
Toggle Fields.

WIN

Bits 0-6: 7-bit window value.

Allowed values: 0-127

PSC

Bits 7-8: Prescaler.

Allowed values:
0: Div1: Counter clock (PCLK1 div 4096) div 1
1: Div2: Counter clock (PCLK1 div 4096) div 2
2: Div4: Counter clock (PCLK1 div 4096) div 4
3: Div8: Counter clock (PCLK1 div 4096) div 8

EWIE

Bit 9: Early wakeup interrupt.

Allowed values:
1: Enable: interrupt occurs whenever the counter reaches the value 0x40

STAT

Status register

Offset: 0x8, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
rw
Toggle Fields.

EWIF

Bit 0: Early wakeup interrupt flag.

Allowed values:
1: Pending: The EWI Interrupt Service Routine has been triggered
0: Finished: The EWI Interrupt Service Routine has been serviced