Overall: 2326/8806 fields covered

ADC0

0x40012400: Analog to digital converter

7/103 fields covered. Toggle Registers.

STAT

status register

Offset: 0x0, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDE2
rw 		WDE1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRC
rw 		STIC
rw 		EOIC
rw 		EOC
rw 		WDE0
rw
Toggle Fields.

WDE0

Bit 0: Analog watchdog event flag.

EOC

Bit 1: End of group conversion flag.

EOIC

Bit 2: End of inserted group conversion flag.

STIC

Bit 3: Start flag of inserted channel group.

STRC

Bit 4: Start flag of regular channel group.

WDE1

Bit 30: Analog watchdog 1 event flag.

WDE2

Bit 31: Analog watchdog 2 event flag.

CTL0

control register 0

Offset: 0x4, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDE2IE
rw 		WDE1IE
rw 		RWD0EN
rw 		IWD0EN
rw 		SYNCM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISNUM
rw 		DISIC
rw 		DISRC
rw 		ICA
rw 		WD0SC
rw 		SM
rw 		EOICIE
rw 		WDE0IE
rw 		EOCIE
rw 		WD0CHSEL
rw
Toggle Fields.

WD0CHSEL

Bits 0-4: Analog watchdog 0 channel select.

EOCIE

Bit 5: Interrupt enable for EOC.

WDE0IE

Bit 6: Interrupt enable for WDE0.

EOICIE

Bit 7: Interrupt enable for EOIC.

SM

Bit 8: Scan mode.

WD0SC

Bit 9: When in scan mode, analog watchdog 0 is effective on a single channel.

ICA

Bit 10: Inserted channel group convert automatically.

DISRC

Bit 11: Discontinuous mode on regular channels.

DISIC

Bit 12: Discontinuous mode on inserted channels.

DISNUM

Bits 13-15: Number of conversions in discontinuous mode.

SYNCM

Bits 16-19: sync mode selection.

IWD0EN

Bit 22: Inserted channel analog watchdog 0 enable.

RWD0EN

Bit 23: Regular channel analog watchdog 0 enable.

WDE1IE

Bit 30: Interrupt enable for WDE1.

WDE2IE

Bit 31: Interrupt enable for WDE2.

CTL1

control register 1

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETSRC_3
rw 		ETSIC_3
rw 		TSVREN
rw 		SWRCST
rw 		SWICST
rw 		ETERC
rw 		ETSRC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETEIC
rw 		ETSIC
rw 		DAL
rw 		DMA
rw 		CALNUM
rw 		RSTCLB
rw 		CLB
rw 		CTN
rw 		ADCON
rw
Toggle Fields.

ADCON

Bit 0: ADC on.

CTN

Bit 1: Continuous mode.

CLB

Bit 2: ADC calibration.

RSTCLB

Bit 3: Reset calibration.

CALNUM

Bits 4-6: Calibration Times.

DMA

Bit 8: DMA request enable.

DAL

Bit 11: Data alignment.

ETSIC

Bits 12-14: External trigger select for inserted channel.

ETEIC

Bit 15: External trigger enable for inserted channel.

ETSRC

Bits 17-19: External trigger select for regular channel.

ETERC

Bit 20: External trigger enable for regular channel.

SWICST

Bit 21: Start on inserted channel.

SWRCST

Bit 22: Start on regular channel.

TSVREN

Bit 23: Channel 16 and 17 enable of ADC0.

ETSIC_3

Bit 30: The third bit of ETSIC.

ETSRC_3

Bit 31: The third bit of ETSRC.

SAMPT0

Sample time register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT17
rw 		SPT16
rw 		SPT15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT15
rw 		SPT14
rw 		SPT13
rw 		SPT12
rw 		SPT11
rw 		SPT10
rw
Toggle Fields.

SPT10

Bits 0-2: Channel 10 sample time selection.

SPT11

Bits 3-5: Channel 11 sample time selection.

SPT12

Bits 6-8: Channel 12 sample time selection.

SPT13

Bits 9-11: Channel 13 sample time selection.

SPT14

Bits 12-14: Channel 14 sample time selection.

SPT15

Bits 15-17: Channel 15 sample time selection.

SPT16

Bits 18-20: Channel 16 sample time selection.

SPT17

Bits 21-23: Channel 17 sample time selection.

SAMPT1

Sample time register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT9
rw 		SPT8
rw 		SPT7
rw 		SPT6
rw 		SPT5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT5
rw 		SPT4
rw 		SPT3
rw 		SPT2
rw 		SPT1
rw 		SPT0
rw
Toggle Fields.

SPT0

Bits 0-2: Channel 0 sample time selection.

SPT1

Bits 3-5: Channel 1 sample time selection.

SPT2

Bits 6-8: Channel 2 sample time selection.

SPT3

Bits 9-11: Channel 3 sample time selection.

SPT4

Bits 12-14: Channel 4 sample time selection.

SPT5

Bits 15-17: Channel 5 sample time selection.

SPT6

Bits 18-20: Channel 6 sample time selection.

SPT7

Bits 21-23: Channel 7 sample time selection.

SPT8

Bits 24-26: Channel 8 sample time selection.

SPT9

Bits 27-29: Channel 9 sample time selection.

IOFF0

Inserted channel data offset register 0

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 0.

IOFF1

Inserted channel data offset register 1

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 1.

IOFF2

Inserted channel data offset register 2

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 2.

IOFF3

Inserted channel data offset register 3

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 3.

WDHT

watchdog higher threshold register 0

Offset: 0x24, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDHT0
rw
Toggle Fields.

WDHT0

Bits 0-11: Analog watchdog 0 higher threshold.

WDLT0

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDLT0
rw
Toggle Fields.

WDLT0

Bits 0-11: Analog watchdog 0 lower threshold.

RSQ0

regular sequence register 0

Offset: 0x2C, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RL
rw 		RSQ15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ15
rw 		RSQ14
rw 		RSQ13
rw 		RSQ12
rw
Toggle Fields.

RSQ12

Bits 0-4: 13th conversion in regular sequence.

RSQ13

Bits 5-9: 14th conversion in regular sequence.

RSQ14

Bits 10-14: 15th conversion in regular sequence.

RSQ15

Bits 15-19: 16th conversion in regular sequence.

RL

Bits 20-23: Regular channel group length.

RSQ1

regular sequence register 1

Offset: 0x30, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ11
rw 		RSQ10
rw 		RSQ9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ9
rw 		RSQ8
rw 		RSQ7
rw 		RSQ6
rw
Toggle Fields.

RSQ6

Bits 0-4: 7th conversion in regular sequence.

RSQ7

Bits 5-9: 8th conversion in regular sequence.

RSQ8

Bits 10-14: 9th conversion in regular sequence.

RSQ9

Bits 15-19: 10th conversion in regular sequence.

RSQ10

Bits 20-24: 11th conversion in regular sequence.

RSQ11

Bits 25-29: 12th conversion in regular sequence.

RSQ2

regular sequence register 2

Offset: 0x34, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ5
rw 		RSQ4
rw 		RSQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ3
rw 		RSQ2
rw 		RSQ1
rw 		RSQ0
rw
Toggle Fields.

RSQ0

Bits 0-4: 1st conversion in regular sequence.

RSQ1

Bits 5-9: 2nd conversion in regular sequence.

RSQ2

Bits 10-14: 3rd conversion in regular sequence.

RSQ3

Bits 15-19: 4th conversion in regular sequence.

RSQ4

Bits 20-24: 5th conversion in regular sequence.

RSQ5

Bits 25-29: 6th conversion in regular sequence.

ISQ

Inserted sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IL
rw 		ISQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISQ3
rw 		ISQ2
rw 		ISQ1
rw 		ISQ0
rw
Toggle Fields.

ISQ0

Bits 0-4: 1st conversion in inserted sequence.

ISQ1

Bits 5-9: 2nd conversion in inserted sequence.

ISQ2

Bits 10-14: 3rd conversion in inserted sequence.

ISQ3

Bits 15-19: 4th conversion in inserted sequence.

IL

Bits 20-21: Inserted channel group length.

IDATA0

Inserted data register 0

Offset: 0x3C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

IDATA1

Inserted data register 1

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

IDATA2

Inserted data register 2

Offset: 0x44, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

IDATA3

Inserted data register 3

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

RDATA

regular data register

Offset: 0x4C, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADC1RDTR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle Fields.

RDATA

Bits 0-15: Regular channel data.

ADC1RDTR

Bits 16-31: ADCegular channel data.

OVSAMPCTL

Oversample control register

Offset: 0x80, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRES
rw 		TOVS
rw 		OVSS
rw 		OVSR
rw 		OVSEN
rw
Toggle Fields.

OVSEN

Bit 0: Oversampling Enable.

OVSR

Bits 2-4: Oversampling ratio.

OVSS

Bits 5-8: Oversampling shift.

TOVS

Bit 9: Triggered Oversampling.

DRES

Bits 12-13: ADC resolution.

WD1SR

Watchdog 1 Channel Selection Register

Offset: 0xA0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD1CS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD1CS
rw
Toggle Fields.

AWD1CS

Bits 0-17: Analog watchdog 1 channel selection.

WD2SR

Watchdog 2 Channel Selection Register

Offset: 0xA4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD2CS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD2CS
rw
Toggle Fields.

AWD2CS

Bits 0-17: Analog watchdog 2 channel selection.

WDT1

Watchdog threshold register 1

Offset: 0xA8, reset: 0x00FF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDHT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDLT1
rw
Toggle Fields.

WDLT1

Bits 0-7: Analog watchdog 1 low threshold.

WDHT1

Bits 16-23: Analog watchdog 1 high threshold.

WDT2

Watchdog threshold register 2

Offset: 0xAC, reset: 0x00FF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDHT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDLT2
rw
Toggle Fields.

WDLT2

Bits 0-7: Analog watchdog 2 low threshold.

WDHT2

Bits 16-23: Analog watchdog 2 high threshold.

DIFCTL

Differential mode control register

Offset: 0xB0, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIFCTL_17_15
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIFCTL_17_15
r 		DIFCTL_14_0
rw
Toggle Fields.

DIFCTL_14_0

Bits 0-14: Differential mode for channel 14 to 0.

DIFCTL_17_15

Bits 15-17: Differential mode for channel 17 to 15.

ADC1

0x40012800: Analog to digital converter

7/102 fields covered. Toggle Registers.

STAT

status register

Offset: 0x0, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDE2
rw 		WDE1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRC
rw 		STIC
rw 		EOIC
rw 		EOC
rw 		WDE0
rw
Toggle Fields.

WDE0

Bit 0: Analog watchdog event flag.

EOC

Bit 1: End of group conversion flag.

EOIC

Bit 2: End of inserted group conversion flag.

STIC

Bit 3: Start flag of inserted channel group.

STRC

Bit 4: Start flag of regular channel group.

WDE1

Bit 30: Analog watchdog 1 event flag.

WDE2

Bit 31: Analog watchdog 2 event flag.

CTL0

control register 0

Offset: 0x4, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDE2IE
rw 		WDE1IE
rw 		RWD0EN
rw 		IWD0EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISNUM
rw 		DISIC
rw 		DISRC
rw 		ICA
rw 		WD0SC
rw 		SM
rw 		EOICIE
rw 		WDE0IE
rw 		EOCIE
rw 		WD0CHSEL
rw
Toggle Fields.

WD0CHSEL

Bits 0-4: Analog watchdog 0 channel select.

EOCIE

Bit 5: Interrupt enable for EOC.

WDE0IE

Bit 6: Interrupt enable for WDE0.

EOICIE

Bit 7: Interrupt enable for EOIC.

SM

Bit 8: Scan mode.

WD0SC

Bit 9: When in scan mode, analog watchdog 0 is effective on a single channel.

ICA

Bit 10: Inserted channel group convert automatically.

DISRC

Bit 11: Discontinuous mode on regular channels.

DISIC

Bit 12: Discontinuous mode on inserted channels.

DISNUM

Bits 13-15: Number of conversions in discontinuous mode.

IWD0EN

Bit 22: Inserted channel analog watchdog 0 enable.

RWD0EN

Bit 23: Regular channel analog watchdog 0 enable.

WDE1IE

Bit 30: Interrupt enable for WDE1.

WDE2IE

Bit 31: Interrupt enable for WDE2.

CTL1

control register 1

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETSRC_3
rw 		ETSIC_3
rw 		TSVREN
rw 		SWRCST
rw 		SWICST
rw 		ETERC
rw 		ETSRC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETEIC
rw 		ETSIC
rw 		DAL
rw 		DMA
rw 		CALNUM
rw 		RSTCLB
rw 		CLB
rw 		CTN
rw 		ADCON
rw
Toggle Fields.

ADCON

Bit 0: ADC on.

CTN

Bit 1: Continuous mode.

CLB

Bit 2: ADC calibration.

RSTCLB

Bit 3: Reset calibration.

CALNUM

Bits 4-6: Calibration Times.

DMA

Bit 8: DMA request enable.

DAL

Bit 11: Data alignment.

ETSIC

Bits 12-14: External trigger select for inserted channel.

ETEIC

Bit 15: External trigger enable for inserted channel.

ETSRC

Bits 17-19: External trigger select for regular channel.

ETERC

Bit 20: External trigger enable for regular channel.

SWICST

Bit 21: Start on inserted channel.

SWRCST

Bit 22: Start on regular channel.

TSVREN

Bit 23: Channel 16 and 17 enable of ADC0.

ETSIC_3

Bit 30: The third bit of ETSIC.

ETSRC_3

Bit 31: The third bit of ETSRC.

SAMPT0

Sample time register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT17
rw 		SPT16
rw 		SPT15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT15
rw 		SPT14
rw 		SPT13
rw 		SPT12
rw 		SPT11
rw 		SPT10
rw
Toggle Fields.

SPT10

Bits 0-2: Channel 10 sample time selection.

SPT11

Bits 3-5: Channel 11 sample time selection.

SPT12

Bits 6-8: Channel 12 sample time selection.

SPT13

Bits 9-11: Channel 13 sample time selection.

SPT14

Bits 12-14: Channel 14 sample time selection.

SPT15

Bits 15-17: Channel 15 sample time selection.

SPT16

Bits 18-20: Channel 16 sample time selection.

SPT17

Bits 21-23: Channel 17 sample time selection.

SAMPT1

Sample time register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT9
rw 		SPT8
rw 		SPT7
rw 		SPT6
rw 		SPT5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT5
rw 		SPT4
rw 		SPT3
rw 		SPT2
rw 		SPT1
rw 		SPT0
rw
Toggle Fields.

SPT0

Bits 0-2: Channel 0 sample time selection.

SPT1

Bits 3-5: Channel 1 sample time selection.

SPT2

Bits 6-8: Channel 2 sample time selection.

SPT3

Bits 9-11: Channel 3 sample time selection.

SPT4

Bits 12-14: Channel 4 sample time selection.

SPT5

Bits 15-17: Channel 5 sample time selection.

SPT6

Bits 18-20: Channel 6 sample time selection.

SPT7

Bits 21-23: Channel 7 sample time selection.

SPT8

Bits 24-26: Channel 8 sample time selection.

SPT9

Bits 27-29: Channel 9 sample time selection.

IOFF0

Inserted channel data offset register 0

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 0.

IOFF1

Inserted channel data offset register 1

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 1.

IOFF2

Inserted channel data offset register 2

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 2.

IOFF3

Inserted channel data offset register 3

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 3.

WDHT

watchdog higher threshold register 0

Offset: 0x24, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDHT0
rw
Toggle Fields.

WDHT0

Bits 0-11: Analog watchdog 0 higher threshold.

WDLT0

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDLT0
rw
Toggle Fields.

WDLT0

Bits 0-11: Analog watchdog 0 lower threshold.

RSQ0

regular sequence register 0

Offset: 0x2C, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RL
rw 		RSQ15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ15
rw 		RSQ14
rw 		RSQ13
rw 		RSQ12
rw
Toggle Fields.

RSQ12

Bits 0-4: 13th conversion in regular sequence.

RSQ13

Bits 5-9: 14th conversion in regular sequence.

RSQ14

Bits 10-14: 15th conversion in regular sequence.

RSQ15

Bits 15-19: 16th conversion in regular sequence.

RL

Bits 20-23: Regular channel group length.

RSQ1

regular sequence register 1

Offset: 0x30, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ11
rw 		RSQ10
rw 		RSQ9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ9
rw 		RSQ8
rw 		RSQ7
rw 		RSQ6
rw
Toggle Fields.

RSQ6

Bits 0-4: 7th conversion in regular sequence.

RSQ7

Bits 5-9: 8th conversion in regular sequence.

RSQ8

Bits 10-14: 9th conversion in regular sequence.

RSQ9

Bits 15-19: 10th conversion in regular sequence.

RSQ10

Bits 20-24: 11th conversion in regular sequence.

RSQ11

Bits 25-29: 12th conversion in regular sequence.

RSQ2

regular sequence register 2

Offset: 0x34, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ5
rw 		RSQ4
rw 		RSQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ3
rw 		RSQ2
rw 		RSQ1
rw 		RSQ0
rw
Toggle Fields.

RSQ0

Bits 0-4: 1st conversion in regular sequence.

RSQ1

Bits 5-9: 2nd conversion in regular sequence.

RSQ2

Bits 10-14: 3rd conversion in regular sequence.

RSQ3

Bits 15-19: 4th conversion in regular sequence.

RSQ4

Bits 20-24: 5th conversion in regular sequence.

RSQ5

Bits 25-29: 6th conversion in regular sequence.

ISQ

Inserted sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IL
rw 		ISQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISQ3
rw 		ISQ2
rw 		ISQ1
rw 		ISQ0
rw
Toggle Fields.

ISQ0

Bits 0-4: 1st conversion in inserted sequence.

ISQ1

Bits 5-9: 2nd conversion in inserted sequence.

ISQ2

Bits 10-14: 3rd conversion in inserted sequence.

ISQ3

Bits 15-19: 4th conversion in inserted sequence.

IL

Bits 20-21: Inserted channel group length.

IDATA0

Inserted data register 0

Offset: 0x3C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

IDATA1

Inserted data register 1

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

IDATA2

Inserted data register 2

Offset: 0x44, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

IDATA3

Inserted data register 3

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

RDATA

regular data register

Offset: 0x4C, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADC1RDTR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle Fields.

RDATA

Bits 0-15: Regular channel data.

ADC1RDTR

Bits 16-31: ADCegular channel data.

OVSAMPCTL

Oversample control register

Offset: 0x80, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRES
rw 		TOVS
rw 		OVSS
rw 		OVSR
rw 		OVSEN
rw
Toggle Fields.

OVSEN

Bit 0: Oversampling Enable.

OVSR

Bits 2-4: Oversampling ratio.

OVSS

Bits 5-8: Oversampling shift.

TOVS

Bit 9: Triggered Oversampling.

DRES

Bits 12-13: ADC resolution.

WD1SR

Watchdog 1 Channel Selection Register

Offset: 0xA0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD1CS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD1CS
rw
Toggle Fields.

AWD1CS

Bits 0-17: Analog watchdog 1 channel selection.

WD2SR

Watchdog 2 Channel Selection Register

Offset: 0xA4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD2CS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD2CS
rw
Toggle Fields.

AWD2CS

Bits 0-17: Analog watchdog 2 channel selection.

WDT1

Watchdog threshold register 1

Offset: 0xA8, reset: 0x00FF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDHT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDLT1
rw
Toggle Fields.

WDLT1

Bits 0-7: Analog watchdog 1 low threshold.

WDHT1

Bits 16-23: Analog watchdog 1 high threshold.

WDT2

Watchdog threshold register 2

Offset: 0xAC, reset: 0x00FF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDHT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDLT2
rw
Toggle Fields.

WDLT2

Bits 0-7: Analog watchdog 2 low threshold.

WDHT2

Bits 16-23: Analog watchdog 2 high threshold.

DIFCTL

Differential mode control register

Offset: 0xB0, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIFCTL_17_15
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIFCTL_17_15
r 		DIFCTL_14_0
rw
Toggle Fields.

DIFCTL_14_0

Bits 0-14: Differential mode for channel 14 to 0.

DIFCTL_17_15

Bits 15-17: Differential mode for channel 17 to 15.

ADC2

0x40013C00: Analog to digital converter

7/102 fields covered. Toggle Registers.

STAT

status register

Offset: 0x0, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDE2
rw 		WDE1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRC
rw 		STIC
rw 		EOIC
rw 		EOC
rw 		WDE0
rw
Toggle Fields.

WDE0

Bit 0: Analog watchdog event flag.

EOC

Bit 1: End of group conversion flag.

EOIC

Bit 2: End of inserted group conversion flag.

STIC

Bit 3: Start flag of inserted channel group.

STRC

Bit 4: Start flag of regular channel group.

WDE1

Bit 30: Analog watchdog 1 event flag.

WDE2

Bit 31: Analog watchdog 2 event flag.

CTL0

control register 0

Offset: 0x4, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDE2IE
rw 		WDE1IE
rw 		RWD0EN
rw 		IWD0EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISNUM
rw 		DISIC
rw 		DISRC
rw 		ICA
rw 		WD0SC
rw 		SM
rw 		EOICIE
rw 		WDE0IE
rw 		EOCIE
rw 		WD0CHSEL
rw
Toggle Fields.

WD0CHSEL

Bits 0-4: Analog watchdog 0 channel select.

EOCIE

Bit 5: Interrupt enable for EOC.

WDE0IE

Bit 6: Interrupt enable for WDE0.

EOICIE

Bit 7: Interrupt enable for EOIC.

SM

Bit 8: Scan mode.

WD0SC

Bit 9: When in scan mode, analog watchdog 0 is effective on a single channel.

ICA

Bit 10: Inserted channel group convert automatically.

DISRC

Bit 11: Discontinuous mode on regular channels.

DISIC

Bit 12: Discontinuous mode on inserted channels.

DISNUM

Bits 13-15: Number of conversions in discontinuous mode.

IWD0EN

Bit 22: Inserted channel analog watchdog 0 enable.

RWD0EN

Bit 23: Regular channel analog watchdog 0 enable.

WDE1IE

Bit 30: Interrupt enable for WDE1.

WDE2IE

Bit 31: Interrupt enable for WDE2.

CTL1

control register 1

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETSRC_3
rw 		ETSIC_3
rw 		TSVREN
rw 		SWRCST
rw 		SWICST
rw 		ETERC
rw 		ETSRC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETEIC
rw 		ETSIC
rw 		DAL
rw 		DMA
rw 		CALNUM
rw 		RSTCLB
rw 		CLB
rw 		CTN
rw 		ADCON
rw
Toggle Fields.

ADCON

Bit 0: ADC on.

CTN

Bit 1: Continuous mode.

CLB

Bit 2: ADC calibration.

RSTCLB

Bit 3: Reset calibration.

CALNUM

Bits 4-6: Calibration Times.

DMA

Bit 8: DMA request enable.

DAL

Bit 11: Data alignment.

ETSIC

Bits 12-14: External trigger select for inserted channel.

ETEIC

Bit 15: External trigger enable for inserted channel.

ETSRC

Bits 17-19: External trigger select for regular channel.

ETERC

Bit 20: External trigger enable for regular channel.

SWICST

Bit 21: Start on inserted channel.

SWRCST

Bit 22: Start on regular channel.

TSVREN

Bit 23: Channel 16 and 17 enable of ADC0.

ETSIC_3

Bit 30: The third bit of ETSIC.

ETSRC_3

Bit 31: The third bit of ETSRC.

SAMPT0

Sample time register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT17
rw 		SPT16
rw 		SPT15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT15
rw 		SPT14
rw 		SPT13
rw 		SPT12
rw 		SPT11
rw 		SPT10
rw
Toggle Fields.

SPT10

Bits 0-2: Channel 10 sample time selection.

SPT11

Bits 3-5: Channel 11 sample time selection.

SPT12

Bits 6-8: Channel 12 sample time selection.

SPT13

Bits 9-11: Channel 13 sample time selection.

SPT14

Bits 12-14: Channel 14 sample time selection.

SPT15

Bits 15-17: Channel 15 sample time selection.

SPT16

Bits 18-20: Channel 16 sample time selection.

SPT17

Bits 21-23: Channel 17 sample time selection.

SAMPT1

Sample time register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT9
rw 		SPT8
rw 		SPT7
rw 		SPT6
rw 		SPT5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT5
rw 		SPT4
rw 		SPT3
rw 		SPT2
rw 		SPT1
rw 		SPT0
rw
Toggle Fields.

SPT0

Bits 0-2: Channel 0 sample time selection.

SPT1

Bits 3-5: Channel 1 sample time selection.

SPT2

Bits 6-8: Channel 2 sample time selection.

SPT3

Bits 9-11: Channel 3 sample time selection.

SPT4

Bits 12-14: Channel 4 sample time selection.

SPT5

Bits 15-17: Channel 5 sample time selection.

SPT6

Bits 18-20: Channel 6 sample time selection.

SPT7

Bits 21-23: Channel 7 sample time selection.

SPT8

Bits 24-26: Channel 8 sample time selection.

SPT9

Bits 27-29: Channel 9 sample time selection.

IOFF0

Inserted channel data offset register 0

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 0.

IOFF1

Inserted channel data offset register 1

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 1.

IOFF2

Inserted channel data offset register 2

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 2.

IOFF3

Inserted channel data offset register 3

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 3.

WDHT

watchdog higher threshold register 0

Offset: 0x24, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDHT0
rw
Toggle Fields.

WDHT0

Bits 0-11: Analog watchdog 0 higher threshold.

WDLT0

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDLT0
rw
Toggle Fields.

WDLT0

Bits 0-11: Analog watchdog 0 lower threshold.

RSQ0

regular sequence register 0

Offset: 0x2C, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RL
rw 		RSQ15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ15
rw 		RSQ14
rw 		RSQ13
rw 		RSQ12
rw
Toggle Fields.

RSQ12

Bits 0-4: 13th conversion in regular sequence.

RSQ13

Bits 5-9: 14th conversion in regular sequence.

RSQ14

Bits 10-14: 15th conversion in regular sequence.

RSQ15

Bits 15-19: 16th conversion in regular sequence.

RL

Bits 20-23: Regular channel group length.

RSQ1

regular sequence register 1

Offset: 0x30, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ11
rw 		RSQ10
rw 		RSQ9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ9
rw 		RSQ8
rw 		RSQ7
rw 		RSQ6
rw
Toggle Fields.

RSQ6

Bits 0-4: 7th conversion in regular sequence.

RSQ7

Bits 5-9: 8th conversion in regular sequence.

RSQ8

Bits 10-14: 9th conversion in regular sequence.

RSQ9

Bits 15-19: 10th conversion in regular sequence.

RSQ10

Bits 20-24: 11th conversion in regular sequence.

RSQ11

Bits 25-29: 12th conversion in regular sequence.

RSQ2

regular sequence register 2

Offset: 0x34, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ5
rw 		RSQ4
rw 		RSQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ3
rw 		RSQ2
rw 		RSQ1
rw 		RSQ0
rw
Toggle Fields.

RSQ0

Bits 0-4: 1st conversion in regular sequence.

RSQ1

Bits 5-9: 2nd conversion in regular sequence.

RSQ2

Bits 10-14: 3rd conversion in regular sequence.

RSQ3

Bits 15-19: 4th conversion in regular sequence.

RSQ4

Bits 20-24: 5th conversion in regular sequence.

RSQ5

Bits 25-29: 6th conversion in regular sequence.

ISQ

Inserted sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IL
rw 		ISQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISQ3
rw 		ISQ2
rw 		ISQ1
rw 		ISQ0
rw
Toggle Fields.

ISQ0

Bits 0-4: 1st conversion in inserted sequence.

ISQ1

Bits 5-9: 2nd conversion in inserted sequence.

ISQ2

Bits 10-14: 3rd conversion in inserted sequence.

ISQ3

Bits 15-19: 4th conversion in inserted sequence.

IL

Bits 20-21: Inserted channel group length.

IDATA0

Inserted data register 0

Offset: 0x3C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

IDATA1

Inserted data register 1

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

IDATA2

Inserted data register 2

Offset: 0x44, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

IDATA3

Inserted data register 3

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

RDATA

regular data register

Offset: 0x4C, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADC1RDTR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle Fields.

RDATA

Bits 0-15: Regular channel data.

ADC1RDTR

Bits 16-31: ADCegular channel data.

OVSAMPCTL

Oversample control register

Offset: 0x80, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRES
rw 		TOVS
rw 		OVSS
rw 		OVSR
rw 		OVSEN
rw
Toggle Fields.

OVSEN

Bit 0: Oversampling Enable.

OVSR

Bits 2-4: Oversampling ratio.

OVSS

Bits 5-8: Oversampling shift.

TOVS

Bit 9: Triggered Oversampling.

DRES

Bits 12-13: ADC resolution.

WD1SR

Watchdog 1 Channel Selection Register

Offset: 0xA0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD1CS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD1CS
rw
Toggle Fields.

AWD1CS

Bits 0-17: Analog watchdog 1 channel selection.

WD2SR

Watchdog 2 Channel Selection Register

Offset: 0xA4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD2CS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD2CS
rw
Toggle Fields.

AWD2CS

Bits 0-17: Analog watchdog 2 channel selection.

WDT1

Watchdog threshold register 1

Offset: 0xA8, reset: 0x00FF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDHT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDLT1
rw
Toggle Fields.

WDLT1

Bits 0-7: Analog watchdog 1 low threshold.

WDHT1

Bits 16-23: Analog watchdog 1 high threshold.

WDT2

Watchdog threshold register 2

Offset: 0xAC, reset: 0x00FF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDHT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDLT2
rw
Toggle Fields.

WDLT2

Bits 0-7: Analog watchdog 2 low threshold.

WDHT2

Bits 16-23: Analog watchdog 2 high threshold.

DIFCTL

Differential mode control register

Offset: 0xB0, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIFCTL_17_15
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIFCTL_17_15
r 		DIFCTL_14_0
rw
Toggle Fields.

DIFCTL_14_0

Bits 0-14: Differential mode for channel 14 to 0.

DIFCTL_17_15

Bits 15-17: Differential mode for channel 17 to 15.

AFIO

0x40010000: Alternate-function I/Os

1/100 fields covered. Toggle Registers.

EC

Event control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOE
rw 		PORT
rw 		PIN
rw
Toggle Fields.

PIN

Bits 0-3: Event output pin selection.

PORT

Bits 4-6: Event output port selection.

EOE

Bit 7: Event output enable.

PCF0

AFIO port configuration register 0

Offset: 0x4, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTP_PPS_REMAP
rw 		TIMER1ITR0_REMAP
rw 		SPI2_REMAP
rw 		SWJ_CFG
rw 		ENET_PHY_SEL
rw 		CAN1_REMAP
rw 		ENET_REMAP
rw 		TIMER4CH3_IREMAP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD01_REMAP
rw 		CAN0_REMAP
rw 		TIMER3_REMAP
rw 		TIMER2_REMAP
rw 		TIMER1_REMAP
rw 		TIMER0_REMAP
rw 		USART2_REMAP
rw 		USART1_REMAP
rw 		USART0_REMAP
rw 		I2C0_REMAP
rw 		SPI0_REMAP
rw
Toggle Fields.

SPI0_REMAP

Bit 0: SPI0 remapping.

I2C0_REMAP

Bit 1: I2C0 remapping.

USART0_REMAP

Bit 2: USART0 remapping.

USART1_REMAP

Bit 3: USART1 remapping.

USART2_REMAP

Bits 4-5: USART2 remapping.

TIMER0_REMAP

Bits 6-7: TIMER0 remapping.

TIMER1_REMAP

Bits 8-9: TIMER1 remapping.

TIMER2_REMAP

Bits 10-11: TIMER2 remapping.

TIMER3_REMAP

Bit 12: TIMER3 remapping.

CAN0_REMAP

Bits 13-14: CAN0 alternate interface remapping.

PD01_REMAP

Bit 15: Port D0/Port D1 mapping on OSC_IN/OSC_OUT.

TIMER4CH3_IREMAP

Bit 16: TIMER4 channel3 internal remapping.

ENET_REMAP

Bit 21: Ethernet MAC I/O remapping.

CAN1_REMAP

Bit 22: CAN1 I/O remapping.

ENET_PHY_SEL

Bit 23: Ethernet MII or RMII PHY selection.

SWJ_CFG

Bits 24-26: Serial wire JTAG configuration.

SPI2_REMAP

Bit 28: SPI2/I2S2 remapping.

TIMER1ITR0_REMAP

Bit 29: TIMER1 internal trigger 0 remapping.

PTP_PPS_REMAP

Bit 30: Ethernet PTP PPS remapping.

EXTISS0

EXTI sources selection register 0

Offset: 0x8, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3_SS
rw 		EXTI2_SS
rw 		EXTI1_SS
rw 		EXTI0_SS
rw
Toggle Fields.

EXTI0_SS

Bits 0-3: EXTI 0 sources selection.

EXTI1_SS

Bits 4-7: EXTI 1 sources selection.

EXTI2_SS

Bits 8-11: EXTI 2 sources selection.

EXTI3_SS

Bits 12-15: EXTI 3 sources selection.

EXTISS1

EXTI sources selection register 1

Offset: 0xC, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7_SS
rw 		EXTI6_SS
rw 		EXTI5_SS
rw 		EXTI4_SS
rw
Toggle Fields.

EXTI4_SS

Bits 0-3: EXTI 4 sources selection.

EXTI5_SS

Bits 4-7: EXTI 5 sources selection.

EXTI6_SS

Bits 8-11: EXTI 6 sources selection.

EXTI7_SS

Bits 12-15: EXTI 7 sources selection.

EXTISS2

EXTI sources selection register 2

Offset: 0x10, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11_SS
rw 		EXTI10_SS
rw 		EXTI9_SS
rw 		EXTI8_SS
rw
Toggle Fields.

EXTI8_SS

Bits 0-3: EXTI 8 sources selection.

EXTI9_SS

Bits 4-7: EXTI 9 sources selection.

EXTI10_SS

Bits 8-11: EXTI 10 sources selection.

EXTI11_SS

Bits 12-15: EXTI 11 sources selection.

EXTISS3

EXTI sources selection register 3

Offset: 0x14, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15_SS
rw 		EXTI14_SS
rw 		EXTI13_SS
rw 		EXTI12_SS
rw
Toggle Fields.

EXTI12_SS

Bits 0-3: EXTI 12 sources selection.

EXTI13_SS

Bits 4-7: EXTI 13 sources selection.

EXTI14_SS

Bits 8-11: EXTI 14 sources selection.

EXTI15_SS

Bits 12-15: EXTI 15 sources selection.

PCF1

AFIO port configuration register 1

Offset: 0x1C, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTC_REMAP
rw 		EXMC_NADV
rw 		TIMER13_REMAP
rw 		TIMER12_REMAP
rw 		TIMER10_REMAP
rw 		TIMER9_REMAP
rw 		TIMER8_REMAP
rw
Toggle Fields.

TIMER8_REMAP

Bit 5: TIMER8 remapping.

TIMER9_REMAP

Bit 6: TIMER9 remapping.

TIMER10_REMAP

Bit 7: TIMER10 remapping.

TIMER12_REMAP

Bit 8: TIMER12 remapping.

TIMER13_REMAP

Bit 9: TIMER13 remapping.

EXMC_NADV

Bit 10: EXMC_NADV connect/disconnect.

CTC_REMAP

Bits 11-12: CTC remapping.

CPSCTL

IO compensation control register

Offset: 0x20, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPS_RDY
r 		CPS_EN
rw
Toggle Fields.

CPS_EN

Bit 0: I/O compensation cell enable.

CPS_RDY

Bit 8: I/O compensation cell is really or not.

PCFA

AFIO port configuration register A

Offset: 0x3C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA15_AFCFG
rw 		PA12_AFCFG
rw 		PA11_AFCFG
rw 		PA10_AFCFG
rw 		PA9_AFCFG
rw 		PA8_AFCFG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA5_AFCFG
rw 		PA3_AFCFG
rw 		PA2_AFCFG
rw
Toggle Fields.

PA2_AFCFG

Bit 4: PA2 AF function configuration bitse.

PA3_AFCFG

Bit 6: PA3 AF function configuration bitse.

PA5_AFCFG

Bit 10: PA5 AF function configuration bitse.

PA8_AFCFG

Bits 16-17: PA8 AF function configuration bitse.

PA9_AFCFG

Bits 18-19: PA9 AF function configuration bitse.

PA10_AFCFG

Bits 20-21: PA10 AF function configuration bitse.

PA11_AFCFG

Bits 22-23: PA11 AF function configuration bitse.

PA12_AFCFG

Bits 24-25: PA12 AF function configuration bitse.

PA15_AFCFG

Bit 30: PA15 AF function configuration bit.

PCFB

AFIO port configuration register B

Offset: 0x40, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PB15_AFCFG
rw 		PB14_AFCFG
rw 		PB13_AFCFG
rw 		PB12_AFCFG
rw 		PB11_AFCFG
rw 		PB10_AFCFG
rw 		PB9_AFCFG
rw 		PB8_AFCFG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PB7_AFCFG
rw 		PB6_AFCFG
rw 		PB5_AFCFG
rw 		PB4_AFCFG
rw 		PB3_AFCFG
rw 		PB2_AFCFG
rw 		PB1_AFCFG
rw 		PB0_AFCFG
rw
Toggle Fields.

PB0_AFCFG

Bit 0: PB0 AF function configuration bitse.

PB1_AFCFG

Bits 2-3: PB1 AF function configuration bitse.

PB2_AFCFG

Bits 4-5: PB2 AF function configuration bitse.

PB3_AFCFG

Bit 6: PB3 AF function configuration bitse.

PB4_AFCFG

Bits 8-9: PB4 AF function configuration bitse.

PB5_AFCFG

Bits 10-11: PB5 AF function configuration bitse.

PB6_AFCFG

Bit 12: PB6 AF function configuration bitse.

PB7_AFCFG

Bit 14: PB7 AF function configuration bitse.

PB8_AFCFG

Bits 16-17: PB8 AF function configuration bitse.

PB9_AFCFG

Bits 18-19: PB9 AF function configuration bitse.

PB10_AFCFG

Bits 20-21: PB10 AF function configuration bitse.

PB11_AFCFG

Bits 22-23: PB11 AF function configuration bitse.

PB12_AFCFG

Bits 24-25: PB12 AF function configuration bitse.

PB13_AFCFG

Bits 26-27: PB13 AF function configuration bit.

PB14_AFCFG

Bits 28-29: PB14 AF function configuration bit.

PB15_AFCFG

Bit 30: PB15 AF function configuration bit.

PCFC

AFIO port configuration register C

Offset: 0x44, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PC12_AFCFG
rw 		PC11_AFCFG
rw 		PC10_AFCFG
rw 		PC9_AFCFG
rw 		PC8_AFCFG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PC7_AFCFG
rw 		PC6_AFCFG
rw 		PC3_AFCFG
rw 		PC2_AFCFG
rw 		PC0_AFCFG
rw
Toggle Fields.

PC0_AFCFG

Bit 0: PC0 AF function configuration bitse.

PC2_AFCFG

Bits 4-5: PC2 AF function configuration bitse.

PC3_AFCFG

Bit 6: PC3 AF function configuration bitse.

PC6_AFCFG

Bits 12-13: PC6 AF function configuration bitse.

PC7_AFCFG

Bits 14-15: PC7 AF function configuration bitse.

PC8_AFCFG

Bits 16-17: PC8 AF function configuration bitse.

PC9_AFCFG

Bits 18-19: PC9 AF function configuration bitse.

PC10_AFCFG

Bit 20: PC10 AF function configuration bitse.

PC11_AFCFG

Bits 22-23: PC11 AF function configuration bitse.

PC12_AFCFG

Bit 24: PC12 AF function configuration bitse.

PCFD

AFIO port configuration register D

Offset: 0x48, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD5_AFCFG
rw 		PD4_AFCFG
rw
Toggle Fields.

PD4_AFCFG

Bit 8: PD4 AF function configuration bitse.

PD5_AFCFG

Bit 10: PD5 AF function configuration bitse.

PCFE

AFIO port configuration register E

Offset: 0x4C, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PE13_AFCFG
rw 		PE12_AFCFG
rw 		PE11_AFCFG
rw 		PE10_AFCFG
rw 		PE9_AFCFG
rw 		PE8_AFCFG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PE1_AFCFG
rw 		PE0_AFCFG
rw
Toggle Fields.

PE0_AFCFG

Bits 0-1: PE0 AF function configuration bitse.

PE1_AFCFG

Bits 2-3: PE1 AF function configuration bitse.

PE8_AFCFG

Bits 16-17: PE8 AF function configuration bitse.

PE9_AFCFG

Bits 18-19: PE9 AF function configuration bitse.

PE10_AFCFG

Bit 20: PE10 AF function configuration bitse.

PE11_AFCFG

Bits 22-23: PE11 AF function configuration bitse.

PE12_AFCFG

Bit 24: PE12 AF function configuration bitse.

PE13_AFCFG

Bit 26: PE13 AF function configuration bitse.

PCFG

AFIO port configuration register G

Offset: 0x54, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PG14_AFCFG
rw 		PG13_AFCFG
rw 		PG12_AFCFG
rw 		PG11_AFCFG
rw 		PG10_AFCFG
rw 		PG9_AFCFG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PG7_AFCFG
rw 		PG6_AFCFG
rw
Toggle Fields.

PG6_AFCFG

Bit 12: PG6 AF function configuration bitse.

PG7_AFCFG

Bits 14-15: PG7 AF function configuration bitse.

PG9_AFCFG

Bits 18-19: PG9 AF function configuration bitse.

PG10_AFCFG

Bit 20: PG10 AF function configuration bitse.

PG11_AFCFG

Bits 22-23: PG11 AF function configuration bitse.

PG12_AFCFG

Bit 24: PG12 AF function configuration bitse.

PG13_AFCFG

Bit 26: PG13 AF function configuration bitse.

PG14_AFCFG

Bit 28: PG14 AF function configuration bitse.

BKP

0x40006C00: Backup registers

0/55 fields covered. Toggle Registers.

DATA0

Backup data register 0

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA1

Backup data register 1

Offset: 0x8, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA2

Backup data register 2

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA3

Backup data register 3

Offset: 0x10, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA4

Backup data register 4

Offset: 0x14, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA5

Backup data register 5

Offset: 0x18, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA6

Backup data register 6

Offset: 0x1C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA7

Backup data register 7

Offset: 0x20, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA8

Backup data register 8

Offset: 0x24, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA9

Backup data register 9

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

OCTL

RTC signal output control register

Offset: 0x2C, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALDIR
rw 		CCOSEL
rw 		ROSEL
rw 		ASOEN
rw 		COEN
rw 		RCCV
rw
Toggle Fields.

RCCV

Bits 0-6: RTC clock calibration value.

COEN

Bit 7: RTC clock calibration output enable.

ASOEN

Bit 8: RTC alarm or second signal output enable.

ROSEL

Bit 9: RTC output selection.

CCOSEL

Bit 14: RTC clock output selection.

CALDIR

Bit 15: RTC clock calibration direction.

TPCTL

Tamper pin control register

Offset: 0x30, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPAL
rw 		TPEN
rw
Toggle Fields.

TPEN

Bit 0: TAMPER detection enable.

TPAL

Bit 1: TAMPER pin active level.

TPCS

Tamper control and status register

Offset: 0x34, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIF
rw 		TEF
rw 		TPIE
rw 		TIR
rw 		TER
rw
Toggle Fields.

TER

Bit 0: Tamper event reset.

TIR

Bit 1: Tamper interrupt reset.

TPIE

Bit 2: Tamper interrupt enable.

TEF

Bit 8: Tamper event flag.

TIF

Bit 9: Tamper interrupt flag.

DATA10

Backup data register 10

Offset: 0x40, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA11

Backup data register 11

Offset: 0x44, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA12

Backup data register 12

Offset: 0x48, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA13

Backup data register 13

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA14

Backup data register 14

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA15

Backup data register 15

Offset: 0x54, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA16

Backup data register 16

Offset: 0x58, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA17

Backup data register 17

Offset: 0x5C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA18

Backup data register 18

Offset: 0x60, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA19

Backup data register 19

Offset: 0x64, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA20

Backup data register 20

Offset: 0x68, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA21

Backup data register 21

Offset: 0x6C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA22

Backup data register 22

Offset: 0x70, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA23

Backup data register 23

Offset: 0x74, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA24

Backup data register 24

Offset: 0x78, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA25

Backup data register 25

Offset: 0x7C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA26

Backup data register 26

Offset: 0x80, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA27

Backup data register 27

Offset: 0x84, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA28

Backup data register 28

Offset: 0x88, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA29

Backup data register 29

Offset: 0x8C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA30

Backup data register 30

Offset: 0x90, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA31

Backup data register 31

Offset: 0x94, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA32

Backup data register 32

Offset: 0x98, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA33

Backup data register 33

Offset: 0x9C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA34

Backup data register 34

Offset: 0xA0, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA35

Backup data register 35

Offset: 0xA4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA36

Backup data register 36

Offset: 0xA8, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA37

Backup data register 37

Offset: 0xAC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA38

Backup data register 38

Offset: 0xB0, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA39

Backup data register 39

Offset: 0xB4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA40

Backup data register 40

Offset: 0xB8, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA41

Backup data register 41

Offset: 0xBC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

CAN0

0x40006400: Controller area network

50/2062 fields covered. Toggle Registers.

CTL

Control register

Offset: 0x0, reset: 0x00010002, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
rw 		TTC
rw 		ABOR
rw 		AWU
rw 		ARD
rw 		RFOD
rw 		TFO
rw 		SLPWMOD
rw 		IWMOD
rw
Toggle Fields.

IWMOD

Bit 0: Initial working mode.

SLPWMOD

Bit 1: Sleep working mode.

TFO

Bit 2: Transmit FIFO order.

RFOD

Bit 3: Receive FIFO overwrite disable.

ARD

Bit 4: Automatic retransmission disable.

AWU

Bit 5: Automatic wakeup.

ABOR

Bit 6: Automatic bus-off recovery.

TTC

Bit 7: Time-triggered communication.

SWRST

Bit 15: Software reset.

DFZ

Bit 16: Debug freeze.

STAT

Status register

Offset: 0x4, reset: 0x00000C02, access: Unspecified

6/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXL
r 		LASTRX
r 		RS
r 		TS
r 		SLPIF
rw 		WUIF
rw 		ERRIF
rw 		SLPWS
r 		IWS
r
Toggle Fields.

IWS

Bit 0: Initial working state.

SLPWS

Bit 1: Sleep working state.

ERRIF

Bit 2: Error interrupt flag.

WUIF

Bit 3: Status change interrupt flag of wakeup from sleep working mode.

SLPIF

Bit 4: Status change interrupt flag of sleep working mode entering.

TS

Bit 8: Transmitting state.

RS

Bit 9: Receiving state.

LASTRX

Bit 10: Last sample value of RX pin.

RXL

Bit 11: RX level.

TSTAT

Transmit status register

Offset: 0x8, reset: 0x1C000000, access: Unspecified

7/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TMLS2
r 		TMLS1
r 		TMLS0
r 		TME2
r 		TME1
r 		TME0
r 		NUM
r 		MST2
rw 		MTE2
rw 		MAL2
rw 		MTFNERR2
rw 		MTF2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MST1
rw 		MTE1
rw 		MAL1
rw 		MTFNERR1
rw 		MTF1
rw 		MST0
rw 		MTE0
rw 		MAL0
rw 		MTFNERR0
rw 		MTF0
rw
Toggle Fields.

MTF0

Bit 0: Mailbox 0 transmit finished.

MTFNERR0

Bit 1: Mailbox 0 transmit finished and no error.

MAL0

Bit 2: Mailbox 0 arbitration lost.

MTE0

Bit 3: Mailbox 0 transmit error.

MST0

Bit 7: Mailbox 0 stop transmitting.

MTF1

Bit 8: Mailbox 1 transmit finished.

MTFNERR1

Bit 9: Mailbox 1 transmit finished and no error.

MAL1

Bit 10: Mailbox 1 arbitration lost.

MTE1

Bit 11: Mailbox 1 transmit error.

MST1

Bit 15: Mailbox 1 stop transmitting.

MTF2

Bit 16: Mailbox 2 transmit finished.

MTFNERR2

Bit 17: Mailbox 2 transmit finished and no error.

MAL2

Bit 18: Mailbox 2 arbitration lost.

MTE2

Bit 19: Mailbox 2 transmit error.

MST2

Bit 23: Mailbox 2 stop transmitting.

NUM

Bits 24-25: number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty.

TME0

Bit 26: Transmit mailbox 0 empty.

TME1

Bit 27: Transmit mailbox 1 empty.

TME2

Bit 28: Transmit mailbox 2 empty.

TMLS0

Bit 29: Transmit mailbox 0 last sending in transmit FIFO.

TMLS1

Bit 30: Transmit mailbox 1 last sending in transmit FIFO.

TMLS2

Bit 31: Transmit mailbox 2 last sending in transmit FIFO.

RFIFO0

Receive message FIFO0 register

Offset: 0xC, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFD0
rw 		RFO0
rw 		RFF0
rw 		RFL0
r
Toggle Fields.

RFL0

Bits 0-1: Receive FIFO0 length.

RFF0

Bit 3: Receive FIFO0 full.

RFO0

Bit 4: Receive FIFO0 overfull.

RFD0

Bit 5: Receive FIFO0 dequeue.

RFIFO1

Receive message FIFO1 register

Offset: 0x10, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFD1
rw 		RFO1
rw 		RFF1
rw 		RFL1
r
Toggle Fields.

RFL1

Bits 0-1: Receive FIFO1 length.

RFF1

Bit 3: Receive FIFO1 full.

RFO1

Bit 4: Receive FIFO1 overfull.

RFD1

Bit 5: Receive FIFO1 dequeue.

INTEN

Interrupt enable register

Offset: 0x14, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLPWIE
rw 		WIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE
rw 		ERRNIE
rw 		BOIE
rw 		PERRIE
rw 		WERRIE
rw 		RFOIE1
rw 		RFFIE1
rw 		RFNEIE1
rw 		RFOIE0
rw 		RFFIE0
rw 		RFNEIE0
rw 		TMEIE
rw
Toggle Fields.

TMEIE

Bit 0: Transmit mailbox empty interrupt enable.

RFNEIE0

Bit 1: Receive FIFO0 not empty interrupt enable.

RFFIE0

Bit 2: Receive FIFO0 full interrupt enable.

RFOIE0

Bit 3: Receive FIFO0 overfull interrupt enable.

RFNEIE1

Bit 4: Receive FIFO1 not empty interrupt enable.

RFFIE1

Bit 5: Receive FIFO1 full interrupt enable.

RFOIE1

Bit 6: Receive FIFO1 overfull interrupt enable.

WERRIE

Bit 8: Warning error interrupt enable.

PERRIE

Bit 9: Passive error interrupt enable.

BOIE

Bit 10: Bus-off interrupt enable.

ERRNIE

Bit 11: Error number interrupt enable.

ERRIE

Bit 15: Error interrupt enable.

WIE

Bit 16: Wakeup interrupt enable.

SLPWIE

Bit 17: Sleep working interrupt enable.

ERR

Error register

Offset: 0x18, reset: 0x00000000, access: Unspecified

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECNT
r 		TECNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRN
rw 		BOERR
r 		PERR
r 		WERR
r
Toggle Fields.

WERR

Bit 0: Warning error.

PERR

Bit 1: Passive error.

BOERR

Bit 2: Bus-off error.

ERRN

Bits 4-6: Error number.

TECNT

Bits 16-23: Transmit Error Count defined by the CAN standard.

RECNT

Bits 24-31: Receive Error Count defined by the CAN standard.

BT

Bit timing register

Offset: 0x1C, reset: 0x01230000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCMOD
rw 		LCMOD
rw 		SJW
rw 		BS2
rw 		BS1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BAUDPSC
rw
Toggle Fields.

BAUDPSC

Bits 0-9: Baud rate prescaler.

BS1

Bits 16-19: Bit segment 1.

BS2

Bits 20-22: Bit segment 2.

SJW

Bits 24-28: Resynchronization jump width.

LCMOD

Bit 30: Loopback communication mode.

SCMOD

Bit 31: Silent communication mode.

TMI0

Transmit mailbox identifier register 0

Offset: 0x180, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

FT

Bit 1: Frame type.

FF

Bit 2: Frame format.

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP0

Transmit mailbox property register 0

Offset: 0x184, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

TSEN

Bit 8: Time stamp enable.

TS

Bits 16-31: Time stamp.

TMDATA00

Transmit mailbox data0 register

Offset: 0x188, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

DB1

Bits 8-15: Data byte 1.

DB2

Bits 16-23: Data byte 2.

DB3

Bits 24-31: Data byte 3.

TMDATA10

Transmit mailbox data1 register

Offset: 0x18C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

DB5

Bits 8-15: Data byte 5.

DB6

Bits 16-23: Data byte 6.

DB7

Bits 24-31: Data byte 7.

TMI1

Transmit mailbox identifier register 1

Offset: 0x190, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

FT

Bit 1: Frame type.

FF

Bit 2: Frame format.

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP1

Transmit mailbox property register 1

Offset: 0x194, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

TSEN

Bit 8: Time stamp enable.

TS

Bits 16-31: Time stamp.

TMDATA01

Transmit mailbox data0 register

Offset: 0x198, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

DB1

Bits 8-15: Data byte 1.

DB2

Bits 16-23: Data byte 2.

DB3

Bits 24-31: Data byte 3.

TMDATA11

Transmit mailbox data1 register

Offset: 0x19C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

DB5

Bits 8-15: Data byte 5.

DB6

Bits 16-23: Data byte 6.

DB7

Bits 24-31: Data byte 7.

TMI2

Transmit mailbox identifier register 2

Offset: 0x1A0, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

FT

Bit 1: Frame type.

FF

Bit 2: Frame format.

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP2

Transmit mailbox property register 2

Offset: 0x1A4, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		FDF
rw 		BRS
rw 		ESI
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

ESI

Bit 4: Error status indicator.

BRS

Bit 5: Bit rate of data switch.

FDF

Bit 7: CAN FD frame flag.

TSEN

Bit 8: Time stamp enable.

TS

Bits 16-31: Time stamp.

TMDATA02

Transmit mailbox data0 register

Offset: 0x1A8, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

DB1

Bits 8-15: Data byte 1.

DB2

Bits 16-23: Data byte 2.

DB3

Bits 24-31: Data byte 3.

TMDATA12

Transmit mailbox data1 register

Offset: 0x1AC, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

DB5

Bits 8-15: Data byte 5.

DB6

Bits 16-23: Data byte 6.

DB7

Bits 24-31: Data byte 7.

RFIFOMI0

Receive FIFO mailbox identifier register

Offset: 0x1B0, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
r 		EFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
r 		FF
r 		FT
r
Toggle Fields.

FT

Bit 1: Frame type.

FF

Bit 2: Frame format.

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

RFIFOMP0

Receive FIFO0 mailbox property register

Offset: 0x1B4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FI
r 		DLENC
r
Toggle Fields.

DLENC

Bits 0-3: Data length code.

FI

Bits 8-15: Filtering index.

TS

Bits 16-31: Time stamp.

RFIFOMDATA00

Receive FIFO0 mailbox data0 register

Offset: 0x1B8, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
r 		DB2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
r 		DB0
r
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

DB1

Bits 8-15: Data byte 1.

DB2

Bits 16-23: Data byte 2.

DB3

Bits 24-31: Data byte 3.

RFIFOMDATA10

Receive FIFO0 mailbox data1 register

Offset: 0x1BC, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
r 		DB6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
r 		DB4
r
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

DB5

Bits 8-15: Data byte 5.

DB6

Bits 16-23: Data byte 6.

DB7

Bits 24-31: Data byte 7.

RFIFOMI1

Receive FIFO1 mailbox identifier register

Offset: 0x1C0, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
r 		EFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
r 		FF
r 		FT
r
Toggle Fields.

FT

Bit 1: Frame type.

FF

Bit 2: Frame format.

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

RFIFOMP1

Receive FIFO1 mailbox property register

Offset: 0x1C4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FI
r 		DLENC
r
Toggle Fields.

DLENC

Bits 0-3: Data length code.

FI

Bits 8-15: Filtering index.

TS

Bits 16-31: Time stamp.

RFIFOMDATA01

Receive FIFO1 mailbox data0 register

Offset: 0x1C8, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
r 		DB2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
r 		DB0
r
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

DB1

Bits 8-15: Data byte 1.

DB2

Bits 16-23: Data byte 2.

DB3

Bits 24-31: Data byte 3.

RFIFOMDATA11

Receive FIFO1 mailbox data1 register

Offset: 0x1CC, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
r 		DB6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
r 		DB4
r
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

DB5

Bits 8-15: Data byte 5.

DB6

Bits 16-23: Data byte 6.

DB7

Bits 24-31: Data byte 7.

FCTL

Filter control register

Offset: 0x200, reset: 0x2A1C0E01, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HBC1F
rw 		FLD
rw
Toggle Fields.

FLD

Bit 0: Filter lock disable.

HBC1F

Bits 8-13: Header bank of CAN1 filter.

FMCFG

Filter mode configuration register

Offset: 0x204, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FMOD27
rw 		FMOD26
rw 		FMOD25
rw 		FMOD24
rw 		FMOD23
rw 		FMOD22
rw 		FMOD21
rw 		FMOD20
rw 		FMOD19
rw 		FMOD18
rw 		FMOD17
rw 		FMOD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMOD15
rw 		FMOD14
rw 		FMOD13
rw 		FMOD12
rw 		FMOD11
rw 		FMOD10
rw 		FMOD9
rw 		FMOD8
rw 		FMOD7
rw 		FMOD6
rw 		FMOD5
rw 		FMOD4
rw 		FMOD3
rw 		FMOD2
rw 		FMOD1
rw 		FMOD0
rw
Toggle Fields.

FMOD0

Bit 0: Filter mode.

FMOD1

Bit 1: Filter mode.

FMOD2

Bit 2: Filter mode.

FMOD3

Bit 3: Filter mode.

FMOD4

Bit 4: Filter mode.

FMOD5

Bit 5: Filter mode.

FMOD6

Bit 6: Filter mode.

FMOD7

Bit 7: Filter mode.

FMOD8

Bit 8: Filter mode.

FMOD9

Bit 9: Filter mode.

FMOD10

Bit 10: Filter mode.

FMOD11

Bit 11: Filter mode.

FMOD12

Bit 12: Filter mode.

FMOD13

Bit 13: Filter mode.

FMOD14

Bit 14: Filter mode.

FMOD15

Bit 15: Filter mode.

FMOD16

Bit 16: Filter mode.

FMOD17

Bit 17: Filter mode.

FMOD18

Bit 18: Filter mode.

FMOD19

Bit 19: Filter mode.

FMOD20

Bit 20: Filter mode.

FMOD21

Bit 21: Filter mode.

FMOD22

Bit 22: Filter mode.

FMOD23

Bit 23: Filter mode.

FMOD24

Bit 24: Filter mode.

FMOD25

Bit 25: Filter mode.

FMOD26

Bit 26: Filter mode.

FMOD27

Bit 27: Filter mode.

FSCFG

Filter scale configuration register

Offset: 0x20C, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FS27
rw 		FS26
rw 		FS25
rw 		FS24
rw 		FS23
rw 		FS22
rw 		FS21
rw 		FS20
rw 		FS19
rw 		FS18
rw 		FS17
rw 		FS16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FS15
rw 		FS14
rw 		FS13
rw 		FS12
rw 		FS11
rw 		FS10
rw 		FS9
rw 		FS8
rw 		FS7
rw 		FS6
rw 		FS5
rw 		FS4
rw 		FS3
rw 		FS2
rw 		FS1
rw 		FS0
rw
Toggle Fields.

FS0

Bit 0: Filter scale configuration.

FS1

Bit 1: Filter scale configuration.

FS2

Bit 2: Filter scale configuration.

FS3

Bit 3: Filter scale configuration.

FS4

Bit 4: Filter scale configuration.

FS5

Bit 5: Filter scale configuration.

FS6

Bit 6: Filter scale configuration.

FS7

Bit 7: Filter scale configuration.

FS8

Bit 8: Filter scale configuration.

FS9

Bit 9: Filter scale configuration.

FS10

Bit 10: Filter scale configuration.

FS11

Bit 11: Filter scale configuration.

FS12

Bit 12: Filter scale configuration.

FS13

Bit 13: Filter scale configuration.

FS14

Bit 14: Filter scale configuration.

FS15

Bit 15: Filter scale configuration.

FS16

Bit 16: Filter scale configuration.

FS17

Bit 17: Filter scale configuration.

FS18

Bit 18: Filter scale configuration.

FS19

Bit 19: Filter scale configuration.

FS20

Bit 20: Filter scale configuration.

FS21

Bit 21: Filter scale configuration.

FS22

Bit 22: Filter scale configuration.

FS23

Bit 23: Filter scale configuration.

FS24

Bit 24: Filter scale configuration.

FS25

Bit 25: Filter scale configuration.

FS26

Bit 26: Filter scale configuration.

FS27

Bit 27: Filter scale configuration.

FAFIFO

Filter associated FIFO register

Offset: 0x214, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FAF27
rw 		FAF26
rw 		FAF25
rw 		FAF24
rw 		FAF23
rw 		FAF22
rw 		FAF21
rw 		FAF20
rw 		FAF19
rw 		FAF18
rw 		FAF17
rw 		FAF16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAF15
rw 		FAF14
rw 		FAF13
rw 		FAF12
rw 		FAF11
rw 		FAF10
rw 		FAF9
rw 		FAF8
rw 		FAF7
rw 		FAF6
rw 		FAF5
rw 		FAF4
rw 		FAF3
rw 		FAF2
rw 		FAF1
rw 		FAF0
rw
Toggle Fields.

FAF0

Bit 0: Filter 0 associated with FIFO.

FAF1

Bit 1: Filter 1 associated with FIFO.

FAF2

Bit 2: Filter 2 associated with FIFO.

FAF3

Bit 3: Filter 3 associated with FIFO.

FAF4

Bit 4: Filter 4 associated with FIFO.

FAF5

Bit 5: Filter 5 associated with FIFO.

FAF6

Bit 6: Filter 6 associated with FIFO.

FAF7

Bit 7: Filter 7 associated with FIFO.

FAF8

Bit 8: Filter 8 associated with FIFO.

FAF9

Bit 9: Filter 9 associated with FIFO.

FAF10

Bit 10: Filter 10 associated with FIFO.

FAF11

Bit 11: Filter 11 associated with FIFO.

FAF12

Bit 12: Filter 12 associated with FIFO.

FAF13

Bit 13: Filter 13 associated with FIFO.

FAF14

Bit 14: Filter 14 associated with FIFO.

FAF15

Bit 15: Filter 15 associated with FIFO.

FAF16

Bit 16: Filter 16 associated with FIFO.

FAF17

Bit 17: Filter 17 associated with FIFO.

FAF18

Bit 18: Filter 18 associated with FIFO.

FAF19

Bit 19: Filter 19 associated with FIFO.

FAF20

Bit 20: Filter 20 associated with FIFO.

FAF21

Bit 21: Filter 21 associated with FIFO.

FAF22

Bit 22: Filter 22 associated with FIFO.

FAF23

Bit 23: Filter 23 associated with FIFO.

FAF24

Bit 24: Filter 24 associated with FIFO.

FAF25

Bit 25: Filter 25 associated with FIFO.

FAF26

Bit 26: Filter 26 associated with FIFO.

FAF27

Bit 27: Filter 27 associated with FIFO.

FW

Filter working register

Offset: 0x21C, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FW27
rw 		FW26
rw 		FW25
rw 		FW24
rw 		FW23
rw 		FW22
rw 		FW21
rw 		FW20
rw 		FW19
rw 		FW18
rw 		FW17
rw 		FW16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FW15
rw 		FW14
rw 		FW13
rw 		FW12
rw 		FW11
rw 		FW10
rw 		FW9
rw 		FW8
rw 		FW7
rw 		FW6
rw 		FW5
rw 		FW4
rw 		FW3
rw 		FW2
rw 		FW1
rw 		FW0
rw
Toggle Fields.

FW0

Bit 0: Filter working.

FW1

Bit 1: Filter working.

FW2

Bit 2: Filter working.

FW3

Bit 3: Filter working.

FW4

Bit 4: Filter working.

FW5

Bit 5: Filter working.

FW6

Bit 6: Filter working.

FW7

Bit 7: Filter working.

FW8

Bit 8: Filter working.

FW9

Bit 9: Filter working.

FW10

Bit 10: Filter working.

FW11

Bit 11: Filter working.

FW12

Bit 12: Filter working.

FW13

Bit 13: Filter working.

FW14

Bit 14: Filter working.

FW15

Bit 15: Filter working.

FW16

Bit 16: Filter working.

FW17

Bit 17: Filter working.

FW18

Bit 18: Filter working.

FW19

Bit 19: Filter working.

FW20

Bit 20: Filter working.

FW21

Bit 21: Filter working.

FW22

Bit 22: Filter working.

FW23

Bit 23: Filter working.

FW24

Bit 24: Filter working.

FW25

Bit 25: Filter working.

FW26

Bit 26: Filter working.

FW27

Bit 27: Filter working.

F0DATA0

Filter 0 data 0 register

Offset: 0x240, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F0DATA1

Filter 0 data 1 register

Offset: 0x244, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F1DATA0

Filter 1 data 0 register

Offset: 0x248, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F1DATA1

Filter 1 data 1 register

Offset: 0x24C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F2DATA0

Filter 2 data 0 register

Offset: 0x250, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F2DATA1

Filter 2 data 1 register

Offset: 0x254, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F3DATA0

Filter 3 data 0 register

Offset: 0x258, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F3DATA1

Filter 3 data 1 register

Offset: 0x25C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F4DATA0

Filter 4 data 0 register

Offset: 0x260, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F4DATA1

Filter 4 data 1 register

Offset: 0x264, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F5DATA0

Filter 5 data 0 register

Offset: 0x268, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F5DATA1

Filter 5 data 1 register

Offset: 0x26C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F6DATA0

Filter 6 data 0 register

Offset: 0x270, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F6DATA1

Filter 6 data 1 register

Offset: 0x274, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F7DATA0

Filter 7 data 0 register

Offset: 0x278, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F7DATA1

Filter 7 data 1 register

Offset: 0x27C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F8DATA0

Filter 8 data 0 register

Offset: 0x280, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F8DATA1

Filter 8 data 1 register

Offset: 0x284, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F9DATA0

Filter 9 data 0 register

Offset: 0x288, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F9DATA1

Filter 9 data 1 register

Offset: 0x28C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F10DATA0

Filter 10 data 0 register

Offset: 0x290, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F10DATA1

Filter 10 data 1 register

Offset: 0x294, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F11DATA0

Filter 11 data 0 register

Offset: 0x298, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F11DATA1

Filter 11 data 1 register

Offset: 0x29C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F12DATA0

Filter 12 data 0 register

Offset: 0x2A0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F12DATA1

Filter 12 data 1 register

Offset: 0x2A4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F13DATA0

Filter 13 data 0 register

Offset: 0x2A8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F13DATA1

Filter 13 data 1 register

Offset: 0x2AC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F14DATA0

Filter 14 data 0 register

Offset: 0x2B0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F14DATA1

Filter 14 data 1 register

Offset: 0x2B4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F15DATA0

Filter 15 data 0 register

Offset: 0x2B8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F15DATA1

Filter 15 data 1 register

Offset: 0x2BC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F16DATA0

Filter 16 data 0 register

Offset: 0x2C0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F16DATA1

Filter 16 data 1 register

Offset: 0x2C4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F17DATA0

Filter 17 data 0 register

Offset: 0x2C8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F17DATA1

Filter 17 data 1 register

Offset: 0x2CC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F18DATA0

Filter 18 data 0 register

Offset: 0x2D0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F18DATA1

Filter 18 data 1 register

Offset: 0x2D4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F19DATA0

Filter 19 data 0 register

Offset: 0x2D8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F19DATA1

Filter 19 data 1 register

Offset: 0x2DC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F20DATA0

Filter 20 data 0 register

Offset: 0x2E0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F20DATA1

Filter 20 data 1 register

Offset: 0x2E4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F21DATA0

Filter 21 data 0 register

Offset: 0x2E8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F21DATA1

Filter 21 data 1 register

Offset: 0x2EC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F22DATA0

Filter 22 data 0 register

Offset: 0x2F0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F22DATA1

Filter 22 data 1 register

Offset: 0x2F4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F23DATA0

Filter 23 data 0 register

Offset: 0x2F8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F23DATA1

Filter 23 data 1 register

Offset: 0x2FC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F24DATA0

Filter 24 data 0 register

Offset: 0x300, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F24DATA1

Filter 24 data 1 register

Offset: 0x304, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F25DATA0

Filter 25 data 0 register

Offset: 0x308, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F25DATA1

Filter 25 data 1 register

Offset: 0x30C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F26DATA0

Filter 26 data 0 register

Offset: 0x310, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F26DATA1

Filter 26 data 1 register

Offset: 0x314, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F27DATA0

Filter 27 data 0 register

Offset: 0x318, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F27DATA1

Filter 27 data 1 register

Offset: 0x31C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

CAN1

0x40006800: Controller area network

50/156 fields covered. Toggle Registers.

CTL

Control register

Offset: 0x0, reset: 0x00010002, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
rw 		TTC
rw 		ABOR
rw 		AWU
rw 		ARD
rw 		RFOD
rw 		TFO
rw 		SLPWMOD
rw 		IWMOD
rw
Toggle Fields.

IWMOD

Bit 0: Initial working mode.

SLPWMOD

Bit 1: Sleep working mode.

TFO

Bit 2: Transmit FIFO order.

RFOD

Bit 3: Receive FIFO overwrite disable.

ARD

Bit 4: Automatic retransmission disable.

AWU

Bit 5: Automatic wakeup.

ABOR

Bit 6: Automatic bus-off recovery.

TTC

Bit 7: Time-triggered communication.

SWRST

Bit 15: Software reset.

DFZ

Bit 16: Debug freeze.

STAT

Status register

Offset: 0x4, reset: 0x00000C02, access: Unspecified

6/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXL
r 		LASTRX
r 		RS
r 		TS
r 		SLPIF
rw 		WUIF
rw 		ERRIF
rw 		SLPWS
r 		IWS
r
Toggle Fields.

IWS

Bit 0: Initial working state.

SLPWS

Bit 1: Sleep working state.

ERRIF

Bit 2: Error interrupt flag.

WUIF

Bit 3: Status change interrupt flag of wakeup from sleep working mode.

SLPIF

Bit 4: Status change interrupt flag of sleep working mode entering.

TS

Bit 8: Transmitting state.

RS

Bit 9: Receiving state.

LASTRX

Bit 10: Last sample value of RX pin.

RXL

Bit 11: RX level.

TSTAT

Transmit status register

Offset: 0x8, reset: 0x1C000000, access: Unspecified

7/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TMLS2
r 		TMLS1
r 		TMLS0
r 		TME2
r 		TME1
r 		TME0
r 		NUM
r 		MST2
rw 		MTE2
rw 		MAL2
rw 		MTFNERR2
rw 		MTF2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MST1
rw 		MTE1
rw 		MAL1
rw 		MTFNERR1
rw 		MTF1
rw 		MST0
rw 		MTE0
rw 		MAL0
rw 		MTFNERR0
rw 		MTF0
rw
Toggle Fields.

MTF0

Bit 0: Mailbox 0 transmit finished.

MTFNERR0

Bit 1: Mailbox 0 transmit finished and no error.

MAL0

Bit 2: Mailbox 0 arbitration lost.

MTE0

Bit 3: Mailbox 0 transmit error.

MST0

Bit 7: Mailbox 0 stop transmitting.

MTF1

Bit 8: Mailbox 1 transmit finished.

MTFNERR1

Bit 9: Mailbox 1 transmit finished and no error.

MAL1

Bit 10: Mailbox 1 arbitration lost.

MTE1

Bit 11: Mailbox 1 transmit error.

MST1

Bit 15: Mailbox 1 stop transmitting.

MTF2

Bit 16: Mailbox 2 transmit finished.

MTFNERR2

Bit 17: Mailbox 2 transmit finished and no error.

MAL2

Bit 18: Mailbox 2 arbitration lost.

MTE2

Bit 19: Mailbox 2 transmit error.

MST2

Bit 23: Mailbox 2 stop transmitting.

NUM

Bits 24-25: number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty.

TME0

Bit 26: Transmit mailbox 0 empty.

TME1

Bit 27: Transmit mailbox 1 empty.

TME2

Bit 28: Transmit mailbox 2 empty.

TMLS0

Bit 29: Transmit mailbox 0 last sending in transmit FIFO.

TMLS1

Bit 30: Transmit mailbox 1 last sending in transmit FIFO.

TMLS2

Bit 31: Transmit mailbox 2 last sending in transmit FIFO.

RFIFO0

Receive message FIFO0 register

Offset: 0xC, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFD0
rw 		RFO0
rw 		RFF0
rw 		RFL0
r
Toggle Fields.

RFL0

Bits 0-1: Receive FIFO0 length.

RFF0

Bit 3: Receive FIFO0 full.

RFO0

Bit 4: Receive FIFO0 overfull.

RFD0

Bit 5: Receive FIFO0 dequeue.

RFIFO1

Receive message FIFO1 register

Offset: 0x10, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFD1
rw 		RFO1
rw 		RFF1
rw 		RFL1
r
Toggle Fields.

RFL1

Bits 0-1: Receive FIFO1 length.

RFF1

Bit 3: Receive FIFO1 full.

RFO1

Bit 4: Receive FIFO1 overfull.

RFD1

Bit 5: Receive FIFO1 dequeue.

INTEN

Interrupt enable register

Offset: 0x14, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLPWIE
rw 		WIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE
rw 		ERRNIE
rw 		BOIE
rw 		PERRIE
rw 		WERRIE
rw 		RFOIE1
rw 		RFFIE1
rw 		RFNEIE1
rw 		RFOIE0
rw 		RFFIE0
rw 		RFNEIE0
rw 		TMEIE
rw
Toggle Fields.

TMEIE

Bit 0: Transmit mailbox empty interrupt enable.

RFNEIE0

Bit 1: Receive FIFO0 not empty interrupt enable.

RFFIE0

Bit 2: Receive FIFO0 full interrupt enable.

RFOIE0

Bit 3: Receive FIFO0 overfull interrupt enable.

RFNEIE1

Bit 4: Receive FIFO1 not empty interrupt enable.

RFFIE1

Bit 5: Receive FIFO1 full interrupt enable.

RFOIE1

Bit 6: Receive FIFO1 overfull interrupt enable.

WERRIE

Bit 8: Warning error interrupt enable.

PERRIE

Bit 9: Passive error interrupt enable.

BOIE

Bit 10: Bus-off interrupt enable.

ERRNIE

Bit 11: Error number interrupt enable.

ERRIE

Bit 15: Error interrupt enable.

WIE

Bit 16: Wakeup interrupt enable.

SLPWIE

Bit 17: Sleep working interrupt enable.

ERR

Error register

Offset: 0x18, reset: 0x00000000, access: Unspecified

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECNT
r 		TECNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRN
rw 		BOERR
r 		PERR
r 		WERR
r
Toggle Fields.

WERR

Bit 0: Warning error.

PERR

Bit 1: Passive error.

BOERR

Bit 2: Bus-off error.

ERRN

Bits 4-6: Error number.

TECNT

Bits 16-23: Transmit Error Count defined by the CAN standard.

RECNT

Bits 24-31: Receive Error Count defined by the CAN standard.

BT

Bit timing register

Offset: 0x1C, reset: 0x01230000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCMOD
rw 		LCMOD
rw 		SJW
rw 		BS2
rw 		BS1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BAUDPSC
rw
Toggle Fields.

BAUDPSC

Bits 0-9: Baud rate prescaler.

BS1

Bits 16-19: Bit segment 1.

BS2

Bits 20-22: Bit segment 2.

SJW

Bits 24-28: Resynchronization jump width.

LCMOD

Bit 30: Loopback communication mode.

SCMOD

Bit 31: Silent communication mode.

TMI0

Transmit mailbox identifier register 0

Offset: 0x180, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

FT

Bit 1: Frame type.

FF

Bit 2: Frame format.

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP0

Transmit mailbox property register 0

Offset: 0x184, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

TSEN

Bit 8: Time stamp enable.

TS

Bits 16-31: Time stamp.

TMDATA00

Transmit mailbox data0 register

Offset: 0x188, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

DB1

Bits 8-15: Data byte 1.

DB2

Bits 16-23: Data byte 2.

DB3

Bits 24-31: Data byte 3.

TMDATA10

Transmit mailbox data1 register

Offset: 0x18C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

DB5

Bits 8-15: Data byte 5.

DB6

Bits 16-23: Data byte 6.

DB7

Bits 24-31: Data byte 7.

TMI1

Transmit mailbox identifier register 1

Offset: 0x190, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

FT

Bit 1: Frame type.

FF

Bit 2: Frame format.

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP1

Transmit mailbox property register 1

Offset: 0x194, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

TSEN

Bit 8: Time stamp enable.

TS

Bits 16-31: Time stamp.

TMDATA01

Transmit mailbox data0 register

Offset: 0x198, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

DB1

Bits 8-15: Data byte 1.

DB2

Bits 16-23: Data byte 2.

DB3

Bits 24-31: Data byte 3.

TMDATA11

Transmit mailbox data1 register

Offset: 0x19C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

DB5

Bits 8-15: Data byte 5.

DB6

Bits 16-23: Data byte 6.

DB7

Bits 24-31: Data byte 7.

TMI2

Transmit mailbox identifier register 2

Offset: 0x1A0, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

FT

Bit 1: Frame type.

FF

Bit 2: Frame format.

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP2

Transmit mailbox property register 2

Offset: 0x1A4, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		FDF
rw 		BRS
rw 		ESI
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

ESI

Bit 4: Error status indicator.

BRS

Bit 5: Bit rate of data switch.

FDF

Bit 7: CAN FD frame flag.

TSEN

Bit 8: Time stamp enable.

TS

Bits 16-31: Time stamp.

TMDATA02

Transmit mailbox data0 register

Offset: 0x1A8, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

DB1

Bits 8-15: Data byte 1.

DB2

Bits 16-23: Data byte 2.

DB3

Bits 24-31: Data byte 3.

TMDATA12

Transmit mailbox data1 register

Offset: 0x1AC, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

DB5

Bits 8-15: Data byte 5.

DB6

Bits 16-23: Data byte 6.

DB7

Bits 24-31: Data byte 7.

RFIFOMI0

Receive FIFO mailbox identifier register

Offset: 0x1B0, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
r 		EFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
r 		FF
r 		FT
r
Toggle Fields.

FT

Bit 1: Frame type.

FF

Bit 2: Frame format.

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

RFIFOMP0

Receive FIFO0 mailbox property register

Offset: 0x1B4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FI
r 		DLENC
r
Toggle Fields.

DLENC

Bits 0-3: Data length code.

FI

Bits 8-15: Filtering index.

TS

Bits 16-31: Time stamp.

RFIFOMDATA00

Receive FIFO0 mailbox data0 register

Offset: 0x1B8, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
r 		DB2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
r 		DB0
r
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

DB1

Bits 8-15: Data byte 1.

DB2

Bits 16-23: Data byte 2.

DB3

Bits 24-31: Data byte 3.

RFIFOMDATA10

Receive FIFO0 mailbox data1 register

Offset: 0x1BC, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
r 		DB6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
r 		DB4
r
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

DB5

Bits 8-15: Data byte 5.

DB6

Bits 16-23: Data byte 6.

DB7

Bits 24-31: Data byte 7.

RFIFOMI1

Receive FIFO1 mailbox identifier register

Offset: 0x1C0, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
r 		EFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
r 		FF
r 		FT
r
Toggle Fields.

FT

Bit 1: Frame type.

FF

Bit 2: Frame format.

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

RFIFOMP1

Receive FIFO1 mailbox property register

Offset: 0x1C4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FI
r 		DLENC
r
Toggle Fields.

DLENC

Bits 0-3: Data length code.

FI

Bits 8-15: Filtering index.

TS

Bits 16-31: Time stamp.

RFIFOMDATA01

Receive FIFO1 mailbox data0 register

Offset: 0x1C8, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
r 		DB2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
r 		DB0
r
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

DB1

Bits 8-15: Data byte 1.

DB2

Bits 16-23: Data byte 2.

DB3

Bits 24-31: Data byte 3.

RFIFOMDATA11

Receive FIFO1 mailbox data1 register

Offset: 0x1CC, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
r 		DB6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
r 		DB4
r
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

DB5

Bits 8-15: Data byte 5.

DB6

Bits 16-23: Data byte 6.

DB7

Bits 24-31: Data byte 7.

CRC

0x40023000: cyclic redundancy check calculation unit

3/8 fields covered. Toggle Registers.

DATA

Data register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: CRC calculation result bits.

Allowed values: 0-4294967295

FDATA

Free data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDATA
rw
Toggle Fields.

FDATA

Bits 0-7: Free Data Register bits.

Allowed values: 0-255

CTL

Control register

Offset: 0x8, reset: 0x00000000, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_O
rw 		REV_I
rw 		PS
rw 		RST
rw
Toggle Fields.

RST

Bit 0: reset bit.

Allowed values:
1: Reset: Resets the DATA register to IDATA, with no effect on FDATA

PS

Bits 3-4: Size of polynomial.

REV_I

Bits 5-6: Reverse type for input data.

REV_O

Bit 7: Reverse output data value in bit order.

IDATA

Initialization data register

Offset: 0x10, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATA
rw
Toggle Fields.

IDATA

Bits 0-31: Configurable initial CRC data value.

POLY

Polynomial register

Offset: 0x14, reset: 0x04C11DB7, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
POLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POLY
rw
Toggle Fields.

POLY

Bits 0-31: User configurable polynomial value.

CTC

0x4000C800: Clock trim controller

9/26 fields covered. Toggle Registers.

CTL0

Control register 0

Offset: 0x0, reset: 0x00002000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMVALUE
rw 		SWREFPUL
rw 		AUTOTRIM
rw 		CNTEN
rw 		EREFIE
rw 		ERRIE
rw 		CKWARNIE
rw 		CKOKIE
rw
Toggle Fields.

CKOKIE

Bit 0: Clock trim ok interrupt enable.

CKWARNIE

Bit 1: Clock trim warning interrupt enable.

ERRIE

Bit 2: Error interrupt enable.

EREFIE

Bit 3: EREFIF interrupt enable.

CNTEN

Bit 5: CTC counter enable.

AUTOTRIM

Bit 6: Hardware automatically trim mode.

SWREFPUL

Bit 7: Software reference source sync pulse.

TRIMVALUE

Bits 8-13: IRC48M trim value.

CTL1

Control register 1

Offset: 0x4, reset: 0x2022BB7F, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REFPOL
rw 		REFSEL
rw 		REFPSC
rw 		CKLIM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RLVALUE
rw
Toggle Fields.

RLVALUE

Bits 0-15: CTC counter reload value.

CKLIM

Bits 16-23: Clock trim base limit value.

REFPSC

Bits 24-26: Reference signal source prescaler.

REFSEL

Bits 28-29: Reference signal source selection.

REFPOL

Bit 31: Reference signal source polarity.

STAT

Status register

Offset: 0x8, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REFCAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REFDIR
r 		TRIMERR
r 		REFMISS
r 		CKERR
r 		EREFIF
r 		ERRIF
r 		CKWARNIF
r 		CKOKIF
r
Toggle Fields.

CKOKIF

Bit 0: Clock trim OK interrupt flag.

CKWARNIF

Bit 1: Clock trim warning interrupt flag.

ERRIF

Bit 2: Error interrupt flag.

EREFIF

Bit 3: Expect reference interrupt flag.

CKERR

Bit 8: Clock trim error bit.

REFMISS

Bit 9: Reference sync pulse miss.

TRIMERR

Bit 10: Trim value error bit.

REFDIR

Bit 15: CTC trim counter direction when reference sync pulse.

REFCAP

Bits 16-31: CTC counter capture when reference sync pulse.

INTC

Interrupt clear register

Offset: 0xC, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EREFIC
w 		ERRIC
w 		CKWARNIC
w 		CKOKIC
w
Toggle Fields.

CKOKIC

Bit 0: CKOKIF interrupt clear bit.

CKWARNIC

Bit 1: CKWARNIF interrupt clear bit.

ERRIC

Bit 2: ERRIF interrupt clear bit.

EREFIC

Bit 3: EREFIF interrupt clear bit.

DAC

0x40007400: Digital-to-analog converter

8/52 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTSEL1_3
rw 		DDUDRIE1
rw 		DDMAEN1
rw 		DWBW1
rw 		DWM1
rw 		DTSEL1
rw 		DTEN1
rw 		DBOFF1
rw 		DEN1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTSEL0_3
rw 		DDUDRIE0
rw 		DDMAEN0
rw 		DWBW0
rw 		DWM0
rw 		DTSEL0
rw 		DTEN0
rw 		DBOFF0
rw 		DEN0
rw
Toggle Fields.

DEN0

Bit 0: DAC0 enable.

DBOFF0

Bit 1: DAC0 output buffer turn off.

DTEN0

Bit 2: DAC0 trigger enable.

DTSEL0

Bits 3-5: DAC0 trigger selection.

DWM0

Bits 6-7: DAC0 noise wave mode.

DWBW0

Bits 8-11: DAC0 noise wave bit width.

DDMAEN0

Bit 12: DAC0 DMA enable.

DDUDRIE0

Bit 13: DAC_OUT0 DMA underrun interrupt enable.

DTSEL0_3

Bit 14: DAC_OUT0 trigger selection bit[3], refer to DTSEL0[2:0].

DEN1

Bit 16: DAC1 enable.

DBOFF1

Bit 17: DAC1 output buffer turn off.

DTEN1

Bit 18: DAC1 trigger enable.

DTSEL1

Bits 19-21: DAC1 trigger selection.

DWM1

Bits 22-23: DAC1 noise wave mode.

DWBW1

Bits 24-27: DAC1 noise wave bit width.

DDMAEN1

Bit 28: DAC1 DMA enable.

DDUDRIE1

Bit 29: DAC_OUT1 DMA underrun interrupt enable.

DTSEL1_3

Bit 30: DAC_OUT1 trigger selection bit[3], refer to DTSEL1[2:0].

SWT

software trigger register

Offset: 0x4, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTR1
w 		SWTR0
w
Toggle Fields.

SWTR0

Bit 0: DAC0 software trigger.

SWTR1

Bit 1: DAC1 software trigger.

OUT0_R12DH

DAC_OUT0 12-bit right-aligned data holding register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUT0_DH
rw
Toggle Fields.

OUT0_DH

Bits 0-11: DAC_OUT0 12-bit right-aligned data.

OUT0_L12DH

DAC_OUT0 12-bit left-aligned data holding register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUT0_DH
rw
Toggle Fields.

OUT0_DH

Bits 4-15: DAC_OUT0 12-bit left-aligned data.

OUT0_R8DH

DAC_OUT0 8-bit right aligned data holding register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUT0_DH
rw
Toggle Fields.

OUT0_DH

Bits 0-7: DAC_OUT0 8-bit right-aligned data.

OUT1_R12DH

DAC_OUT1 12-bit right-aligned data holding register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUT1_DH
rw
Toggle Fields.

OUT1_DH

Bits 0-11: DAC_OUT1 12-bit right-aligned data.

OUT1_L12DH

DAC_OUT1 12-bit left aligned data holding register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUT1_DH
rw
Toggle Fields.

OUT1_DH

Bits 4-15: DAC_OUT1 12-bit left-aligned data.

OUT1_R8DH

DAC_OUT1 8-bit right aligned data holding register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUT1_DH
rw
Toggle Fields.

OUT1_DH

Bits 0-7: DAC_OUT1 8-bit right-aligned data.

DACC_R12DH

DAC concurrent mode 12-bit right-aligned data holding register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OUT1_DH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUT0_DH
rw
Toggle Fields.

OUT0_DH

Bits 0-11: DAC_OUT0 12-bit right-aligned data.

OUT1_DH

Bits 16-27: DAC_OUT1 12-bit right-aligned data.

DACC_L12DH

DAC concurrent mode 12-bit left aligned data holding register

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OUT1_DH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUT0_DH
rw
Toggle Fields.

OUT0_DH

Bits 4-15: DAC_OUT0 12-bit left-aligned data.

OUT1_DH

Bits 20-31: DAC_OUT1 12-bit left-aligned data.

DACC_R8DH

DAC concurrent mode 8-bit right aligned data holding register

Offset: 0x28, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUT1_DH
rw 		OUT0_DH
rw
Toggle Fields.

OUT0_DH

Bits 0-7: DAC_OUT0 8-bit right-aligned data.

OUT1_DH

Bits 8-15: DAC_OUT1 8-bit right-aligned data.

OUT0_DO

DAC_OUT0 data output register

Offset: 0x2C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUT0_DO
r
Toggle Fields.

OUT0_DO

Bits 0-11: DAC_OUT0 data output.

OUT1_DO

DAC_OUT1 data output register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUT1_DO
r
Toggle Fields.

OUT1_DO

Bits 0-11: DAC_OUT1 data output.

STAT0

DAC Status register 0

Offset: 0x34, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DDUDR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDUDR0
rw
Toggle Fields.

DDUDR0

Bit 13: DAC_OUT0 DMA underrun flag.

DDUDR1

Bit 29: DAC_OUT1 DMA underrun flag.

CTL1

DAC Control Register 1

Offset: 0x80, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOUDRIE1
rw 		FIFOOVRIE1
rw 		FIFOEN1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOUDRIE0
rw 		FIFOOVRIE0
rw 		FIFOEN0
rw
Toggle Fields.

FIFOEN0

Bit 0: DAC_OUT0 data FIFO enable.

FIFOOVRIE0

Bit 1: DAC_OUT0 FIFO overflow interrupt enable.

FIFOUDRIE0

Bit 2: DAC_OUT0 FIFO underflow interrupt enable.

FIFOEN1

Bit 16: DAC_OUT1 data FIFO enable.

FIFOOVRIE1

Bit 17: DAC_OUT1 FIFO overflow interrupt enable.

FIFOUDRIE1

Bit 18: DAC_OUT1 FIFO underflow interrupt enable.

STAT1

DAC Status register 1

Offset: 0x84, reset: 0x00000002, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFONUM1
r 		FIFOUDR1
rw 		FIFOOVR1
rw 		FE1
r 		FF1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFONUM0
r 		FIFOUDR0
rw 		FIFOOVR0
rw 		FE0
r 		FF0
r
Toggle Fields.

FF0

Bit 0: DAC_OUT0 FIFO full flag.

FE0

Bit 1: DAC_OUT0 FIFO empty flag.

FIFOOVR0

Bit 2: DAC_OUT0 FIFO overflow flag.

FIFOUDR0

Bit 3: DAC_OUT0 FIFO underflow flag.

FIFONUM0

Bits 4-6: Number of data in the DAC_OUT0 FIFO.

FF1

Bit 16: DAC_OUT1 FIFO full flag.

FE1

Bit 17: DAC_OUT1 FIFO empty flag.

FIFOOVR1

Bit 18: DAC_OUT1 FIFO overflow flag.

FIFOUDR1

Bit 19: DAC_OUT1 FIFO underflow flag.

FIFONUM1

Bits 20-22: Number of data in the DAC_OUT1 FIFO.

DBG

0xE0044000: Debug support

1/28 fields covered. Toggle Registers.

ID

ID code register

Offset: 0x0, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID_CODE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID_CODE
r
Toggle Fields.

ID_CODE

Bits 0-31: DBG ID code register.

CTL0

Control register 0

Offset: 0x4, reset: 0x00000000, access: read-write

0/27 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SHRTIMER_HOLD
rw 		TIMER10_HOLD
rw 		TIMER9_HOLD
rw 		TIMER8_HOLD
rw 		TIMER13_HOLD
rw 		TIMER12_HOLD
rw 		TIMER11_HOLD
rw 		I2C2_HOLD
rw 		CAN1_HOLD
rw 		TIMER6_HOLD
rw 		TIMER5_HOLD
rw 		TIMER4_HOLD
rw 		TIMER7_HOLD
rw 		I2C1_HOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C0_HOLD
rw 		CAN0_HOLD
rw 		TIMER3_HOLD
rw 		TIMER2_HOLD
rw 		TIMER1_HOLD
rw 		TIMER0_HOLD
rw 		WWDGT_HOLD
rw 		FWDGT_HOLD
rw 		TRACE_MODE
rw 		TRACE_IOEN
rw 		STB_HOLD
rw 		DSLP_HOLD
rw 		SLP_HOLD
rw
Toggle Fields.

SLP_HOLD

Bit 0: Sleep mode hold register.

DSLP_HOLD

Bit 1: Deep-sleep mode hold register.

STB_HOLD

Bit 2: Standby mode hold register.

TRACE_IOEN

Bit 5: Trace pin allocation enable.

TRACE_MODE

Bits 6-7: Trace pin allocation mode.

FWDGT_HOLD

Bit 8: FWDGT hold bit.

WWDGT_HOLD

Bit 9: WWDGT hold bit.

TIMER0_HOLD

Bit 10: TIMER 0 hold bit.

TIMER1_HOLD

Bit 11: TIMER 1 hold bit.

TIMER2_HOLD

Bit 12: TIMER 2 hold bit.

TIMER3_HOLD

Bit 13: TIMER 23 hold bit.

CAN0_HOLD

Bit 14: CAN0 hold bit.

I2C0_HOLD

Bit 15: I2C0 hold bit.

I2C1_HOLD

Bit 16: I2C1 hold bit.

TIMER7_HOLD

Bit 17: TIMER7_HOLD.

TIMER4_HOLD

Bit 18: TIMER4_HOLD.

TIMER5_HOLD

Bit 19: TIMER 5 hold bit.

TIMER6_HOLD

Bit 20: TIMER 6 hold bit.

CAN1_HOLD

Bit 21: CAN1 hold bit.

I2C2_HOLD

Bit 22: I2C2 hold bit.

TIMER11_HOLD

Bit 25: TIMER 11 hold bit.

TIMER12_HOLD

Bit 26: TIMER 12 hold bit.

TIMER13_HOLD

Bit 27: TIMER 13 hold bit.

TIMER8_HOLD

Bit 28: TIMER 8 hold bit.

TIMER9_HOLD

Bit 29: TIMER 9 hold bit.

TIMER10_HOLD

Bit 30: TIMER 10 hold bit.

SHRTIMER_HOLD

Bit 31: SHRTIMER hold bit.

DMA0

0x40020000: DMA controller

147/161 fields covered. Toggle Registers.

INTF

Interrupt flag register

Offset: 0x0, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERRIF6
r 		HTFIF6
r 		FTFIF6
r 		GIF6
r 		ERRIF5
r 		HTFIF5
r 		FTFIF5
r 		GIF5
r 		ERRIF4
r 		HTFIF4
r 		FTFIF4
r 		GIF4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIF3
r 		HTFIF3
r 		FTFIF3
r 		GIF3
r 		ERRIF2
r 		HTFIF2
r 		FTFIF2
r 		GIF2
r 		ERRIF1
r 		HTFIF1
r 		FTFIF1
r 		GIF1
r 		ERRIF0
r 		HTFIF0
r 		FTFIF0
r 		GIF0
r
Toggle Fields.

GIF0

Bit 0: Global interrupt flag of channel 0.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF0

Bit 1: Full Transfer finish flag of channe 0.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF0

Bit 2: Half transfer finish flag of channel 0.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF0

Bit 3: Error flag of channel 0.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF1

Bit 4: Global interrupt flag of channel 1.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF1

Bit 5: Full Transfer finish flag of channe 1.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF1

Bit 6: Half transfer finish flag of channel 1.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF1

Bit 7: Error flag of channel 1.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF2

Bit 8: Global interrupt flag of channel 2.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF2

Bit 9: Full Transfer finish flag of channe 2.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF2

Bit 10: Half transfer finish flag of channel 2.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF2

Bit 11: Error flag of channel 2.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF3

Bit 12: Global interrupt flag of channel 3.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF3

Bit 13: Full Transfer finish flag of channe 3.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF3

Bit 14: Half transfer finish flag of channel 3.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF3

Bit 15: Error flag of channel 3.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF4

Bit 16: Global interrupt flag of channel 4.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF4

Bit 17: Full Transfer finish flag of channe 4.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF4

Bit 18: Half transfer finish flag of channel 4.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF4

Bit 19: Error flag of channel 4.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF5

Bit 20: Global interrupt flag of channel 5.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF5

Bit 21: Full Transfer finish flag of channe 5.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF5

Bit 22: Half transfer finish flag of channel 5.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF5

Bit 23: Error flag of channel 5.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF6

Bit 24: Global interrupt flag of channel 6.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF6

Bit 25: Full Transfer finish flag of channe 6.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF6

Bit 26: Half transfer finish flag of channel 6.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF6

Bit 27: Error flag of channel 6.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

INTC

Interrupt flag clear register

Offset: 0x4, reset: 0x00000000, access: write-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERRIFC6
w 		HTFIFC6
w 		FTFIFC6
w 		GIFC6
w 		ERRIFC5
w 		HTFIFC5
w 		FTFIFC5
w 		GIFC5
w 		ERRIFC4
w 		HTFIFC4
w 		FTFIFC4
w 		GIFC4
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIFC3
w 		HTFIFC3
w 		FTFIFC3
w 		GIFC3
w 		ERRIFC2
w 		HTFIFC2
w 		FTFIFC2
w 		GIFC2
w 		ERRIFC1
w 		HTFIFC1
w 		FTFIFC1
w 		GIFC1
w 		ERRIFC0
w 		HTFIFC0
w 		FTFIFC0
w 		GIFC0
w
Toggle Fields.

GIFC0

Bit 0: Clear global interrupt flag of channel 0.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC0

Bit 1: Clear bit for full transfer finish flag of channel 0.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC0

Bit 2: Clear bit for half transfer finish flag of channel 0.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC0

Bit 3: Clear bit for error flag of channel 0.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC1

Bit 4: Clear global interrupt flag of channel 1.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC1

Bit 5: Clear bit for full transfer finish flag of channel 1.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC1

Bit 6: Clear bit for half transfer finish flag of channel 1.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC1

Bit 7: Clear bit for error flag of channel 1.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC2

Bit 8: Clear global interrupt flag of channel 2.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC2

Bit 9: Clear bit for full transfer finish flag of channel 2.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC2

Bit 10: Clear bit for half transfer finish flag of channel 2.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC2

Bit 11: Clear bit for error flag of channel 2.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC3

Bit 12: Clear global interrupt flag of channel 3.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC3

Bit 13: Clear bit for full transfer finish flag of channel 3.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC3

Bit 14: Clear bit for half transfer finish flag of channel 3.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC3

Bit 15: Clear bit for error flag of channel 3.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC4

Bit 16: Clear global interrupt flag of channel 4.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC4

Bit 17: Clear bit for full transfer finish flag of channel 4.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC4

Bit 18: Clear bit for half transfer finish flag of channel 4.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC4

Bit 19: Clear bit for error flag of channel 4.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC5

Bit 20: Clear global interrupt flag of channel 5.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC5

Bit 21: Clear bit for full transfer finish flag of channel 5.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC5

Bit 22: Clear bit for half transfer finish flag of channel 5.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC5

Bit 23: Clear bit for error flag of channel 5.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC6

Bit 24: Clear global interrupt flag of channel 6.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC6

Bit 25: Clear bit for full transfer finish flag of channel 6.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC6

Bit 26: Clear bit for half transfer finish flag of channel 6.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC6

Bit 27: Clear bit for error flag of channel 6.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

CH0CTL

Channel 0 control register

Offset: 0x8, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH0CNT

Channel 0 counter register

Offset: 0xC, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH0PADDR

Channel 0 peripheral base address register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH0MADDR

Channel 0 memory base address register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH1CTL

Channel 1 control register

Offset: 0x1C, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH1CNT

Channel 1 counter register

Offset: 0x20, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH1PADDR

Channel 1 peripheral base address register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH1MADDR

Channel 1 memory base address register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH2CTL

Channel 2 control register

Offset: 0x30, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH2CNT

Channel 2 counter register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH2PADDR

Channel 2 peripheral base address register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH2MADDR

Channel 2 memory base address register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH3CTL

Channel 3 control register

Offset: 0x44, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH3CNT

Channel 3 counter register

Offset: 0x48, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH3PADDR

Channel 3 peripheral base address register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH3MADDR

Channel 3 memory base address register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH4CTL

Channel 4 control register

Offset: 0x58, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH4CNT

Channel 4 counter register

Offset: 0x5C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH4PADDR

Channel 4 peripheral base address register

Offset: 0x60, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH4MADDR

Channel 4 memory base address register

Offset: 0x64, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH5CTL

Channel 5 control register

Offset: 0x6C, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH5CNT

Channel 5 counter register

Offset: 0x70, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH5PADDR

Channel 5 peripheral base address register

Offset: 0x74, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH5MADDR

Channel 5 memory base address register

Offset: 0x78, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH6CTL

Channel 6 control register

Offset: 0x80, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH6CNT

Channel 6 counter register

Offset: 0x84, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH6PADDR

Channel 6 peripheral base address register

Offset: 0x88, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH6MADDR

Channel 6 memory base address register

Offset: 0x8C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

DMA1

0x40020400: DMA controller

105/115 fields covered. Toggle Registers.

INTF

Interrupt flag register

Offset: 0x0, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERRIF4
r 		HTFIF4
r 		FTFIF4
r 		GIF4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIF3
r 		HTFIF3
r 		FTFIF3
r 		GIF3
r 		ERRIF2
r 		HTFIF2
r 		FTFIF2
r 		GIF2
r 		ERRIF1
r 		HTFIF1
r 		FTFIF1
r 		GIF1
r 		ERRIF0
r 		HTFIF0
r 		FTFIF0
r 		GIF0
r
Toggle Fields.

GIF0

Bit 0: Global interrupt flag of channel 0.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF0

Bit 1: Full Transfer finish flag of channe 0.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF0

Bit 2: Half transfer finish flag of channel 0.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF0

Bit 3: Error flag of channel 0.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF1

Bit 4: Global interrupt flag of channel 1.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF1

Bit 5: Full Transfer finish flag of channe 1.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF1

Bit 6: Half transfer finish flag of channel 1.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF1

Bit 7: Error flag of channel 1.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF2

Bit 8: Global interrupt flag of channel 2.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF2

Bit 9: Full Transfer finish flag of channe 2.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF2

Bit 10: Half transfer finish flag of channel 2.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF2

Bit 11: Error flag of channel 2.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF3

Bit 12: Global interrupt flag of channel 3.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF3

Bit 13: Full Transfer finish flag of channe 3.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF3

Bit 14: Half transfer finish flag of channel 3.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF3

Bit 15: Error flag of channel 3.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF4

Bit 16: Global interrupt flag of channel 4.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF4

Bit 17: Full Transfer finish flag of channe 4.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF4

Bit 18: Half transfer finish flag of channel 4.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF4

Bit 19: Error flag of channel 4.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

INTC

Interrupt flag clear register

Offset: 0x4, reset: 0x00000000, access: write-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERRIFC4
w 		HTFIFC4
w 		FTFIFC4
w 		GIFC4
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIFC3
w 		HTFIFC3
w 		FTFIFC3
w 		GIFC3
w 		ERRIFC2
w 		HTFIFC2
w 		FTFIFC2
w 		GIFC2
w 		ERRIFC1
w 		HTFIFC1
w 		FTFIFC1
w 		GIFC1
w 		ERRIFC0
w 		HTFIFC0
w 		FTFIFC0
w 		GIFC0
w
Toggle Fields.

GIFC0

Bit 0: Clear global interrupt flag of channel 0.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC0

Bit 1: Clear bit for full transfer finish flag of channel 0.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC0

Bit 2: Clear bit for half transfer finish flag of channel 0.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC0

Bit 3: Clear bit for error flag of channel 0.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC1

Bit 4: Clear global interrupt flag of channel 1.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC1

Bit 5: Clear bit for full transfer finish flag of channel 1.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC1

Bit 6: Clear bit for half transfer finish flag of channel 1.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC1

Bit 7: Clear bit for error flag of channel 1.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC2

Bit 8: Clear global interrupt flag of channel 2.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC2

Bit 9: Clear bit for full transfer finish flag of channel 2.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC2

Bit 10: Clear bit for half transfer finish flag of channel 2.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC2

Bit 11: Clear bit for error flag of channel 2.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC3

Bit 12: Clear global interrupt flag of channel 3.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC3

Bit 13: Clear bit for full transfer finish flag of channel 3.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC3

Bit 14: Clear bit for half transfer finish flag of channel 3.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC3

Bit 15: Clear bit for error flag of channel 3.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC4

Bit 16: Clear global interrupt flag of channel 4.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC4

Bit 17: Clear bit for full transfer finish flag of channel 4.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC4

Bit 18: Clear bit for half transfer finish flag of channel 4.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC4

Bit 19: Clear bit for error flag of channel 4.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

CH0CTL

Channel 0 control register

Offset: 0x8, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH0CNT

Channel 0 counter register

Offset: 0xC, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH0PADDR

Channel 0 peripheral base address register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH0MADDR

Channel 0 memory base address register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH1CTL

Channel 1 control register

Offset: 0x1C, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH1CNT

Channel 1 counter register

Offset: 0x20, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH1PADDR

Channel 1 peripheral base address register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH1MADDR

Channel 1 memory base address register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH2CTL

Channel 2 control register

Offset: 0x30, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH2CNT

Channel 2 counter register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH2PADDR

Channel 2 peripheral base address register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH2MADDR

Channel 2 memory base address register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH3CTL

Channel 3 control register

Offset: 0x44, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH3CNT

Channel 3 counter register

Offset: 0x48, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH3PADDR

Channel 3 peripheral base address register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH3MADDR

Channel 3 memory base address register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH4CTL

Channel 4 control register

Offset: 0x58, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH4CNT

Channel 4 counter register

Offset: 0x5C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH4PADDR

Channel 4 peripheral base address register

Offset: 0x60, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH4MADDR

Channel 4 memory base address register

Offset: 0x64, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

EXMC

0xA0000000: External memory controller

2/183 fields covered. Toggle Registers.

SNCTL0

SRAM/NOR flash control register 0

Offset: 0x0, reset: 0x000030DA, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCWR
rw 		CPS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXMODEN
rw 		NRWTEN
rw 		WREN
rw 		NRWTCFG
rw 		WRAPEN
rw 		NRWTPOL
rw 		SBRSTEN
rw 		NREN
rw 		NRW
rw 		NRTP
rw 		NRMUX
rw 		NRBKEN
rw
Toggle Fields.

NRBKEN

Bit 0: NOR bank enable.

NRMUX

Bit 1: NOR bank memory address/data multiplexing.

NRTP

Bits 2-3: NOR bank memory type.

NRW

Bits 4-5: NOR bank memory data bus width.

NREN

Bit 6: NOR Flash access enable.

SBRSTEN

Bit 8: Synchronous burst enable.

NRWTPOL

Bit 9: NWAIT signal polarity.

WRAPEN

Bit 10: Wrapped burst mode enable.

NRWTCFG

Bit 11: NWAIT signal configuration, only work in synchronous mode.

WREN

Bit 12: Write enable.

NRWTEN

Bit 13: NWAIT signal enable.

EXMODEN

Bit 14: Extended mode enable.

ASYNCWAIT

Bit 15: Asynchronous wait.

CPS

Bits 16-18: CRAM page size.

SYNCWR

Bit 19: Synchronous write.

SNTCFG0

SRAM/NOR flash timing configuration register 0

Offset: 0x4, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ASYNCMOD
rw 		DLAT
rw 		CKDIV
rw 		BUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSET
rw 		AHLD
rw 		ASET
rw
Toggle Fields.

ASET

Bits 0-3: Address setup time.

AHLD

Bits 4-7: Address hold time.

DSET

Bits 8-15: Data setup time.

BUSLAT

Bits 16-19: Bus latency.

CKDIV

Bits 20-23: Synchronous clock divide ratio.

DLAT

Bits 24-27: Data latency for NOR Flash.

ASYNCMOD

Bits 28-29: Asynchronous access mode.

SNCTL1

SRAM/NOR flash control register 1

Offset: 0x8, reset: 0x000030D2, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCWR
rw 		CPS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXMODEN
rw 		NRWTEN
rw 		WREN
rw 		NRWTCFG
rw 		WRAPEN
rw 		NRWTPOL
rw 		SBRSTEN
rw 		NREN
rw 		NRW
rw 		NRTP
rw 		NRMUX
rw 		NRBKEN
rw
Toggle Fields.

NRBKEN

Bit 0: NOR bank enable.

NRMUX

Bit 1: NOR bank memory address/data multiplexing.

NRTP

Bits 2-3: NOR bank memory type.

NRW

Bits 4-5: NOR bank memory data bus width.

NREN

Bit 6: NOR Flash access enable.

SBRSTEN

Bit 8: Synchronous burst enable.

NRWTPOL

Bit 9: NWAIT signal polarity.

WRAPEN

Bit 10: Wrapped burst mode enable.

NRWTCFG

Bit 11: NWAIT signal configuration, only work in synchronous mode.

WREN

Bit 12: Write enable.

NRWTEN

Bit 13: NWAIT signal enable.

EXMODEN

Bit 14: Extended mode enable.

ASYNCWAIT

Bit 15: Asynchronous wait.

CPS

Bits 16-18: CRAM page size.

SYNCWR

Bit 19: Synchronous write.

SNTCFG1

SRAM/NOR flash timing configuration register 1

Offset: 0xC, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ASYNCMOD
rw 		DLAT
rw 		CKDIV
rw 		BUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSET
rw 		AHLD
rw 		ASET
rw
Toggle Fields.

ASET

Bits 0-3: Address setup time.

AHLD

Bits 4-7: Address hold time.

DSET

Bits 8-15: Data setup time.

BUSLAT

Bits 16-19: Bus latency.

CKDIV

Bits 20-23: Synchronous clock divide ratio.

DLAT

Bits 24-27: Data latency for NOR Flash.

ASYNCMOD

Bits 28-29: Asynchronous access mode.

SNCTL2

SRAM/NOR flash control register 2

Offset: 0x10, reset: 0x000030D2, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCWR
rw 		CPS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXMODEN
rw 		NRWTEN
rw 		WREN
rw 		NRWTCFG
rw 		WRAPEN
rw 		NRWTPOL
rw 		SBRSTEN
rw 		NREN
rw 		NRW
rw 		NRTP
rw 		NRMUX
rw 		NRBKEN
rw
Toggle Fields.

NRBKEN

Bit 0: NOR bank enable.

NRMUX

Bit 1: NOR bank memory address/data multiplexing.

NRTP

Bits 2-3: NOR bank memory type.

NRW

Bits 4-5: NOR bank memory data bus width.

NREN

Bit 6: NOR Flash access enable.

SBRSTEN

Bit 8: Synchronous burst enable.

NRWTPOL

Bit 9: NWAIT signal polarity.

WRAPEN

Bit 10: Wrapped burst mode enable.

NRWTCFG

Bit 11: NWAIT signal configuration, only work in synchronous mode.

WREN

Bit 12: Write enable.

NRWTEN

Bit 13: NWAIT signal enable.

EXMODEN

Bit 14: Extended mode enable.

ASYNCWAIT

Bit 15: Asynchronous wait.

CPS

Bits 16-18: CRAM page size.

SYNCWR

Bit 19: Synchronous write.

SNTCFG2

SRAM/NOR flash timing configuration register 2

Offset: 0x14, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ASYNCMOD
rw 		DLAT
rw 		CKDIV
rw 		BUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSET
rw 		AHLD
rw 		ASET
rw
Toggle Fields.

ASET

Bits 0-3: Address setup time.

AHLD

Bits 4-7: Address hold time.

DSET

Bits 8-15: Data setup time.

BUSLAT

Bits 16-19: Bus latency.

CKDIV

Bits 20-23: Synchronous clock divide ratio.

DLAT

Bits 24-27: Data latency for NOR Flash.

ASYNCMOD

Bits 28-29: Asynchronous access mode.

SNCTL3

SRAM/NOR flash control register 3

Offset: 0x18, reset: 0x000030D2, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCWR
rw 		CPS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXMODEN
rw 		NRWTEN
rw 		WREN
rw 		NRWTCFG
rw 		WRAPEN
rw 		NRWTPOL
rw 		SBRSTEN
rw 		NREN
rw 		NRW
rw 		NRTP
rw 		NRMUX
rw 		NRBKEN
rw
Toggle Fields.

NRBKEN

Bit 0: NOR bank enable.

NRMUX

Bit 1: NOR bank memory address/data multiplexing.

NRTP

Bits 2-3: NOR bank memory type.

NRW

Bits 4-5: NOR bank memory data bus width.

NREN

Bit 6: NOR Flash access enable.

SBRSTEN

Bit 8: Synchronous burst enable.

NRWTPOL

Bit 9: NWAIT signal polarity.

WRAPEN

Bit 10: Wrapped burst mode enable.

NRWTCFG

Bit 11: NWAIT signal configuration, only work in synchronous mode.

WREN

Bit 12: Write enable.

NRWTEN

Bit 13: NWAIT signal enable.

EXMODEN

Bit 14: Extended mode enable.

ASYNCWAIT

Bit 15: Asynchronous wait.

CPS

Bits 16-18: CRAM page size.

SYNCWR

Bit 19: Synchronous write.

SNTCFG3

SRAM/NOR flash timing configuration register 3

Offset: 0x1C, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ASYNCMOD
rw 		DLAT
rw 		CKDIV
rw 		BUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSET
rw 		AHLD
rw 		ASET
rw
Toggle Fields.

ASET

Bits 0-3: Address setup time.

AHLD

Bits 4-7: Address hold time.

DSET

Bits 8-15: Data setup time.

BUSLAT

Bits 16-19: Bus latency.

CKDIV

Bits 20-23: Synchronous clock divide ratio.

DLAT

Bits 24-27: Data latency for NOR Flash.

ASYNCMOD

Bits 28-29: Asynchronous access mode.

NPCTL1

NAND flash/PC card control register 1

Offset: 0x60, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCSZ
rw 		ATR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATR
rw 		CTR
rw 		ECCEN
rw 		NDW
rw 		NDTP
rw 		NDBKEN
rw 		NDWTEN
rw
Toggle Fields.

NDWTEN

Bit 1: Wait feature enable.

NDBKEN

Bit 2: NAND bank enable.

NDTP

Bit 3: NAND bank memory type.

NDW

Bits 4-5: NAND bank memory data bus width.

ECCEN

Bit 6: ECC enable.

CTR

Bits 9-12: CLE to RE delay.

ATR

Bits 13-16: ALE to RE delay.

ECCSZ

Bits 17-19: ECC size.

NPINTEN1

NAND flash/PC card interrupt enable register 1

Offset: 0x64, reset: 0x00000042, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFEPT
rw 		INTFEN
rw 		INTHEN
rw 		INTREN
rw 		INTFS
rw 		INTHS
rw 		INTRS
rw
Toggle Fields.

INTRS

Bit 0: Interrupt rising edge status.

INTHS

Bit 1: Interrupt high-level status.

INTFS

Bit 2: Interrupt falling edge status.

INTREN

Bit 3: Interrupt rising edge detection enable bit.

INTHEN

Bit 4: Interrupt high-level detection enable.

INTFEN

Bit 5: Interrupt falling edge detection enable.

FFEPT

Bit 6: FIFO empty flag.

NPCTCFG1

NAND flash/PC card common space timing configuration register 1

Offset: 0x68, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMHIZ
rw 		COMHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMWAIT
rw 		COMSET
rw
Toggle Fields.

COMSET

Bits 0-7: Common memory setup time.

COMWAIT

Bits 8-15: Common memory wait time.

COMHLD

Bits 16-23: Common memory hold time.

COMHIZ

Bits 24-31: Common memory data bus HiZ time.

NPATCFG1

NAND flash/PC card attribute space timing configuration register 1

Offset: 0x6C, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw 		ATTHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw 		ATTSET
rw
Toggle Fields.

ATTSET

Bits 0-7: Attribute memory setup time.

ATTWAIT

Bits 8-15: Attribute memory wait time.

ATTHLD

Bits 16-23: Attribute memory hold time.

ATTHIZ

Bits 24-31: Attribute memory data bus HiZ time.

NECC1

NAND flash ECC register 1

Offset: 0x74, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC
r
Toggle Fields.

ECC

Bits 0-31: ECC result.

NPCTL2

NAND flash/PC card control register 2

Offset: 0x80, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCSZ
rw 		ATR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATR
rw 		CTR
rw 		ECCEN
rw 		NDW
rw 		NDTP
rw 		NDBKEN
rw 		NDWTEN
rw
Toggle Fields.

NDWTEN

Bit 1: Wait feature enable.

NDBKEN

Bit 2: NAND bank enable.

NDTP

Bit 3: NAND bank memory type.

NDW

Bits 4-5: NAND bank memory data bus width.

ECCEN

Bit 6: ECC enable.

CTR

Bits 9-12: CLE to RE delay.

ATR

Bits 13-16: ALE to RE delay.

ECCSZ

Bits 17-19: ECC size.

NPINTEN2

NAND flash/PC card interrupt enable register 2

Offset: 0x84, reset: 0x00000042, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFEPT
rw 		INTFEN
rw 		INTHEN
rw 		INTREN
rw 		INTFS
rw 		INTHS
rw 		INTRS
rw
Toggle Fields.

INTRS

Bit 0: Interrupt rising edge status.

INTHS

Bit 1: Interrupt high-level status.

INTFS

Bit 2: Interrupt falling edge status.

INTREN

Bit 3: Interrupt rising edge detection enable bit.

INTHEN

Bit 4: Interrupt high-level detection enable.

INTFEN

Bit 5: Interrupt falling edge detection enable.

FFEPT

Bit 6: FIFO empty flag.

NPCTCFG2

NAND flash/PC card common space timing configuration register 2

Offset: 0x88, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMHIZ
rw 		COMHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMWAIT
rw 		COMSET
rw
Toggle Fields.

COMSET

Bits 0-7: Common memory setup time.

COMWAIT

Bits 8-15: Common memory wait time.

COMHLD

Bits 16-23: Common memory hold time.

COMHIZ

Bits 24-31: Common memory data bus HiZ time.

NPATCFG2

NAND flash/PC card attribute space timing configuration register 2

Offset: 0x8C, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw 		ATTHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw 		ATTSET
rw
Toggle Fields.

ATTSET

Bits 0-7: Attribute memory setup time.

ATTWAIT

Bits 8-15: Attribute memory wait time.

ATTHLD

Bits 16-23: Attribute memory hold time.

ATTHIZ

Bits 24-31: Attribute memory data bus HiZ time.

NECC2

NAND flash ECC register 2

Offset: 0x94, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC
r
Toggle Fields.

ECC

Bits 0-31: ECC result.

NPCTL3

NAND flash/PC card control register 3

Offset: 0xA0, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCSZ
rw 		ATR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATR
rw 		CTR
rw 		ECCEN
rw 		NDW
rw 		NDTP
rw 		NDBKEN
rw 		NDWTEN
rw
Toggle Fields.

NDWTEN

Bit 1: Wait feature enable.

NDBKEN

Bit 2: NAND bank enable.

NDTP

Bit 3: NAND bank memory type.

NDW

Bits 4-5: NAND bank memory data bus width.

ECCEN

Bit 6: ECC enable.

CTR

Bits 9-12: CLE to RE delay.

ATR

Bits 13-16: ALE to RE delay.

ECCSZ

Bits 17-19: ECC size.

NPINTEN3

NAND flash/PC card interrupt enable register 3

Offset: 0xA4, reset: 0x00000042, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFEPT
rw 		INTFEN
rw 		INTHEN
rw 		INTREN
rw 		INTFS
rw 		INTHS
rw 		INTRS
rw
Toggle Fields.

INTRS

Bit 0: Interrupt rising edge status.

INTHS

Bit 1: Interrupt high-level status.

INTFS

Bit 2: Interrupt falling edge status.

INTREN

Bit 3: Interrupt rising edge detection enable bit.

INTHEN

Bit 4: Interrupt high-level detection enable.

INTFEN

Bit 5: Interrupt falling edge detection enable.

FFEPT

Bit 6: FIFO empty flag.

NPCTCFG3

NAND flash/PC card common space timing configuration register 3

Offset: 0xA8, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMHIZ
rw 		COMHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMWAIT
rw 		COMSET
rw
Toggle Fields.

COMSET

Bits 0-7: Common memory setup time.

COMWAIT

Bits 8-15: Common memory wait time.

COMHLD

Bits 16-23: Common memory hold time.

COMHIZ

Bits 24-31: Common memory data bus HiZ time.

NPATCFG3

NAND flash/PC card attribute space timing configuration register 3

Offset: 0xAC, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw 		ATTHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw 		ATTSET
rw
Toggle Fields.

ATTSET

Bits 0-7: Attribute memory setup time.

ATTWAIT

Bits 8-15: Attribute memory wait time.

ATTHLD

Bits 16-23: Attribute memory hold time.

ATTHIZ

Bits 24-31: Attribute memory data bus HiZ time.

PIOTCFG3

PC card I/O space timing configuration register

Offset: 0xB0, reset: 0xFFFFFFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOHIZ
rw 		IOHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOWAIT
rw 		IOSET
rw
Toggle Fields.

IOSET

Bits 0-7: IO space setup time.

IOWAIT

Bits 8-15: IO space wait time.

IOHLD

Bits 16-23: IO space hold time.

IOHIZ

Bits 24-31: IO space data bus HiZ time.

SNWTCFG0

SRAM/NOR flash write timing configuration register 0

Offset: 0x104, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WASYNCMOD
rw 		WBUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDSET
rw 		WAHLD
rw 		WASET
rw
Toggle Fields.

WASET

Bits 0-3: Address setup time.

WAHLD

Bits 4-7: Address hold time.

WDSET

Bits 8-15: Data setup time.

WBUSLAT

Bits 16-19: Bus latency.

WASYNCMOD

Bits 28-29: Asynchronous access mode.

SNWTCFG1

SRAM/NOR flash write timing configuration register 1

Offset: 0x10C, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WASYNCMOD
rw 		WBUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDSET
rw 		WAHLD
rw 		WASET
rw
Toggle Fields.

WASET

Bits 0-3: Address setup time.

WAHLD

Bits 4-7: Address hold time.

WDSET

Bits 8-15: Data setup time.

WBUSLAT

Bits 16-19: Bus latency.

WASYNCMOD

Bits 28-29: Asynchronous access mode.

SNWTCFG2

SRAM/NOR flash write timing configuration register 2

Offset: 0x114, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WASYNCMOD
rw 		WBUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDSET
rw 		WAHLD
rw 		WASET
rw
Toggle Fields.

WASET

Bits 0-3: Address setup time.

WAHLD

Bits 4-7: Address hold time.

WDSET

Bits 8-15: Data setup time.

WBUSLAT

Bits 16-19: Bus latency.

WASYNCMOD

Bits 28-29: Asynchronous access mode.

SNWTCFG3

SRAM/NOR flash write timing configuration register 3

Offset: 0x11C, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WASYNCMOD
rw 		WBUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDSET
rw 		WAHLD
rw 		WASET
rw
Toggle Fields.

WASET

Bits 0-3: Address setup time.

WAHLD

Bits 4-7: Address hold time.

WDSET

Bits 8-15: Data setup time.

WBUSLAT

Bits 16-19: Bus latency.

WASYNCMOD

Bits 28-29: Asynchronous access mode.

EXTI

0x40010400: External interrupt/event controller

132/132 fields covered. Toggle Registers.

INTEN

Interrupt enable register (EXTI_INTEN)

Offset: 0x0, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INTEN21
rw 		INTEN20
rw 		INTEN19
rw 		INTEN18
rw 		INTEN17
rw 		INTEN16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTEN15
rw 		INTEN14
rw 		INTEN13
rw 		INTEN12
rw 		INTEN11
rw 		INTEN10
rw 		INTEN9
rw 		INTEN8
rw 		INTEN7
rw 		INTEN6
rw 		INTEN5
rw 		INTEN4
rw 		INTEN3
rw 		INTEN2
rw 		INTEN1
rw 		INTEN0
rw
Toggle Fields.

INTEN0

Bit 0: Enable Interrupt on line 0.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN1

Bit 1: Enable Interrupt on line 1.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN2

Bit 2: Enable Interrupt on line 2.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN3

Bit 3: Enable Interrupt on line 3.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN4

Bit 4: Enable Interrupt on line 4.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN5

Bit 5: Enable Interrupt on line 5.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN6

Bit 6: Enable Interrupt on line 6.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN7

Bit 7: Enable Interrupt on line 7.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN8

Bit 8: Enable Interrupt on line 8.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN9

Bit 9: Enable Interrupt on line 9.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN10

Bit 10: Enable Interrupt on line 10.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN11

Bit 11: Enable Interrupt on line 11.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN12

Bit 12: Enable Interrupt on line 12.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN13

Bit 13: Enable Interrupt on line 13.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN14

Bit 14: Enable Interrupt on line 14.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN15

Bit 15: Enable Interrupt on line 15.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN16

Bit 16: Enable Interrupt on line 16.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN17

Bit 17: Enable Interrupt on line 17.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN18

Bit 18: Enable Interrupt on line 18.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN19

Bit 19: Enable Interrupt on line 19.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN20

Bit 20: Enable Interrupt on line 20.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN21

Bit 21: Enable Interrupt on line 21.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

EVEN

Event enable register (EXTI_EVEN)

Offset: 0x4, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EVEN21
rw 		EVEN20
rw 		EVEN19
rw 		EVEN18
rw 		EVEN17
rw 		EVEN16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EVEN15
rw 		EVEN14
rw 		EVEN13
rw 		EVEN12
rw 		EVEN11
rw 		EVEN10
rw 		EVEN9
rw 		EVEN8
rw 		EVEN7
rw 		EVEN6
rw 		EVEN5
rw 		EVEN4
rw 		EVEN3
rw 		EVEN2
rw 		EVEN1
rw 		EVEN0
rw
Toggle Fields.

EVEN0

Bit 0: Enable Event on line 0.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN1

Bit 1: Enable Event on line 1.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN2

Bit 2: Enable Event on line 2.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN3

Bit 3: Enable Event on line 3.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN4

Bit 4: Enable Event on line 4.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN5

Bit 5: Enable Event on line 5.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN6

Bit 6: Enable Event on line 6.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN7

Bit 7: Enable Event on line 7.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN8

Bit 8: Enable Event on line 8.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN9

Bit 9: Enable Event on line 9.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN10

Bit 10: Enable Event on line 10.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN11

Bit 11: Enable Event on line 11.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN12

Bit 12: Enable Event on line 12.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN13

Bit 13: Enable Event on line 13.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN14

Bit 14: Enable Event on line 14.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN15

Bit 15: Enable Event on line 15.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN16

Bit 16: Enable Event on line 16.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN17

Bit 17: Enable Event on line 17.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN18

Bit 18: Enable Event on line 18.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN19

Bit 19: Enable Event on line 19.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN20

Bit 20: Enable Event on line 20.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN21

Bit 21: Enable Event on line 21.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

RTEN

Rising Edge Trigger Enable register (EXTI_RTEN)

Offset: 0x8, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTEN21
rw 		RTEN20
rw 		RTEN19
rw 		RTEN18
rw 		RTEN17
rw 		RTEN16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTEN15
rw 		RTEN14
rw 		RTEN13
rw 		RTEN12
rw 		RTEN11
rw 		RTEN10
rw 		RTEN9
rw 		RTEN8
rw 		RTEN7
rw 		RTEN6
rw 		RTEN5
rw 		RTEN4
rw 		RTEN3
rw 		RTEN2
rw 		RTEN1
rw 		RTEN0
rw
Toggle Fields.

RTEN0

Bit 0: Rising edge trigger enable of line 0.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN1

Bit 1: Rising edge trigger enable of line 1.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN2

Bit 2: Rising edge trigger enable of line 2.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN3

Bit 3: Rising edge trigger enable of line 3.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN4

Bit 4: Rising edge trigger enable of line 4.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN5

Bit 5: Rising edge trigger enable of line 5.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN6

Bit 6: Rising edge trigger enable of line 6.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN7

Bit 7: Rising edge trigger enable of line 7.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN8

Bit 8: Rising edge trigger enable of line 8.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN9

Bit 9: Rising edge trigger enable of line 9.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN10

Bit 10: Rising edge trigger enable of line 10.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN11

Bit 11: Rising edge trigger enable of line 11.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN12

Bit 12: Rising edge trigger enable of line 12.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN13

Bit 13: Rising edge trigger enable of line 13.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN14

Bit 14: Rising edge trigger enable of line 14.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN15

Bit 15: Rising edge trigger enable of line 15.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN16

Bit 16: Rising edge trigger enable of line 16.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN17

Bit 17: Rising edge trigger enable of line 17.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN18

Bit 18: Rising edge trigger enable of line 18.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN19

Bit 19: Rising edge trigger enable of line 19.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN20

Bit 20: Rising edge trigger enable of line 20.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN21

Bit 21: Rising edge trigger enable of line 21.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTEN

Falling Egde Trigger Enable register (EXTI_FTEN)

Offset: 0xC, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTEN21
rw 		FTEN20
rw 		FTEN19
rw 		FTEN18
rw 		FTEN17
rw 		FTEN16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTEN15
rw 		FTEN14
rw 		FTEN13
rw 		FTEN12
rw 		FTEN11
rw 		FTEN10
rw 		FTEN9
rw 		FTEN8
rw 		FTEN7
rw 		FTEN6
rw 		FTEN5
rw 		FTEN4
rw 		FTEN3
rw 		FTEN2
rw 		FTEN1
rw 		FTEN0
rw
Toggle Fields.

FTEN0

Bit 0: Falling edge trigger enable of line 0.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN1

Bit 1: Falling edge trigger enable of line 1.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN2

Bit 2: Falling edge trigger enable of line 2.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN3

Bit 3: Falling edge trigger enable of line 3.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN4

Bit 4: Falling edge trigger enable of line 4.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN5

Bit 5: Falling edge trigger enable of line 5.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN6

Bit 6: Falling edge trigger enable of line 6.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN7

Bit 7: Falling edge trigger enable of line 7.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN8

Bit 8: Falling edge trigger enable of line 8.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN9

Bit 9: Falling edge trigger enable of line 9.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN10

Bit 10: Falling edge trigger enable of line 10.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN11

Bit 11: Falling edge trigger enable of line 11.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN12

Bit 12: Falling edge trigger enable of line 12.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN13

Bit 13: Falling edge trigger enable of line 13.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN14

Bit 14: Falling edge trigger enable of line 14.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN15

Bit 15: Falling edge trigger enable of line 15.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN16

Bit 16: Falling edge trigger enable of line 16.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN17

Bit 17: Falling edge trigger enable of line 17.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN18

Bit 18: Falling edge trigger enable of line 18.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN19

Bit 19: Falling edge trigger enable of line 19.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN20

Bit 20: Falling edge trigger enable of line 20.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN21

Bit 21: Falling edge trigger enable of line 21.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIEV

Software interrupt event register (EXTI_SWIEV)

Offset: 0x10, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWIEV21
rw 		SWIEV20
rw 		SWIEV19
rw 		SWIEV18
rw 		SWIEV17
rw 		SWIEV16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWIEV15
rw 		SWIEV14
rw 		SWIEV13
rw 		SWIEV12
rw 		SWIEV11
rw 		SWIEV10
rw 		SWIEV9
rw 		SWIEV8
rw 		SWIEV7
rw 		SWIEV6
rw 		SWIEV5
rw 		SWIEV4
rw 		SWIEV3
rw 		SWIEV2
rw 		SWIEV1
rw 		SWIEV0
rw
Toggle Fields.

SWIEV0

Bit 0: Interrupt/Event software trigger on line 0.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV1

Bit 1: Interrupt/Event software trigger on line 1.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV2

Bit 2: Interrupt/Event software trigger on line 2.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV3

Bit 3: Interrupt/Event software trigger on line 3.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV4

Bit 4: Interrupt/Event software trigger on line 4.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV5

Bit 5: Interrupt/Event software trigger on line 5.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV6

Bit 6: Interrupt/Event software trigger on line 6.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV7

Bit 7: Interrupt/Event software trigger on line 7.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV8

Bit 8: Interrupt/Event software trigger on line 8.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV9

Bit 9: Interrupt/Event software trigger on line 9.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV10

Bit 10: Interrupt/Event software trigger on line 10.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV11

Bit 11: Interrupt/Event software trigger on line 11.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV12

Bit 12: Interrupt/Event software trigger on line 12.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV13

Bit 13: Interrupt/Event software trigger on line 13.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV14

Bit 14: Interrupt/Event software trigger on line 14.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV15

Bit 15: Interrupt/Event software trigger on line 15.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV16

Bit 16: Interrupt/Event software trigger on line 16.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV17

Bit 17: Interrupt/Event software trigger on line 17.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV18

Bit 18: Interrupt/Event software trigger on line 18.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV19

Bit 19: Interrupt/Event software trigger on line 19.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV20

Bit 20: Interrupt/Event software trigger on line 20.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV21

Bit 21: Interrupt/Event software trigger on line 21.

Allowed values:
1: Pend: Generates an interrupt request

PD

Pending register (EXTI_PD)

Offset: 0x14, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PD21
rw 		PD20
rw 		PD19
rw 		PD18
rw 		PD17
rw 		PD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle Fields.

PD0

Bit 0: Interrupt pending status of line 0.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD1

Bit 1: Interrupt pending status of line 1.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD2

Bit 2: Interrupt pending status of line 2.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD3

Bit 3: Interrupt pending status of line 3.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD4

Bit 4: Interrupt pending status of line 4.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD5

Bit 5: Interrupt pending status of line 5.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD6

Bit 6: Interrupt pending status of line 6.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD7

Bit 7: Interrupt pending status of line 7.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD8

Bit 8: Interrupt pending status of line 8.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD9

Bit 9: Interrupt pending status of line 9.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD10

Bit 10: Interrupt pending status of line 10.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD11

Bit 11: Interrupt pending status of line 11.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD12

Bit 12: Interrupt pending status of line 12.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD13

Bit 13: Interrupt pending status of line 13.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD14

Bit 14: Interrupt pending status of line 14.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD15

Bit 15: Interrupt pending status of line 15.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD16

Bit 16: Interrupt pending status of line 16.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD17

Bit 17: Interrupt pending status of line 17.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD18

Bit 18: Interrupt pending status of line 18.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD19

Bit 19: Interrupt pending status of line 19.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD20

Bit 20: Interrupt pending status of line 20.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD21

Bit 21: Interrupt pending status of line 21.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FMC

0x40022000: FMC

24/30 fields covered. Toggle Registers.

WS

wait state counter register

Offset: 0x0, reset: 0x00000630, access: read-write

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCRST
rw 		ICRST
rw 		DCEN
rw 		ICEN
rw 		PFEN
rw 		WSCNT
rw
Toggle Fields.

WSCNT

Bits 0-2: wait state counter register.

Allowed values:
0: WS0: 0 wait states added
1: WS1: 1 wait state added
2: WS2: 2 wait states added

PFEN

Bit 4: Pre-fetch enable.

ICEN

Bit 9: IBUS cache enable.

DCEN

Bit 10: DBUS cache enable.

ICRST

Bit 11: IBUS cache reset.

DCRST

Bit 12: DBUS cache reset.

KEY

Unlock key register

Offset: 0x4, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-31: FMC_CTL unlock register.

Allowed values: 0-4294967295

OBKEY

Option byte unlock key register

Offset: 0x8, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OBKEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OBKEY
w
Toggle Fields.

OBKEY

Bits 0-31: FMC_ OBCTL0 option byte operation unlock register.

Allowed values: 0-4294967295

STAT

Status register

Offset: 0xC, reset: 0x00000000, access: Unspecified

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENDF
rw 		WPERR
rw 		PGAERR
rw 		PGERR
rw 		BUSY
r
Toggle Fields.

BUSY

Bit 0: The flash is busy bit.

Allowed values:
0: Inactive: No operation is in progress
1: Active: An operation is in progress

PGERR

Bit 2: Program error flag bit.

Allowed values:
0: NoError: There was no error
1: Error: There was an error programming flash

PGAERR

Bit 3: Program alignment error flag bit.

WPERR

Bit 4: Erase/Program protection error flag bit.

Allowed values:
0: NoError: There was no error
1: Error: There was an error erasing/programming protected pages

ENDF

Bit 5: End of operation flag bit.

Allowed values:
0: NoEvent: No end of operation occurred
1: Event: An end of operation event occurred

CTL

Control register

Offset: 0x10, reset: 0x00000080, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENDIE
rw 		ERRIE
rw 		OBWEN
rw 		LK
rw 		START
rw 		OBER
rw 		OBPG
rw 		MER
rw 		PER
rw 		PG
rw
Toggle Fields.

PG

Bit 0: Main flash program for bank0 command bit.

Allowed values:
1: Program: Flash programming activated

PER

Bit 1: Main flash page erase for bank0 command bit.

Allowed values:
1: PageErase: Erase activated for selected page

MER

Bit 2: Main flash mass erase for bank0 command bit.

Allowed values:
1: MassErase: Erase activated for all user sectors

OBPG

Bit 4: Option bytes program command bit.

Allowed values:
1: OptionByteProgramming: Program option byte activated

OBER

Bit 5: Option bytes erase command bit.

Allowed values:
1: OptionByteErase: Erase option byte activated

START

Bit 6: Send erase command to FMC bit.

Allowed values:
1: Start: Trigger an erase operation

LK

Bit 7: FMC_CTL0 lock bit.

Allowed values:
0: Unlocked: CTL register is unlocked
1: Locked: CTL register is locked

OBWEN

Bit 9: Option byte erase/program enable bit.

Allowed values:
0: Disabled: Option byte write disabled
1: Enabled: Option byte write enabled

ERRIE

Bit 10: Error interrupt enable bit.

Allowed values:
0: Disabled: Error interrupt generation disabled
1: Enabled: Error interrupt generation enabled

ENDIE

Bit 12: End of operation interrupt enable bit.

Allowed values:
0: Disabled: End of operation interrupt disabled
1: Enabled: End of operation interrupt enabled

ADDR

Address register

Offset: 0x14, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
w
Toggle Fields.

ADDR

Bits 0-31: Flash erase/program command address bits.

Allowed values: 0-4294967295

OBSTAT

Option byte status register

Offset: 0x1C, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r 		USER
r 		SPC
r 		OBERR
r
Toggle Fields.

OBERR

Bit 0: Option bytes read error bit.

SPC

Bit 1: Option bytes security protection code.

USER

Bits 2-9: Store USER of option bytes block after system reset.

DATA

Bits 10-25: Store DATA[15:0] of option bytes block after system reset.

WP

Erase/Program Protection register

Offset: 0x20, reset: 0xFFFFFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WP
r
Toggle Fields.

WP

Bits 0-31: Store WP[31:0] of option bytes block after system reset.

PID

Product ID register

Offset: 0x100, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PID
r
Toggle Fields.

PID

Bits 0-31: Product reserved ID code register.

Allowed values: 0-4294967295

FWDGT

0x40003000: free watchdog timer

5/5 fields covered. Toggle Registers.

CTL

Control register

Offset: 0x0, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMD
w
Toggle Fields.

CMD

Bits 0-15: Key value.

Allowed values:
21845: Enable: Enable access to PR, RLR and WINR registers (0x5555)
43690: Reset: Reset the watchdog value (0xAAAA)
52428: Start: Start the watchdog (0xCCCC)

PSC

Prescaler register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-2: Free watchdog timer prescaler selection.

Allowed values:
0: DivideBy4: Divider /4
1: DivideBy8: Divider /8
2: DivideBy16: Divider /16
3: DivideBy32: Divider /32
4: DivideBy64: Divider /64
5: DivideBy128: Divider /128
6: DivideBy256: Divider /256
7: DivideBy256bis: Divider /256

RLD

Reload register

Offset: 0x8, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RLD
rw
Toggle Fields.

RLD

Bits 0-11: Free watchdog timer counter reload value.

Allowed values: 0-4095

STAT

Status register

Offset: 0xC, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RUD
r 		PUD
r
Toggle Fields.

PUD

Bit 0: Free watchdog timer prescaler value update.

Allowed values:
0: Valid: The value read from the PSC register is valid
1: Ongoing: A write operation to to the PSC register is ongoing, so the value read is invalid

RUD

Bit 1: Free watchdog timer counter reload value update.

Allowed values:
0: Valid: The value read from the RLD register is valid
1: Ongoing: A write operation to to the RLD register is ongoing, so the value read is invalid

GPIOA

0x40010800: General-purpose I/Os

129/145 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK1

Bit 1: Port Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK2

Bit 2: Port Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK3

Bit 3: Port Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK4

Bit 4: Port Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK5

Bit 5: Port Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK6

Bit 6: Port Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK7

Bit 7: Port Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK8

Bit 8: Port Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK9

Bit 9: Port Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK10

Bit 10: Port Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK11

Bit 11: Port Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK12

Bit 12: Port Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK13

Bit 13: Port Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK14

Bit 14: Port Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK15

Bit 15: Port Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LKK

Bit 16: Lock sequence key .

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

SPD

Port bit speed register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPD15
rw 		SPD14
rw 		SPD13
rw 		SPD12
rw 		SPD11
rw 		SPD10
rw 		SPD9
rw 		SPD8
rw 		SPD7
rw 		SPD6
rw 		SPD5
rw 		SPD4
rw 		SPD3
rw 		SPD2
rw 		SPD1
rw 		SPD0
rw
Toggle Fields.

SPD0

Bit 0: Port 0 output max speed bits.

SPD1

Bit 1: Port 1 output max speed bits.

SPD2

Bit 2: Port 2 output max speed bits.

SPD3

Bit 3: Port 3 output max speed bits.

SPD4

Bit 4: Port 4 output max speed bits.

SPD5

Bit 5: Port 5 output max speed bits.

SPD6

Bit 6: Port 6 output max speed bits.

SPD7

Bit 7: Port 7 output max speed bits.

SPD8

Bit 8: Port 8 output max speed bits.

SPD9

Bit 9: Port 9 output max speed bits.

SPD10

Bit 10: Port 10 output max speed bits.

SPD11

Bit 11: Port 11 output max speed bits.

SPD12

Bit 12: Port 12 output max speed bits.

SPD13

Bit 13: Port 13 output max speed bits.

SPD14

Bit 14: Port 14 output max speed bits.

SPD15

Bit 15: Port 15 output max speed bits.

GPIOB

0x40010C00: General-purpose I/Os

129/145 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK1

Bit 1: Port Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK2

Bit 2: Port Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK3

Bit 3: Port Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK4

Bit 4: Port Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK5

Bit 5: Port Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK6

Bit 6: Port Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK7

Bit 7: Port Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK8

Bit 8: Port Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK9

Bit 9: Port Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK10

Bit 10: Port Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK11

Bit 11: Port Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK12

Bit 12: Port Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK13

Bit 13: Port Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK14

Bit 14: Port Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK15

Bit 15: Port Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LKK

Bit 16: Lock sequence key .

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

SPD

Port bit speed register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPD15
rw 		SPD14
rw 		SPD13
rw 		SPD12
rw 		SPD11
rw 		SPD10
rw 		SPD9
rw 		SPD8
rw 		SPD7
rw 		SPD6
rw 		SPD5
rw 		SPD4
rw 		SPD3
rw 		SPD2
rw 		SPD1
rw 		SPD0
rw
Toggle Fields.

SPD0

Bit 0: Port 0 output max speed bits.

SPD1

Bit 1: Port 1 output max speed bits.

SPD2

Bit 2: Port 2 output max speed bits.

SPD3

Bit 3: Port 3 output max speed bits.

SPD4

Bit 4: Port 4 output max speed bits.

SPD5

Bit 5: Port 5 output max speed bits.

SPD6

Bit 6: Port 6 output max speed bits.

SPD7

Bit 7: Port 7 output max speed bits.

SPD8

Bit 8: Port 8 output max speed bits.

SPD9

Bit 9: Port 9 output max speed bits.

SPD10

Bit 10: Port 10 output max speed bits.

SPD11

Bit 11: Port 11 output max speed bits.

SPD12

Bit 12: Port 12 output max speed bits.

SPD13

Bit 13: Port 13 output max speed bits.

SPD14

Bit 14: Port 14 output max speed bits.

SPD15

Bit 15: Port 15 output max speed bits.

GPIOC

0x40011000: General-purpose I/Os

112/145 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

LK1

Bit 1: Port Lock bit 1.

LK2

Bit 2: Port Lock bit 2.

LK3

Bit 3: Port Lock bit 3.

LK4

Bit 4: Port Lock bit 4.

LK5

Bit 5: Port Lock bit 5.

LK6

Bit 6: Port Lock bit 6.

LK7

Bit 7: Port Lock bit 7.

LK8

Bit 8: Port Lock bit 8.

LK9

Bit 9: Port Lock bit 9.

LK10

Bit 10: Port Lock bit 10.

LK11

Bit 11: Port Lock bit 11.

LK12

Bit 12: Port Lock bit 12.

LK13

Bit 13: Port Lock bit 13.

LK14

Bit 14: Port Lock bit 14.

LK15

Bit 15: Port Lock bit 15.

LKK

Bit 16: Lock sequence key .

SPD

Port bit speed register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPD15
rw 		SPD14
rw 		SPD13
rw 		SPD12
rw 		SPD11
rw 		SPD10
rw 		SPD9
rw 		SPD8
rw 		SPD7
rw 		SPD6
rw 		SPD5
rw 		SPD4
rw 		SPD3
rw 		SPD2
rw 		SPD1
rw 		SPD0
rw
Toggle Fields.

SPD0

Bit 0: Port 0 output max speed bits.

SPD1

Bit 1: Port 1 output max speed bits.

SPD2

Bit 2: Port 2 output max speed bits.

SPD3

Bit 3: Port 3 output max speed bits.

SPD4

Bit 4: Port 4 output max speed bits.

SPD5

Bit 5: Port 5 output max speed bits.

SPD6

Bit 6: Port 6 output max speed bits.

SPD7

Bit 7: Port 7 output max speed bits.

SPD8

Bit 8: Port 8 output max speed bits.

SPD9

Bit 9: Port 9 output max speed bits.

SPD10

Bit 10: Port 10 output max speed bits.

SPD11

Bit 11: Port 11 output max speed bits.

SPD12

Bit 12: Port 12 output max speed bits.

SPD13

Bit 13: Port 13 output max speed bits.

SPD14

Bit 14: Port 14 output max speed bits.

SPD15

Bit 15: Port 15 output max speed bits.

GPIOD

0x40011400: General-purpose I/Os

112/145 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

LK1

Bit 1: Port Lock bit 1.

LK2

Bit 2: Port Lock bit 2.

LK3

Bit 3: Port Lock bit 3.

LK4

Bit 4: Port Lock bit 4.

LK5

Bit 5: Port Lock bit 5.

LK6

Bit 6: Port Lock bit 6.

LK7

Bit 7: Port Lock bit 7.

LK8

Bit 8: Port Lock bit 8.

LK9

Bit 9: Port Lock bit 9.

LK10

Bit 10: Port Lock bit 10.

LK11

Bit 11: Port Lock bit 11.

LK12

Bit 12: Port Lock bit 12.

LK13

Bit 13: Port Lock bit 13.

LK14

Bit 14: Port Lock bit 14.

LK15

Bit 15: Port Lock bit 15.

LKK

Bit 16: Lock sequence key .

SPD

Port bit speed register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPD15
rw 		SPD14
rw 		SPD13
rw 		SPD12
rw 		SPD11
rw 		SPD10
rw 		SPD9
rw 		SPD8
rw 		SPD7
rw 		SPD6
rw 		SPD5
rw 		SPD4
rw 		SPD3
rw 		SPD2
rw 		SPD1
rw 		SPD0
rw
Toggle Fields.

SPD0

Bit 0: Port 0 output max speed bits.

SPD1

Bit 1: Port 1 output max speed bits.

SPD2

Bit 2: Port 2 output max speed bits.

SPD3

Bit 3: Port 3 output max speed bits.

SPD4

Bit 4: Port 4 output max speed bits.

SPD5

Bit 5: Port 5 output max speed bits.

SPD6

Bit 6: Port 6 output max speed bits.

SPD7

Bit 7: Port 7 output max speed bits.

SPD8

Bit 8: Port 8 output max speed bits.

SPD9

Bit 9: Port 9 output max speed bits.

SPD10

Bit 10: Port 10 output max speed bits.

SPD11

Bit 11: Port 11 output max speed bits.

SPD12

Bit 12: Port 12 output max speed bits.

SPD13

Bit 13: Port 13 output max speed bits.

SPD14

Bit 14: Port 14 output max speed bits.

SPD15

Bit 15: Port 15 output max speed bits.

GPIOE

0x40011800: General-purpose I/Os

112/145 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

LK1

Bit 1: Port Lock bit 1.

LK2

Bit 2: Port Lock bit 2.

LK3

Bit 3: Port Lock bit 3.

LK4

Bit 4: Port Lock bit 4.

LK5

Bit 5: Port Lock bit 5.

LK6

Bit 6: Port Lock bit 6.

LK7

Bit 7: Port Lock bit 7.

LK8

Bit 8: Port Lock bit 8.

LK9

Bit 9: Port Lock bit 9.

LK10

Bit 10: Port Lock bit 10.

LK11

Bit 11: Port Lock bit 11.

LK12

Bit 12: Port Lock bit 12.

LK13

Bit 13: Port Lock bit 13.

LK14

Bit 14: Port Lock bit 14.

LK15

Bit 15: Port Lock bit 15.

LKK

Bit 16: Lock sequence key .

SPD

Port bit speed register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPD15
rw 		SPD14
rw 		SPD13
rw 		SPD12
rw 		SPD11
rw 		SPD10
rw 		SPD9
rw 		SPD8
rw 		SPD7
rw 		SPD6
rw 		SPD5
rw 		SPD4
rw 		SPD3
rw 		SPD2
rw 		SPD1
rw 		SPD0
rw
Toggle Fields.

SPD0

Bit 0: Port 0 output max speed bits.

SPD1

Bit 1: Port 1 output max speed bits.

SPD2

Bit 2: Port 2 output max speed bits.

SPD3

Bit 3: Port 3 output max speed bits.

SPD4

Bit 4: Port 4 output max speed bits.

SPD5

Bit 5: Port 5 output max speed bits.

SPD6

Bit 6: Port 6 output max speed bits.

SPD7

Bit 7: Port 7 output max speed bits.

SPD8

Bit 8: Port 8 output max speed bits.

SPD9

Bit 9: Port 9 output max speed bits.

SPD10

Bit 10: Port 10 output max speed bits.

SPD11

Bit 11: Port 11 output max speed bits.

SPD12

Bit 12: Port 12 output max speed bits.

SPD13

Bit 13: Port 13 output max speed bits.

SPD14

Bit 14: Port 14 output max speed bits.

SPD15

Bit 15: Port 15 output max speed bits.

GPIOF

0x40011C00: General-purpose I/Os

112/145 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

LK1

Bit 1: Port Lock bit 1.

LK2

Bit 2: Port Lock bit 2.

LK3

Bit 3: Port Lock bit 3.

LK4

Bit 4: Port Lock bit 4.

LK5

Bit 5: Port Lock bit 5.

LK6

Bit 6: Port Lock bit 6.

LK7

Bit 7: Port Lock bit 7.

LK8

Bit 8: Port Lock bit 8.

LK9

Bit 9: Port Lock bit 9.

LK10

Bit 10: Port Lock bit 10.

LK11

Bit 11: Port Lock bit 11.

LK12

Bit 12: Port Lock bit 12.

LK13

Bit 13: Port Lock bit 13.

LK14

Bit 14: Port Lock bit 14.

LK15

Bit 15: Port Lock bit 15.

LKK

Bit 16: Lock sequence key .

SPD

Port bit speed register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPD15
rw 		SPD14
rw 		SPD13
rw 		SPD12
rw 		SPD11
rw 		SPD10
rw 		SPD9
rw 		SPD8
rw 		SPD7
rw 		SPD6
rw 		SPD5
rw 		SPD4
rw 		SPD3
rw 		SPD2
rw 		SPD1
rw 		SPD0
rw
Toggle Fields.

SPD0

Bit 0: Port 0 output max speed bits.

SPD1

Bit 1: Port 1 output max speed bits.

SPD2

Bit 2: Port 2 output max speed bits.

SPD3

Bit 3: Port 3 output max speed bits.

SPD4

Bit 4: Port 4 output max speed bits.

SPD5

Bit 5: Port 5 output max speed bits.

SPD6

Bit 6: Port 6 output max speed bits.

SPD7

Bit 7: Port 7 output max speed bits.

SPD8

Bit 8: Port 8 output max speed bits.

SPD9

Bit 9: Port 9 output max speed bits.

SPD10

Bit 10: Port 10 output max speed bits.

SPD11

Bit 11: Port 11 output max speed bits.

SPD12

Bit 12: Port 12 output max speed bits.

SPD13

Bit 13: Port 13 output max speed bits.

SPD14

Bit 14: Port 14 output max speed bits.

SPD15

Bit 15: Port 15 output max speed bits.

GPIOG

0x40012000: General-purpose I/Os

112/145 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

LK1

Bit 1: Port Lock bit 1.

LK2

Bit 2: Port Lock bit 2.

LK3

Bit 3: Port Lock bit 3.

LK4

Bit 4: Port Lock bit 4.

LK5

Bit 5: Port Lock bit 5.

LK6

Bit 6: Port Lock bit 6.

LK7

Bit 7: Port Lock bit 7.

LK8

Bit 8: Port Lock bit 8.

LK9

Bit 9: Port Lock bit 9.

LK10

Bit 10: Port Lock bit 10.

LK11

Bit 11: Port Lock bit 11.

LK12

Bit 12: Port Lock bit 12.

LK13

Bit 13: Port Lock bit 13.

LK14

Bit 14: Port Lock bit 14.

LK15

Bit 15: Port Lock bit 15.

LKK

Bit 16: Lock sequence key .

SPD

Port bit speed register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPD15
rw 		SPD14
rw 		SPD13
rw 		SPD12
rw 		SPD11
rw 		SPD10
rw 		SPD9
rw 		SPD8
rw 		SPD7
rw 		SPD6
rw 		SPD5
rw 		SPD4
rw 		SPD3
rw 		SPD2
rw 		SPD1
rw 		SPD0
rw
Toggle Fields.

SPD0

Bit 0: Port 0 output max speed bits.

SPD1

Bit 1: Port 1 output max speed bits.

SPD2

Bit 2: Port 2 output max speed bits.

SPD3

Bit 3: Port 3 output max speed bits.

SPD4

Bit 4: Port 4 output max speed bits.

SPD5

Bit 5: Port 5 output max speed bits.

SPD6

Bit 6: Port 6 output max speed bits.

SPD7

Bit 7: Port 7 output max speed bits.

SPD8

Bit 8: Port 8 output max speed bits.

SPD9

Bit 9: Port 9 output max speed bits.

SPD10

Bit 10: Port 10 output max speed bits.

SPD11

Bit 11: Port 11 output max speed bits.

SPD12

Bit 12: Port 12 output max speed bits.

SPD13

Bit 13: Port 13 output max speed bits.

SPD14

Bit 14: Port 14 output max speed bits.

SPD15

Bit 15: Port 15 output max speed bits.

I2C0

0x40005400: Inter integrated circuit

15/80 fields covered. Toggle Registers.

CTL0

Control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRESET
rw 		SALT
rw 		PECTRANS
rw 		POAP
rw 		ACKEN
rw 		STOP
rw 		START
rw 		SS
rw 		GCEN
rw 		PECEN
rw 		ARPEN
rw 		SMBSEL
rw 		SMBEN
rw 		I2CEN
rw
Toggle Fields.

I2CEN

Bit 0: I2C peripheral enable.

SMBEN

Bit 1: SMBus/I2C mode switch.

SMBSEL

Bit 3: SMBusType Selection.

ARPEN

Bit 4: ARP protocol in SMBus switch.

PECEN

Bit 5: PEC Calculation Switch.

GCEN

Bit 6: Whether or not to response to a General Call (0x00).

SS

Bit 7: Whether to stretch SCL low when data is not ready in slave mode.

START

Bit 8: Generate a START condition on I2C bus.

STOP

Bit 9: Generate a STOP condition on I2C bus.

ACKEN

Bit 10: Whether or not to send an ACK.

POAP

Bit 11: Position of ACK and PEC when receiving.

PECTRANS

Bit 12: PEC Transfer.

SALT

Bit 13: SMBus alert.

SRESET

Bit 15: Software reset.

CTL1

Control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMALST
rw 		DMAON
rw 		BUFIE
rw 		EVIE
rw 		ERRIE
rw 		I2CCLK
rw
Toggle Fields.

I2CCLK

Bits 0-6: I2C Peripheral clock frequency.

ERRIE

Bit 8: Error interrupt enable.

EVIE

Bit 9: Event interrupt enable.

BUFIE

Bit 10: Buffer interrupt enable.

DMAON

Bit 11: DMA mode switch.

DMALST

Bit 12: Flag indicating DMA last transfer.

SADDR0

Slave address register 0

Offset: 0x8, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDFORMAT
rw 		ADDRESS9_8
rw 		ADDRESS7_1
rw 		ADDRESS0
rw
Toggle Fields.

ADDRESS0

Bit 0: Bit 0 of a 10-bit address.

ADDRESS7_1

Bits 1-7: 7-bit address or bits 7:1 of a 10-bit address.

ADDRESS9_8

Bits 8-9: Highest two bits of a 10-bit address.

ADDFORMAT

Bit 15: Address mode for the I2C slave.

SADDR1

Slave address register 1

Offset: 0xC, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS2
rw 		DUADEN
rw
Toggle Fields.

DUADEN

Bit 0: Dual-Address mode switch.

ADDRESS2

Bits 1-7: Second I2C address for the slave in Dual-Address mode.

DATA

Transfer buffer register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRB
rw
Toggle Fields.

TRB

Bits 0-7: Transmission or reception data buffer register.

STAT0

Transfer status register 0

Offset: 0x14, reset: 0x00000000, access: Unspecified

7/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALT
rw 		SMBTO
rw 		PECERR
rw 		OUERR
rw 		AERR
rw 		LOSTARB
rw 		BERR
rw 		TBE
r 		RBNE
r 		STPDET
r 		ADD10SEND
r 		BTC
r 		ADDSEND
r 		SBSEND
r
Toggle Fields.

SBSEND

Bit 0: START condition sent out in master mode.

ADDSEND

Bit 1: Address is sent in master mode or received and matches in slave mode.

BTC

Bit 2: Byte transmission completed.

ADD10SEND

Bit 3: Header of 10-bit address is sent in master mode.

STPDET

Bit 4: STOP condition detected in slave mode.

RBNE

Bit 6: I2C_DATA is not Empty during receiving.

TBE

Bit 7: I2C_DATA is Empty during transmitting.

BERR

Bit 8: A bus error occurs indication a unexpected START or STOP condition on I2C bus.

LOSTARB

Bit 9: Arbitration Lost in master mode.

AERR

Bit 10: Acknowledge error.

OUERR

Bit 11: Over-run or under-run situation occurs in slave mode.

PECERR

Bit 12: PEC error when receiving data.

SMBTO

Bit 14: Timeout signal in SMBus mode.

SMBALT

Bit 15: SMBus Alert status.

STAT1

Transfer status register 1

Offset: 0x18, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PECV
r 		DUMODF
r 		HSTSMB
r 		DEFSMB
r 		RXGC
r 		TR
r 		I2CBSY
r 		MASTER
r
Toggle Fields.

MASTER

Bit 0: A flag indicating whether I2C block is in master or slave mode.

I2CBSY

Bit 1: Busy flag.

TR

Bit 2: Whether the I2C is a transmitter or a receiver.

RXGC

Bit 4: General call address (00h) received.

DEFSMB

Bit 5: Default address of SMBusDevice.

HSTSMB

Bit 6: SMBus Host Header detected in slave mode.

DUMODF

Bit 7: Dual Flag in slave mode.

PECV

Bits 8-15: Packet Error Checking Value that calculated by hardware when PEC is enabled.

CKCFG

Clock configure register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAST
rw 		DTCY
rw 		CLKC
rw
Toggle Fields.

CLKC

Bits 0-11: I2C Clock control in master mode.

DTCY

Bit 14: Duty cycle in fast mode.

FAST

Bit 15: I2C speed selection in master mode.

RT

Rise time register

Offset: 0x20, reset: 0x00000002, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RISETIME
rw
Toggle Fields.

RISETIME

Bits 0-6: Maximum rise time in master mode.

SAMCS

SAM control and status register

Offset: 0x80, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFR
rw 		RFF
rw 		TFR
rw 		TFF
rw 		RXF
rw 		TXF
rw 		RFRIE
rw 		RFFIE
rw 		TFRIE
rw 		TFFIE
rw 		STOEN
rw 		SAMEN
rw
Toggle Fields.

SAMEN

Bit 0: SAM_V interface enable.

STOEN

Bit 1: SAM_V interface timeout detect enable.

TFFIE

Bit 4: Tx frame fall interrupt enable.

TFRIE

Bit 5: Tx frame rise interrupt enable.

RFFIE

Bit 6: Rx frame fall interrupt enable.

RFRIE

Bit 7: Rx frame rise interrupt enable.

TXF

Bit 8: level of tx frame signal.

RXF

Bit 9: level of rx frame signal.

TFF

Bit 12: Txframe fall flag.

TFR

Bit 13: Txframe rise flag.

RFF

Bit 14: Rxframe fall flag.

RFR

Bit 15: Rxframe rise flag.

CTL2

Control register 2

Offset: 0x90, reset: 0x0000FE00, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDM
rw 		RADD
rw 		TOEN
rw 		SETM
rw 		FMPEN
rw
Toggle Fields.

FMPEN

Bit 0: Fast mode plus enable.

SETM

Bit 1: Start Early Termination Mode.

TOEN

Bit 4: Timeout calculation enable.

RADD

Bit 8: slave address recorde enable .

ADDM

Bits 9-15: ingnore specify bits.

CS

Control and status register

Offset: 0x94, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STPSENDIE
rw 		STLOIE
rw 		STPSEND
rw 		STLO
rw
Toggle Fields.

STLO

Bit 0: Start lost flag.

STPSEND

Bit 1: Stop condition sent out in master mode.

STLOIE

Bit 8: Interrupt enable for start lost.

STPSENDIE

Bit 9: Interrupt enable for stop condition sent.

STATC

Status clear register

Offset: 0x98, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRCEN
rw 		STOPFC
rw 		ADD10SENDC
rw 		BTCC
rw 		ADDSENDC
rw 		SBSENDC
rw
Toggle Fields.

SBSENDC

Bit 0: Start send status clear .

ADDSENDC

Bit 1: ADDSEND status clear .

BTCC

Bit 2: BTC status clear.

ADD10SENDC

Bit 3: ADD10SEND status clear .

STOPFC

Bit 4: STOPF status clear.

SRCEN

Bit 15: Status register clear enable.

I2C1

0x40005800: Inter integrated circuit

15/80 fields covered. Toggle Registers.

CTL0

Control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRESET
rw 		SALT
rw 		PECTRANS
rw 		POAP
rw 		ACKEN
rw 		STOP
rw 		START
rw 		SS
rw 		GCEN
rw 		PECEN
rw 		ARPEN
rw 		SMBSEL
rw 		SMBEN
rw 		I2CEN
rw
Toggle Fields.

I2CEN

Bit 0: I2C peripheral enable.

SMBEN

Bit 1: SMBus/I2C mode switch.

SMBSEL

Bit 3: SMBusType Selection.

ARPEN

Bit 4: ARP protocol in SMBus switch.

PECEN

Bit 5: PEC Calculation Switch.

GCEN

Bit 6: Whether or not to response to a General Call (0x00).

SS

Bit 7: Whether to stretch SCL low when data is not ready in slave mode.

START

Bit 8: Generate a START condition on I2C bus.

STOP

Bit 9: Generate a STOP condition on I2C bus.

ACKEN

Bit 10: Whether or not to send an ACK.

POAP

Bit 11: Position of ACK and PEC when receiving.

PECTRANS

Bit 12: PEC Transfer.

SALT

Bit 13: SMBus alert.

SRESET

Bit 15: Software reset.

CTL1

Control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMALST
rw 		DMAON
rw 		BUFIE
rw 		EVIE
rw 		ERRIE
rw 		I2CCLK
rw
Toggle Fields.

I2CCLK

Bits 0-6: I2C Peripheral clock frequency.

ERRIE

Bit 8: Error interrupt enable.

EVIE

Bit 9: Event interrupt enable.

BUFIE

Bit 10: Buffer interrupt enable.

DMAON

Bit 11: DMA mode switch.

DMALST

Bit 12: Flag indicating DMA last transfer.

SADDR0

Slave address register 0

Offset: 0x8, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDFORMAT
rw 		ADDRESS9_8
rw 		ADDRESS7_1
rw 		ADDRESS0
rw
Toggle Fields.

ADDRESS0

Bit 0: Bit 0 of a 10-bit address.

ADDRESS7_1

Bits 1-7: 7-bit address or bits 7:1 of a 10-bit address.

ADDRESS9_8

Bits 8-9: Highest two bits of a 10-bit address.

ADDFORMAT

Bit 15: Address mode for the I2C slave.

SADDR1

Slave address register 1

Offset: 0xC, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS2
rw 		DUADEN
rw
Toggle Fields.

DUADEN

Bit 0: Dual-Address mode switch.

ADDRESS2

Bits 1-7: Second I2C address for the slave in Dual-Address mode.

DATA

Transfer buffer register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRB
rw
Toggle Fields.

TRB

Bits 0-7: Transmission or reception data buffer register.

STAT0

Transfer status register 0

Offset: 0x14, reset: 0x00000000, access: Unspecified

7/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALT
rw 		SMBTO
rw 		PECERR
rw 		OUERR
rw 		AERR
rw 		LOSTARB
rw 		BERR
rw 		TBE
r 		RBNE
r 		STPDET
r 		ADD10SEND
r 		BTC
r 		ADDSEND
r 		SBSEND
r
Toggle Fields.

SBSEND

Bit 0: START condition sent out in master mode.

ADDSEND

Bit 1: Address is sent in master mode or received and matches in slave mode.

BTC

Bit 2: Byte transmission completed.

ADD10SEND

Bit 3: Header of 10-bit address is sent in master mode.

STPDET

Bit 4: STOP condition detected in slave mode.

RBNE

Bit 6: I2C_DATA is not Empty during receiving.

TBE

Bit 7: I2C_DATA is Empty during transmitting.

BERR

Bit 8: A bus error occurs indication a unexpected START or STOP condition on I2C bus.

LOSTARB

Bit 9: Arbitration Lost in master mode.

AERR

Bit 10: Acknowledge error.

OUERR

Bit 11: Over-run or under-run situation occurs in slave mode.

PECERR

Bit 12: PEC error when receiving data.

SMBTO

Bit 14: Timeout signal in SMBus mode.

SMBALT

Bit 15: SMBus Alert status.

STAT1

Transfer status register 1

Offset: 0x18, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PECV
r 		DUMODF
r 		HSTSMB
r 		DEFSMB
r 		RXGC
r 		TR
r 		I2CBSY
r 		MASTER
r
Toggle Fields.

MASTER

Bit 0: A flag indicating whether I2C block is in master or slave mode.

I2CBSY

Bit 1: Busy flag.

TR

Bit 2: Whether the I2C is a transmitter or a receiver.

RXGC

Bit 4: General call address (00h) received.

DEFSMB

Bit 5: Default address of SMBusDevice.

HSTSMB

Bit 6: SMBus Host Header detected in slave mode.

DUMODF

Bit 7: Dual Flag in slave mode.

PECV

Bits 8-15: Packet Error Checking Value that calculated by hardware when PEC is enabled.

CKCFG

Clock configure register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAST
rw 		DTCY
rw 		CLKC
rw
Toggle Fields.

CLKC

Bits 0-11: I2C Clock control in master mode.

DTCY

Bit 14: Duty cycle in fast mode.

FAST

Bit 15: I2C speed selection in master mode.

RT

Rise time register

Offset: 0x20, reset: 0x00000002, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RISETIME
rw
Toggle Fields.

RISETIME

Bits 0-6: Maximum rise time in master mode.

SAMCS

SAM control and status register

Offset: 0x80, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFR
rw 		RFF
rw 		TFR
rw 		TFF
rw 		RXF
rw 		TXF
rw 		RFRIE
rw 		RFFIE
rw 		TFRIE
rw 		TFFIE
rw 		STOEN
rw 		SAMEN
rw
Toggle Fields.

SAMEN

Bit 0: SAM_V interface enable.

STOEN

Bit 1: SAM_V interface timeout detect enable.

TFFIE

Bit 4: Tx frame fall interrupt enable.

TFRIE

Bit 5: Tx frame rise interrupt enable.

RFFIE

Bit 6: Rx frame fall interrupt enable.

RFRIE

Bit 7: Rx frame rise interrupt enable.

TXF

Bit 8: level of tx frame signal.

RXF

Bit 9: level of rx frame signal.

TFF

Bit 12: Txframe fall flag.

TFR

Bit 13: Txframe rise flag.

RFF

Bit 14: Rxframe fall flag.

RFR

Bit 15: Rxframe rise flag.

CTL2

Control register 2

Offset: 0x90, reset: 0x0000FE00, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDM
rw 		RADD
rw 		TOEN
rw 		SETM
rw 		FMPEN
rw
Toggle Fields.

FMPEN

Bit 0: Fast mode plus enable.

SETM

Bit 1: Start Early Termination Mode.

TOEN

Bit 4: Timeout calculation enable.

RADD

Bit 8: slave address recorde enable .

ADDM

Bits 9-15: ingnore specify bits.

CS

Control and status register

Offset: 0x94, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STPSENDIE
rw 		STLOIE
rw 		STPSEND
rw 		STLO
rw
Toggle Fields.

STLO

Bit 0: Start lost flag.

STPSEND

Bit 1: Stop condition sent out in master mode.

STLOIE

Bit 8: Interrupt enable for start lost.

STPSENDIE

Bit 9: Interrupt enable for stop condition sent.

STATC

Status clear register

Offset: 0x98, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRCEN
rw 		STOPFC
rw 		ADD10SENDC
rw 		BTCC
rw 		ADDSENDC
rw 		SBSENDC
rw
Toggle Fields.

SBSENDC

Bit 0: Start send status clear .

ADDSENDC

Bit 1: ADDSEND status clear .

BTCC

Bit 2: BTC status clear.

ADD10SENDC

Bit 3: ADD10SEND status clear .

STOPFC

Bit 4: STOPF status clear.

SRCEN

Bit 15: Status register clear enable.

I2C2

0x4000C000: Inter integrated circuit

17/78 fields covered. Toggle Registers.

CTL0

Control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		SMBALTEN
rw 		SMBDAEN
rw 		SMBHAEN
rw 		GCEN
rw 		WUEN
rw 		SS
rw 		SBCTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DENR
rw 		DENT
rw 		ANOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STPDETIE
rw 		NACKIE
rw 		ADDMIE
rw 		RBNEIE
rw 		TIE
rw 		I2CEN
rw
Toggle Fields.

I2CEN

Bit 0: I2C peripheral enable.

TIE

Bit 1: Receive interrupt enable.

RBNEIE

Bit 2: Receive interrupt enable.

ADDMIE

Bit 3: Address match interrupt enable in slave mode.

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STPDETIE

Bit 5: Stop detection interrupt enable.

TCIE

Bit 6: Transfer complete interrupt enable.

ERRIE

Bit 7: Error interrupt enable.

DNF

Bits 8-11: Digital noise filter.

ANOFF

Bit 12: Analog noise filter disable.

DENT

Bit 14: DMA enable for transmission.

DENR

Bit 15: DMA enable for reception.

SBCTL

Bit 16: Slave byte control.

SS

Bit 17: Whether to stretch SCL low when data is not ready in slave mode.

WUEN

Bit 18: Wakeup from Deep-sleep mode enable.

GCEN

Bit 19: Whether or not to response to a General Call.

SMBHAEN

Bit 20: SMBus Host address enable.

SMBDAEN

Bit 21: SMBus device default address enable.

SMBALTEN

Bit 22: SMBus Alert enable.

PECEN

Bit 23: PEC Calculation Switch.

CTL1

Control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECTRANS
rw 		AUTOEND
rw 		RELOAD
rw 		BYTENUM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACKEN
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10EN
rw 		TRDIR
rw 		SADDRESS
rw
Toggle Fields.

SADDRESS

Bits 0-9: Slave address to be sent.

TRDIR

Bit 10: Transfer direction in master mode.

ADD10EN

Bit 11: 10-bit addressing mode enable in master mode.

HEAD10R

Bit 12: 10-bit address header executes read direction only in master receive mode.

START

Bit 13: Generate a START condition on I2C bus.

STOP

Bit 14: Generate a STOP condition on I2C bus.

NACKEN

Bit 15: Generate NACK in slave mode.

BYTENUM

Bits 16-23: Number of bytes to be transferred.

RELOAD

Bit 24: Reload mode.

AUTOEND

Bit 25: Automatic end mode in master mode.

PECTRANS

Bit 26: PEC Transfer.

SADDR0

Slave address register 0

Offset: 0x8, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESSEN
rw 		ADDFORMAT
rw 		ADDRESS_8_9
rw 		ADDRESS_1_7
rw 		ADDRESS_0
rw
Toggle Fields.

ADDRESS_0

Bit 0: Bit 0 of a 10-bit address.

ADDRESS_1_7

Bits 1-7: Highest two bits of a 10-bit address.

ADDRESS_8_9

Bits 8-9: 7-bit address or bits 7:1 of a 10-bit address.

ADDFORMAT

Bit 10: Address mode for the I2C slave.

ADDRESSEN

Bit 15: I2C address enable.

SADDR1

Slave address register 1

Offset: 0xC, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS2EN
rw 		ADDMSK2
rw 		ADDRESS2
rw
Toggle Fields.

ADDRESS2

Bits 1-7: Second I2C address for the slave.

ADDMSK2

Bits 8-10: ADDRESS2[7:1] mask.

ADDRESS2EN

Bit 15: Second I2C address enable.

TIMING

Timing register

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PSC
rw 		SCLDELY
rw 		SDADELY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle Fields.

SCLL

Bits 0-7: SCL low period.

SCLH

Bits 8-15: SCL high period.

SDADELY

Bits 16-19: Data hold time.

SCLDELY

Bits 20-23: Data setup time.

PSC

Bits 28-31: Timing prescaler.

TIMEOUT

timeout register

Offset: 0x14, reset: 0x00000000, access: Unspecified

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTOEN
rw 		BUSTOB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOEN
rw 		TOIDLE
rw 		BUSTOA
rw
Toggle Fields.

BUSTOA

Bits 0-11: Bus timeout A.

TOIDLE

Bit 12: Idle clock timeout detection.

TOEN

Bit 15: Clock timeout detection enable.

BUSTOB

Bits 16-27: Bus timeout B.

EXTOEN

Bit 31: Extended clock timeout detection enable.

STAT

Transfer status register

Offset: 0x18, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
READDR
r 		TR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2CBSY
r 		SMBALT
r 		TIMEOUT
r 		PECERR
r 		OUERR
r 		LOSTARB
r 		BERR
r 		TCR
r 		TC
r 		STPDET
r 		NACK
r 		ADDSEND
r 		RBNE
r 		TI
rw 		TBE
rw
Toggle Fields.

TBE

Bit 0: I2C_TDATA is empty during transmitting.

TI

Bit 1: Transmit interrupt.

RBNE

Bit 2: I2C_RDATA is not empty during receiving.

ADDSEND

Bit 3: Address received matches in slave mode.

NACK

Bit 4: Not Acknowledge flag.

STPDET

Bit 5: STOP condition is detected on the bus.

TC

Bit 6: Transfer complete in master mode.

TCR

Bit 7: Transfer complete reload.

BERR

Bit 8: Bus error.

LOSTARB

Bit 9: Arbitration Lost.

OUERR

Bit 10: Overrun/Underrun error in slave mode.

PECERR

Bit 11: PEC error.

TIMEOUT

Bit 12: TIMEOUT flag.

SMBALT

Bit 13: SMBus Alert.

I2CBSY

Bit 15: Busy flag.

TR

Bit 16: Whether the I2C is a transmitter or a receiver in slave mode.

READDR

Bits 17-23: Received match address in slave mode.

STATC

Status clear register

Offset: 0x1C, reset: 0x00000000, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALTC
w 		TIMEOUTC
w 		PECERRC
w 		OUERRC
w 		LOSTARBC
w 		BERRC
w 		STPDETC
w 		NACKC
w 		ADDSENDC
w
Toggle Fields.

ADDSENDC

Bit 3: ADDSEND flag clear.

NACKC

Bit 4: Not Acknowledge flag clear.

STPDETC

Bit 5: STPDET flag clear.

BERRC

Bit 8: Bus error flag clear.

LOSTARBC

Bit 9: Arbitration Lost flag clear.

OUERRC

Bit 10: Overrun/Underrun flag clear.

PECERRC

Bit 11: PEC error flag clear.

TIMEOUTC

Bit 12: TIMEOUT flag clear.

SMBALTC

Bit 13: SMBus Alert flag clear.

PEC

Packet Error Checking

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PECV
r
Toggle Fields.

PECV

Bits 0-7: Packet Error Checking Value.

RDATA

receive data register

Offset: 0x24, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle Fields.

RDATA

Bits 0-7: Receive data value.

TDATA

Transmit data register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDATA
rw
Toggle Fields.

TDATA

Bits 0-7: Transmit data value.

MASTER_TIMER

0x40017400: SHRTIMER Master TIMER

7/55 fields covered. Toggle Registers.

MTCTL0

SHRTIMER Master_TIMER control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPSEL
rw 		UPREP
rw 		SHWEN
rw 		DACTRGS
rw 		ST4CEN
rw 		ST3CEN
rw 		ST2CEN
rw 		ST1CEN
rw 		ST0CEN
rw 		MTCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNOSRC
rw 		SYNOPLS
rw 		SYNISTRT
rw 		SYNIRST
rw 		SYNISRC
rw 		HALFM
rw 		CNTRSTM
rw 		CTNM
rw 		CNTCKDIV
rw
Toggle Fields.

CNTCKDIV

Bits 0-1: Counter clock division.

CTNM

Bit 3: Continuous mode.

CNTRSTM

Bit 4: Counter reset mode.

HALFM

Bit 5: Half mode.

SYNISRC

Bits 8-9: Synchronization input source.

SYNIRST

Bit 10: Synchronization input reset counter.

SYNISTRT

Bit 11: Synchronization input start counter.

SYNOPLS

Bits 12-13: Synchronization output pulse.

SYNOSRC

Bits 14-15: Synchronization output source.

MTCEN

Bit 16: The counter of Master_TIMER enable.

ST0CEN

Bit 17: The counter of Slave_TIMER0 enable.

ST1CEN

Bit 18: The counter of Slave_TIMER1 enable.

ST2CEN

Bit 19: The counter of Slave_TIMER2 enable.

ST3CEN

Bit 20: The counter of Slave_TIMER3 enable.

ST4CEN

Bit 21: The counter of Slave_TIMER4 enable.

DACTRGS

Bits 25-26: Trigger source to DAC.

SHWEN

Bit 27: Shadow registers enable.

UPREP

Bit 29: Update event generated by repetition event.

UPSEL

Bits 30-31: Update event selection.

MTINTF

SHRTIMER Master_TIMER interrupt flag register

Offset: 0x4, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPIF
r 		SYNIIF
r 		REPIF
r 		CMP3IF
r 		CMP2IF
r 		CMP1IF
r 		CMP0IF
r
Toggle Fields.

CMP0IF

Bit 0: Compare 0 interrupt flag.

CMP1IF

Bit 1: Compare 1 interrupt flag.

CMP2IF

Bit 2: Compare 2 interrupt flag.

CMP3IF

Bit 3: Compare 3 interrupt flag.

REPIF

Bit 4: Repetition interrupt flag.

SYNIIF

Bit 5: Synchronization input interrupt flag.

UPIF

Bit 6: Update interrupt flag.

MTINTC

SHRTIMER Master_TIMER interrupt flag clear register

Offset: 0x8, reset: 0x00000000, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPIFC
w 		SYNIIFC
w 		REPIFC
w 		CMP3IFC
w 		CMP2IFC
w 		CMP1IFC
w 		CMP0IFC
w
Toggle Fields.

CMP0IFC

Bit 0: Clear compare 0 interrupt flag.

CMP1IFC

Bit 1: Clear compare 1 interrupt flag.

CMP2IFC

Bit 2: Clear compare 2 interrupt flag.

CMP3IFC

Bit 3: Clear compare 3 interrupt flag.

REPIFC

Bit 4: Clear repetition interrupt flag.

SYNIIFC

Bit 5: Clear synchronization input interrupt flag.

UPIFC

Bit 6: Clear update interrupt flag.

MTDMAINTEN

SHRTIMER Master_TIMER DMA and interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPDEN
rw 		SYNIDEN
rw 		REPDEN
rw 		CMP3DEN
rw 		CMP2DEN
rw 		CMP1DEN
rw 		CMP0DEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPIE
rw 		SYNIIE
rw 		REPIE
rw 		CMP3IE
rw 		CMP2IE
rw 		CMP1IE
rw 		CMP0IE
rw
Toggle Fields.

CMP0IE

Bit 0: Compare 0 interrupt enable.

CMP1IE

Bit 1: Compare 1 interrupt enable.

CMP2IE

Bit 2: Compare 2 interrupt enable.

CMP3IE

Bit 3: Compare 3 interrupt enable.

REPIE

Bit 4: Repetition interrupt enable.

SYNIIE

Bit 5: Synchronization input interrupt enable.

UPIE

Bit 6: Update interrupt enable.

CMP0DEN

Bit 16: Compare 0 DMA request enable.

CMP1DEN

Bit 17: Compare 1 DMA request enable.

CMP2DEN

Bit 18: Compare 2 DMA request enable.

CMP3DEN

Bit 19: Compare 3 DMA request enable.

REPDEN

Bit 20: Repetition DMA request enable.

SYNIDEN

Bit 21: Synchronization input DMA request enable.

UPDEN

Bit 22: Update DMA request enable.

MTCNT

SHRTIMER Master_TIMER counter register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: The current counter value.

MTCAR

SHRTIMER Master_TIMER counter auto reload register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARL
rw
Toggle Fields.

CARL

Bits 0-15: Counter auto reload value.

MTCREP

SHRTIMER Master_TIMER counter repetition register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CREP
rw
Toggle Fields.

CREP

Bits 0-7: Counter repetition value.

MTCMP0V

SHRTIMER Master_TIMER compare 0 value register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP0VAL
rw
Toggle Fields.

CMP0VAL

Bits 0-15: Compare 0 value.

MTCMP1V

SHRTIMER Master_TIMER compare 1 value register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP1VAL
rw
Toggle Fields.

CMP1VAL

Bits 0-15: Compare 1 value.

MTCMP2V

SHRTIMER Master_TIMER compare 2 value register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP2VAL
rw
Toggle Fields.

CMP2VAL

Bits 0-15: Compare 2 value.

MTCMP3V

SHRTIMER Master_TIMER compare 3 value register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP3VAL
rw
Toggle Fields.

CMP3VAL

Bits 0-15: Compare 3 value.

MTACTL

SHRTIMER Master_TIMER additional control register

Offset: 0x7C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNTCKDIV_3
rw
Toggle Fields.

CNTCKDIV_3

Bit 3: Counter clock division.

NVIC

0xE000E100: Nested Vectored Interrupt Controller

0/74 fields covered. Toggle Registers.

ISER

Interrupt Set Enable Register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ICER

Interrupt Clear Enable Register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ISPR

Interrupt Set-Pending Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ICPR

Interrupt Clear-Pending Register

Offset: 0x180, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

IABR

Interrupt Active bit Register

Offset: 0x200, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IABR
rw
Toggle Fields.

IABR

Bits 0-31: IABR.

IPR0

Interrupt Priority Register 0

Offset: 0x300, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_00
rw
Toggle Fields.

PRI_00

Bits 0-7: PRI_00.

IPR1

Interrupt Priority Register 1

Offset: 0x301, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_01
rw
Toggle Fields.

PRI_01

Bits 0-7: PRI_01.

IPR2

Interrupt Priority Register 2

Offset: 0x302, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_02
rw
Toggle Fields.

PRI_02

Bits 0-7: PRI_02.

IPR3

Interrupt Priority Register 3

Offset: 0x303, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_03
rw
Toggle Fields.

PRI_03

Bits 0-7: PRI_03.

IPR4

Interrupt Priority Register 4

Offset: 0x304, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_04
rw
Toggle Fields.

PRI_04

Bits 0-7: PRI_04.

IPR5

Interrupt Priority Register 5

Offset: 0x305, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_05
rw
Toggle Fields.

PRI_05

Bits 0-7: PRI_05.

IPR6

Interrupt Priority Register 6

Offset: 0x306, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_06
rw
Toggle Fields.

PRI_06

Bits 0-7: PRI_06.

IPR7

Interrupt Priority Register 7

Offset: 0x307, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_07
rw
Toggle Fields.

PRI_07

Bits 0-7: PRI_07.

IPR8

Interrupt Priority Register 8

Offset: 0x308, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_08
rw
Toggle Fields.

PRI_08

Bits 0-7: PRI_08.

IPR9

Interrupt Priority Register 9

Offset: 0x309, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_09
rw
Toggle Fields.

PRI_09

Bits 0-7: PRI_09.

IPR10

Interrupt Priority Register 10

Offset: 0x30A, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_10
rw
Toggle Fields.

PRI_10

Bits 0-7: PRI_10.

IPR11

Interrupt Priority Register 11

Offset: 0x30B, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_11
rw
Toggle Fields.

PRI_11

Bits 0-7: PRI_11.

IPR12

Interrupt Priority Register 12

Offset: 0x30C, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_12
rw
Toggle Fields.

PRI_12

Bits 0-7: PRI_12.

IPR13

Interrupt Priority Register 13

Offset: 0x30D, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_13
rw
Toggle Fields.

PRI_13

Bits 0-7: PRI_13.

IPR14

Interrupt Priority Register 14

Offset: 0x30E, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_14
rw
Toggle Fields.

PRI_14

Bits 0-7: PRI_14.

IPR15

Interrupt Priority Register 15

Offset: 0x30F, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_15
rw
Toggle Fields.

PRI_15

Bits 0-7: PRI_15.

IPR16

Interrupt Priority Register 16

Offset: 0x310, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_16
rw
Toggle Fields.

PRI_16

Bits 0-7: PRI_16.

IPR17

Interrupt Priority Register 17

Offset: 0x311, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_17
rw
Toggle Fields.

PRI_17

Bits 0-7: PRI_17.

IPR18

Interrupt Priority Register 18

Offset: 0x312, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_18
rw
Toggle Fields.

PRI_18

Bits 0-7: PRI_18.

IPR19

Interrupt Priority Register 19

Offset: 0x313, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_19
rw
Toggle Fields.

PRI_19

Bits 0-7: PRI_19.

IPR20

Interrupt Priority Register 20

Offset: 0x314, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_20
rw
Toggle Fields.

PRI_20

Bits 0-7: PRI_20.

IPR21

Interrupt Priority Register 21

Offset: 0x315, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_21
rw
Toggle Fields.

PRI_21

Bits 0-7: PRI_21.

IPR22

Interrupt Priority Register 22

Offset: 0x316, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_22
rw
Toggle Fields.

PRI_22

Bits 0-7: PRI_22.

IPR23

Interrupt Priority Register 23

Offset: 0x317, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_23
rw
Toggle Fields.

PRI_23

Bits 0-7: PRI_23.

IPR24

Interrupt Priority Register 24

Offset: 0x318, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_24
rw
Toggle Fields.

PRI_24

Bits 0-7: PRI_24.

IPR25

Interrupt Priority Register 25

Offset: 0x319, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_25
rw
Toggle Fields.

PRI_25

Bits 0-7: PRI_25.

IPR26

Interrupt Priority Register 26

Offset: 0x31A, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_26
rw
Toggle Fields.

PRI_26

Bits 0-7: PRI_26.

IPR27

Interrupt Priority Register 27

Offset: 0x31B, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_27
rw
Toggle Fields.

PRI_27

Bits 0-7: PRI_27.

IPR28

Interrupt Priority Register 28

Offset: 0x31C, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_28
rw
Toggle Fields.

PRI_28

Bits 0-7: PRI_28.

IPR29

Interrupt Priority Register 29

Offset: 0x31D, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_29
rw
Toggle Fields.

PRI_29

Bits 0-7: PRI_29.

IPR30

Interrupt Priority Register 30

Offset: 0x31E, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_30
rw
Toggle Fields.

PRI_30

Bits 0-7: PRI_30.

IPR31

Interrupt Priority Register 31

Offset: 0x31F, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_31
rw
Toggle Fields.

PRI_31

Bits 0-7: PRI_31.

IPR32

Interrupt Priority Register 32

Offset: 0x320, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_32
rw
Toggle Fields.

PRI_32

Bits 0-7: PRI_32.

IPR33

Interrupt Priority Register 33

Offset: 0x321, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_33
rw
Toggle Fields.

PRI_33

Bits 0-7: PRI_33.

IPR34

Interrupt Priority Register 34

Offset: 0x322, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_34
rw
Toggle Fields.

PRI_34

Bits 0-7: PRI_34.

IPR35

Interrupt Priority Register 35

Offset: 0x323, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_35
rw
Toggle Fields.

PRI_35

Bits 0-7: PRI_35.

IPR36

Interrupt Priority Register 36

Offset: 0x324, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_36
rw
Toggle Fields.

PRI_36

Bits 0-7: PRI_36.

IPR37

Interrupt Priority Register 37

Offset: 0x325, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_37
rw
Toggle Fields.

PRI_37

Bits 0-7: PRI_37.

IPR38

Interrupt Priority Register 38

Offset: 0x326, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_38
rw
Toggle Fields.

PRI_38

Bits 0-7: PRI_38.

IPR39

Interrupt Priority Register 39

Offset: 0x327, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_39
rw
Toggle Fields.

PRI_39

Bits 0-7: PRI_39.

IPR40

Interrupt Priority Register 40

Offset: 0x328, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_40
rw
Toggle Fields.

PRI_40

Bits 0-7: PRI_40.

IPR41

Interrupt Priority Register 41

Offset: 0x329, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_41
rw
Toggle Fields.

PRI_41

Bits 0-7: PRI_41.

IPR42

Interrupt Priority Register 42

Offset: 0x32A, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_42
rw
Toggle Fields.

PRI_42

Bits 0-7: PRI_42.

IPR43

Interrupt Priority Register 43

Offset: 0x32B, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_43
rw
Toggle Fields.

PRI_43

Bits 0-7: PRI_43.

IPR44

Interrupt Priority Register 44

Offset: 0x32C, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_44
rw
Toggle Fields.

PRI_44

Bits 0-7: PRI_44.

IPR45

Interrupt Priority Register 45

Offset: 0x32D, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_45
rw
Toggle Fields.

PRI_45

Bits 0-7: PRI_45.

IPR46

Interrupt Priority Register 46

Offset: 0x32E, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_46
rw
Toggle Fields.

PRI_46

Bits 0-7: PRI_46.

IPR47

Interrupt Priority Register 47

Offset: 0x32F, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_47
rw
Toggle Fields.

PRI_47

Bits 0-7: PRI_47.

IPR48

Interrupt Priority Register 48

Offset: 0x330, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_48
rw
Toggle Fields.

PRI_48

Bits 0-7: PRI_48.

IPR49

Interrupt Priority Register 49

Offset: 0x331, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_49
rw
Toggle Fields.

PRI_49

Bits 0-7: PRI_49.

IPR50

Interrupt Priority Register 50

Offset: 0x332, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_50
rw
Toggle Fields.

PRI_50

Bits 0-7: PRI_50.

IPR51

Interrupt Priority Register 51

Offset: 0x333, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_51
rw
Toggle Fields.

PRI_51

Bits 0-7: PRI_51.

IPR52

Interrupt Priority Register 52

Offset: 0x334, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_52
rw
Toggle Fields.

PRI_52

Bits 0-7: PRI_52.

IPR53

Interrupt Priority Register 53

Offset: 0x335, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_53
rw
Toggle Fields.

PRI_53

Bits 0-7: PRI_53.

IPR54

Interrupt Priority Register 54

Offset: 0x336, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_54
rw
Toggle Fields.

PRI_54

Bits 0-7: PRI_54.

IPR55

Interrupt Priority Register 55

Offset: 0x337, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_55
rw
Toggle Fields.

PRI_55

Bits 0-7: PRI_55.

IPR56

Interrupt Priority Register 56

Offset: 0x338, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_56
rw
Toggle Fields.

PRI_56

Bits 0-7: PRI_56.

IPR57

Interrupt Priority Register 57

Offset: 0x339, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_57
rw
Toggle Fields.

PRI_57

Bits 0-7: PRI_57.

IPR58

Interrupt Priority Register 58

Offset: 0x33A, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_58
rw
Toggle Fields.

PRI_58

Bits 0-7: PRI_58.

IPR59

Interrupt Priority Register 59

Offset: 0x33B, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_59
rw
Toggle Fields.

PRI_59

Bits 0-7: PRI_59.

IPR60

Interrupt Priority Register 60

Offset: 0x33C, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_60
rw
Toggle Fields.

PRI_60

Bits 0-7: PRI_60.

IPR61

Interrupt Priority Register 61

Offset: 0x33D, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_61
rw
Toggle Fields.

PRI_61

Bits 0-7: PRI_61.

IPR62

Interrupt Priority Register 62

Offset: 0x33E, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_62
rw
Toggle Fields.

PRI_62

Bits 0-7: PRI_62.

IPR63

Interrupt Priority Register 63

Offset: 0x33F, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_63
rw
Toggle Fields.

PRI_63

Bits 0-7: PRI_63.

IPR64

Interrupt Priority Register 64

Offset: 0x340, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_64
rw
Toggle Fields.

PRI_64

Bits 0-7: PRI_64.

IPR65

Interrupt Priority Register 65

Offset: 0x341, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_65
rw
Toggle Fields.

PRI_65

Bits 0-7: PRI_65.

IPR66

Interrupt Priority Register 66

Offset: 0x342, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_66
rw
Toggle Fields.

PRI_66

Bits 0-7: PRI_66.

IPR67

Interrupt Priority Register 67

Offset: 0x343, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_67
rw
Toggle Fields.

PRI_67

Bits 0-7: PRI_67.

STIR

Software Trigger Interrupt Register

Offset: 0xE00, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STIR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STIR
w
Toggle Fields.

STIR

Bits 0-31: STIR.

PMU

0x40007000: Power management unit

5/30 fields covered. Toggle Registers.

CTL0

power control register 0

Offset: 0x0, reset: 0x0000C000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LDEN
rw 		HDS
rw 		HDEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDNP
rw 		LDLP
rw 		BKPWEN
rw 		LVDT
rw 		LVDEN
rw 		STBRST
rw 		WURST
rw 		STBMOD
rw 		LDOLP
rw
Toggle Fields.

LDOLP

Bit 0: LDO Low Power Mode.

STBMOD

Bit 1: Standby Mode.

WURST

Bit 2: Wakeup Flag Reset.

STBRST

Bit 3: Standby Flag Reset.

LVDEN

Bit 4: Low Voltage Detector Enable.

LVDT

Bits 5-7: Low Voltage Detector Threshold.

BKPWEN

Bit 8: Backup Domain Write Enable.

LDLP

Bit 10: Low-driver mode when use low power LDO..

LDNP

Bit 11: Low-driver mode when use normal power LDO.

HDEN

Bit 16: High-driver mode enable.

HDS

Bit 17: High-driver mode switch.

LDEN

Bits 18-19: Low-driver mode enable in Deep-sleep mode.

CS0

power control/status register 0

Offset: 0x4, reset: 0x00000000, access: Unspecified

5/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LDRF
rw 		HDSRF
r 		HDRF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUPEN7
rw 		WUPEN5
rw 		WUPEN4
rw 		WUPEN3
rw 		WUPEN2
rw 		WUPEN1
rw 		WUPEN0
rw 		WUPEN6
rw 		LVDF
r 		STBF
r 		WUF
r
Toggle Fields.

WUF

Bit 0: Wakeup flag.

STBF

Bit 1: Standby flag.

LVDF

Bit 2: Low Voltage Detector Status Flag.

WUPEN6

Bit 7: Enable WKUP pin6.

WUPEN0

Bit 8: Enable WKUP pin0.

WUPEN1

Bit 9: Enable WKUP pin1.

WUPEN2

Bit 10: Enable WKUP pin2.

WUPEN3

Bit 11: Enable WKUP pin3.

WUPEN4

Bit 12: Enable WKUP pin4.

WUPEN5

Bit 13: Enable WKUP pin5.

WUPEN7

Bit 15: Enable WKUP Pin7(PF8).

HDRF

Bit 16: High-driver ready flag.

HDSRF

Bit 17: High-driver switch ready flag.

LDRF

Bits 18-19: Low-driver mode ready flag.

CTL1

power control register 1

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPMOD2
rw 		DPMOD1
rw
Toggle Fields.

DPMOD1

Bit 0: Enable deep-sleep 1 mode.

DPMOD2

Bit 1: Enable deep-sleep 2 mode .

CS1

power control and status register 1

Offset: 0xC, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPF2
rw 		DPF1
rw
Toggle Fields.

DPF1

Bit 0: Deep-sleep1 mode status flag.

DPF2

Bit 1: Deep-sleep 2 mode status flag .

RCU

0x40021000: Reset and clock unit

23/177 fields covered. Toggle Registers.

CTL

Control register

Offset: 0x0, reset: 0x00000083, access: Unspecified

4/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSTB
r 		PLLEN
rw 		CKMEN
rw 		HXTALBPS
rw 		HXTALSTB
r 		HXTALEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRC8MCALIB
r 		IRC8MADJ
rw 		IRC8MSTB
r 		IRC8MEN
rw
Toggle Fields.

IRC8MEN

Bit 0: Internal 8MHz RC oscillator Enable.

IRC8MSTB

Bit 1: IRC8M Internal 8MHz RC Oscillator stabilization Flag.

IRC8MADJ

Bits 3-7: Internal 8MHz RC Oscillator clock trim adjust value.

IRC8MCALIB

Bits 8-15: Internal 8MHz RC Oscillator calibration value register.

HXTALEN

Bit 16: External High Speed oscillator Enable.

HXTALSTB

Bit 17: External crystal oscillator (HXTAL) clock stabilization flag.

HXTALBPS

Bit 18: External crystal oscillator (HXTAL) clock bypass mode enable.

CKMEN

Bit 19: HXTAL Clock Monitor Enable.

PLLEN

Bit 24: PLL enable.

PLLSTB

Bit 25: PLL Clock Stabilization Flag.

CFG0

Clock configuration register 0 (RCU_CFG0)

Offset: 0x4, reset: 0x00000000, access: Unspecified

1/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USBDPSC_2
rw 		PLLMF_5
rw 		ADCPSC_2
rw 		PLLMF_4
rw 		CKOUT0SEL
rw 		USBDPSC
rw 		PLLMF_3_0
rw 		PREDV0
rw 		PLLSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCPSC_1_0
rw 		APB2PSC
rw 		APB1PSC
rw 		AHBPSC
rw 		SCSS
r 		SCS
rw
Toggle Fields.

SCS

Bits 0-1: System clock switch.

SCSS

Bits 2-3: System clock switch status.

AHBPSC

Bits 4-7: AHB prescaler selection.

APB1PSC

Bits 8-10: APB1 prescaler selection.

APB2PSC

Bits 11-13: APB2 prescaler selection.

ADCPSC_1_0

Bits 14-15: ADC clock prescaler selection.

PLLSEL

Bit 16: PLL Clock Source Selection.

PREDV0

Bit 17: PREDV0 division factor.

PLLMF_3_0

Bits 18-21: The PLL clock multiplication factor.

USBDPSC

Bits 22-23: USBD clock prescaler selection.

CKOUT0SEL

Bits 24-26: CKOUT0 Clock Source Selection.

PLLMF_4

Bit 27: Bit 4 of PLLMF.

ADCPSC_2

Bit 28: Bit 2 of ADCPSC.

PLLMF_5

Bit 29: Bit 5 of PLLMF.

USBDPSC_2

Bit 31: Bit 2 of USBHSPSC.

INT

Clock interrupt register (RCU_INT)

Offset: 0x8, reset: 0x00000000, access: Unspecified

6/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKMIC
w 		PLLSTBIC
w 		HXTALSTBIC
w 		IRC8MSTBIC
w 		LXTALSTBIC
w 		IRC40KSTBIC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLSTBIE
rw 		HXTALSTBIE
rw 		IRC8MSTBIE
rw 		LXTALSTBIE
rw 		IRC40KSTBIE
rw 		CKMIF
r 		PLLSTBIF
r 		HXTALSTBIF
r 		IRC8MSTBIF
r 		LXTALSTBIF
r 		IRC40KSTBIF
r
Toggle Fields.

IRC40KSTBIF

Bit 0: IRC40K stabilization interrupt flag.

LXTALSTBIF

Bit 1: LXTAL stabilization interrupt flag.

IRC8MSTBIF

Bit 2: IRC8M stabilization interrupt flag.

HXTALSTBIF

Bit 3: HXTAL stabilization interrupt flag.

PLLSTBIF

Bit 4: PLL stabilization interrupt flag.

CKMIF

Bit 7: HXTAL Clock Stuck Interrupt Flag.

IRC40KSTBIE

Bit 8: IRC40K Stabilization interrupt enable.

LXTALSTBIE

Bit 9: LXTAL Stabilization Interrupt Enable.

IRC8MSTBIE

Bit 10: IRC8M Stabilization Interrupt Enable.

HXTALSTBIE

Bit 11: HXTAL Stabilization Interrupt Enable.

PLLSTBIE

Bit 12: PLL Stabilization Interrupt Enable.

IRC40KSTBIC

Bit 16: IRC40K Stabilization Interrupt Clear.

LXTALSTBIC

Bit 17: LXTAL Stabilization Interrupt Clear.

IRC8MSTBIC

Bit 18: IRC8M Stabilization Interrupt Clear.

HXTALSTBIC

Bit 19: HXTAL Stabilization Interrupt Clear.

PLLSTBIC

Bit 20: PLL stabilization Interrupt Clear.

CKMIC

Bit 23: HXTAL Clock Stuck Interrupt Clear.

APB2RST

APB2 reset register (RCU_APB2RST)

Offset: 0xC, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SHRTIMERRST
rw 		USART5RST
rw 		TIMER10RST
rw 		TIMER9RST
rw 		TIMER8RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC2RST
rw 		USART0RST
rw 		TIMER7RST
rw 		SPI0RST
rw 		TIMER0RST
rw 		ADC1RST
rw 		ADC0RST
rw 		PGRST
rw 		PFRST
rw 		PERST
rw 		PDRST
rw 		PCRST
rw 		PBRST
rw 		PARST
rw 		AFRST
rw
Toggle Fields.

AFRST

Bit 0: Alternate function I/O reset.

PARST

Bit 2: GPIO port A reset.

PBRST

Bit 3: GPIO port B reset.

PCRST

Bit 4: GPIO port C reset.

PDRST

Bit 5: GPIO port D reset.

PERST

Bit 6: GPIO port E reset.

PFRST

Bit 7: GPIO portF reset.

PGRST

Bit 8: GPIO port G reset.

ADC0RST

Bit 9: ADC0 reset.

ADC1RST

Bit 10: ADC1 reset.

TIMER0RST

Bit 11: Timer 0 reset.

SPI0RST

Bit 12: SPI0 reset.

TIMER7RST

Bit 13: Timer 7 reset.

USART0RST

Bit 14: USART0 Reset.

ADC2RST

Bit 15: ADC2 reset.

TIMER8RST

Bit 19: Timer 8 reset.

TIMER9RST

Bit 20: Timer 9 reset.

TIMER10RST

Bit 21: Timer 10 reset.

USART5RST

Bit 28: USART5 reset.

SHRTIMERRST

Bit 29: SHRTIMER reset.

APB1RST

APB1 reset register (RCU_APB1RST)

Offset: 0x10, reset: 0x00000000, access: read-write

0/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACRST
rw 		PMURST
rw 		BKPIRST
rw 		CAN1RST
rw 		CAN0RST
rw 		I2C2RST
rw 		USBDRST
rw 		I2C1RST
rw 		I2C0RST
rw 		UART4RST
rw 		UART3RST
rw 		USART2RST
rw 		USART1RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2RST
rw 		SPI1RST
rw 		WWDGTRST
rw 		TIMER13RST
rw 		TIMER12RST
rw 		TIMER11RST
rw 		TIMER6RST
rw 		TIMER5RST
rw 		TIMER4RST
rw 		TIMER3RST
rw 		TIMER2RST
rw 		TIMER1RST
rw
Toggle Fields.

TIMER1RST

Bit 0: TIMER1 timer reset.

TIMER2RST

Bit 1: TIMER2 timer reset.

TIMER3RST

Bit 2: TIMER3 timer reset.

TIMER4RST

Bit 3: TIMER4 timer reset.

TIMER5RST

Bit 4: TIMER5 timer reset.

TIMER6RST

Bit 5: TIMER6 timer reset.

TIMER11RST

Bit 6: TIMER11 timer reset.

TIMER12RST

Bit 7: TIMER12 timer reset.

TIMER13RST

Bit 8: TIMER13 timer reset.

WWDGTRST

Bit 11: Window watchdog timer reset.

SPI1RST

Bit 14: SPI1 reset.

SPI2RST

Bit 15: SPI2 reset.

USART1RST

Bit 17: USART1 reset.

USART2RST

Bit 18: USART2 reset.

UART3RST

Bit 19: UART3 reset.

UART4RST

Bit 20: UART4 reset.

I2C0RST

Bit 21: I2C0 reset.

I2C1RST

Bit 22: I2C1 reset.

USBDRST

Bit 23: USBD reset.

I2C2RST

Bit 24: I2C2 reset.

CAN0RST

Bit 25: CAN0 reset.

CAN1RST

Bit 26: CAN1 reset.

BKPIRST

Bit 27: Backup interface reset.

PMURST

Bit 28: Power control reset.

DACRST

Bit 29: DAC reset.

AHBEN

AHB enable register

Offset: 0x14, reset: 0x00000014, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQPIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDIOEN
rw 		EXMCEN
rw 		CRCEN
rw 		FMCSPEN
rw 		SRAMSPEN
rw 		DMA1EN
rw 		DMA0EN
rw
Toggle Fields.

DMA0EN

Bit 0: DMA0 clock enable.

DMA1EN

Bit 1: DMA1 clock enable.

SRAMSPEN

Bit 2: SRAM interface clock enable when sleep mode.

FMCSPEN

Bit 4: FMC clock enable when sleep mode.

CRCEN

Bit 6: CRC clock enable.

EXMCEN

Bit 8: EXMC clock enable.

SDIOEN

Bit 10: SDIO clock enable.

SQPIEN

Bit 31: SQPI clock enable.

APB2EN

APB2 clock enable register (RCU_APB2EN)

Offset: 0x18, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SHRTIMEREN
rw 		USART5EN
rw 		TIMER10EN
rw 		TIMER9EN
rw 		TIMER8EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC2EN
rw 		USART0EN
rw 		TIMER7EN
rw 		SPI0EN
rw 		TIMER0EN
rw 		ADC1EN
rw 		ADC0EN
rw 		PGEN
rw 		PFEN
rw 		PEEN
rw 		PDEN
rw 		PCEN
rw 		PBEN
rw 		PAEN
rw 		AFEN
rw
Toggle Fields.

AFEN

Bit 0: Alternate function IO clock enable .

PAEN

Bit 2: GPIO port A clock enable.

PBEN

Bit 3: GPIO port B clock enable.

PCEN

Bit 4: GPIO port C clock enable.

PDEN

Bit 5: GPIO port D clock enable .

PEEN

Bit 6: GPIO port E clock enable .

PFEN

Bit 7: GPIO port F clock enable .

PGEN

Bit 8: GPIO port G clock enable.

ADC0EN

Bit 9: ADC0 clock enable.

ADC1EN

Bit 10: ADC1 clock enable.

TIMER0EN

Bit 11: TIMER0 clock enable .

SPI0EN

Bit 12: SPI0 clock enable.

TIMER7EN

Bit 13: TIMER7 clock enable.

USART0EN

Bit 14: USART0 clock enable.

ADC2EN

Bit 15: ADC2 clock enable.

TIMER8EN

Bit 19: TIMER8 clock enable.

TIMER9EN

Bit 20: TIMER9 clock enable .

TIMER10EN

Bit 21: TIMER10 clock enable .

USART5EN

Bit 28: USART5 clock enable .

SHRTIMEREN

Bit 29: SHRTIMER clock enable .

APB1EN

APB1 clock enable register (RCU_APB1EN)

Offset: 0x1C, reset: 0x00000000, access: read-write

0/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACEN
rw 		PMUEN
rw 		BKPIEN
rw 		CAN1EN
rw 		CAN0EN
rw 		I2C2EN
rw 		USBDEN
rw 		I2C1EN
rw 		I2C0EN
rw 		UART4EN
rw 		UART3EN
rw 		USART2EN
rw 		USART1EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2EN
rw 		SPI1EN
rw 		WWDGTEN
rw 		TIMER13EN
rw 		TIMER12EN
rw 		TIMER11EN
rw 		TIMER6EN
rw 		TIMER5EN
rw 		TIMER4EN
rw 		TIMER3EN
rw 		TIMER2EN
rw 		TIMER1EN
rw
Toggle Fields.

TIMER1EN

Bit 0: TIMER1 timer clock enable.

TIMER2EN

Bit 1: TIMER2 timer clock enable.

TIMER3EN

Bit 2: TIMER3 timer clock enable.

TIMER4EN

Bit 3: TIMER4 timer clock enable.

TIMER5EN

Bit 4: TIMER5 timer clock enable.

TIMER6EN

Bit 5: TIMER6 timer clock enable.

TIMER11EN

Bit 6: TIMER11 timer clock enable.

TIMER12EN

Bit 7: TIMER12 timer clock enable.

TIMER13EN

Bit 8: TIMER13 timer clock enable.

WWDGTEN

Bit 11: Window watchdog timer clock enable.

SPI1EN

Bit 14: SPI1 clock enable.

SPI2EN

Bit 15: SPI2 clock enable.

USART1EN

Bit 17: USART1 clock enable.

USART2EN

Bit 18: USART2 clock enable.

UART3EN

Bit 19: UART3 clock enable.

UART4EN

Bit 20: UART4 clock enable.

I2C0EN

Bit 21: I2C0 clock enable.

I2C1EN

Bit 22: I2C1 clock enable.

USBDEN

Bit 23: USBD clock enable.

I2C2EN

Bit 24: I2C2 clock enable.

CAN0EN

Bit 25: CAN0 clock enable.

CAN1EN

Bit 26: CAN1 clock enable.

BKPIEN

Bit 27: Backup interface clock enable .

PMUEN

Bit 28: Power control clock enable .

DACEN

Bit 29: DAC clock enable.

BDCTL

Backup domain control register (RCU_BDCTL)

Offset: 0x20, reset: 0x00000018, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKPRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCEN
rw 		RTCSRC
rw 		LXTALDRI
rw 		LXTALBPS
rw 		LXTALSTB
r 		LXTALEN
rw
Toggle Fields.

LXTALEN

Bit 0: LXTAL enable.

LXTALSTB

Bit 1: External low-speed oscillator stabilization.

LXTALBPS

Bit 2: LXTAL bypass mode enable.

LXTALDRI

Bits 3-4: LXTAL drive capability.

RTCSRC

Bits 8-9: RTC clock entry selection.

RTCEN

Bit 15: RTC clock enable.

BKPRST

Bit 16: Backup domain reset.

RSTSCK

Reset source /clock register (RCU_RSTSCK)

Offset: 0x24, reset: 0x0C000000, access: Unspecified

7/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPRSTF
r 		WWDGTRSTF
r 		FWDGTRSTF
r 		SWRSTF
r 		PORRSTF
r 		EPRSTF
r 		BORRSTF
rw 		RSTFC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRC40KSTB
r 		IRC40KEN
rw
Toggle Fields.

IRC40KEN

Bit 0: IRC40K enable.

IRC40KSTB

Bit 1: IRC40K stabilization.

RSTFC

Bit 24: Reset flag clear.

BORRSTF

Bit 25: BORt flag clear.

EPRSTF

Bit 26: External PIN reset flag.

PORRSTF

Bit 27: Power reset flag.

SWRSTF

Bit 28: Software reset flag.

FWDGTRSTF

Bit 29: Free Watchdog timer reset flag.

WWDGTRSTF

Bit 30: Window watchdog timer reset flag.

LPRSTF

Bit 31: Low-power reset flag.

AHBRST

AHB reset register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQPIRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

SQPIRST

Bit 31: SQPI reset.

CFG1

Clock Configuration register 1

Offset: 0x2C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLPRESEL
rw 		ADCPSC_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

ADCPSC_3

Bit 29: Bit 3 of ADCPSC.

PLLPRESEL

Bit 30: PLL Clock Source Selection.

DSV

Deep sleep mode Voltage register

Offset: 0x34, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSLPVS
rw
Toggle Fields.

DSLPVS

Bits 0-2: Deep-sleep mode voltage select.

ADDCTL

Additional clock control register

Offset: 0xC0, reset: 0x80000000, access: Unspecified

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IRC48MCALIB
r 		IRC48MSTB
r 		IRC48MEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CK48MSEL
rw
Toggle Fields.

CK48MSEL

Bits 0-1: 48MHz clock selection.

IRC48MEN

Bit 16: Internal 48MHz RC oscillator enable.

IRC48MSTB

Bit 17: Internal 48MHz RC oscillator clock stabilization Flag.

IRC48MCALIB

Bits 24-31: Internal 48MHz RC oscillator calibration value register.

ADDINT

Additional clock interrupt register

Offset: 0xCC, reset: 0x00000000, access: Unspecified

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IRC48MSTBIC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRC48MSTBIE
rw 		PLLUSBSTBIF
r 		IRC48MSTBIF
r
Toggle Fields.

IRC48MSTBIF

Bit 6: IRC48M stabilization interrupt flag.

PLLUSBSTBIF

Bit 7: PLLUSB stabilization interrupt flag.

IRC48MSTBIE

Bit 14: Internal 48 MHz RC oscillator Stabilization Interrupt Enable.

IRC48MSTBIC

Bit 22: Internal 48 MHz RC oscillator Stabilization Interrupt Clear.

PLLSSCTL

PLL clock spread spectrum control register

Offset: 0xD0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSCGON
rw 		SS_TYPE
rw 		MODSTEP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODSTEP
rw 		MODCNT
rw
Toggle Fields.

MODCNT

Bits 0-12: Configure PLL spread spectrum modulation profile amplitude and frequency.

MODSTEP

Bits 13-27: Configure PLL spread spectrum modulation profile amplitude and frequency.

SS_TYPE

Bit 30: PLL spread spectrum modulation type select.

SSCGON

Bit 31: PLL spread spectrum modulation enable.

CFG2

Clock configuration register 2

Offset: 0xD4, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C2SEL
rw 		USART5SEL
rw
Toggle Fields.

USART5SEL

Bits 0-1: USART5 Clock Source Selection.

I2C2SEL

Bits 4-5: I2C2 Clock Source Selection.

ADDAPB1RST

APB1 additional reset register

Offset: 0xE0, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTCRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

CTCRST

Bit 27: CTC reset.

ADDAPB1EN

APB1 additional enable register

Offset: 0xE4, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

CTCEN

Bit 27: CTC clock enable.

RTC

0x40002800: Real-time clock

3/17 fields covered. Toggle Registers.

INTEN

RTC interrupt enable register

Offset: 0x0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVIE
rw 		ALRMIE
rw 		SCIE
rw
Toggle Fields.

SCIE

Bit 0: Second interrupt.

ALRMIE

Bit 1: Alarm interrupt enable.

OVIE

Bit 2: Overflow interrupt enable.

CTL

control register

Offset: 0x4, reset: 0x00000020, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LWOFF
r 		CMF
rw 		RSYNF
rw 		OVIF
rw 		ALRMIF
rw 		SCIF
rw
Toggle Fields.

SCIF

Bit 0: Sencond interrupt flag.

ALRMIF

Bit 1: Alarm interrupt flag.

OVIF

Bit 2: Overflow interrupt flag.

RSYNF

Bit 3: Registers synchronized flag.

CMF

Bit 4: Configuration mode flag.

LWOFF

Bit 5: Last write operation finished flag.

PSCH

RTC prescaler high register

Offset: 0x8, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
w
Toggle Fields.

PSC

Bits 0-3: RTC prescaler value high.

PSCL

RTC prescaler low register

Offset: 0xC, reset: 0x00008000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
w
Toggle Fields.

PSC

Bits 0-15: RTC prescaler value low.

DIVH

RTC divider high register

Offset: 0x10, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
r
Toggle Fields.

DIV

Bits 0-3: RTC divider value high.

DIVL

RTC divider low register

Offset: 0x14, reset: 0x00008000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
r
Toggle Fields.

DIV

Bits 0-15: RTC divider value low.

CNTH

RTC counter high register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: RTC counter value high.

CNTL

RTC counter low register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: RTC conuter value low.

ALRMH

Alarm high register

Offset: 0x20, reset: 0x0000FFFF, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALRM
w
Toggle Fields.

ALRM

Bits 0-15: Alarm value high.

ALRML

RTC alarm low register

Offset: 0x24, reset: 0x0000FFFF, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALRM
w
Toggle Fields.

ALRM

Bits 0-15: alarm value low.

SDIO

0x40018000: Secure digital input/output interface

31/99 fields covered. Toggle Registers.

PWRCTL

Power control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWRCTL
rw
Toggle Fields.

PWRCTL

Bits 0-1: SDIO power control bits.

CLKCTL

Clock control register

Offset: 0x4, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIV_8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HWCLKEN
rw 		CLKEDGE
rw 		BUSMODE
rw 		CLKBYP
rw 		CLKPWRSAV
rw 		CLKEN
rw 		DIV_0_7
rw
Toggle Fields.

DIV_0_7

Bits 0-7: Clock division.

CLKEN

Bit 8: SDIO_CLK clock output enable bit.

CLKPWRSAV

Bit 9: SDIO_CLK clock dynamic switch on/off for power saving.

CLKBYP

Bit 10: Clock bypass enable bit.

BUSMODE

Bits 11-12: SDIO card bus mode control bit.

CLKEDGE

Bit 13: SDIO_CLK clock edge selection bit.

HWCLKEN

Bit 14: Hardware Clock Control enable bit.

DIV_8

Bit 31: MSB of Clock division.

CMDAGMT

Command argument register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDAGMT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDAGMT
rw
Toggle Fields.

CMDAGMT

Bits 0-31: SDIO card command argument.

CMDCTL

Command control register

Offset: 0xC, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATAEN
rw 		NINTEN
rw 		ENCMDC
rw 		SUSPEND
rw 		CSMEN
rw 		WAITDEND
rw 		INTWAIT
rw 		CMDRESP
rw 		CMDIDX
rw
Toggle Fields.

CMDIDX

Bits 0-5: Command index.

CMDRESP

Bits 6-7: Command response type bits.

INTWAIT

Bit 8: Interrupt wait instead of timeout.

WAITDEND

Bit 9: Waits for ends of data transfer.

CSMEN

Bit 10: Command state machine (CSM) enable bit.

SUSPEND

Bit 11: SD I/O suspend command(SD I/O only).

ENCMDC

Bit 12: CMD completion signal enabled (CE-ATA only).

NINTEN

Bit 13: No CE-ATA Interrupt (CE-ATA only).

ATAEN

Bit 14: CE-ATA command enable(CE-ATA only).

RSPCMDIDX

Command index response register

Offset: 0x10, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSPCMDIDX
r
Toggle Fields.

RSPCMDIDX

Bits 0-5: Last response command index.

RESP0

Response register 0

Offset: 0x14, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESP0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESP0
r
Toggle Fields.

RESP0

Bits 0-31: Card state.

RESP1

Response register 1

Offset: 0x18, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESP1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESP1
r
Toggle Fields.

RESP1

Bits 0-31: Card state.

RESP2

Response register 2

Offset: 0x1C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESP2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESP2
r
Toggle Fields.

RESP2

Bits 0-31: Card state.

RESP3

Response register 3

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESP3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESP3
r
Toggle Fields.

RESP3

Bits 0-31: Response register 3.

DATATO

Data timeout register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATATO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATATO
rw
Toggle Fields.

DATATO

Bits 0-31: Data timeout period.

DATALEN

Data length register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATALEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATALEN
rw
Toggle Fields.

DATALEN

Bits 0-24: Data transfer length.

DATACTL

Data control register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOEN
rw 		RWTYPE
rw 		RWSTOP
rw 		RWEN
rw 		BLKSZ
rw 		DMAEN
rw 		TRANSMOD
rw 		DATADIR
rw 		DATAEN
rw
Toggle Fields.

DATAEN

Bit 0: Data transfer enabled bit.

DATADIR

Bit 1: Data transfer direction.

TRANSMOD

Bit 2: Data transfer mode.

DMAEN

Bit 3: DMA enable bit.

BLKSZ

Bits 4-7: Data block size.

RWEN

Bit 8: Read wait mode enabled.

RWSTOP

Bit 9: Read wait stop.

RWTYPE

Bit 10: Read wait type.

IOEN

Bit 11: SD I/O specific function enable.

DATACNT

Data counter register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATACNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATACNT
r
Toggle Fields.

DATACNT

Bits 0-24: Data count value.

STAT

Status register

Offset: 0x34, reset: 0x00000000, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATAEND
r 		SDIOINT
r 		RXDTVAL
r 		TXDTVAL
r 		RFE
r 		TFE
r 		RFF
r 		TFF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFH
r 		TFH
r 		RXRUN
r 		TXRUN
r 		CMDRUN
r 		DTBLKEND
r 		STBITE
r 		DTEND
r 		CMDSEND
r 		CMDRECV
r 		RXORE
r 		TXURE
r 		DTTMOUT
r 		CMDTMOUT
r 		DTCRCERR
r 		CCRCERR
r
Toggle Fields.

CCRCERR

Bit 0: Command response received.

DTCRCERR

Bit 1: Data block sent/received.

CMDTMOUT

Bit 2: Command response timeout.

DTTMOUT

Bit 3: Data timeout.

TXURE

Bit 4: Transmit FIFO underrun error occurs.

RXORE

Bit 5: Received FIFO overrun error occurs.

CMDRECV

Bit 6: Command response received.

CMDSEND

Bit 7: Command sent.

DTEND

Bit 8: Data end.

STBITE

Bit 9: Start bit error in the bus.

DTBLKEND

Bit 10: Data block sent/received.

CMDRUN

Bit 11: Command transmission in progress.

TXRUN

Bit 12: Data transmission in progress.

RXRUN

Bit 13: Data reception in progress.

TFH

Bit 14: Transmit FIFO is half empty.

RFH

Bit 15: Receive FIFO is half full.

TFF

Bit 16: Transmit FIFO is full.

RFF

Bit 17: Receive FIFO is full.

TFE

Bit 18: Transmit FIFO is empty.

RFE

Bit 19: Receive FIFO is empty.

TXDTVAL

Bit 20: Data is valid in transmit FIFO.

RXDTVAL

Bit 21: Data is valid in receive FIFO.

SDIOINT

Bit 22: SD I/O interrupt received.

ATAEND

Bit 23: CE-ATA command completion signal received.

INTC

Interrupt clear register

Offset: 0x38, reset: 0x00000000, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATAENDC
w 		SDIOINTC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTBLKENDC
w 		STBITEC
w 		DTENDC
w 		CMDSENDC
w 		CMDRECVC
w 		RXOREC
w 		TXUREC
w 		DTTMOUTC
w 		CMDTMOUTC
w 		DTCRCERRC
w 		CCRCERRC
w
Toggle Fields.

CCRCERRC

Bit 0: CCRCERR flag clear bit.

DTCRCERRC

Bit 1: DTCRCERR flag clear bit.

CMDTMOUTC

Bit 2: CMDTMOUT flag clear bit.

DTTMOUTC

Bit 3: DTTMOUT flag clear bit.

TXUREC

Bit 4: TXURE flag clear bit.

RXOREC

Bit 5: RXORE flag clear bit.

CMDRECVC

Bit 6: CMDRECV flag clear bit.

CMDSENDC

Bit 7: CMDSEND flag clear bit.

DTENDC

Bit 8: DTEND flag clear bit.

STBITEC

Bit 9: STBITE flag clear bit.

DTBLKENDC

Bit 10: DTBLKEND flag clear bit.

SDIOINTC

Bit 22: SDIOINT flag clear bit.

ATAENDC

Bit 23: ATAEND flag clear bit.

INTEN

Interrupt enable register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATAENDIE
rw 		SDIOINTIE
rw 		RXDTVALIE
rw 		TXDTVALIE
rw 		RFEIE
rw 		TFEIE
rw 		RFFIE
rw 		TFFIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFHIE
rw 		TFHIE
rw 		RXRUNIE
rw 		TXRUNIE
rw 		CMDRUNIE
rw 		DTBLKENDIE
rw 		STBITEIE
rw 		DTENDIE
rw 		CMDSENDIE
rw 		CMDRECVIE
rw 		RXOREIE
rw 		TXUREIE
rw 		DTTMOUTIE
rw 		CMDTMOUTIE
rw 		DTCRCERRIE
rw 		CCRCERRIE
rw
Toggle Fields.

CCRCERRIE

Bit 0: Command response CRC fail interrupt enable.

DTCRCERRIE

Bit 1: Data CRC fail interrupt enable.

CMDTMOUTIE

Bit 2: Command response timeout interrupt enable.

DTTMOUTIE

Bit 3: Data timeout interrupt enable.

TXUREIE

Bit 4: Transmit FIFO underrun error interrupt enable.

RXOREIE

Bit 5: Received FIFO overrun error interrupt enable.

CMDRECVIE

Bit 6: Command response received interrupt enable.

CMDSENDIE

Bit 7: Command sent interrupt enable.

DTENDIE

Bit 8: Data end interrupt enable.

STBITEIE

Bit 9: Start bit error interrupt enable.

DTBLKENDIE

Bit 10: Data block end interrupt enable.

CMDRUNIE

Bit 11: Command transmission interrupt enable.

TXRUNIE

Bit 12: Data transmission interrupt enable.

RXRUNIE

Bit 13: Data reception interrupt enable.

TFHIE

Bit 14: Transmit FIFO half empty interrupt enable.

RFHIE

Bit 15: Receive FIFO half full interrupt enable.

TFFIE

Bit 16: Transmit FIFO full interrupt enable.

RFFIE

Bit 17: Receive FIFO full interrupt enable.

TFEIE

Bit 18: Transmit FIFO empty interrupt enable.

RFEIE

Bit 19: Receive FIFO empty interrupt enable.

TXDTVALIE

Bit 20: Data valid in transmit FIFO interrupt enable.

RXDTVALIE

Bit 21: Data valid in receive FIFO interrupt enable.

SDIOINTIE

Bit 22: SD I/O interrupt received interrupt enable.

ATAENDIE

Bit 23: CE-ATA command completion signal received interrupt enable.

FIFOCNT

FIFO counter register

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCNT
r
Toggle Fields.

FIFOCNT

Bits 0-23: FIFO counter.

FIFO

FIFO data register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODT
rw
Toggle Fields.

FIFODT

Bits 0-31: Receive FIFO data or transmit FIFO data.

SHRTIMER_COMMON

0x40017780: SHRTIMER Common registers

18/431 fields covered. Toggle Registers.

CTL0

SHRTIMER control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADTG3USRC
rw 		ADTG2USRC
rw 		ADTG1USRC
rw 		ADTG0USRC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST4UPDIS
rw 		ST3UPDIS
rw 		ST2UPDIS
rw 		ST0UPDIS
rw 		MTUPDIS
rw
Toggle Fields.

MTUPDIS

Bit 0: Master_TIMER update disable.

ST0UPDIS

Bit 1: Slave_TIMER0 update disable.

ST2UPDIS

Bit 3: Slave_TIMER2 update disable.

ST3UPDIS

Bit 4: Slave_TIMER3 update disable.

ST4UPDIS

Bit 5: Slave_TIMER4 update disable.

ADTG0USRC

Bits 16-18: SHRTIMER_ADCTRIG0 update source.

ADTG1USRC

Bits 19-21: SHRTIMER_ADCTRIG1 update source.

ADTG2USRC

Bits 22-24: SHRTIMER_ADCTRIG2 update source.

ADTG3USRC

Bits 25-27: SHRTIMER_ADCTRIG3 update source.

CTL1

SHRTIMER control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST4SRST
rw 		ST3SRST
rw 		ST2SRST
rw 		ST1SRST
rw 		ST0SRST
rw 		MTSRST
rw 		ST4SUP
rw 		ST3SUP
rw 		ST2SUP
rw 		ST1SUP
rw 		ST0SUP
rw 		MTSUP
rw
Toggle Fields.

MTSUP

Bit 0: Master_TIMER software update.

ST0SUP

Bit 1: Slave_TIMER0 software update.

ST1SUP

Bit 2: Slave_TIMER1 software update.

ST2SUP

Bit 3: Slave_TIMER2 software update.

ST3SUP

Bit 4: Slave_TIMER3 software update.

ST4SUP

Bit 5: Slave_TIMER4 software update.

MTSRST

Bit 8: Master_TIMER software reset.

ST0SRST

Bit 9: Slave_TIMER0 software reset.

ST1SRST

Bit 10: Slave_TIMER1 software reset.

ST2SRST

Bit 11: Slave_TIMER2 software reset.

ST3SRST

Bit 12: Slave_TIMER3 software reset.

ST4SRST

Bit 13: Slave_TIMER4 software reset.

INTF

SHRTIMER interrupt flag register

Offset: 0x8, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BMPERIF
r 		DLLCALIF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSFLTIF
r 		FLT4IF
r 		FLT3IF
r 		FLT2IF
r 		FLT1IF
r 		FLT0IF
r
Toggle Fields.

FLT0IF

Bit 0: Fault 0 interrupt flag.

FLT1IF

Bit 1: Fault 1 interrupt flag.

FLT2IF

Bit 2: Fault 2 interrupt flag.

FLT3IF

Bit 3: Fault 3 interrupt flag.

FLT4IF

Bit 4: Fault 4 interrupt flag.

SYSFLTIF

Bit 5: System fault interrupt flag.

DLLCALIF

Bit 16: DLL calibration completed interrupt flag.

BMPERIF

Bit 17: Bunch mode period interrupt flag.

INTC

SHRTIMER interrupt flag clear register

Offset: 0xC, reset: 0x00000000, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BMPERIFC
w 		DLLCALIF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSFLTIFC
w 		FLT4IFC
w 		FLT3IFC
w 		FLT2IFC
w 		FLT1IF
w 		FLT0IFC
w
Toggle Fields.

FLT0IFC

Bit 0: Fault 0 interrupt flag.

FLT1IF

Bit 1: Fault 1 interrupt flag.

FLT2IFC

Bit 2: Clear fault 2 interrupt flag.

FLT3IFC

Bit 3: Clear fault 3 interrupt flag.

FLT4IFC

Bit 4: Clear fault 4 interrupt flag.

SYSFLTIFC

Bit 5: Clear system fault interrupt flag.

DLLCALIF

Bit 16: Clear DLL calibration completed interrupt flag.

BMPERIFC

Bit 17: Clear bunch mode period interrupt flag.

INTEN

SHRTIMER interrupt enable register

Offset: 0x10, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BMPERIE
rw 		DLLCALIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSFLTIE
rw
Toggle Fields.

SYSFLTIE

Bit 5: System fault interrupt enable.

DLLCALIE

Bit 16: DLL calibration completed interrupt enable.

BMPERIE

Bit 17: Bunch mode period interrupt enable.

CHOUTEN

SHRTIMER channel output enable register

Offset: 0x14, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST4CH1EN
rw 		ST4CH0EN
rw 		ST3CH1EN
rw 		ST3CH0EN
rw 		ST2CH1EN
rw 		ST2CH0EN
rw 		ST1CH1EN
rw 		ST1CH0EN
rw 		ST0CH1EN
rw 		ST0CH0EN
rw
Toggle Fields.

ST0CH0EN

Bit 0: Slave_TIMER0 channel 0 output (ST0CH0_O) enable.

ST0CH1EN

Bit 1: Slave_TIMER0 channel 1 output (ST0CH1_O) enable.

ST1CH0EN

Bit 2: Slave_TIMER1 channel 0 output (ST1CH0_O) enable.

ST1CH1EN

Bit 3: Slave_TIMER1 channel 1 output (ST1CH1_O) enable.

ST2CH0EN

Bit 4: Slave_TIMER2 channel 0 output (ST2CH0_O) enable.

ST2CH1EN

Bit 5: Slave_TIMER2 channel 1 output (ST2CH1_O) enable.

ST3CH0EN

Bit 6: Slave_TIMER3 channel 0 output (ST3CH0_O) enable.

ST3CH1EN

Bit 7: Slave_TIMER3 channel 1 output (ST3CH1_O) enable.

ST4CH0EN

Bit 8: Slave_TIMER4 channel 0 output (ST4CH0_O) enable.

ST4CH1EN

Bit 9: Slave_TIMER4 channel 1 output (ST4CH1_O) enable.

CHOUTDIS

SHRTIMER channel output disable register

Offset: 0x18, reset: 0x00000000, access: write-only

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST4CH1DIS
w 		ST4CH0DIS
w 		ST3CH1DIS
w 		ST3CH0DIS
w 		ST2CH1DIS
w 		ST2CH0DIS
w 		ST1CH1DIS
w 		ST1CH0DIS
w 		ST0CH1DIS
w 		ST0CH0DIS
w
Toggle Fields.

ST0CH0DIS

Bit 0: Slave_TIMER0 channel 0 output (ST0CH0_O) disable.

ST0CH1DIS

Bit 1: Slave_TIMER0 channel 1 output (ST4CH0_O) disable.

ST1CH0DIS

Bit 2: Slave_TIMER1 channel 0 output (ST1CH0_O) disable.

ST1CH1DIS

Bit 3: Slave_TIMER1 channel 1 output (ST1CH1_O) disable.

ST2CH0DIS

Bit 4: Slave_TIMER2 channel 0 output (ST2CH0_O) disable.

ST2CH1DIS

Bit 5: Slave_TIMER2 channel 1 output (ST2CH1_O) disable.

ST3CH0DIS

Bit 6: Slave_TIMER3 channel 0 output (ST3CH0_O) disable.

ST3CH1DIS

Bit 7: Slave_TIMER3 channel 1 output (ST3CH1_O) disable.

ST4CH0DIS

Bit 8: Slave_TIMER4 channel 0 output (ST4CH0_O) disable.

ST4CH1DIS

Bit 9: Slave_TIMER4 channel 1 output (ST4CH1_O) disable.

CHOUTDISF

SHRTIMER channel output disable flag register

Offset: 0x1C, reset: 0x00000000, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST4CH1DISF
r 		ST4CH0DISF
r 		ST3CH1DISF
r 		ST3CH0DISF
r 		ST2CH1DISF
r 		ST2CH0DISF
r 		ST1CH1DISF
r 		ST1CH0DISF
r 		ST0CH1DISF
r 		ST0CH0DISF
r
Toggle Fields.

ST0CH0DISF

Bit 0: Slave_TIMER0 channel 0 output (ST0CH0_O) disable flag.

ST0CH1DISF

Bit 1: Slave_TIMER0 channel 1 output (ST0CH1_O) disable flag.

ST1CH0DISF

Bit 2: Slave_TIMER1 channel 0 output (ST1CH0_O) disable flag.

ST1CH1DISF

Bit 3: Slave_TIMER1 channel 1 output (ST1CH1_O) disable flag.

ST2CH0DISF

Bit 4: Slave_TIMER2 channel 0 output (ST2CH0_O) disable flag.

ST2CH1DISF

Bit 5: Slave_TIMER2 channel 1 output (ST2CH1_O) disable flag.

ST3CH0DISF

Bit 6: Slave_TIMER3 channel 0 output (ST3CH0_O) disable flag.

ST3CH1DISF

Bit 7: Slave_TIMER3 channel 1 output (ST3CH1_O) disable flag.

ST4CH0DISF

Bit 8: Slave_TIMER4 channel 0 output (ST4CH0_O) disable flag.

ST4CH1DISF

Bit 9: Slave_TIMER4 channel 1 output (ST4CH1_O) disable flag.

BMCTL

SHRTIMER bunch mode control register

Offset: 0x20, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BMOPTF
rw 		BMST4
rw 		BMST3
rw 		BMST2
rw 		BMST1
rw 		BMST0
rw 		BMMT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BMSE
rw 		BMPSC
rw 		BMCLKS
rw 		BMCTN
rw 		BMEN
rw
Toggle Fields.

BMEN

Bit 0: Bunch mode enable.

BMCTN

Bit 1: Continuous mode in bunch mode.

BMCLKS

Bits 2-5: Bunch mode clock source.

BMPSC

Bits 6-9: Bunch mode clock division.

BMSE

Bit 10: Bunch mode shadow enable.

BMMT

Bit 16: Master_TIMER bunch mode.

BMST0

Bit 17: Slave_TIMER0 bunch mode.

BMST1

Bit 18: Slave_TIMER1 bunch mode.

BMST2

Bit 19: Slave_TIMER2 bunch mode.

BMST3

Bit 20: Slave_TIMER3 bunch mode.

BMST4

Bit 21: Slave_TIMER4 bunch mode.

BMOPTF

Bit 31: Bunch mode operating flag.

BMSTRG

SHRTIMER bunch mode start trigger register

Offset: 0x24, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CISGN
rw 		EXEV7
rw 		EXEV6
rw 		ST3EXEV7
rw 		ST0EXEV6
rw 		ST4CMP1
rw 		ST4CMP0
rw 		ST4REP
rw 		ST4RST
rw 		ST3CMP1
rw 		ST3CMP0
rw 		ST3REP
rw 		ST3RST
rw 		ST2CMP1
rw 		ST2CMP0
rw 		ST2REP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST2RST
rw 		ST1CMP1
rw 		ST1CMP0
rw 		ST1REP
rw 		ST1RST
rw 		ST0CMP1
rw 		ST0CMP0
rw 		ST0REP
rw 		ST0RST
rw 		MTCMP3
rw 		MTCMP2
rw 		MTCMP1
rw 		MTCMP0
rw 		MTREP
rw 		MTRST
rw 		SWTRG
rw
Toggle Fields.

SWTRG

Bit 0: Software triggers bunch mode operation.

MTRST

Bit 1: Master_TIMER reset event triggers bunch mode operation.

MTREP

Bit 2: Master_TIMER repetition event triggers bunch mode operation.

MTCMP0

Bit 3: Master_TIMER compare 0 event triggers bunch mode operation.

MTCMP1

Bit 4: Master_TIMER compare 1 event triggers bunch mode operation.

MTCMP2

Bit 5: Master_TIMER compare 2 event triggers bunch mode operation.

MTCMP3

Bit 6: Master_TIMER compare 3 event triggers bunch mode operation.

ST0RST

Bit 7: Slave_TIMER0 reset event triggers bunch mode operation.

ST0REP

Bit 8: Slave_TIMER0 repetition event triggers bunch mode operation.

ST0CMP0

Bit 9: Slave_TIMER0 compare 0 event triggers bunch mode operation.

ST0CMP1

Bit 10: Slave_TIMER0 compare 1 event triggers bunch mode operation.

ST1RST

Bit 11: Slave_TIMER1 reset event triggers bunch mode operation.

ST1REP

Bit 12: Slave_TIMER1 repetition event triggers bunch mode operation.

ST1CMP0

Bit 13: Slave_TIMER1 compare 0 event triggers bunch mode operation.

ST1CMP1

Bit 14: Slave_TIMER1 compare 1 event triggers bunch mode operation.

ST2RST

Bit 15: Slave_TIMER2 reset event triggers bunch mode operation.

ST2REP

Bit 16: Slave_TIMER1 repetition event triggers bunch mode operation.

ST2CMP0

Bit 17: Slave_TIMER2 compare 0 event triggers bunch mode operation.

ST2CMP1

Bit 18: Slave_TIMER2 compare 1 event triggers bunch mode operation.

ST3RST

Bit 19: Slave_TIMER3 reset event triggers bunch mode operation.

ST3REP

Bit 20: Slave_TIMER3 repetition event triggers bunch mode operation.

ST3CMP0

Bit 21: Slave_TIMER3 compare 0 event triggers bunch mode operation.

ST3CMP1

Bit 22: Slave_TIMER3 compare 1 event triggers bunch mode operation.

ST4RST

Bit 23: Slave_TIMER4 reset event triggers bunch mode operation.

ST4REP

Bit 24: Slave_TIMER4 repetition event triggers bunch mode operation.

ST4CMP0

Bit 25: Slave_TIMER4 compare 0 event triggers bunch mode operation.

ST4CMP1

Bit 26: Slave_TIMER4 compare 1 event triggers bunch mode operation.

ST0EXEV6

Bit 27: Slave_TIMER0 period event following external event 6 triggers bunch mode operation.

ST3EXEV7

Bit 28: Slave_TIMER3 period event following external event 7 triggers bunch mode operation.

EXEV6

Bit 29: External event 6 triggers bunch mode operation.

EXEV7

Bit 30: External event 7 triggers bunch mode operation.

CISGN

Bit 31: Chip internal signal triggers bunch mode operation.

BMCMPV

SHRTIMER bunch mode compare value register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BMCMPVAL
rw
Toggle Fields.

BMCMPVAL

Bits 0-15: Bunch mode compare value.

BMCAR

SHRTIMER bunch mode counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BMCARL
rw
Toggle Fields.

BMCARL

Bits 0-15: Bunch mode counter auto reload value.

EXEVCFG0

SHRTIMER external event configuration register 0

Offset: 0x30, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXEV4EG
rw 		EXEV4P
rw 		EXEV4SRC
rw 		EXEV3EG
rw 		EXEV3P
rw 		EXEV3SRC
rw 		EXEV2EG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXEV2EG
rw 		EXEV2P
rw 		EXEV2SRC
rw 		EXEV1EG
rw 		EXEV1P
rw 		EXEV1SRC
rw 		EXEV0EG
rw 		EXEV0P
rw 		EXEV0SRC
rw
Toggle Fields.

EXEV0SRC

Bits 0-1: External event 0 source.

EXEV0P

Bit 2: External event 0 polarity.

EXEV0EG

Bits 3-4: External event 0 edge sensitivity.

EXEV1SRC

Bits 6-7: External event 1 source.

EXEV1P

Bit 8: External event 1 polarity.

EXEV1EG

Bits 9-10: External event 1 edge sensitivity.

EXEV2SRC

Bits 12-13: External event 2 source.

EXEV2P

Bit 14: External event 2 polarity.

EXEV2EG

Bits 15-16: External event 2 edge sensitivity.

EXEV3SRC

Bits 18-19: External event 3 source.

EXEV3P

Bit 20: External event 3 polarity.

EXEV3EG

Bits 21-22: External event 3 edge sensitivity.

EXEV4SRC

Bits 24-25: External event 4 source.

EXEV4P

Bit 26: External event 4 polarity.

EXEV4EG

Bits 27-28: External event 4 edge sensitivity.

EXEVCFG1

SHRTIMER external event configuration register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXEV9EG
rw 		EXEV9P
rw 		EXEV9SRC
rw 		EXEV8EG
rw 		EXEV8P
rw 		EXEV8SRC
rw 		EXEV7EG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXEV7EG
rw 		EXEV7P
rw 		EXEV7SRC
rw 		EXEV6EG
rw 		EXEV6P
rw 		EXEV6SRC
rw 		EXEV5EG
rw 		EXEV5P
rw 		EXEV5SRC
rw
Toggle Fields.

EXEV5SRC

Bits 0-1: External event 0 source.

EXEV5P

Bit 2: External event 0 polarity.

EXEV5EG

Bits 3-4: External event 0 edge sensitivity.

EXEV6SRC

Bits 6-7: External event 1 source.

EXEV6P

Bit 8: External event 1 polarity.

EXEV6EG

Bits 9-10: External event 6 edge sensitivity.

EXEV7SRC

Bits 12-13: External event 7 source.

EXEV7P

Bit 14: External event 7polarity.

EXEV7EG

Bits 15-16: External event 7 edge sensitivity.

EXEV8SRC

Bits 18-19: External event 8 source.

EXEV8P

Bit 20: External event 8 polarity.

EXEV8EG

Bits 21-22: External event 8 edge sensitivity.

EXEV9SRC

Bits 24-25: External event 9 source.

EXEV9P

Bit 26: External event 9 polarity.

EXEV9EG

Bits 27-28: External event 9 edge sensitivity.

EXEVDFCTL

SHRTIMER external event digital filter control register

Offset: 0x38, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXEVFDIV
rw 		EXEV9FC
rw 		EXEV8FC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXEV7FC
rw 		EXEV6FC
rw 		EXEV5FC
rw
Toggle Fields.

EXEV5FC

Bits 0-3: External event 5 filter control.

EXEV6FC

Bits 6-9: External event 6 filter control.

EXEV7FC

Bits 12-15: External event 7 filter control.

EXEV8FC

Bits 18-21: External event 8 filter control.

EXEV9FC

Bits 24-27: External event 9 filter control.

EXEVFDIV

Bits 30-31: External event digital filter clock division.

ADCTRIGS0

SHRTIMER trigger source 0 to ADC register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRG0ST4PER
rw 		TRG0ST4C3
rw 		TRG0ST4C2
rw 		TRG0ST4C1
rw 		TRG0ST3PER
rw 		TRG0ST3C3
rw 		TRG0ST3C2
rw 		TRG0ST3C1
rw 		TRG0ST2PER
rw 		TRG0ST2C3
rw 		TRG0ST2C2
rw 		TRG0ST2C1
rw 		TRG0ST1RST
rw 		TRG0ST1PER
rw 		TRG0ST1C3
rw 		TRG0ST1C2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRG0ST1C1
rw 		TRG0ST0RST
rw 		TRG0ST0PER
rw 		TRG0ST0C3
rw 		TRG0ST0C2
rw 		TRG0ST0C1
rw 		TRG0EXEV4
rw 		TRG0EXEV3
rw 		TRG0EXEV2
rw 		TRG0EXEV1
rw 		TRG0EXEV0
rw 		TRG0MTPER
rw 		TRG0MTC3
rw 		TRG0MTC2
rw 		TRG0MTC1
rw 		TRG0MTC0
rw
Toggle Fields.

TRG0MTC0

Bit 0: SHRTIMER_ADCTRIG0 on Master_TIMER compare 0 event.

TRG0MTC1

Bit 1: SHRTIMER_ADCTRIG0 on Master_TIMER compare 1 event.

TRG0MTC2

Bit 2: SHRTIMER_ADCTRIG0 on Master_TIMER compare 2 event.

TRG0MTC3

Bit 3: SHRTIMER_ADCTRIG0 on Master_TIMER compare 3 event.

TRG0MTPER

Bit 4: SHRTIMER_ADCTRIG0 on Master_TIMER period event.

TRG0EXEV0

Bit 5: SHRTIMER_ADCTRIG0 on external event 0.

TRG0EXEV1

Bit 6: SHRTIMER_ADCTRIG0 on external event 1.

TRG0EXEV2

Bit 7: SHRTIMER_ADCTRIG0 on external event 2.

TRG0EXEV3

Bit 8: SHRTIMER_ADCTRIG0 on external event 3.

TRG0EXEV4

Bit 9: SHRTIMER_ADCTRIG0 on external event 4.

TRG0ST0C1

Bit 10: SHRTIMER_ADCTRIG0 on Slave_TIMER0 compare 1 event.

TRG0ST0C2

Bit 11: SHRTIMER_ADCTRIG0 on Slave_TIMER0 compare 2 event.

TRG0ST0C3

Bit 12: SHRTIMER_ADCTRIG0 on Slave_TIMER0 compare 3 event.

TRG0ST0PER

Bit 13: SHRTIMER_ADCTRIG0 on Slave_TIMER0 period event.

TRG0ST0RST

Bit 14: SHRTIMER_ADCTRIG0 on Slave_TIMER0 reset.

TRG0ST1C1

Bit 15: SHRTIMER_ADCTRIG0 on Slave_TIMER1 compare 1 event.

TRG0ST1C2

Bit 16: SHRTIMER_ADCTRIG0 on Slave_TIMER1 compare 2 event.

TRG0ST1C3

Bit 17: SHRTIMER_ADCTRIG0 on Slave_TIMER1 compare 3 event.

TRG0ST1PER

Bit 18: SHRTIMER_ADCTRIG0 on Slave_TIMER1 period event.

TRG0ST1RST

Bit 19: SHRTIMER_ADCTRIG0 on Slave_TIMER1 reset.

TRG0ST2C1

Bit 20: SHRTIMER_ADCTRIG0 on Slave_TIMER2 compare 1 event.

TRG0ST2C2

Bit 21: SHRTIMER_ADCTRIG0 on Slave_TIMER2 compare 2 event.

TRG0ST2C3

Bit 22: SHRTIMER_ADCTRIG0 on Slave_TIMER2 compare 3 event.

TRG0ST2PER

Bit 23: SHRTIMER_ADCTRIG0 on Slave_TIMER2 period event.

TRG0ST3C1

Bit 24: SHRTIMER_ADCTRIG0 on Slave_TIMER3 compare 1 event.

TRG0ST3C2

Bit 25: SHRTIMER_ADCTRIG0 on Slave_TIMER3 compare 2 event.

TRG0ST3C3

Bit 26: SHRTIMER_ADCTRIG0 on Slave_TIMER3 compare 3 event.

TRG0ST3PER

Bit 27: SHRTIMER_ADCTRIG0 on Slave_TIMER3 period event.

TRG0ST4C1

Bit 28: SHRTIMER_ADCTRIG0 on Slave_TIMER4 compare 1 event.

TRG0ST4C2

Bit 29: SHRTIMER_ADCTRIG0 on Slave_TIMER4 compare 2 event.

TRG0ST4C3

Bit 30: SHRTIMER_ADCTRIG0 on Slave_TIMER4 compare 3 event.

TRG0ST4PER

Bit 31: SHRTIMER_ADCTRIG0 on Slave_TIMER4 period event.

ADCTRIGS1

SHRTIMER trigger source 1 to ADC register

Offset: 0x40, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRG1ST4RST
rw 		TRG1ST4C3
rw 		TRG1ST4C2
rw 		TRG1ST4C1
rw 		TRG1ST3RST
rw 		TRG1ST3PER
rw 		TRG1ST3C3
rw 		TRG1ST3C2
rw 		TRG1ST3C1
rw 		TRG1ST2RST
rw 		TRG1ST2PER
rw 		TRG1ST2C3
rw 		TRG1ST2C2
rw 		TRG1ST2C1
rw 		TRG1ST1PER
rw 		TRG1ST1C3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRG1ST1C2
rw 		TRG1ST1C1
rw 		TRG1ST0PER
rw 		TRG1ST0C3
rw 		TRG1ST0C2
rw 		TRG1ST0C1
rw 		TRG1EXEV9
rw 		TRG1EXEV8
rw 		TRG1EXEV7
rw 		TRG1EXEV6
rw 		TRG1EXEV5
rw 		TRG1MTPER
rw 		TRG1MTC3
rw 		TRG1MTC2
rw 		TRG1MTC1
rw 		TRG1MTC0
rw
Toggle Fields.

TRG1MTC0

Bit 0: SHRTIMER_ADCTRIG1 on Master_TIMER compare 0 event.

TRG1MTC1

Bit 1: SHRTIMER_ADCTRIG1 on Master_TIMER compare 1 event.

TRG1MTC2

Bit 2: SHRTIMER_ADCTRIG1 on Master_TIMER compare 2 event.

TRG1MTC3

Bit 3: SHRTIMER_ADCTRIG1 on Master_TIMER compare 3 event.

TRG1MTPER

Bit 4: SHRTIMER_ADCTRIG1 on Master_TIMER period event.

TRG1EXEV5

Bit 5: SHRTIMER_ADCTRIG1 on external event 5.

TRG1EXEV6

Bit 6: SHRTIMER_ADCTRIG1 on external event 6.

TRG1EXEV7

Bit 7: SHRTIMER_ADCTRIG1 on external event 7.

TRG1EXEV8

Bit 8: SHRTIMER_ADCTRIG1 on external event 8.

TRG1EXEV9

Bit 9: SHRTIMER_ADCTRIG1 on external event 9.

TRG1ST0C1

Bit 10: SHRTIMER_ADCTRIG1 on Slave_TIMER0 compare 1 event.

TRG1ST0C2

Bit 11: SHRTIMER_ADCTRIG1 on Slave_TIMER0 compare 2 event.

TRG1ST0C3

Bit 12: SHRTIMER_ADCTRIG1 on Slave_TIMER0 compare 3 event.

TRG1ST0PER

Bit 13: SHRTIMER_ADCTRIG1 on Slave_TIMER0 period event.

TRG1ST1C1

Bit 14: SHRTIMER_ADCTRIG1 on Slave_TIMER1 compare 1 event.

TRG1ST1C2

Bit 15: SHRTIMER_ADCTRIG1 on Slave_TIMER1 compare 2 event.

TRG1ST1C3

Bit 16: SHRTIMER_ADCTRIG1 on Slave_TIMER1 compare 3 event.

TRG1ST1PER

Bit 17: SHRTIMER_ADCTRIG1 on Slave_TIMER1 period event.

TRG1ST2C1

Bit 18: SHRTIMER_ADCTRIG1 on Slave_TIMER2 compare 1 event.

TRG1ST2C2

Bit 19: SHRTIMER_ADCTRIG1 on Slave_TIMER2 compare 2 event.

TRG1ST2C3

Bit 20: SHRTIMER_ADCTRIG1 on Slave_TIMER2 compare 3 event.

TRG1ST2PER

Bit 21: SHRTIMER_ADCTRIG1 on Slave_TIMER2 period event.

TRG1ST2RST

Bit 22: SHRTIMER_ADCTRIG1 on Slave_TIMER2 reset .

TRG1ST3C1

Bit 23: SHRTIMER_ADCTRIG1 on Slave_TIMER3 compare 1 event.

TRG1ST3C2

Bit 24: SHRTIMER_ADCTRIG1 on Slave_TIMER3 compare 2 event.

TRG1ST3C3

Bit 25: SHRTIMER_ADCTRIG1 on Slave_TIMER3 compare 3 event.

TRG1ST3PER

Bit 26: SHRTIMER_ADCTRIG1 on Slave_TIMER3 period event.

TRG1ST3RST

Bit 27: SHRTIMER_ADCTRIG1 on Slave_TIMER3 reset .

TRG1ST4C1

Bit 28: SHRTIMER_ADCTRIG1 on Slave_TIMER4 compare 1 event.

TRG1ST4C2

Bit 29: SHRTIMER_ADCTRIG1 on Slave_TIMER4 compare 2 event.

TRG1ST4C3

Bit 30: SHRTIMER_ADCTRIG1 on Slave_TIMER4 compare 3 event.

TRG1ST4RST

Bit 31: SHRTIMER_ADCTRIG1 on Slave_TIMER4 reset .

ADCTRIGS2

SHRTIMER trigger source 2 to ADC register

Offset: 0x44, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRG2ST4PER
rw 		TRG2ST4C3
rw 		TRG2ST4C2
rw 		TRG2ST4C1
rw 		TRG2ST3PER
rw 		TRG2ST3C3
rw 		TRG2ST3C2
rw 		TRG2ST3C1
rw 		TRG2ST2PER
rw 		TRG2ST2C3
rw 		TRG2ST2C2
rw 		TRG2ST2C1
rw 		TRG2ST1RST
rw 		TRG2ST1PER
rw 		TRG2ST1C3
rw 		TRG2ST1C2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRG2ST1C1
rw 		TRG2ST0RST
rw 		TRG2ST0PER
rw 		TRG2ST0C3
rw 		TRG2ST0C2
rw 		TRG2ST0C1
rw 		TRG2EXEV4
rw 		TRG2EXEV3
rw 		TRG2EXEV2
rw 		TRG2EXEV1
rw 		TRG2EXEV0
rw 		TRG2MTPER
rw 		TRG2MTC3
rw 		TRG2MTC2
rw 		TRG2MTC1
rw 		TRG2MTC0
rw
Toggle Fields.

TRG2MTC0

Bit 0: SHRTIMER_ADCTRIG2 on Master_TIMER compare 0 event.

TRG2MTC1

Bit 1: SHRTIMER_ADCTRIG2 on Master_TIMER compare 1 event.

TRG2MTC2

Bit 2: SHRTIMER_ADCTRIG2 on Master_TIMER compare 2 event.

TRG2MTC3

Bit 3: SHRTIMER_ADCTRIG2 on Master_TIMER compare 3 event.

TRG2MTPER

Bit 4: SHRTIMER_ADCTRIG2 on Master_TIMER period event.

TRG2EXEV0

Bit 5: SHRTIMER_ADCTRIG2 on external event 0.

TRG2EXEV1

Bit 6: SHRTIMER_ADCTRIG2 on external event 1.

TRG2EXEV2

Bit 7: SHRTIMER_ADCTRIG2 on external event 2.

TRG2EXEV3

Bit 8: SHRTIMER_ADCTRIG2 on external event 3.

TRG2EXEV4

Bit 9: SHRTIMER_ADCTRIG2 on external event 4.

TRG2ST0C1

Bit 10: SHRTIMER_ADCTRIG2 on Slave_TIMER0 compare 1 event.

TRG2ST0C2

Bit 11: SHRTIMER_ADCTRIG2 on Slave_TIMER0 compare 2 event.

TRG2ST0C3

Bit 12: SHRTIMER_ADCTRIG2 on Slave_TIMER0 compare 3 event.

TRG2ST0PER

Bit 13: SHRTIMER_ADCTRIG2 on Slave_TIMER0 period event.

TRG2ST0RST

Bit 14: SHRTIMER_ADCTRIG2 on Slave_TIMER0 reset .

TRG2ST1C1

Bit 15: SHRTIMER_ADCTRIG2 on Slave_TIMER1 compare 1 event.

TRG2ST1C2

Bit 16: SHRTIMER_ADCTRIG2 on Slave_TIMER1 compare 2 event.

TRG2ST1C3

Bit 17: SHRTIMER_ADCTRIG2 on Slave_TIMER1 compare 3 event.

TRG2ST1PER

Bit 18: SHRTIMER_ADCTRIG2 on Slave_TIMER1 period event.

TRG2ST1RST

Bit 19: SHRTIMER_ADCTRIG2 on Slave_TIMER1 reset .

TRG2ST2C1

Bit 20: SHRTIMER_ADCTRIG2 on Slave_TIMER2 compare 1 event.

TRG2ST2C2

Bit 21: SHRTIMER_ADCTRIG2 on Slave_TIMER2 compare 2 event.

TRG2ST2C3

Bit 22: SHRTIMER_ADCTRIG2 on Slave_TIMER2 compare 3 event.

TRG2ST2PER

Bit 23: SHRTIMER_ADCTRIG2 on Slave_TIMER2 period event.

TRG2ST3C1

Bit 24: SHRTIMER_ADCTRIG2 on Slave_TIMER3 compare 1 event.

TRG2ST3C2

Bit 25: SHRTIMER_ADCTRIG2 on Slave_TIMER3 compare 2 event.

TRG2ST3C3

Bit 26: SHRTIMER_ADCTRIG2 on Slave_TIMER3 compare 3 event.

TRG2ST3PER

Bit 27: SHRTIMER_ADCTRIG2 on Slave_TIMER3 period event.

TRG2ST4C1

Bit 28: SHRTIMER_ADCTRIG2 on Slave_TIMER4 compare 1 event.

TRG2ST4C2

Bit 29: SHRTIMER_ADCTRIG2 on Slave_TIMER4 compare 2 event.

TRG2ST4C3

Bit 30: SHRTIMER_ADCTRIG2 on Slave_TIMER4 compare 3 event.

TRG2ST4PER

Bit 31: SHRTIMER_ADCTRIG2 on Slave_TIMER4 period event.

ADCTRIGS3

SHRTIMER trigger source 3 to ADC register

Offset: 0x48, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRG3ST4RST
rw 		TRG3ST4C3
rw 		TRG3ST4C2
rw 		TRG3ST4C1
rw 		TRG3ST3RST
rw 		TRG3ST3PER
rw 		TRG3ST3C3
rw 		TRG3ST3C2
rw 		TRG3ST3C1
rw 		TRG3ST2RST
rw 		TRG3ST2PER
rw 		TRG3ST2C3
rw 		TRG3ST2C2
rw 		TRG3ST2C1
rw 		TRG1ST3PER
rw 		TRG3ST1C3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRG3ST1C2
rw 		TRG3ST1C1
rw 		TRG3ST0PER
rw 		TRG3ST0C3
rw 		TRG3ST0C2
rw 		TRG3ST0C1
rw 		TRG3EXEV9
rw 		TRG3EXEV8
rw 		TRG3EXEV7
rw 		TRG3EXEV6
rw 		TRG3EXEV5
rw 		TRG3MTPER
rw 		TRG3MTC3
rw 		TRG3MTC2
rw 		TRG1MTC3
rw 		TRG3MTC0
rw
Toggle Fields.

TRG3MTC0

Bit 0: SHRTIMER_ADCTRIG3 on Master_TIMER compare 0 event.

TRG1MTC3

Bit 1: SHRTIMER_ADCTRIG3 on Master_TIMER compare 1 event.

TRG3MTC2

Bit 2: SHRTIMER_ADCTRIG3 on Master_TIMER compare 2 event.

TRG3MTC3

Bit 3: SHRTIMER_ADCTRIG3 on Master_TIMER compare 3 event.

TRG3MTPER

Bit 4: SHRTIMER_ADCTRIG3 on Master_TIMER period event.

TRG3EXEV5

Bit 5: SHRTIMER_ADCTRIG3 on external event 5.

TRG3EXEV6

Bit 6: SHRTIMER_ADCTRIG3 on external event 6.

TRG3EXEV7

Bit 7: SHRTIMER_ADCTRIG3 on external event 7.

TRG3EXEV8

Bit 8: SHRTIMER_ADCTRIG3 on external event 8.

TRG3EXEV9

Bit 9: SHRTIMER_ADCTRIG3 on external event 9.

TRG3ST0C1

Bit 10: SHRTIMER_ADCTRIG3 on Slave_TIMER0 compare 1 event.

TRG3ST0C2

Bit 11: SHRTIMER_ADCTRIG3 on Slave_TIMER0 compare 2 event.

TRG3ST0C3

Bit 12: SHRTIMER_ADCTRIG3 on Slave_TIMER0 compare 3 event.

TRG3ST0PER

Bit 13: SHRTIMER_ADCTRIG3 on Slave_TIMER0 period event.

TRG3ST1C1

Bit 14: SHRTIMER_ADCTRIG3 on Slave_TIMER1 compare 1 event.

TRG3ST1C2

Bit 15: SHRTIMER_ADCTRIG3 on Slave_TIMER1 compare 2 event.

TRG3ST1C3

Bit 16: SHRTIMER_ADCTRIG3 on Slave_TIMER1 compare 3 event.

TRG1ST3PER

Bit 17: SHRTIMER_ADCTRIG3 on Slave_TIMER1 period event.

TRG3ST2C1

Bit 18: SHRTIMER_ADCTRIG3 on Slave_TIMER2 compare 1 event.

TRG3ST2C2

Bit 19: SHRTIMER_ADCTRIG3 on Slave_TIMER2 compare 2 event.

TRG3ST2C3

Bit 20: SHRTIMER_ADCTRIG3 on Slave_TIMER2 compare 3 event.

TRG3ST2PER

Bit 21: SHRTIMER_ADCTRIG3 on Slave_TIMER2 period event.

TRG3ST2RST

Bit 22: SHRTIMER_ADCTRIG3 on Slave_TIMER2 reset .

TRG3ST3C1

Bit 23: SHRTIMER_ADCTRIG3 on Slave_TIMER3 compare 1 event.

TRG3ST3C2

Bit 24: SHRTIMER_ADCTRIG3 on Slave_TIMER3 compare 2 event.

TRG3ST3C3

Bit 25: SHRTIMER_ADCTRIG3 on Slave_TIMER3 compare 3 event.

TRG3ST3PER

Bit 26: SHRTIMER_ADCTRIG3 on Slave_TIMER3 period event.

TRG3ST3RST

Bit 27: SHRTIMER_ADCTRIG3 on Slave_TIMER3 reset .

TRG3ST4C1

Bit 28: SHRTIMER_ADCTRIG3 on Slave_TIMER4 compare 1 event.

TRG3ST4C2

Bit 29: SHRTIMER_ADCTRIG3 on Slave_TIMER4 compare 2 event.

TRG3ST4C3

Bit 30: SHRTIMER_ADCTRIG3 on Slave_TIMER4 compare 3 event.

TRG3ST4RST

Bit 31: SHRTIMER_ADCTRIG3 on Slave_TIMER4 reset .

DLLCCTL

SHRTIMER DLL calibration control register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLBPER
rw 		CLBPEREN
rw 		CLBSTRT
rw
Toggle Fields.

CLBSTRT

Bit 0: DLL calibration start once.

CLBPEREN

Bit 1: DLL periodic calibration enable.

CLBPER

Bits 2-3: DLL calibration period.

FLTINCFG0

SHRTIMER fault input configuration register 0

Offset: 0x50, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLT3INPROT
rw 		FLT3INFC
rw 		FLT3INSRC
rw 		FLT3INP
rw 		FLT3INEN
rw 		FLT2INPROT
rw 		FLT2INFC
rw 		FLT2INSRC
rw 		FLT2INP
rw 		FLT2INEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT1INPROT
rw 		FLT1INFC
rw 		FLT1INSRC
rw 		FLT1INP
rw 		FLT1INEN
rw 		FLT0INPROT
rw 		FLT0INFC
rw 		FLT0INSRC
rw 		FLT0INP
rw 		FLT0INEN
rw
Toggle Fields.

FLT0INEN

Bit 0: Fault 0 input enable .

FLT0INP

Bit 1: Fault 0 input polarity.

FLT0INSRC

Bit 2: Fault 0 input source.

FLT0INFC

Bits 3-6: Fault 0 input filter control.

FLT0INPROT

Bit 7: Protect fault 0 input configuration .

FLT1INEN

Bit 8: Fault 1 input enable .

FLT1INP

Bit 9: Fault 1 input polarity.

FLT1INSRC

Bit 10: Fault 2 input source.

FLT1INFC

Bits 11-14: Fault 1 input filter control.

FLT1INPROT

Bit 15: Protect fault 1 input configuration .

FLT2INEN

Bit 16: Fault 2 input enable .

FLT2INP

Bit 17: Fault 2 input polarity.

FLT2INSRC

Bit 18: Fault 2 input source.

FLT2INFC

Bits 19-22: Fault 2 input filter control.

FLT2INPROT

Bit 23: Protect fault 2 input configuration .

FLT3INEN

Bit 24: Fault 3 input enable .

FLT3INP

Bit 25: Fault 3 input polarity.

FLT3INSRC

Bit 26: Fault 3 input source.

FLT3INFC

Bits 27-30: Fault 3 input filter control.

FLT3INPROT

Bit 31: Protect fault 3 input configuration .

FLTINCFG1

SHRTIMER fault input configuration register 1

Offset: 0x54, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTFDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT4INPROT
rw 		FLT4INFC
rw 		FLT4INSRC
rw 		FLT4INP
rw 		FLT4INEN
rw
Toggle Fields.

FLT4INEN

Bit 0: Fault 4 input enable .

FLT4INP

Bit 1: Fault 4 input polarity.

FLT4INSRC

Bit 2: Fault 4 input source.

FLT4INFC

Bits 3-6: Fault 4 input filter control.

FLT4INPROT

Bit 7: Protect fault 4 input configuration .

FLTFDIV

Bits 24-25: Fault input digital filter clock division.

DMAUPMTR

SHRTIMER DMA update Master_TIMER register

Offset: 0x58, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTACTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MTCMP3V
rw 		MTCMP2V
rw 		MTCMP1V
rw 		MTCMP0V
rw 		MTCREP
rw 		MTCAR
rw 		MTCNT
rw 		MTDMAINTEN
rw 		MTINTC
rw 		MTCTL0
rw
Toggle Fields.

MTCTL0

Bit 0: SHRTIMER_MTCTL0 update by DMA mode .

MTINTC

Bit 1: SHRTIMER_MTINTC update by DMA mode .

MTDMAINTEN

Bit 2: SHRTIMER_MTDMAINTEN update by DMA mode .

MTCNT

Bit 3: SHRTIMER_MTCNT update by DMA mode .

MTCAR

Bit 4: SHRTIMER_MTCAR update by DMA mode .

MTCREP

Bit 5: SHRTIMER_MTCAR update by DMA mode .

MTCMP0V

Bit 6: SHRTIMER_MTCMP0V update by DMA mode.

MTCMP1V

Bit 7: SHRTIMER_MTCMP1V update by DMA mode.

MTCMP2V

Bit 8: SHRTIMER_MTCMP2V update by DMA mode.

MTCMP3V

Bit 9: SHRTIMER_MTCMP3V update by DMA mode .

MTACTL

Bit 31: SHRTIMER_MTACTL update by DMA mode.

DMAUPST0R

SHRTIMER DMA update Slave_TIMER0 register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ST0ACTL
rw 		ST0FLTCTL
rw 		ST0CHOCTL
rw 		ST0CSCTL
rw 		ST0CNTRST
rw 		ST0EXEVFCFG1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST0EXEVFCFG0
rw 		ST0CH1RST
rw 		ST0CH1SET
rw 		ST0CH0RST
rw 		ST0CH0SET
rw 		ST0DTCTL
rw 		ST0CMP3V
rw 		ST0CMP2V
rw 		ST0CMP1V
rw 		ST0CMP0V
rw 		ST0CREP
rw 		ST0CAR
rw 		ST0CNT
rw 		ST0DMAINTEN
rw 		ST0INTC
rw 		ST0CTL0
rw
Toggle Fields.

ST0CTL0

Bit 0: SHRTIMER_ST0CTL0 update by DMA mode.

ST0INTC

Bit 1: SHRTIMER_ST0INTC update by DMA mode .

ST0DMAINTEN

Bit 2: SHRTIMER_ST0DMAINTEN update by DMA mode .

ST0CNT

Bit 3: SHRTIMER_ST0CNT update by DMA mode .

ST0CAR

Bit 4: SHRTIMER_ST0CAR update by DMA mode.

ST0CREP

Bit 5: SHRTIMER_ST0CREP update by DMA mode .

ST0CMP0V

Bit 6: SHRTIMER_ST0CMP0V update by DMA mode.

ST0CMP1V

Bit 7: SHRTIMER_ST0CMP1V update by DMA mode.

ST0CMP2V

Bit 8: SHRTIMER_ST0CMP2V update by DMA mode.

ST0CMP3V

Bit 9: SHRTIMER_ST0CMP3V update by DMA mode.

ST0DTCTL

Bit 10: SHRTIMER_ST0DTCTL update by DMA mode .

ST0CH0SET

Bit 11: SHRTIMER_ST0CH0SET update by DMA mode .

ST0CH0RST

Bit 12: SHRTIMER_ST0CH0RST update by DMA mode .

ST0CH1SET

Bit 13: SHRTIMER_ST0CH1SET update by DMA mode .

ST0CH1RST

Bit 14: SHRTIMER_ST0CH1RST update by DMA mode .

ST0EXEVFCFG0

Bit 15: SHRTIMER_ST0EXEVFCFG0update by DMA mode .

ST0EXEVFCFG1

Bit 16: SHRTIMER_ST0EXEVFCFG1update by DMA mode .

ST0CNTRST

Bit 17: SHRTIMER_ST0CNTRST update by DMA mode.

ST0CSCTL

Bit 18: SHRTIMER_ST0CSCTL update by DMA mode.

ST0CHOCTL

Bit 19: SHRTIMER_ST0CHOCTL update by DMA mode.

ST0FLTCTL

Bit 20: SHRTIMER_ST0FLTCTL update by DMA mode .

ST0ACTL

Bit 31: SHRTIMER_ST0ACTL update by DMA mode.

DMAUPST1R

SHRTIMER DMA update Slave_TIMER1 register

Offset: 0x60, reset: 0x00000000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ST1ACTL
rw 		ST1FLTCTL
rw 		ST1CHOCTL
rw 		ST1CSCTL
rw 		ST1CNTRST
rw 		ST1EXEVFCFG1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST1EXEVFCFG0
rw 		ST1CH1RST
rw 		ST1CH1SET
rw 		ST1CH0RST
rw 		ST1CH0SET
rw 		ST1DTCTL
rw 		ST1CMP3V
rw 		ST1CMP2V
rw 		ST1CMP1V
rw 		ST1CMP0V
rw 		ST1CREP
rw 		ST1CAR
rw 		ST1CNT
rw 		ST1DMAINTEN
rw 		ST1INTC
rw 		ST1CTL0
rw
Toggle Fields.

ST1CTL0

Bit 0: SHRTIMER_ST1CTL0 update by DMA mode.

ST1INTC

Bit 1: SHRTIMER_ST1INTC update by DMA mode .

ST1DMAINTEN

Bit 2: SHRTIMER_ST1DMAINTEN update by DMA mode .

ST1CNT

Bit 3: SHRTIMER_ST1CNT update by DMA mode .

ST1CAR

Bit 4: SHRTIMER_ST1CAR update by DMA mode.

ST1CREP

Bit 5: SHRTIMER_ST1CREP update by DMA mode .

ST1CMP0V

Bit 6: SHRTIMER_ST1CMP0V update by DMA mode.

ST1CMP1V

Bit 7: SHRTIMER_ST1CMP1V update by DMA mode.

ST1CMP2V

Bit 8: SHRTIMER_ST1CMP2V update by DMA mode.

ST1CMP3V

Bit 9: SHRTIMER_ST1CMP3V update by DMA mode.

ST1DTCTL

Bit 10: SHRTIMER_ST1DTCTL update by DMA mode .

ST1CH0SET

Bit 11: SHRTIMER_ST1CH0SET update by DMA mode .

ST1CH0RST

Bit 12: SHRTIMER_ST1CH0RST update by DMA mode .

ST1CH1SET

Bit 13: SHRTIMER_ST1CH1SET update by DMA mode .

ST1CH1RST

Bit 14: SHRTIMER_ST1CH1RST update by DMA mode .

ST1EXEVFCFG0

Bit 15: SHRTIMER_ST1EXEVFCFG0update by DMA mode .

ST1EXEVFCFG1

Bit 16: SHRTIMER_ST1EXEVFCFG1update by DMA mode .

ST1CNTRST

Bit 17: SHRTIMER_ST1CNTRST update by DMA mode.

ST1CSCTL

Bit 18: SHRTIMER_ST1CSCTL update by DMA mode.

ST1CHOCTL

Bit 19: SHRTIMER_ST1CHOCTL update by DMA mode.

ST1FLTCTL

Bit 20: SHRTIMER_ST1FLTCTL update by DMA mode .

ST1ACTL

Bit 31: SHRTIMER_ST1ACTL update by DMA mode.

DMAUPST2R

SHRTIMER DMA update Slave_TIMER2 register

Offset: 0x64, reset: 0x00000000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ST2ACTL
rw 		ST2FLTCTL
rw 		ST2CHOCTL
rw 		ST2CSCTL
rw 		ST2CNTRST
rw 		ST2EXEVFCFG1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST2EXEVFCFG0
rw 		ST2CH1RST
rw 		ST2CH1SET
rw 		ST2CH0RST
rw 		ST2CH0SET
rw 		ST2DTCTL
rw 		ST2CMP3V
rw 		ST2CMP2V
rw 		ST2CMP1V
rw 		ST2CMP0V
rw 		ST2CREP
rw 		ST2CAR
rw 		ST2CNT
rw 		ST2DMAINTEN
rw 		ST2INTC
rw 		ST2CTL0
rw
Toggle Fields.

ST2CTL0

Bit 0: SHRTIMER_ST2CTL0 update by DMA mode.

ST2INTC

Bit 1: SHRTIMER_ST2INTC update by DMA mode .

ST2DMAINTEN

Bit 2: SHRTIMER_ST2DMAINTEN update by DMA mode .

ST2CNT

Bit 3: SHRTIMER_ST2CNT update by DMA mode .

ST2CAR

Bit 4: SHRTIMER_ST2CAR update by DMA mode.

ST2CREP

Bit 5: SHRTIMER_ST2CREP update by DMA mode .

ST2CMP0V

Bit 6: SHRTIMER_ST2CMP0V update by DMA mode.

ST2CMP1V

Bit 7: SHRTIMER_ST2CMP1V update by DMA mode.

ST2CMP2V

Bit 8: SHRTIMER_ST2CMP2V update by DMA mode.

ST2CMP3V

Bit 9: SHRTIMER_ST2CMP3V update by DMA mode.

ST2DTCTL

Bit 10: SHRTIMER_ST2DTCTL update by DMA mode .

ST2CH0SET

Bit 11: SHRTIMER_ST2CH0SET update by DMA mode .

ST2CH0RST

Bit 12: SHRTIMER_ST2CH0RST update by DMA mode .

ST2CH1SET

Bit 13: SHRTIMER_ST2CH1SET update by DMA mode .

ST2CH1RST

Bit 14: SHRTIMER_ST2CH1RST update by DMA mode .

ST2EXEVFCFG0

Bit 15: SHRTIMER_ST2EXEVFCFG0update by DMA mode .

ST2EXEVFCFG1

Bit 16: SHRTIMER_ST2EXEVFCFG1update by DMA mode .

ST2CNTRST

Bit 17: SHRTIMER_ST2CNTRST update by DMA mode.

ST2CSCTL

Bit 18: SHRTIMER_ST2CSCTL update by DMA mode.

ST2CHOCTL

Bit 19: SHRTIMER_ST2CHOCTL update by DMA mode.

ST2FLTCTL

Bit 20: SHRTIMER_ST2FLTCTL update by DMA mode .

ST2ACTL

Bit 31: SHRTIMER_ST2ACTL update by DMA mode.

DMAUPST3R

SHRTIMER DMA update Slave_TIMER3 register

Offset: 0x68, reset: 0x00000000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ST3ACTL
rw 		ST3FLTCTL
rw 		ST3CHOCTL
rw 		ST3CSCTL
rw 		ST3CNTRST
rw 		ST3EXEVFCFG1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST3EXEVFCFG0
rw 		ST3CH1RST
rw 		ST3CH1SET
rw 		ST3CH0RST
rw 		ST3CH0SET
rw 		ST3DTCTL
rw 		ST3CMP3V
rw 		ST3CMP2V
rw 		ST3CMP1V
rw 		ST3CMP0V
rw 		ST3CREP
rw 		ST3CAR
rw 		ST3CNT
rw 		ST3DMAINTEN
rw 		ST3INTC
rw 		ST3CTL0
rw
Toggle Fields.

ST3CTL0

Bit 0: SHRTIMER_ST3CTL0 update by DMA mode.

ST3INTC

Bit 1: SHRTIMER_ST3INTC update by DMA mode .

ST3DMAINTEN

Bit 2: SHRTIMER_ST3DMAINTEN update by DMA mode .

ST3CNT

Bit 3: SHRTIMER_ST3CNT update by DMA mode .

ST3CAR

Bit 4: SHRTIMER_ST3CAR update by DMA mode.

ST3CREP

Bit 5: SHRTIMER_ST3CREP update by DMA mode .

ST3CMP0V

Bit 6: SHRTIMER_ST3CMP0V update by DMA mode.

ST3CMP1V

Bit 7: SHRTIMER_ST3CMP1V update by DMA mode.

ST3CMP2V

Bit 8: SHRTIMER_ST3CMP2V update by DMA mode.

ST3CMP3V

Bit 9: SHRTIMER_ST3CMP3V update by DMA mode.

ST3DTCTL

Bit 10: SHRTIMER_ST3DTCTL update by DMA mode .

ST3CH0SET

Bit 11: SHRTIMER_ST3CH0SET update by DMA mode .

ST3CH0RST

Bit 12: SHRTIMER_ST3CH0RST update by DMA mode .

ST3CH1SET

Bit 13: SHRTIMER_ST3CH1SET update by DMA mode .

ST3CH1RST

Bit 14: SHRTIMER_ST3CH1RST update by DMA mode .

ST3EXEVFCFG0

Bit 15: SHRTIMER_ST3EXEVFCFG0update by DMA mode .

ST3EXEVFCFG1

Bit 16: SHRTIMER_ST3EXEVFCFG1update by DMA mode .

ST3CNTRST

Bit 17: SHRTIMER_ST3CNTRST update by DMA mode.

ST3CSCTL

Bit 18: SHRTIMER_ST3CSCTL update by DMA mode.

ST3CHOCTL

Bit 19: SHRTIMER_ST3CHOCTL update by DMA mode.

ST3FLTCTL

Bit 20: SHRTIMER_ST3FLTCTL update by DMA mode .

ST3ACTL

Bit 31: SHRTIMER_ST3ACTL update by DMA mode.

DMAUPST4R

SHRTIMER DMA update Slave_TIMER4 register

Offset: 0x6C, reset: 0x00000000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ST4ACTL
rw 		ST4FLTCTL
rw 		ST4CHOCTL
rw 		ST4CSCTL
rw 		ST4CNTRST
rw 		ST4EXEVFCFG1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST4EXEVFCFG0
rw 		ST4CH1RST
rw 		ST4CH1SET
rw 		ST4CH0RST
rw 		ST4CH0SET
rw 		ST4DTCTL
rw 		ST4CMP3V
rw 		ST4CMP2V
rw 		ST4CMP1V
rw 		ST4CMP0V
rw 		ST4CREP
rw 		ST4CAR
rw 		ST4CNT
rw 		ST4DMAINTEN
rw 		ST4INTC
rw 		ST4CTL0
rw
Toggle Fields.

ST4CTL0

Bit 0: SHRTIMER_ST4CTL0 update by DMA mode.

ST4INTC

Bit 1: SHRTIMER_ST4INTC update by DMA mode .

ST4DMAINTEN

Bit 2: SHRTIMER_ST4DMAINTEN update by DMA mode .

ST4CNT

Bit 3: SHRTIMER_ST4CNT update by DMA mode .

ST4CAR

Bit 4: SHRTIMER_ST4CAR update by DMA mode.

ST4CREP

Bit 5: SHRTIMER_ST4CREP update by DMA mode .

ST4CMP0V

Bit 6: SHRTIMER_ST4CMP0V update by DMA mode.

ST4CMP1V

Bit 7: SHRTIMER_ST4CMP1V update by DMA mode.

ST4CMP2V

Bit 8: SHRTIMER_ST4CMP2V update by DMA mode.

ST4CMP3V

Bit 9: SHRTIMER_ST4CMP3V update by DMA mode.

ST4DTCTL

Bit 10: SHRTIMER_ST4DTCTL update by DMA mode .

ST4CH0SET

Bit 11: SHRTIMER_ST4CH0SET update by DMA mode .

ST4CH0RST

Bit 12: SHRTIMER_ST4CH0RST update by DMA mode .

ST4CH1SET

Bit 13: SHRTIMER_ST4CH1SET update by DMA mode .

ST4CH1RST

Bit 14: SHRTIMER_ST4CH1RST update by DMA mode .

ST4EXEVFCFG0

Bit 15: SHRTIMER_ST4EXEVFCFG0update by DMA mode .

ST4EXEVFCFG1

Bit 16: SHRTIMER_ST4EXEVFCFG1update by DMA mode .

ST4CNTRST

Bit 17: SHRTIMER_ST4CNTRST update by DMA mode.

ST4CSCTL

Bit 18: SHRTIMER_ST4CSCTL update by DMA mode.

ST4CHOCTL

Bit 19: SHRTIMER_ST4CHOCTL update by DMA mode.

ST4FLTCTL

Bit 20: SHRTIMER_ST4FLTCTL update by DMA mode .

ST4ACTL

Bit 31: SHRTIMER_ST4ACTL update by DMA mode.

DMATB

SHRTIMER DMA transfer buffer register

Offset: 0x70, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMATB
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
w
Toggle Fields.

DMATB

Bits 0-31: DMA transfer buffer.

SLAVE_TIMER0

0x40017480: SHRTIMER Slave TIMER0 registers(

18/336 fields covered. Toggle Registers.

ST0CTL0

SHRTIMER Slave_TIMER0 control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPSEL
rw 		SHWEN
rw 		DACTRGS
rw 		UPBMT
rw 		UPBST4
rw 		UPBST3
rw 		UPBST2
rw 		UPBST1
rw 		UPRST
rw 		UPREP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DELCMP3M
rw 		DELCMP1M
rw 		SYNISTRT
rw 		SYNIRST
rw 		BLNMEN
rw 		HALFM
rw 		CNTRSTM
rw 		CTNM
rw 		CNTCKDIV
rw
Toggle Fields.

CNTCKDIV

Bits 0-2: Counter clock division.

CTNM

Bit 3: Continuous mode.

CNTRSTM

Bit 4: Counter reset mode.

HALFM

Bit 5: Half mode.

BLNMEN

Bit 6: Balanced mode enable.

SYNIRST

Bit 10: Synchronization input reset counter.

SYNISTRT

Bit 11: Synchronization input start counter.

DELCMP1M

Bits 12-13: Compare 1 delayed mode.

DELCMP3M

Bits 14-15: Compare 3 delayed mode.

UPREP

Bit 17: Update event generated by repetition event.

UPRST

Bit 18: Update event generated by reset event.

UPBST1

Bit 20: Update by Slave_TIMER1 update event.

UPBST2

Bit 21: Update by Slave_TIMER2 update event.

UPBST3

Bit 22: Update by Slave_TIMER3 update event.

UPBST4

Bit 23: Update by Slave_TIMER4 update event.

UPBMT

Bit 24: Update by Master_TIMER update event.

DACTRGS

Bits 25-26: Trigger source to DAC.

SHWEN

Bit 27: Shadow registers enable.

UPSEL

Bits 28-31: Update event selection.

ST0INTF

SHRTIMER Slave_TIMER0 interrupt flag register

Offset: 0x4, reset: 0x00000000, access: read-only

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1F
r 		CH0F
r 		BLNIF
r 		CBLNF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYIIF
r 		RSTIF
r 		CH1ONAIF
r 		CH1OAIF
r 		CH0ONAIF
r 		CH0OAIF
r 		CAP1IF
r 		CAP0IF
r 		UPIF
r 		REPIF
r 		CMP3IF
r 		CMP2IF
r 		CMP1IF
r 		CMP0IF
r
Toggle Fields.

CMP0IF

Bit 0: Compare 0 interrupt flag.

CMP1IF

Bit 1: Compare 1 interrupt flag.

CMP2IF

Bit 2: Compare 2 interrupt flag.

CMP3IF

Bit 3: Compare 3 interrupt flag.

REPIF

Bit 4: Repetition interrupt flag.

UPIF

Bit 6: Update interrupt flag.

CAP0IF

Bit 7: Capture 0 interrupt flag.

CAP1IF

Bit 8: Capture 1 interrupt flag.

CH0OAIF

Bit 9: Channel 0 output active interrupt flag.

CH0ONAIF

Bit 10: Channel 0 output inactive interrupt flag.

CH1OAIF

Bit 11: Channel 1 output active interrupt flag.

CH1ONAIF

Bit 12: Channel 1 output inactive interrupt flag.

RSTIF

Bit 13: Counter reset interrupt flag.

DLYIIF

Bit 14: Delayed IDLE mode entry interrupt flag.

CBLNF

Bit 16: Current balanced flag.

BLNIF

Bit 17: Balanced IDLE flag.

CH0F

Bit 20: Channel 0 output flag.

CH1F

Bit 21: Channel 1 output flag.

ST0INTC

SHRTIMER Slave_TIMER0 interrupt flag clear register

Offset: 0x8, reset: 0x00000000, access: write-only

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYIIFC
w 		RSTIFC
w 		CH1ONAIFC
w 		CH1OAIFC
w 		CH0ONAIFC
w 		CH0OAIFC
w 		CAP1IFC
w 		CAP0IFC
w 		UPIFC
w 		REPIFC
w 		CMP3IFC
w 		CMP2IFC
w 		CMP1IFC
w 		CMP0IFC
w
Toggle Fields.

CMP0IFC

Bit 0: Clear compare 0 interrupt flag.

CMP1IFC

Bit 1: Clear compare 1 interrupt flag.

CMP2IFC

Bit 2: Clear compare 2 interrupt flag.

CMP3IFC

Bit 3: Clear compare 3 interrupt flag.

REPIFC

Bit 4: Clear repetition interrupt flag.

UPIFC

Bit 6: Clear update interrupt flag.

CAP0IFC

Bit 7: Clear capture 0 interrupt flag.

CAP1IFC

Bit 8: Clear capture 1 interrupt flag.

CH0OAIFC

Bit 9: Clear channel 0 output active interrupt flag.

CH0ONAIFC

Bit 10: Clear channel 0 output inactive interrupt flag.

CH1OAIFC

Bit 11: Clear channel 1 output active interrupt flag.

CH1ONAIFC

Bit 12: Clear channel 1 output inactive interrupt flag.

RSTIFC

Bit 13: Clear counter reset interrupt flag.

DLYIIFC

Bit 14: Clear delayed IDLE mode entry interrupt flag.

ST0DMAINTEN

SHRTIMER Slave_TIMER0 DMA and interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYIDEN
rw 		RSTDEN
rw 		CH1ONADEN
rw 		CH1OADEN
rw 		CH0ONADEN
rw 		CH0ADEN
rw 		CAP1DEN
rw 		CAP0DEN
rw 		UPDEN
rw 		REPDEN
rw 		CMP3DEN
rw 		CMP2DEN
rw 		CMP1DEN
rw 		CMP0DEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYIIE
rw 		RSTIE
rw 		CH1ONAIE
rw 		CH1OAIE
rw 		CH0ONAIE
rw 		CH0OAIE
rw 		CAP1IE
rw 		CAP0IE
rw 		UPIE
rw 		REPIE
rw 		CMP3IE
rw 		CMP2IE
rw 		CMP1IE
rw 		CMP0IE
rw
Toggle Fields.

CMP0IE

Bit 0: Compare 0 interrupt enable.

CMP1IE

Bit 1: Compare 1 interrupt enable.

CMP2IE

Bit 2: Compare 2 interrupt enable.

CMP3IE

Bit 3: Compare 3 interrupt enable.

REPIE

Bit 4: Repetition interrupt enable.

UPIE

Bit 6: Update interrupt enable.

CAP0IE

Bit 7: Capture 0 interrupt enable.

CAP1IE

Bit 8: Capture 1 interrupt enable.

CH0OAIE

Bit 9: Channel 0 output active interrupt enable.

CH0ONAIE

Bit 10: Channel 0 output inactive interrupt enable.

CH1OAIE

Bit 11: Channel 1 output active interrupt enable.

CH1ONAIE

Bit 12: Channel 1 output inactive interrupt enable.

RSTIE

Bit 13: Counter reset interrupt enable.

DLYIIE

Bit 14: Delayed IDLE mode entry interrupt enable.

CMP0DEN

Bit 16: Compare 0 DMA request enable.

CMP1DEN

Bit 17: Compare 1 DMA request enable.

CMP2DEN

Bit 18: Compare 2 DMA request enable.

CMP3DEN

Bit 19: Compare 3 DMA request enable.

REPDEN

Bit 20: Repetition DMA request enable.

UPDEN

Bit 22: Update DMA request enable.

CAP0DEN

Bit 23: Capture 0 DMA request enable.

CAP1DEN

Bit 24: Capture 1 DMA request enable.

CH0ADEN

Bit 25: Channel 0 output active DMA request enable.

CH0ONADEN

Bit 26: Channel 0 output inactive DMA request enable.

CH1OADEN

Bit 27: Channel 1 output active DMA request enable.

CH1ONADEN

Bit 28: Channel 1 output inactive DMA request enable.

RSTDEN

Bit 29: Counter reset DMA request enable.

DLYIDEN

Bit 30: Delayed IDLE mode entry DMA request enable.

ST0CNT

SHRTIMER Slave_TIMER0 counter register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: The current counter value.

ST0CAR

SHRTIMER Slave_TIMER0 counter auto reload register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARL
rw
Toggle Fields.

CARL

Bits 0-15: Counter auto reload value.

ST0CREP

SHRTIMER Slave_TIMER0 counter repetition register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CREP
rw
Toggle Fields.

CREP

Bits 0-7: Counter repetition value.

ST0CMP0V

SHRTIMER Slave_TIMER0 compare 0 value register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP0VAL
rw
Toggle Fields.

CMP0VAL

Bits 0-15: Compare 0 value.

ST0CMP0CP

SHRTIMER Slave_TIMER0 compare 0 composite register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CREP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP0VAL
rw
Toggle Fields.

CMP0VAL

Bits 0-15: Compare 0 value.

CREP

Bits 16-23: Counter repetition value.

ST0CMP1V

SHRTIMER Slave_TIMER0 compare 1 value register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP1VAL
rw
Toggle Fields.

CMP1VAL

Bits 0-15: Compare 1 value.

ST0CMP2V

SHRTIMER Slave_TIMER0 compare 2 value register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP2VAL
rw
Toggle Fields.

CMP2VAL

Bits 0-15: Compare 2 value.

ST0CMP3V

SHRTIMER Slave_TIMER0 compare 3 value register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP3VAL
rw
Toggle Fields.

CMP3VAL

Bits 0-15: Compare 3 value.

ST0CAP0V

SHRTIMER Slave_TIMER0 capture 0 value register

Offset: 0x30, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAP0VAL
rw
Toggle Fields.

CAP0VAL

Bits 0-15: Capture 0 value.

ST0CAP1V

SHRTIMER Slave_TIMER0 capture 1 value register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAP1VAL
rw
Toggle Fields.

CAP1VAL

Bits 0-15: Capture 1 value.

ST0DTCTL

SHRTIMER Slave_TIMER0 dead-time control register

Offset: 0x38, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFSVPROT
rw 		DTFSPROT
rw 		DTFS
rw 		DTFCFG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTRSVPROT
rw 		DTRSPROT
rw 		DTGCKDIV
rw 		DTRS
rw 		DTRCFG
rw
Toggle Fields.

DTRCFG

Bits 0-8: Falling edge dead-time value.

DTRS

Bit 9: The sign of falling edge dead-time value.

DTGCKDIV

Bits 10-13: Dead time generator clock division.

DTRSPROT

Bit 14: Dead-time rising edge protection for sign.

DTRSVPROT

Bit 15: Dead-time rising edge protection for value and sign.

DTFCFG

Bits 16-24: Falling edge dead-time value.

DTFS

Bit 25: The sign of falling edge dead-time value.

DTFSPROT

Bit 30: Dead-time falling edge protection for sign.

DTFSVPROT

Bit 31: Dead-time falling edge protection for value and sign.

ST0CH0SET

SHRTIMER Slave_TIMERx channel 0 set request register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH0SUP
rw 		CH0SEXEV9
rw 		CH0SEXEV8
rw 		CH0SEXEV7
rw 		CH0SEXEV6
rw 		CH0SEXEV5
rw 		CH0SEXEV4
rw 		CH0SEXEV3
rw 		CH0SEXEV2
rw 		CH0SEXEV1
rw 		CH0SEXEV0
rw 		CH0SSTEV8
rw 		CH0SSTEV7
rw 		CH0SSTEV6
rw 		CH0SSTEV5
rw 		CH0SSTEV4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0SSTEV3
rw 		CH0SSTEV2
rw 		CH0SSTEV1
rw 		CH0SSTEV0
rw 		CH0SMTCMP3
rw 		CH0SMTCMP2
rw 		CH0SMTCMP1
rw 		CH0SMTCMP0
rw 		CH0SMTPER
rw 		CH0SCMP3
rw 		CH0SCMP2
rw 		CH0SCMP1
rw 		CH0SCMP0
rw 		CH0SPER
rw 		CH0SRST
rw 		CH0SSEV
rw
Toggle Fields.

CH0SSEV

Bit 0: Software event generates channel 0 .

CH0SRST

Bit 1: Slave_TIMER0 reset event generates channel 0 .

CH0SPER

Bit 2: Slave_TIMER0 period event generates channel 0 .

CH0SCMP0

Bit 3: Slave_TIMER0 compare 0 event generates channel 0 .

CH0SCMP1

Bit 4: Slave_TIMER0 compare 1 event generates channel 0 .

CH0SCMP2

Bit 5: Slave_TIMER0 compare 2 event generates channel 0 .

CH0SCMP3

Bit 6: Slave_TIMER0 compare 3 event generates channel 0 .

CH0SMTPER

Bit 7: Master_TIMER period event generates channel 0 .

CH0SMTCMP0

Bit 8: Master_TIMER compare 0 event generates channel 0 .

CH0SMTCMP1

Bit 9: Master_TIMER compare 1 event generates channel 0 .

CH0SMTCMP2

Bit 10: Master_TIMER compare 2 event generates channel 0 .

CH0SMTCMP3

Bit 11: Master_TIMER compare 3 event generates channel 0 .

CH0SSTEV0

Bit 12: Slave_TIMER0 interconnection event 0 generates channel 0 .

CH0SSTEV1

Bit 13: Slave_TIMER0 interconnection event 1 generates channel 0 .

CH0SSTEV2

Bit 14: Slave_TIMER0 interconnection event 2 generates channel 0 .

CH0SSTEV3

Bit 15: Slave_TIMER0 interconnection event 3 generates channel 0 .

CH0SSTEV4

Bit 16: Slave_TIMER0 interconnection event 4 generates channel 0 .

CH0SSTEV5

Bit 17: Slave_TIMER0 interconnection event 5 generates channel 0 .

CH0SSTEV6

Bit 18: Slave_TIMER0 interconnection event 6 generates channel 0 .

CH0SSTEV7

Bit 19: Slave_TIMER0 interconnection event 7 generates channel 0 .

CH0SSTEV8

Bit 20: Slave_TIMER0 interconnection event 8 generates channel 0 .

CH0SEXEV0

Bit 21: External event 0 generates channel 0 .

CH0SEXEV1

Bit 22: External event 1 generates channel 0 .

CH0SEXEV2

Bit 23: External event 2 generates channel 0 .

CH0SEXEV3

Bit 24: External event 3 generates channel 0 .

CH0SEXEV4

Bit 25: External event 4 generates channel 0 .

CH0SEXEV5

Bit 26: External event 5 generates channel 0 .

CH0SEXEV6

Bit 27: External event 6 generates channel 0 .

CH0SEXEV7

Bit 28: External event 7 generates channel 0 .

CH0SEXEV8

Bit 29: External event 8 generates channel 0 .

CH0SEXEV9

Bit 30: External event 9 generates channel 0 .

CH0SUP

Bit 31: Update event generates channel 0 .

ST0CH0RST

SHRTIMER Slave_TIMER0 channel 0 reset request register

Offset: 0x40, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH0RSUP
rw 		CH0RSEXEV9
rw 		CH0RSEXEV8
rw 		CH0RSEXEV7
rw 		CH0RSEXEV6
rw 		CH0RSEXEV5
rw 		CH0RSEXEV4
rw 		CH0RSEXEV3
rw 		CH0RSEXEV2
rw 		CH0RSEXEV1
rw 		CH0RSEXEV0
rw 		CH0RSSTEV8
rw 		CH0RSSTEV7
rw 		CH0RSSTEV6
rw 		CH0RSSTEV5
rw 		CH0RSSTEV4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0RSSTEV3
rw 		CH0RSSTEV2
rw 		CH0RSSTEV1
rw 		CH0RSSTEV0
rw 		CH0RSMTCMP3
rw 		CH0RSMTCMP2
rw 		CH0RSMTCMP1
rw 		CH0RSMTCMP0
rw 		CH0RSMTPER
rw 		CH0RSCMP3
rw 		CH0RSCMP2
rw 		CH0RSCMP1
rw 		CH0RSCMP0
rw 		CH0RSPER
rw 		CH0RSRST
rw 		CH0RSSEV
rw
Toggle Fields.

CH0RSSEV

Bit 0: Software event generates channel 0 .

CH0RSRST

Bit 1: Slave_TIMER0 reset event generates channel 0 .

CH0RSPER

Bit 2: Slave_TIMER0 period event generates channel 0 .

CH0RSCMP0

Bit 3: Slave_TIMER0 compare 0 event generates channel 0 .

CH0RSCMP1

Bit 4: Slave_TIMER0 compare 1 event generates channel 0 .

CH0RSCMP2

Bit 5: Slave_TIMER0 compare 2 event generates channel 0 .

CH0RSCMP3

Bit 6: Slave_TIMER0 compare 3 event generates channel 0 .

CH0RSMTPER

Bit 7: Master_TIMER period event generates channel 0 .

CH0RSMTCMP0

Bit 8: Master_TIMER compare 0 event generates channel 0 .

CH0RSMTCMP1

Bit 9: Master_TIMER compare 1 event generates channel 0 .

CH0RSMTCMP2

Bit 10: Master_TIMER compare 2 event generates channel 0 .

CH0RSMTCMP3

Bit 11: Master_TIMER compare 3 event generates channel 0 .

CH0RSSTEV0

Bit 12: Slave_TIMER0 interconnection event 0 generates channel 0 .

CH0RSSTEV1

Bit 13: Slave_TIMER0 interconnection event 1 generates channel 0 .

CH0RSSTEV2

Bit 14: Slave_TIMER0 interconnection event 2 generates channel 0 .

CH0RSSTEV3

Bit 15: Slave_TIMER0 interconnection event 3 generates channel 0 .

CH0RSSTEV4

Bit 16: Slave_TIMER0 interconnection event 4 generates channel 0 .

CH0RSSTEV5

Bit 17: Slave_TIMER0 interconnection event 5 generates channel 0 .

CH0RSSTEV6

Bit 18: Slave_TIMER0 interconnection event 6 generates channel 0 .

CH0RSSTEV7

Bit 19: Slave_TIMER0 interconnection event 7 generates channel 0 .

CH0RSSTEV8

Bit 20: Slave_TIMER0 interconnection event 8 generates channel 0 .

CH0RSEXEV0

Bit 21: External event 0 generates channel 0 .

CH0RSEXEV1

Bit 22: External event 1 generates channel 0 .

CH0RSEXEV2

Bit 23: External event 2 generates channel 0 .

CH0RSEXEV3

Bit 24: External event 3 generates channel 0 .

CH0RSEXEV4

Bit 25: External event 4 generates channel 0 .

CH0RSEXEV5

Bit 26: External event 5 generates channel 0 .

CH0RSEXEV6

Bit 27: External event 6 generates channel 0 .

CH0RSEXEV7

Bit 28: External event 7 generates channel 0 .

CH0RSEXEV8

Bit 29: External event 8 generates channel 0 .

CH0RSEXEV9

Bit 30: External event 9 generates channel 0 .

CH0RSUP

Bit 31: Update event generates channel 0 .

ST0CH1SET

SHRTIMER Slave_TIMER0 channel 1 set request register

Offset: 0x44, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1SUP
rw 		CH1SEXEV9
rw 		CH1SEXEV8
rw 		CH1SEXEV7
rw 		CH1SEXEV6
rw 		CH1SEXEV5
rw 		CH1SEXEV4
rw 		CH1SEXEV3
rw 		CH1SEXEV2
rw 		CH1SEXEV1
rw 		CH1SEXEV0
rw 		CH1SSTEV8
rw 		CH1SSTEV7
rw 		CH1SSTEV6
rw 		CH1SSTEV5
rw 		CH1SSTEV4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1SSTEV3
rw 		CH1SSTEV2
rw 		CH1SSTEV1
rw 		CH1SSTEV0
rw 		CH1SMTCMP3
rw 		CH1SMTCMP2
rw 		CH1SMTCMP1
rw 		CH1SMTCMP0
rw 		CH1SMTPER
rw 		CH1SCMP3
rw 		CH1SCMP2
rw 		CH1SCMP1
rw 		CH1SCMP0
rw 		CH1SPER
rw 		CH1SRST
rw 		CH1SSEV
rw
Toggle Fields.

CH1SSEV

Bit 0: Software event generates channel 1 .

CH1SRST

Bit 1: Slave_TIMER0 reset event generates channel 1 .

CH1SPER

Bit 2: Slave_TIMER0 period event generates channel 1 .

CH1SCMP0

Bit 3: Slave_TIMER0 compare 0 event generates channel 1 .

CH1SCMP1

Bit 4: Slave_TIMER0 compare 1 event generates channel 1 .

CH1SCMP2

Bit 5: Slave_TIMER0 compare 2 event generates channel 1 .

CH1SCMP3

Bit 6: Slave_TIMER0 compare 3 event generates channel 1 .

CH1SMTPER

Bit 7: Master_TIMER period event generates channel 1 .

CH1SMTCMP0

Bit 8: Master_TIMER compare 0 event generates channel 1 .

CH1SMTCMP1

Bit 9: Master_TIMER compare 1 event generates channel 1 .

CH1SMTCMP2

Bit 10: Master_TIMER compare 2 event generates channel 1 .

CH1SMTCMP3

Bit 11: Master_TIMER compare 3 event generates channel 1 .

CH1SSTEV0

Bit 12: Slave_TIMER0 interconnection event 0 generates channel 1 .

CH1SSTEV1

Bit 13: Slave_TIMER0 interconnection event 1 generates channel 1 .

CH1SSTEV2

Bit 14: Slave_TIMER0 interconnection event 2 generates channel 1 .

CH1SSTEV3

Bit 15: Slave_TIMER0 interconnection event 3 generates channel 1 .

CH1SSTEV4

Bit 16: Slave_TIMER0 interconnection event 4 generates channel 1 .

CH1SSTEV5

Bit 17: Slave_TIMER0 interconnection event 5 generates channel 1 .

CH1SSTEV6

Bit 18: Slave_TIMER0 interconnection event 6 generates channel 1 .

CH1SSTEV7

Bit 19: Slave_TIMER0 interconnection event 7 generates channel 1 .

CH1SSTEV8

Bit 20: Slave_TIMER0 interconnection event 8 generates channel 1 .

CH1SEXEV0

Bit 21: External event 0 generates channel 1 .

CH1SEXEV1

Bit 22: External event 1 generates channel 1 .

CH1SEXEV2

Bit 23: External event 2 generates channel 1 .

CH1SEXEV3

Bit 24: External event 3 generates channel 1 .

CH1SEXEV4

Bit 25: External event 4 generates channel 1 .

CH1SEXEV5

Bit 26: External event 5 generates channel 1 .

CH1SEXEV6

Bit 27: External event 6 generates channel 1 .

CH1SEXEV7

Bit 28: External event 7 generates channel 1 .

CH1SEXEV8

Bit 29: External event 8 generates channel 1 .

CH1SEXEV9

Bit 30: External event 9 generates channel 1 .

CH1SUP

Bit 31: Update event generates channel 1 .

ST0CH1RST

SHRTIMER Slave_TIMER0 channel 1 reset request register

Offset: 0x48, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1RSUP
rw 		CH1RSEXEV9
rw 		CH1RSEXEV8
rw 		CH1RSEXEV7
rw 		CH1RSEXEV6
rw 		CH1RSEXEV5
rw 		CH1RSEXEV4
rw 		CH1RSEXEV3
rw 		CH1RSEXEV2
rw 		CH1RSEXEV1
rw 		CH1RSEXEV0
rw 		CH1RSSTEV8
rw 		CH1RSSTEV7
rw 		CH1RSSTEV6
rw 		CH1RSSTEV5
rw 		CH1RSSTEV4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1RSSTEV3
rw 		CH1RSSTEV2
rw 		CH1RSSTEV1
rw 		CH1RSSTEV0
rw 		CH1RSMTCMP3
rw 		CH1RSMTCMP2
rw 		CH1RSMTCMP1
rw 		CH1RSMTCMP0
rw 		CH1RSMTPER
rw 		CH1RSCMP3
rw 		CH1RSCMP2
rw 		CH1RSCMP1
rw 		CH1RSCMP0
rw 		CH1RSPER
rw 		CH1RSRST
rw 		CH1RSSEV
rw
Toggle Fields.

CH1RSSEV

Bit 0: Software event generates channel 1 .

CH1RSRST

Bit 1: Slave_TIMER0 reset event generates channel 1 .

CH1RSPER

Bit 2: Slave_TIMER0 period event generates channel 1 .

CH1RSCMP0

Bit 3: Slave_TIMER0 compare 0 event generates channel 1 .

CH1RSCMP1

Bit 4: Slave_TIMER0 compare 1 event generates channel 1 .

CH1RSCMP2

Bit 5: Slave_TIMER0 compare 2 event generates channel 1 .

CH1RSCMP3

Bit 6: Slave_TIMER0 compare 3 event generates channel 1 .

CH1RSMTPER

Bit 7: Master_TIMER period event generates channel 1 .

CH1RSMTCMP0

Bit 8: Master_TIMER compare 0 event generates channel 1 .

CH1RSMTCMP1

Bit 9: Master_TIMER compare 1 event generates channel 1 .

CH1RSMTCMP2

Bit 10: Master_TIMER compare 2 event generates channel 1 .

CH1RSMTCMP3

Bit 11: Master_TIMER compare 3 event generates channel 1 .

CH1RSSTEV0

Bit 12: Slave_TIMER0 interconnection event 0 generates channel 1 .

CH1RSSTEV1

Bit 13: Slave_TIMER0 interconnection event 1 generates channel 1 .

CH1RSSTEV2

Bit 14: Slave_TIMER0 interconnection event 2 generates channel 1 .

CH1RSSTEV3

Bit 15: Slave_TIMER0 interconnection event 3 generates channel 1 .

CH1RSSTEV4

Bit 16: Slave_TIMER0 interconnection event 4 generates channel 1 .

CH1RSSTEV5

Bit 17: Slave_TIMER0 interconnection event 5 generates channel 1 .

CH1RSSTEV6

Bit 18: Slave_TIMER0 interconnection event 6 generates channel 1 .

CH1RSSTEV7

Bit 19: Slave_TIMER0 interconnection event 7 generates channel 1 .

CH1RSSTEV8

Bit 20: Slave_TIMER0 interconnection event 8 generates channel 1 .

CH1RSEXEV0

Bit 21: External event 0 generates channel 1 .

CH1RSEXEV1

Bit 22: External event 1 generates channel 1 .

CH1RSEXEV2

Bit 23: External event 2 generates channel 1 .

CH1RSEXEV3

Bit 24: External event 3 generates channel 1 .

CH1RSEXEV4

Bit 25: External event 4 generates channel 1 .

CH1RSEXEV5

Bit 26: External event 5 generates channel 1 .

CH1RSEXEV6

Bit 27: External event 6 generates channel 1 .

CH1RSEXEV7

Bit 28: External event 7 generates channel 1 .

CH1RSEXEV8

Bit 29: External event 8 generates channel 1 .

CH1RSEXEV9

Bit 30: External event 9 generates channel 1 .

CH1RSUP

Bit 31: Update event generates channel 1 .

ST0EXEVFCFG0

SHRTIMER Slave_TIMERx external event filter configuration register 0

Offset: 0x4C, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXEV4FM
rw 		EXEV4MEEN
rw 		EXEV3FM
rw 		EXEV3MEEN
rw 		EXEV2FM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXEV2FM
rw 		EXEV2MEEN
rw 		EXEV1FM
rw 		EXEV1MEEN
rw 		EXEV0FM
rw 		EXEV0MEEN
rw
Toggle Fields.

EXEV0MEEN

Bit 0: External event 0 memorized enable.

EXEV0FM

Bits 1-4: External event 0 filter mode.

EXEV1MEEN

Bit 6: External event 1 memorized enable.

EXEV1FM

Bits 7-10: External event 1 filter mode.

EXEV2MEEN

Bit 12: External event 2 memorized enable.

EXEV2FM

Bits 13-16: External event 2 filter mode.

EXEV3MEEN

Bit 18: External event 3 memorized enable.

EXEV3FM

Bits 19-22: External event 3 filter mode.

EXEV4MEEN

Bit 24: External event 4 memorized enable.

EXEV4FM

Bits 25-28: External event 4 filter mode.

ST0EXEVFCFG1

SHRTIMER Slave_TIMERx external event filter configuration register 1

Offset: 0x50, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXEV9FM
rw 		EXEV9MEEN
rw 		EXEV8FM
rw 		EXEV8MEEN
rw 		EXEV7FM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXEV7FM
rw 		EXEV7MEEN
rw 		EXEV6FM
rw 		EXEV6MEEN
rw 		EXEV5FM
rw 		EXEV5MEEN
rw
Toggle Fields.

EXEV5MEEN

Bit 0: External event 5 memorized enable.

EXEV5FM

Bits 1-4: External event 5 filter mode.

EXEV6MEEN

Bit 6: External event 6 memorized enable.

EXEV6FM

Bits 7-10: External event 6 filter mode.

EXEV7MEEN

Bit 12: External event 7 memorized enable.

EXEV7FM

Bits 13-16: External event 7 filter mode.

EXEV8MEEN

Bit 18: External event 8 memorized enable.

EXEV8FM

Bits 19-22: External event 8 filter mode.

EXEV9MEEN

Bit 24: External event 9 memorized enable.

EXEV9FM

Bits 25-28: External event 9 filter mode.

ST0CNTRST

SHRTIMER Slave_TIMER0 counter reset register

Offset: 0x54, reset: 0x00000000, access: read-write

0/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ST4CMP3RST
rw 		ST4CMP1RST
rw 		ST4CMP0RST
rw 		ST3CMP3RST
rw 		ST3CMP1RST
rw 		ST3CMP0RST
rw 		ST2CMP3RST
rw 		ST2CMP1RST
rw 		ST2CMP0RST
rw 		ST1CMP3RST
rw 		ST1CMP1RST
rw 		ST1CMP0RST
rw 		EXEV9RST
rw 		EXEV8RST
rw 		EXEV7RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXEV6RST
rw 		EXEV5RST
rw 		EXEV4RST
rw 		EXEV3RST
rw 		EXEV2RST
rw 		EXEV1RST
rw 		EXEV0RST
rw 		MTCMP3RST
rw 		MTCMP2RST
rw 		MTCMP1RST
rw 		MTCMP0RST
rw 		MTPERRST
rw 		CMP3RST
rw 		CMP1RST
rw 		UPRST
rw
Toggle Fields.

UPRST

Bit 1: Slave_TIMER0 update event resets counter.

CMP1RST

Bit 2: Slave_TIMER0 compare 1 event resets counter.

CMP3RST

Bit 3: Slave_TIMER0 compare 3 event resets counter.

MTPERRST

Bit 4: Master_TIMER period event resets counter.

MTCMP0RST

Bit 5: Master_TIMER compare 0 event resets counter.

MTCMP1RST

Bit 6: Master_TIMER compare 1 event resets counter.

MTCMP2RST

Bit 7: Master_TIMER compare 2 event resets counter.

MTCMP3RST

Bit 8: Master_TIMER compare 3 event resets counter.

EXEV0RST

Bit 9: External event 0 resets counter.

EXEV1RST

Bit 10: External event 1 resets counter.

EXEV2RST

Bit 11: External event 2 resets counter.

EXEV3RST

Bit 12: External event 3 resets counter.

EXEV4RST

Bit 13: External event 4 resets counter.

EXEV5RST

Bit 14: External event 5 resets counter.

EXEV6RST

Bit 15: External event 6 resets counter.

EXEV7RST

Bit 16: External event 7 resets counter.

EXEV8RST

Bit 17: External event 8 resets counter.

EXEV9RST

Bit 18: External event 9 resets counter.

ST1CMP0RST

Bit 19: Slave_TIMER1 compare 0 event resets counter.

ST1CMP1RST

Bit 20: Slave_TIMER1 compare 1 event resets counter.

ST1CMP3RST

Bit 21: Slave_TIMER1 compare 3 event resets counter.

ST2CMP0RST

Bit 22: Slave_TIMER2 compare 0 event resets counter.

ST2CMP1RST

Bit 23: Slave_TIMER2 compare 1 event resets counter.

ST2CMP3RST

Bit 24: Slave_TIMER2 compare 3 event resets counter.

ST3CMP0RST

Bit 25: Slave_TIMER3 compare 0 event resets counter.

ST3CMP1RST

Bit 26: Slave_TIMER3 compare 1 event resets counter.

ST3CMP3RST

Bit 27: Slave_TIMER3 compare 3 event resets counter.

ST4CMP0RST

Bit 28: Slave_TIMER4 compare 0 event resets counter.

ST4CMP1RST

Bit 29: Slave_TIMER4 compare 1 event resets counter.

ST4CMP3RST

Bit 30: Slave_TIMER4 compare 3 event resets counter.

ST0CSCTL

SHRTIMER Slave_TIMERx carrier-signal control register

Offset: 0x58, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSFSTPW
rw 		CSDTY
rw 		CSPRD
rw
Toggle Fields.

CSPRD

Bits 0-3: Carrier signal period.

CSDTY

Bits 4-6: Carrier signal duty cycle.

CSFSTPW

Bits 7-10: First carrier-signal pulse width.

ST0CAP0TRG

SHRTIMER Slave_TIMER0 capture 0 trigger register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CP0BST0CMP1
rw 		CP0BST0CMP0
rw 		CP0BST0NA
rw 		CP0BST0A
rw 		CP0BEXEV9
rw 		CP0BEXEV8
rw 		CP0BEXEV7
rw 		CP0BEXEV6
rw 		CP0BEXEV5
rw 		CP0BEXEV4
rw 		CP0BEXEV3
rw 		CP0BEXEV2
rw 		CP0BEXEV1
rw 		CP0BEXEV0
rw 		CP0BUP
rw 		CP0BSW
rw
Toggle Fields.

CP0BSW

Bit 0: Capture 0 triggered by software.

CP0BUP

Bit 1: Capture 0 triggered by update event.

CP0BEXEV0

Bit 2: Capture 0 triggered by external event 0.

CP0BEXEV1

Bit 3: Capture 0 triggered by external event 1.

CP0BEXEV2

Bit 4: Capture 0 triggered by external event 2.

CP0BEXEV3

Bit 5: Capture 0 triggered by external event 3.

CP0BEXEV4

Bit 6: Capture 0 triggered by external event 4.

CP0BEXEV5

Bit 7: Capture 0 triggered by external event 5.

CP0BEXEV6

Bit 8: Capture 0 triggered by external event 6.

CP0BEXEV7

Bit 9: Capture 0 triggered by external event 7.

CP0BEXEV8

Bit 10: Capture 0 triggered by external event 8.

CP0BEXEV9

Bit 11: Capture 0 triggered by external event 9.

CP0BST0A

Bit 12: Capture 0 triggered by ST0CH0_O output inactive to active transition.

CP0BST0NA

Bit 13: Capture 0 triggered by ST0CH0_O output active to inactive transition.

CP0BST0CMP0

Bit 14: Capture 0 triggered by compare 0 event of Slave_TIMER0.

CP0BST0CMP1

Bit 15: Capture 0 triggered by compare 1 event of Slave_TIMER0.

ST0CAP1TRG

SHRTIMER Slave_TIMER0 capture 1 trigger register

Offset: 0x60, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CP1BST0CMP1
rw 		CP1BST0CMP0
rw 		CP1BST0NA
rw 		CP1BST0A
rw 		CP1BEXEV9
rw 		CP1BEXEV8
rw 		CP1BEXEV7
rw 		CP1BEXEV6
rw 		CP1BEXEV5
rw 		CP1BEXEV4
rw 		CP1BEXEV3
rw 		CP1BEXEV2
rw 		CP1BEXEV1
rw 		CP1BEXEV0
rw 		CP1BUP
rw 		CP1BSW
rw
Toggle Fields.

CP1BSW

Bit 0: Capture 1 triggered by software.

CP1BUP

Bit 1: Capture 1 triggered by update event.

CP1BEXEV0

Bit 2: Capture 1 triggered by external event 0.

CP1BEXEV1

Bit 3: Capture 1 triggered by external event 1.

CP1BEXEV2

Bit 4: Capture 1 triggered by external event 2.

CP1BEXEV3

Bit 5: Capture 1 triggered by external event 3.

CP1BEXEV4

Bit 6: Capture 1 triggered by external event 4.

CP1BEXEV5

Bit 7: Capture 1 triggered by external event 5.

CP1BEXEV6

Bit 8: Capture 1 triggered by external event 6.

CP1BEXEV7

Bit 9: Capture 1 triggered by external event 7.

CP1BEXEV8

Bit 10: Capture 1 triggered by external event 8.

CP1BEXEV9

Bit 11: Capture 1 triggered by external event 9.

CP1BST0A

Bit 12: Capture 1 triggered by ST0CH0_O output inactive to active transition.

CP1BST0NA

Bit 13: Capture 1 triggered by ST0CH0_O output active to inactive transition.

CP1BST0CMP0

Bit 14: Capture 1 triggered by compare 0 event of Slave_TIMER0.

CP1BST0CMP1

Bit 15: Capture 1 triggered by compare 1 event of Slave_TIMER0.

ST0CHOCTL

SHRTIMER Slave_TIMERx channel output control register

Offset: 0x64, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BMCH1DTI
rw 		CH1CSEN
rw 		CH1FLTOS
rw 		ISO1
rw 		BMCH1IEN
rw 		CH1P
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYISCH
rw 		DLYISMEN
rw 		DTEN
rw 		BMCH0DTI
rw 		CH0CSEN
rw 		CH0FLTOS
rw 		ISO0
rw 		BMCH0IEN
rw 		CH0P
rw
Toggle Fields.

CH0P

Bit 1: Channel 0 output polarity.

BMCH0IEN

Bit 2: Channel 0 IDLE state enable in bunch mode.

ISO0

Bit 3: Channel 0 output idle state.

CH0FLTOS

Bits 4-5: Channel 0 Fault output state.

CH0CSEN

Bit 6: Channel 0 carrier-signal mode enable.

BMCH0DTI

Bit 7: Channel 0 dead-time insert in bunch mode.

DTEN

Bit 8: Dead time enable.

DLYISMEN

Bit 9: Delayed IDLE state mode enable.

DLYISCH

Bits 10-12: Delayed IDLE source and channel.

CH1P

Bit 17: Channel 1 output polarity.

BMCH1IEN

Bit 18: Channel 1 IDLE state enable in bunch mode.

ISO1

Bit 19: channel 1 output idle state.

CH1FLTOS

Bits 20-21: Channel 1 Fault output state.

CH1CSEN

Bit 22: Channel 1 carrier-signal mode enable.

BMCH1DTI

Bit 23: Channel 1 dead-time insert in bunch mode.

ST0FLTCTL

SHRTIMER Slave_TIMERx fault control register

Offset: 0x68, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTENPROT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT4EN
rw 		FLT3EN
rw 		FLT2EN
rw 		FLT1EN
rw 		FLT0EN
rw
Toggle Fields.

FLT0EN

Bit 0: Fault 0 enable.

FLT1EN

Bit 1: Fault 1 enable.

FLT2EN

Bit 2: Fault 2 enable.

FLT3EN

Bit 3: Fault 3 enable.

FLT4EN

Bit 4: Fault 4 enable.

FLTENPROT

Bit 31: Protect fault enable.

ST0ACTL

SHRTIMER Slave_TIMERx additional control register

Offset: 0x7C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFCFG_15_9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTRCFG_15_9
rw 		CNTCKDIV_3
rw
Toggle Fields.

CNTCKDIV_3

Bit 3: Counter clock division.

DTRCFG_15_9

Bits 9-15: Rising edge dead-time value configure.

DTFCFG_15_9

Bits 25-31: Falling edge dead-time value configure.

SLAVE_TIMER1

0x40017500: SHRTIMER Slave TIMER1 registers(

18/336 fields covered. Toggle Registers.

ST1CTL0

SHRTIMER Slave_TIMER1 control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPSEL
rw 		SHWEN
rw 		DACTRGS
rw 		UPBMT
rw 		UPBST4
rw 		UPBST3
rw 		UPBST2
rw 		UPBST0
rw 		UPRST
rw 		UPREP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DELCMP3M
rw 		DELCMP1M
rw 		SYNISTRT
rw 		SYNIRST
rw 		BLNMEN
rw 		HALFM
rw 		CNTRSTM
rw 		CTNM
rw 		CNTCKDIV
rw
Toggle Fields.

CNTCKDIV

Bits 0-2: Counter clock division.

CTNM

Bit 3: Continuous mode.

CNTRSTM

Bit 4: Counter reset mode.

HALFM

Bit 5: Half mode.

BLNMEN

Bit 6: Balanced mode enable.

SYNIRST

Bit 10: Synchronization input reset counter.

SYNISTRT

Bit 11: Synchronization input start counter.

DELCMP1M

Bits 12-13: Compare 1 delayed mode.

DELCMP3M

Bits 14-15: Compare 3 delayed mode.

UPREP

Bit 17: Update event generated by repetition event.

UPRST

Bit 18: Update event generated by reset event.

UPBST0

Bit 19: Update by Slave_TIMER0 update event.

UPBST2

Bit 21: Update by Slave_TIMER2 update event.

UPBST3

Bit 22: Update by Slave_TIMER3 update event.

UPBST4

Bit 23: Update by Slave_TIMER4 update event.

UPBMT

Bit 24: Update by Master_TIMER update event.

DACTRGS

Bits 25-26: Trigger source to DAC.

SHWEN

Bit 27: Shadow registers enable.

UPSEL

Bits 28-31: Update event selection.

ST1INTF

SHRTIMER Slave_TIMER1 interrupt flag register

Offset: 0x4, reset: 0x00000000, access: read-only

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1F
r 		CH0F
r 		BLNIF
r 		CBLNF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYIIF
r 		RSTIF
r 		CH1ONAIF
r 		CH1OAIF
r 		CH0ONAIF
r 		CH0OAIF
r 		CAP1IF
r 		CAP0IF
r 		UPIF
r 		REPIF
r 		CMP3IF
r 		CMP2IF
r 		CMP1IF
r 		CMP0IF
r
Toggle Fields.

CMP0IF

Bit 0: Compare 0 interrupt flag.

CMP1IF

Bit 1: Compare 1 interrupt flag.

CMP2IF

Bit 2: Compare 2 interrupt flag.

CMP3IF

Bit 3: Compare 3 interrupt flag.

REPIF

Bit 4: Repetition interrupt flag.

UPIF

Bit 6: Update interrupt flag.

CAP0IF

Bit 7: Capture 0 interrupt flag.

CAP1IF

Bit 8: Capture 1 interrupt flag.

CH0OAIF

Bit 9: Channel 0 output active interrupt flag.

CH0ONAIF

Bit 10: Channel 0 output inactive interrupt flag.

CH1OAIF

Bit 11: Channel 1 output active interrupt flag.

CH1ONAIF

Bit 12: Channel 1 output inactive interrupt flag.

RSTIF

Bit 13: Counter reset interrupt flag.

DLYIIF

Bit 14: Delayed IDLE mode entry interrupt flag.

CBLNF

Bit 16: Current balanced flag.

BLNIF

Bit 17: Balanced IDLE flag.

CH0F

Bit 20: Channel 0 output flag.

CH1F

Bit 21: Channel 1 output flag.

ST1INTC

SHRTIMER Slave_TIMER1 interrupt flag clear register

Offset: 0x8, reset: 0x00000000, access: write-only

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYIIFC
w 		RSTIFC
w 		CH1ONAIFC
w 		CH1OAIFC
w 		CH0ONAIFC
w 		CH0OAIFC
w 		CAP1IFC
w 		CAP0IFC
w 		UPIFC
w 		REPIFC
w 		CMP3IFC
w 		CMP2IFC
w 		CMP1IFC
w 		CMP0IFC
w
Toggle Fields.

CMP0IFC

Bit 0: Clear compare 0 interrupt flag.

CMP1IFC

Bit 1: Clear compare 1 interrupt flag.

CMP2IFC

Bit 2: Clear compare 2 interrupt flag.

CMP3IFC

Bit 3: Clear compare 3 interrupt flag.

REPIFC

Bit 4: Clear repetition interrupt flag.

UPIFC

Bit 6: Clear update interrupt flag.

CAP0IFC

Bit 7: Clear capture 0 interrupt flag.

CAP1IFC

Bit 8: Clear capture 1 interrupt flag.

CH0OAIFC

Bit 9: Clear channel 0 output active interrupt flag.

CH0ONAIFC

Bit 10: Clear channel 0 output inactive interrupt flag.

CH1OAIFC

Bit 11: Clear channel 1 output active interrupt flag.

CH1ONAIFC

Bit 12: Clear channel 1 output inactive interrupt flag.

RSTIFC

Bit 13: Clear counter reset interrupt flag.

DLYIIFC

Bit 14: Clear delayed IDLE mode entry interrupt flag.

ST1DMAINTEN

SHRTIMER Slave_TIMER1 DMA and interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYIDEN
rw 		RSTDEN
rw 		CH1ONADEN
rw 		CH1OADEN
rw 		CH0ONADEN
rw 		CH0ADEN
rw 		CAP1DEN
rw 		CAP0DEN
rw 		UPDEN
rw 		REPDEN
rw 		CMP3DEN
rw 		CMP2DEN
rw 		CMP1DEN
rw 		CMP0DEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYIIE
rw 		RSTIE
rw 		CH1ONAIE
rw 		CH1OAIE
rw 		CH0ONAIE
rw 		CH0OAIE
rw 		CAP1IE
rw 		CAP0IE
rw 		UPIE
rw 		REPIE
rw 		CMP3IE
rw 		CMP2IE
rw 		CMP1IE
rw 		CMP0IE
rw
Toggle Fields.

CMP0IE

Bit 0: Compare 0 interrupt enable.

CMP1IE

Bit 1: Compare 1 interrupt enable.

CMP2IE

Bit 2: Compare 2 interrupt enable.

CMP3IE

Bit 3: Compare 3 interrupt enable.

REPIE

Bit 4: Repetition interrupt enable.

UPIE

Bit 6: Update interrupt enable.

CAP0IE

Bit 7: Capture 0 interrupt enable.

CAP1IE

Bit 8: Capture 1 interrupt enable.

CH0OAIE

Bit 9: Channel 0 output active interrupt enable.

CH0ONAIE

Bit 10: Channel 0 output inactive interrupt enable.

CH1OAIE

Bit 11: Channel 1 output active interrupt enable.

CH1ONAIE

Bit 12: Channel 1 output inactive interrupt enable.

RSTIE

Bit 13: Counter reset interrupt enable.

DLYIIE

Bit 14: Delayed IDLE mode entry interrupt enable.

CMP0DEN

Bit 16: Compare 0 DMA request enable.

CMP1DEN

Bit 17: Compare 1 DMA request enable.

CMP2DEN

Bit 18: Compare 2 DMA request enable.

CMP3DEN

Bit 19: Compare 3 DMA request enable.

REPDEN

Bit 20: Repetition DMA request enable.

UPDEN

Bit 22: Update DMA request enable.

CAP0DEN

Bit 23: Capture 0 DMA request enable.

CAP1DEN

Bit 24: Capture 1 DMA request enable.

CH0ADEN

Bit 25: Channel 0 output active DMA request enable.

CH0ONADEN

Bit 26: Channel 0 output inactive DMA request enable.

CH1OADEN

Bit 27: Channel 1 output active DMA request enable.

CH1ONADEN

Bit 28: Channel 1 output inactive DMA request enable.

RSTDEN

Bit 29: Counter reset DMA request enable.

DLYIDEN

Bit 30: Delayed IDLE mode entry DMA request enable.

ST1CNT

SHRTIMER Slave_TIMER1 counter register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: The current counter value.

ST1CAR

SHRTIMER Slave_TIMER1 counter auto reload register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARL
rw
Toggle Fields.

CARL

Bits 0-15: Counter auto reload value.

ST1CREP

SHRTIMER Slave_TIMER1 counter repetition register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CREP
rw
Toggle Fields.

CREP

Bits 0-7: Counter repetition value.

ST1CMP0V

SHRTIMER Slave_TIMER1 compare 0 value register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP0VAL
rw
Toggle Fields.

CMP0VAL

Bits 0-15: Compare 0 value.

ST1CMP0CP

SHRTIMER Slave_TIMER1 compare 0 composite register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CREP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP0VAL
rw
Toggle Fields.

CMP0VAL

Bits 0-15: Compare 0 value.

CREP

Bits 16-23: Counter repetition value.

ST1CMP1V

SHRTIMER Slave_TIMER1 compare 1 value register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP1VAL
rw
Toggle Fields.

CMP1VAL

Bits 0-15: Compare 1 value.

ST1CMP2V

SHRTIMER Slave_TIMER1 compare 2 value register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP2VAL
rw
Toggle Fields.

CMP2VAL

Bits 0-15: Compare 2 value.

ST1CMP3V

SHRTIMER Slave_TIMER1 compare 3 value register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP3VAL
rw
Toggle Fields.

CMP3VAL

Bits 0-15: Compare 3 value.

ST1CAP0V

SHRTIMER Slave_TIMER1 capture 0 value register

Offset: 0x30, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAP0VAL
rw
Toggle Fields.

CAP0VAL

Bits 0-15: Capture 0 value.

ST1CAP1V

SHRTIMER Slave_TIMER1 capture 1 value register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAP1VAL
rw
Toggle Fields.

CAP1VAL

Bits 0-15: Capture 1 value.

ST1DTCTL

SHRTIMER Slave_TIMER1 dead-time control register

Offset: 0x38, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFSVPROT
rw 		DTFSPROT
rw 		DTFS
rw 		DTFCFG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTRSVPROT
rw 		DTRSPROT
rw 		DTGCKDIV
rw 		DTRS
rw 		DTRCFG
rw
Toggle Fields.

DTRCFG

Bits 0-8: Falling edge dead-time value.

DTRS

Bit 9: The sign of falling edge dead-time value.

DTGCKDIV

Bits 10-13: Dead time generator clock division.

DTRSPROT

Bit 14: Dead-time rising edge protection for sign.

DTRSVPROT

Bit 15: Dead-time rising edge protection for value and sign.

DTFCFG

Bits 16-24: Falling edge dead-time value.

DTFS

Bit 25: The sign of falling edge dead-time value.

DTFSPROT

Bit 30: Dead-time falling edge protection for sign.

DTFSVPROT

Bit 31: Dead-time falling edge protection for value and sign.

ST1CH0SET

SHRTIMER Slave_TIMER1 channel 0 set request register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH0SUP
rw 		CH0SEXEV9
rw 		CH0SEXEV8
rw 		CH0SEXEV7
rw 		CH0SEXEV6
rw 		CH0SEXEV5
rw 		CH0SEXEV4
rw 		CH0SEXEV3
rw 		CH0SEXEV2
rw 		CH0SEXEV1
rw 		CH0SEXEV0
rw 		CH0SSTEV8
rw 		CH0SSTEV7
rw 		CH0SSTEV6
rw 		CH0SSTEV5
rw 		CH0SSTEV4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0SSTEV3
rw 		CH0SSTEV2
rw 		CH0SSTEV1
rw 		CH0SSTEV0
rw 		CH0SMTCMP3
rw 		CH0SMTCMP2
rw 		CH0SMTCMP1
rw 		CH0SMTCMP0
rw 		CH0SMTPER
rw 		CH0SCMP3
rw 		CH0SCMP2
rw 		CH0SCMP1
rw 		CH0SCMP0
rw 		CH0SPER
rw 		CH0SRST
rw 		CH0SSEV
rw
Toggle Fields.

CH0SSEV

Bit 0: Software event generates channel 0 .

CH0SRST

Bit 1: Slave_TIMER1 reset event generates channel 0 .

CH0SPER

Bit 2: Slave_TIMER1 period event generates channel 0 .

CH0SCMP0

Bit 3: Slave_TIMER1 compare 0 event generates channel 0 .

CH0SCMP1

Bit 4: Slave_TIMER1 compare 1 event generates channel 0 .

CH0SCMP2

Bit 5: Slave_TIMER1 compare 2 event generates channel 0 .

CH0SCMP3

Bit 6: Slave_TIMER1 compare 3 event generates channel 0 .

CH0SMTPER

Bit 7: Master_TIMER period event generates channel 0 .

CH0SMTCMP0

Bit 8: Master_TIMER compare 0 event generates channel 0 .

CH0SMTCMP1

Bit 9: Master_TIMER compare 1 event generates channel 0 .

CH0SMTCMP2

Bit 10: Master_TIMER compare 2 event generates channel 0 .

CH0SMTCMP3

Bit 11: Master_TIMER compare 3 event generates channel 0 .

CH0SSTEV0

Bit 12: Slave_TIMER1 interconnection event 0 generates channel 0 .

CH0SSTEV1

Bit 13: Slave_TIMER1 interconnection event 1 generates channel 0 .

CH0SSTEV2

Bit 14: Slave_TIMER1 interconnection event 2 generates channel 0 .

CH0SSTEV3

Bit 15: Slave_TIMER1 interconnection event 3 generates channel 0 .

CH0SSTEV4

Bit 16: Slave_TIMER1 interconnection event 4 generates channel 0 .

CH0SSTEV5

Bit 17: Slave_TIMER1 interconnection event 5 generates channel 0 .

CH0SSTEV6

Bit 18: Slave_TIMER1 interconnection event 6 generates channel 0 .

CH0SSTEV7

Bit 19: Slave_TIMER1 interconnection event 7 generates channel 0 .

CH0SSTEV8

Bit 20: Slave_TIMER1 interconnection event 8 generates channel 0 .

CH0SEXEV0

Bit 21: External event 0 generates channel 0 .

CH0SEXEV1

Bit 22: External event 1 generates channel 0 .

CH0SEXEV2

Bit 23: External event 2 generates channel 0 .

CH0SEXEV3

Bit 24: External event 3 generates channel 0 .

CH0SEXEV4

Bit 25: External event 4 generates channel 0 .

CH0SEXEV5

Bit 26: External event 5 generates channel 0 .

CH0SEXEV6

Bit 27: External event 6 generates channel 0 .

CH0SEXEV7

Bit 28: External event 7 generates channel 0 .

CH0SEXEV8

Bit 29: External event 8 generates channel 0 .

CH0SEXEV9

Bit 30: External event 9 generates channel 0 .

CH0SUP

Bit 31: Update event generates channel 0 .

ST1CH0RST

SHRTIMER Slave_TIMER1 channel 0 reset request register

Offset: 0x40, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH0RSUP
rw 		CH0RSEXEV9
rw 		CH0RSEXEV8
rw 		CH0RSEXEV7
rw 		CH0RSEXEV6
rw 		CH0RSEXEV5
rw 		CH0RSEXEV4
rw 		CH0RSEXEV3
rw 		CH0RSEXEV2
rw 		CH0RSEXEV1
rw 		CH0RSEXEV0
rw 		CH0RSSTEV8
rw 		CH0RSSTEV7
rw 		CH0RSSTEV6
rw 		CH0RSSTEV5
rw 		CH0RSSTEV4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0RSSTEV3
rw 		CH0RSSTEV2
rw 		CH0RSSTEV1
rw 		CH0RSSTEV0
rw 		CH0RSMTCMP3
rw 		CH0RSMTCMP2
rw 		CH0RSMTCMP1
rw 		CH0RSMTCMP0
rw 		CH0RSMTPER
rw 		CH0RSCMP3
rw 		CH0RSCMP2
rw 		CH0RSCMP1
rw 		CH0RSCMP0
rw 		CH0RSPER
rw 		CH0RSRST
rw 		CH0RSSEV
rw
Toggle Fields.

CH0RSSEV

Bit 0: Software event generates channel 0 .

CH0RSRST

Bit 1: Slave_TIMER1 reset event generates channel 0 .

CH0RSPER

Bit 2: Slave_TIMER1 period event generates channel 0 .

CH0RSCMP0

Bit 3: Slave_TIMER1 compare 0 event generates channel 0 .

CH0RSCMP1

Bit 4: Slave_TIMER1 compare 1 event generates channel 0 .

CH0RSCMP2

Bit 5: Slave_TIMER1 compare 2 event generates channel 0 .

CH0RSCMP3

Bit 6: Slave_TIMER1 compare 3 event generates channel 0 .

CH0RSMTPER

Bit 7: Master_TIMER period event generates channel 0 .

CH0RSMTCMP0

Bit 8: Master_TIMER compare 0 event generates channel 0 .

CH0RSMTCMP1

Bit 9: Master_TIMER compare 1 event generates channel 0 .

CH0RSMTCMP2

Bit 10: Master_TIMER compare 2 event generates channel 0 .

CH0RSMTCMP3

Bit 11: Master_TIMER compare 3 event generates channel 0 .

CH0RSSTEV0

Bit 12: Slave_TIMER1 interconnection event 0 generates channel 0 .

CH0RSSTEV1

Bit 13: Slave_TIMER1 interconnection event 1 generates channel 0 .

CH0RSSTEV2

Bit 14: Slave_TIMER1 interconnection event 2 generates channel 0 .

CH0RSSTEV3

Bit 15: Slave_TIMER1 interconnection event 3 generates channel 0 .

CH0RSSTEV4

Bit 16: Slave_TIMER1 interconnection event 4 generates channel 0 .

CH0RSSTEV5

Bit 17: Slave_TIMER1 interconnection event 5 generates channel 0 .

CH0RSSTEV6

Bit 18: Slave_TIMER1 interconnection event 6 generates channel 0 .

CH0RSSTEV7

Bit 19: Slave_TIMER1 interconnection event 7 generates channel 0 .

CH0RSSTEV8

Bit 20: Slave_TIMER1 interconnection event 8 generates channel 0 .

CH0RSEXEV0

Bit 21: External event 0 generates channel 0 .

CH0RSEXEV1

Bit 22: External event 1 generates channel 0 .

CH0RSEXEV2

Bit 23: External event 2 generates channel 0 .

CH0RSEXEV3

Bit 24: External event 3 generates channel 0 .

CH0RSEXEV4

Bit 25: External event 4 generates channel 0 .

CH0RSEXEV5

Bit 26: External event 5 generates channel 0 .

CH0RSEXEV6

Bit 27: External event 6 generates channel 0 .

CH0RSEXEV7

Bit 28: External event 7 generates channel 0 .

CH0RSEXEV8

Bit 29: External event 8 generates channel 0 .

CH0RSEXEV9

Bit 30: External event 9 generates channel 0 .

CH0RSUP

Bit 31: Update event generates channel 0 .

ST1CH1SET

SHRTIMER Slave_TIMER1 channel 1 set request register

Offset: 0x44, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1SUP
rw 		CH1SEXEV9
rw 		CH1SEXEV8
rw 		CH1SEXEV7
rw 		CH1SEXEV6
rw 		CH1SEXEV5
rw 		CH1SEXEV4
rw 		CH1SEXEV3
rw 		CH1SEXEV2
rw 		CH1SEXEV1
rw 		CH1SEXEV0
rw 		CH1SSTEV8
rw 		CH1SSTEV7
rw 		CH1SSTEV6
rw 		CH1SSTEV5
rw 		CH1SSTEV4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1SSTEV3
rw 		CH1SSTEV2
rw 		CH1SSTEV1
rw 		CH1SSTEV0
rw 		CH1SMTCMP3
rw 		CH1SMTCMP2
rw 		CH1SMTCMP1
rw 		CH1SMTCMP0
rw 		CH1SMTPER
rw 		CH1SCMP3
rw 		CH1SCMP2
rw 		CH1SCMP1
rw 		CH1SCMP0
rw 		CH1SPER
rw 		CH1SRST
rw 		CH1SSEV
rw
Toggle Fields.

CH1SSEV

Bit 0: Software event generates channel 1 .

CH1SRST

Bit 1: Slave_TIMERx reset event generates channel 1 .

CH1SPER

Bit 2: Slave_TIMERx period event generates channel 1 .

CH1SCMP0

Bit 3: Slave_TIMERx compare 0 event generates channel 1 .

CH1SCMP1

Bit 4: Slave_TIMERx compare 1 event generates channel 1 .

CH1SCMP2

Bit 5: Slave_TIMERx compare 2 event generates channel 1 .

CH1SCMP3

Bit 6: Slave_TIMERx compare 3 event generates channel 1 .

CH1SMTPER

Bit 7: Master_TIMER period event generates channel 1 .

CH1SMTCMP0

Bit 8: Master_TIMER compare 0 event generates channel 1 .

CH1SMTCMP1

Bit 9: Master_TIMER compare 1 event generates channel 1 .

CH1SMTCMP2

Bit 10: Master_TIMER compare 2 event generates channel 1 .

CH1SMTCMP3

Bit 11: Master_TIMER compare 3 event generates channel 1 .

CH1SSTEV0

Bit 12: Slave_TIMERx interconnection event 0 generates channel 1 .

CH1SSTEV1

Bit 13: Slave_TIMERx interconnection event 1 generates channel 1 .

CH1SSTEV2

Bit 14: Slave_TIMERx interconnection event 2 generates channel 1 .

CH1SSTEV3

Bit 15: Slave_TIMERx interconnection event 3 generates channel 1 .

CH1SSTEV4

Bit 16: Slave_TIMERx interconnection event 4 generates channel 1 .

CH1SSTEV5

Bit 17: Slave_TIMERx interconnection event 5 generates channel 1 .

CH1SSTEV6

Bit 18: Slave_TIMERx interconnection event 6 generates channel 1 .

CH1SSTEV7

Bit 19: Slave_TIMERx interconnection event 7 generates channel 1 .

CH1SSTEV8

Bit 20: Slave_TIMERx interconnection event 8 generates channel 1 .

CH1SEXEV0

Bit 21: External event 0 generates channel 1 .

CH1SEXEV1

Bit 22: External event 1 generates channel 1 .

CH1SEXEV2

Bit 23: External event 2 generates channel 1 .

CH1SEXEV3

Bit 24: External event 3 generates channel 1 .

CH1SEXEV4

Bit 25: External event 4 generates channel 1 .

CH1SEXEV5

Bit 26: External event 5 generates channel 1 .

CH1SEXEV6

Bit 27: External event 6 generates channel 1 .

CH1SEXEV7

Bit 28: External event 7 generates channel 1 .

CH1SEXEV8

Bit 29: External event 8 generates channel 1 .

CH1SEXEV9

Bit 30: External event 9 generates channel 1 .

CH1SUP

Bit 31: Update event generates channel 1 .

ST1CH1RST

SHRTIMER Slave_TIMER1 channel 1 reset request register

Offset: 0x48, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1RSUP
rw 		CH1RSEXEV9
rw 		CH1RSEXEV8
rw 		CH1RSEXEV7
rw 		CH1RSEXEV6
rw 		CH1RSEXEV5
rw 		CH1RSEXEV4
rw 		CH1RSEXEV3
rw 		CH1RSEXEV2
rw 		CH1RSEXEV1
rw 		CH1RSEXEV0
rw 		CH1RSSTEV8
rw 		CH1RSSTEV7
rw 		CH1RSSTEV6
rw 		CH1RSSTEV5
rw 		CH1RSSTEV4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1RSSTEV3
rw 		CH1RSSTEV2
rw 		CH1RSSTEV1
rw 		CH1RSSTEV0
rw 		CH1RSMTCMP3
rw 		CH1RSMTCMP2
rw 		CH1RSMTCMP1
rw 		CH1RSMTCMP0
rw 		CH1RSMTPER
rw 		CH1RSCMP3
rw 		CH1RSCMP2
rw 		CH1RSCMP1
rw 		CH1RSCMP0
rw 		CH1RSPER
rw 		CH1RSRST
rw 		CH1RSSEV
rw
Toggle Fields.

CH1RSSEV

Bit 0: Software event generates channel 1 .

CH1RSRST

Bit 1: Slave_TIMERx reset event generates channel 1 .

CH1RSPER

Bit 2: Slave_TIMERx period event generates channel 1 .

CH1RSCMP0

Bit 3: Slave_TIMERx compare 0 event generates channel 1 .

CH1RSCMP1

Bit 4: Slave_TIMERx compare 1 event generates channel 1 .

CH1RSCMP2

Bit 5: Slave_TIMERx compare 2 event generates channel 1 .

CH1RSCMP3

Bit 6: Slave_TIMERx compare 3 event generates channel 1 .

CH1RSMTPER

Bit 7: Master_TIMER period event generates channel 1 .

CH1RSMTCMP0

Bit 8: Master_TIMER compare 0 event generates channel 1 .

CH1RSMTCMP1

Bit 9: Master_TIMER compare 1 event generates channel 1 .

CH1RSMTCMP2

Bit 10: Master_TIMER compare 2 event generates channel 1 .

CH1RSMTCMP3

Bit 11: Master_TIMER compare 3 event generates channel 1 .

CH1RSSTEV0

Bit 12: Slave_TIMERx interconnection event 0 generates channel 1 .

CH1RSSTEV1

Bit 13: Slave_TIMERx interconnection event 1 generates channel 1 .

CH1RSSTEV2

Bit 14: Slave_TIMERx interconnection event 2 generates channel 1 .

CH1RSSTEV3

Bit 15: Slave_TIMERx interconnection event 3 generates channel 1 .

CH1RSSTEV4

Bit 16: Slave_TIMERx interconnection event 4 generates channel 1 .

CH1RSSTEV5

Bit 17: Slave_TIMERx interconnection event 5 generates channel 1 .

CH1RSSTEV6

Bit 18: Slave_TIMERx interconnection event 6 generates channel 1 .

CH1RSSTEV7

Bit 19: Slave_TIMERx interconnection event 7 generates channel 1 .

CH1RSSTEV8

Bit 20: Slave_TIMERx interconnection event 8 generates channel 1 .

CH1RSEXEV0

Bit 21: External event 0 generates channel 1 .

CH1RSEXEV1

Bit 22: External event 1 generates channel 1 .

CH1RSEXEV2

Bit 23: External event 2 generates channel 1 .

CH1RSEXEV3

Bit 24: External event 3 generates channel 1 .

CH1RSEXEV4

Bit 25: External event 4 generates channel 1 .

CH1RSEXEV5

Bit 26: External event 5 generates channel 1 .

CH1RSEXEV6

Bit 27: External event 6 generates channel 1 .

CH1RSEXEV7

Bit 28: External event 7 generates channel 1 .

CH1RSEXEV8

Bit 29: External event 8 generates channel 1 .

CH1RSEXEV9

Bit 30: External event 9 generates channel 1 .

CH1RSUP

Bit 31: Update event generates channel 1 .

ST1EXEVFCFG0

SHRTIMER Slave_TIMERx external event filter configuration register 0

Offset: 0x4C, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXEV4FM
rw 		EXEV4MEEN
rw 		EXEV3FM
rw 		EXEV3MEEN
rw 		EXEV2FM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXEV2FM
rw 		EXEV2MEEN
rw 		EXEV1FM
rw 		EXEV1MEEN
rw 		EXEV0FM
rw 		EXEV0MEEN
rw
Toggle Fields.

EXEV0MEEN

Bit 0: External event 0 memorized enable.

EXEV0FM

Bits 1-4: External event 0 filter mode.

EXEV1MEEN

Bit 6: External event 1 memorized enable.

EXEV1FM

Bits 7-10: External event 1 filter mode.

EXEV2MEEN

Bit 12: External event 2 memorized enable.

EXEV2FM

Bits 13-16: External event 2 filter mode.

EXEV3MEEN

Bit 18: External event 3 memorized enable.

EXEV3FM

Bits 19-22: External event 3 filter mode.

EXEV4MEEN

Bit 24: External event 4 memorized enable.

EXEV4FM

Bits 25-28: External event 4 filter mode.

ST1EXEVFCFG1

SHRTIMER Slave_TIMERx external event filter configuration register 1

Offset: 0x50, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXEV9FM
rw 		EXEV9MEEN
rw 		EXEV8FM
rw 		EXEV8MEEN
rw 		EXEV7FM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXEV7FM
rw 		EXEV7MEEN
rw 		EXEV6FM
rw 		EXEV6MEEN
rw 		EXEV5FM
rw 		EXEV5MEEN
rw
Toggle Fields.

EXEV5MEEN

Bit 0: External event 5 memorized enable.

EXEV5FM

Bits 1-4: External event 5 filter mode.

EXEV6MEEN

Bit 6: External event 6 memorized enable.

EXEV6FM

Bits 7-10: External event 6 filter mode.

EXEV7MEEN

Bit 12: External event 7 memorized enable.

EXEV7FM

Bits 13-16: External event 7 filter mode.

EXEV8MEEN

Bit 18: External event 8 memorized enable.

EXEV8FM

Bits 19-22: External event 8 filter mode.

EXEV9MEEN

Bit 24: External event 9 memorized enable.

EXEV9FM

Bits 25-28: External event 9 filter mode.

ST1CNTRST

SHRTIMER Slave_TIMERx counter reset register

Offset: 0x54, reset: 0x00000000, access: read-write

0/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ST4CMP3RST
rw 		ST4CMP1RST
rw 		ST4CMP0RST
rw 		ST3CMP3RST
rw 		ST3CMP1RST
rw 		ST3CMP0RST
rw 		ST2CMP3RST
rw 		ST2CMP1RST
rw 		ST2CMP0RST
rw 		ST0CMP3RST
rw 		ST0CMP1RST
rw 		ST0CMP0RST
rw 		EXEV9RST
rw 		EXEV8RST
rw 		EXEV7RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXEV6RST
rw 		EXEV5RST
rw 		EXEV4RST
rw 		EXEV3RST
rw 		EXEV2RST
rw 		EXEV1RST
rw 		EXEV0RST
rw 		MTCMP3RST
rw 		MTCMP2RST
rw 		MTCMP1RST
rw 		MTCMP0RST
rw 		MTPERRST
rw 		CMP3RST
rw 		CMP1RST
rw 		UPRST
rw
Toggle Fields.

UPRST

Bit 1: Slave_TIMER1 update event resets counter.

CMP1RST

Bit 2: Slave_TIMER1 compare 1 event resets counter.

CMP3RST

Bit 3: Slave_TIMER1 compare 3 event resets counter.

MTPERRST

Bit 4: Master_TIMER period event resets counter.

MTCMP0RST

Bit 5: Master_TIMER compare 0 event resets counter.

MTCMP1RST

Bit 6: Master_TIMER compare 1 event resets counter.

MTCMP2RST

Bit 7: Master_TIMER compare 2 event resets counter.

MTCMP3RST

Bit 8: Master_TIMER compare 3 event resets counter.

EXEV0RST

Bit 9: External event 0 resets counter.

EXEV1RST

Bit 10: External event 1 resets counter.

EXEV2RST

Bit 11: External event 2 resets counter.

EXEV3RST

Bit 12: External event 3 resets counter.

EXEV4RST

Bit 13: External event 4 resets counter.

EXEV5RST

Bit 14: External event 5 resets counter.

EXEV6RST

Bit 15: External event 6 resets counter.

EXEV7RST

Bit 16: External event 7 resets counter.

EXEV8RST

Bit 17: External event 8 resets counter.

EXEV9RST

Bit 18: External event 9 resets counter.

ST0CMP0RST

Bit 19: Slave_TIMER0 compare 0 event resets counter.

ST0CMP1RST

Bit 20: Slave_TIMER0 compare 1 event resets counter.

ST0CMP3RST

Bit 21: Slave_TIMER0 compare 3 event resets counter.

ST2CMP0RST

Bit 22: Slave_TIMER2 compare 0 event resets counter.

ST2CMP1RST

Bit 23: Slave_TIMER2 compare 1 event resets counter.

ST2CMP3RST

Bit 24: Slave_TIMER2 compare 3 event resets counter.

ST3CMP0RST

Bit 25: Slave_TIMER3 compare 0 event resets counter.

ST3CMP1RST

Bit 26: Slave_TIMER3 compare 1 event resets counter.

ST3CMP3RST

Bit 27: Slave_TIMER3 compare 3 event resets counter.

ST4CMP0RST

Bit 28: Slave_TIMER4 compare 0 event resets counter.

ST4CMP1RST

Bit 29: Slave_TIMER4 compare 1 event resets counter.

ST4CMP3RST

Bit 30: Slave_TIMER4 compare 3 event resets counter.

ST1CSCTL

SHRTIMER Slave_TIMERx carrier-signal control register

Offset: 0x58, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSFSTPW
rw 		CSDTY
rw 		CSPRD
rw
Toggle Fields.

CSPRD

Bits 0-3: Carrier signal period.

CSDTY

Bits 4-6: Carrier signal duty cycle.

CSFSTPW

Bits 7-10: First carrier-signal pulse width.

ST1CAP0TRG

SHRTIMER Slave_TIMERx capture 0 trigger register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CP0BST1CMP1
rw 		CP0BST1CMP0
rw 		CP0BST1NA
rw 		CP0BST1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CP0BEXEV9
rw 		CP0BEXEV8
rw 		CP0BEXEV7
rw 		CP0BEXEV6
rw 		CP0BEXEV5
rw 		CP0BEXEV4
rw 		CP0BEXEV3
rw 		CP0BEXEV2
rw 		CP0BEXEV1
rw 		CP0BEXEV0
rw 		CP0BUP
rw 		CP0BSW
rw
Toggle Fields.

CP0BSW

Bit 0: Capture 0 triggered by software.

CP0BUP

Bit 1: Capture 0 triggered by update event.

CP0BEXEV0

Bit 2: Capture 0 triggered by external event 0.

CP0BEXEV1

Bit 3: Capture 0 triggered by external event 1.

CP0BEXEV2

Bit 4: Capture 0 triggered by external event 2.

CP0BEXEV3

Bit 5: Capture 0 triggered by external event 3.

CP0BEXEV4

Bit 6: Capture 0 triggered by external event 4.

CP0BEXEV5

Bit 7: Capture 0 triggered by external event 5.

CP0BEXEV6

Bit 8: Capture 0 triggered by external event 6.

CP0BEXEV7

Bit 9: Capture 0 triggered by external event 7.

CP0BEXEV8

Bit 10: Capture 0 triggered by external event 8.

CP0BEXEV9

Bit 11: Capture 0 triggered by external event 9.

CP0BST1A

Bit 16: Capture 0 triggered by ST1CH0_O output inactive to active transition.

CP0BST1NA

Bit 17: Capture 0 triggered by ST1CH0_O output active to inactive transition.

CP0BST1CMP0

Bit 18: Capture 0 triggered by compare 0 event of Slave_TIMER1.

CP0BST1CMP1

Bit 19: Capture 0 triggered by compare 1 event of Slave_TIMER1.

ST1CAP1TRG

SHRTIMER Slave_TIMERx capture 1 trigger register

Offset: 0x60, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CP1BST1CMP1
rw 		CP1BST1CMP0
rw 		CP1BST1NA
rw 		CP1BST1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CP1BEXEV9
rw 		CP1BEXEV8
rw 		CP1BEXEV7
rw 		CP1BEXEV6
rw 		CP1BEXEV5
rw 		CP1BEXEV4
rw 		CP1BEXEV3
rw 		CP1BEXEV2
rw 		CP1BEXEV1
rw 		CP1BEXEV0
rw 		CP1BUP
rw 		CP1BSW
rw
Toggle Fields.

CP1BSW

Bit 0: Capture 1 triggered by software.

CP1BUP

Bit 1: Capture 1 triggered by update event.

CP1BEXEV0

Bit 2: Capture 1 triggered by external event 0.

CP1BEXEV1

Bit 3: Capture 1 triggered by external event 1.

CP1BEXEV2

Bit 4: Capture 1 triggered by external event 2.

CP1BEXEV3

Bit 5: Capture 1 triggered by external event 3.

CP1BEXEV4

Bit 6: Capture 1 triggered by external event 4.

CP1BEXEV5

Bit 7: Capture 1 triggered by external event 5.

CP1BEXEV6

Bit 8: Capture 1 triggered by external event 6.

CP1BEXEV7

Bit 9: Capture 1 triggered by external event 7.

CP1BEXEV8

Bit 10: Capture 1 triggered by external event 8.

CP1BEXEV9

Bit 11: Capture 1 triggered by external event 9.

CP1BST1A

Bit 16: Capture 1 triggered by ST1CH0_O output inactive to active transition.

CP1BST1NA

Bit 17: Capture 1 triggered by ST1CH0_O output active to inactive transition.

CP1BST1CMP0

Bit 18: Capture 1 triggered by compare 0 event of Slave_TIMER1.

CP1BST1CMP1

Bit 19: Capture 1 triggered by compare 1 event of Slave_TIMER1.

ST1CHOCTL

SHRTIMER Slave_TIMERx channel output control register

Offset: 0x64, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BMCH1DTI
rw 		CH1CSEN
rw 		CH1FLTOS
rw 		ISO1
rw 		BMCH1IEN
rw 		CH1P
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYISCH
rw 		DLYISMEN
rw 		DTEN
rw 		BMCH0DTI
rw 		CH0CSEN
rw 		CH0FLTOS
rw 		ISO0
rw 		BMCH0IEN
rw 		CH0P
rw
Toggle Fields.

CH0P

Bit 1: Channel 0 output polarity.

BMCH0IEN

Bit 2: Channel 0 IDLE state enable in bunch mode.

ISO0

Bit 3: Channel 0 output idle state.

CH0FLTOS

Bits 4-5: Channel 0 Fault output state.

CH0CSEN

Bit 6: Channel 0 carrier-signal mode enable.

BMCH0DTI

Bit 7: Channel 0 dead-time insert in bunch mode.

DTEN

Bit 8: Dead time enable.

DLYISMEN

Bit 9: Delayed IDLE state mode enable.

DLYISCH

Bits 10-12: Delayed IDLE source and channel.

CH1P

Bit 17: Channel 1 output polarity.

BMCH1IEN

Bit 18: Channel 1 IDLE state enable in bunch mode.

ISO1

Bit 19: channel 1 output idle state.

CH1FLTOS

Bits 20-21: Channel 1 Fault output state.

CH1CSEN

Bit 22: Channel 1 carrier-signal mode enable.

BMCH1DTI

Bit 23: Channel 1 dead-time insert in bunch mode.

ST1FLTCTL

SHRTIMER Slave_TIMERx fault control register

Offset: 0x68, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTENPROT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT4EN
rw 		FLT3EN
rw 		FLT2EN
rw 		FLT1EN
rw 		FLT0EN
rw
Toggle Fields.

FLT0EN

Bit 0: Fault 0 enable.

FLT1EN

Bit 1: Fault 1 enable.

FLT2EN

Bit 2: Fault 2 enable.

FLT3EN

Bit 3: Fault 3 enable.

FLT4EN

Bit 4: Fault 4 enable.

FLTENPROT

Bit 31: Protect fault enable.

ST1ACTL

SHRTIMER Slave_TIMERx additional control register

Offset: 0x7C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFCFG_15_9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTRCFG_15_9
rw 		CNTCKDIV_3
rw
Toggle Fields.

CNTCKDIV_3

Bit 3: Counter clock division.

DTRCFG_15_9

Bits 9-15: Rising edge dead-time value configure.

DTFCFG_15_9

Bits 25-31: Falling edge dead-time value configure.

SLAVE_TIMER2

0x40017580: SHRTIMER Slave TIMER2 registers(

18/336 fields covered. Toggle Registers.

ST2CTL0

SHRTIMER Slave_TIMERx control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPSEL
rw 		SHWEN
rw 		DACTRGS
rw 		UPBMT
rw 		UPBST4
rw 		UPBST3
rw 		UPBST1
rw 		UPBST0
rw 		UPRST
rw 		UPREP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DELCMP3M
rw 		DELCMP1M
rw 		SYNISTRT
rw 		SYNIRST
rw 		BLNMEN
rw 		HALFM
rw 		CNTRSTM
rw 		CTNM
rw 		CNTCKDIV
rw
Toggle Fields.

CNTCKDIV

Bits 0-2: Counter clock division.

CTNM

Bit 3: Continuous mode.

CNTRSTM

Bit 4: Counter reset mode.

HALFM

Bit 5: Half mode.

BLNMEN

Bit 6: Balanced mode enable.

SYNIRST

Bit 10: Synchronization input reset counter.

SYNISTRT

Bit 11: Synchronization input start counter.

DELCMP1M

Bits 12-13: Compare 1 delayed mode.

DELCMP3M

Bits 14-15: Compare 3 delayed mode.

UPREP

Bit 17: Update event generated by repetition event.

UPRST

Bit 18: Update event generated by reset event.

UPBST0

Bit 19: Update by Slave_TIMER0 update event.

UPBST1

Bit 20: Update by Slave_TIMER1 update event.

UPBST3

Bit 22: Update by Slave_TIMER3 update event.

UPBST4

Bit 23: Update by Slave_TIMER4 update event.

UPBMT

Bit 24: Update by Master_TIMER update event.

DACTRGS

Bits 25-26: Trigger source to DAC.

SHWEN

Bit 27: Shadow registers enable.

UPSEL

Bits 28-31: Update event selection.

ST2INTF

SHRTIMER Slave_TIMERx interrupt flag register

Offset: 0x4, reset: 0x00000000, access: read-only

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1F
r 		CH0F
r 		BLNIF
r 		CBLNF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYIIF
r 		RSTIF
r 		CH1ONAIF
r 		CH1OAIF
r 		CH0ONAIF
r 		CH0OAIF
r 		CAP1IF
r 		CAP0IF
r 		UPIF
r 		REPIF
r 		CMP3IF
r 		CMP2IF
r 		CMP1IF
r 		CMP0IF
r
Toggle Fields.

CMP0IF

Bit 0: Compare 0 interrupt flag.

CMP1IF

Bit 1: Compare 1 interrupt flag.

CMP2IF

Bit 2: Compare 2 interrupt flag.

CMP3IF

Bit 3: Compare 3 interrupt flag.

REPIF

Bit 4: Repetition interrupt flag.

UPIF

Bit 6: Update interrupt flag.

CAP0IF

Bit 7: Capture 0 interrupt flag.

CAP1IF

Bit 8: Capture 1 interrupt flag.

CH0OAIF

Bit 9: Channel 0 output active interrupt flag.

CH0ONAIF

Bit 10: Channel 0 output inactive interrupt flag.

CH1OAIF

Bit 11: Channel 1 output active interrupt flag.

CH1ONAIF

Bit 12: Channel 1 output inactive interrupt flag.

RSTIF

Bit 13: Counter reset interrupt flag.

DLYIIF

Bit 14: Delayed IDLE mode entry interrupt flag.

CBLNF

Bit 16: Current balanced flag.

BLNIF

Bit 17: Balanced IDLE flag.

CH0F

Bit 20: Channel 0 output flag.

CH1F

Bit 21: Channel 1 output flag.

ST2INTC

SHRTIMER Slave_TIMERx interrupt flag clear register

Offset: 0x8, reset: 0x00000000, access: write-only

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYIIFC
w 		RSTIFC
w 		CH1ONAIFC
w 		CH1OAIFC
w 		CH0ONAIFC
w 		CH0OAIFC
w 		CAP1IFC
w 		CAP0IFC
w 		UPIFC
w 		REPIFC
w 		CMP3IFC
w 		CMP2IFC
w 		CMP1IFC
w 		CMP0IFC
w
Toggle Fields.

CMP0IFC

Bit 0: Clear compare 0 interrupt flag.

CMP1IFC

Bit 1: Clear compare 1 interrupt flag.

CMP2IFC

Bit 2: Clear compare 2 interrupt flag.

CMP3IFC

Bit 3: Clear compare 3 interrupt flag.

REPIFC

Bit 4: Clear repetition interrupt flag.

UPIFC

Bit 6: Clear update interrupt flag.

CAP0IFC

Bit 7: Clear capture 0 interrupt flag.

CAP1IFC

Bit 8: Clear capture 1 interrupt flag.

CH0OAIFC

Bit 9: Clear channel 0 output active interrupt flag.

CH0ONAIFC

Bit 10: Clear channel 0 output inactive interrupt flag.

CH1OAIFC

Bit 11: Clear channel 1 output active interrupt flag.

CH1ONAIFC

Bit 12: Clear channel 1 output inactive interrupt flag.

RSTIFC

Bit 13: Clear counter reset interrupt flag.

DLYIIFC

Bit 14: Clear delayed IDLE mode entry interrupt flag.

ST2DMAINTEN

SHRTIMER Slave_TIMERx DMA and interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYIDEN
rw 		RSTDEN
rw 		CH1ONADEN
rw 		CH1OADEN
rw 		CH0ONADEN
rw 		CH0ADEN
rw 		CAP1DEN
rw 		CAP0DEN
rw 		UPDEN
rw 		REPDEN
rw 		CMP3DEN
rw 		CMP2DEN
rw 		CMP1DEN
rw 		CMP0DEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYIIE
rw 		RSTIE
rw 		CH1ONAIE
rw 		CH1OAIE
rw 		CH0ONAIE
rw 		CH0OAIE
rw 		CAP1IE
rw 		CAP0IE
rw 		UPIE
rw 		REPIE
rw 		CMP3IE
rw 		CMP2IE
rw 		CMP1IE
rw 		CMP0IE
rw
Toggle Fields.

CMP0IE

Bit 0: Compare 0 interrupt enable.

CMP1IE

Bit 1: Compare 1 interrupt enable.

CMP2IE

Bit 2: Compare 2 interrupt enable.

CMP3IE

Bit 3: Compare 3 interrupt enable.

REPIE

Bit 4: Repetition interrupt enable.

UPIE

Bit 6: Update interrupt enable.

CAP0IE

Bit 7: Capture 0 interrupt enable.

CAP1IE

Bit 8: Capture 1 interrupt enable.

CH0OAIE

Bit 9: Channel 0 output active interrupt enable.

CH0ONAIE

Bit 10: Channel 0 output inactive interrupt enable.

CH1OAIE

Bit 11: Channel 1 output active interrupt enable.

CH1ONAIE

Bit 12: Channel 1 output inactive interrupt enable.

RSTIE

Bit 13: Counter reset interrupt enable.

DLYIIE

Bit 14: Delayed IDLE mode entry interrupt enable.

CMP0DEN

Bit 16: Compare 0 DMA request enable.

CMP1DEN

Bit 17: Compare 1 DMA request enable.

CMP2DEN

Bit 18: Compare 2 DMA request enable.

CMP3DEN

Bit 19: Compare 3 DMA request enable.

REPDEN

Bit 20: Repetition DMA request enable.

UPDEN

Bit 22: Update DMA request enable.

CAP0DEN

Bit 23: Capture 0 DMA request enable.

CAP1DEN

Bit 24: Capture 1 DMA request enable.

CH0ADEN

Bit 25: Channel 0 output active DMA request enable.

CH0ONADEN

Bit 26: Channel 0 output inactive DMA request enable.

CH1OADEN

Bit 27: Channel 1 output active DMA request enable.

CH1ONADEN

Bit 28: Channel 1 output inactive DMA request enable.

RSTDEN

Bit 29: Counter reset DMA request enable.

DLYIDEN

Bit 30: Delayed IDLE mode entry DMA request enable.

ST2CNT

SHRTIMER Slave_TIMERx counter register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: The current counter value.

ST2CAR

SHRTIMER Slave_TIMER2 counter auto reload register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARL
rw
Toggle Fields.

CARL

Bits 0-15: Counter auto reload value.

ST2CREP

SHRTIMER Slave_TIMER2 counter repetition register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CREP
rw
Toggle Fields.

CREP

Bits 0-7: Counter repetition value.

ST2CMP0V

SHRTIMER Slave_TIMER2 compare 0 value register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP0VAL
rw
Toggle Fields.

CMP0VAL

Bits 0-15: Compare 0 value.

ST2CMP0CP

SHRTIMER Slave_TIMERx compare 0 composite register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CREP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP0VAL
rw
Toggle Fields.

CMP0VAL

Bits 0-15: Compare 0 value.

CREP

Bits 16-23: Counter repetition value.

ST2CMP1V

SHRTIMER Slave_TIMERx compare 1 value register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP1VAL
rw
Toggle Fields.

CMP1VAL

Bits 0-15: Compare 1 value.

ST2CMP2V

SHRTIMER Slave_TIMERx compare 2 value register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP2VAL
rw
Toggle Fields.

CMP2VAL

Bits 0-15: Compare 2 value.

ST2CMP3V

SHRTIMER Slave_TIMERx compare 3 value register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP3VAL
rw
Toggle Fields.

CMP3VAL

Bits 0-15: Compare 3 value.

ST2CAP0V

SHRTIMER Slave_TIMERx capture 0 value register

Offset: 0x30, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAP0VAL
rw
Toggle Fields.

CAP0VAL

Bits 0-15: Capture 0 value.

ST2CAP1V

SHRTIMER Slave_TIMERx capture 1 value register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAP1VAL
rw
Toggle Fields.

CAP1VAL

Bits 0-15: Capture 1 value.

ST2DTCTL

SHRTIMER Slave_TIMERx dead-time control register

Offset: 0x38, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFSVPROT
rw 		DTFSPROT
rw 		DTFS
rw 		DTFCFG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTRSVPROT
rw 		DTRSPROT
rw 		DTGCKDIV
rw 		DTRS
rw 		DTRCFG
rw
Toggle Fields.

DTRCFG

Bits 0-8: Falling edge dead-time value.

DTRS

Bit 9: The sign of falling edge dead-time value.

DTGCKDIV

Bits 10-13: Dead time generator clock division.

DTRSPROT

Bit 14: Dead-time rising edge protection for sign.

DTRSVPROT

Bit 15: Dead-time rising edge protection for value and sign.

DTFCFG

Bits 16-24: Falling edge dead-time value.

DTFS

Bit 25: The sign of falling edge dead-time value.

DTFSPROT

Bit 30: Dead-time falling edge protection for sign.

DTFSVPROT

Bit 31: Dead-time falling edge protection for value and sign.

ST2CH0SET

SHRTIMER Slave_TIMERx channel 0 set request register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH0SUP
rw 		CH0SEXEV9
rw 		CH0SEXEV8
rw 		CH0SEXEV7
rw 		CH0SEXEV6
rw 		CH0SEXEV5
rw 		CH0SEXEV4
rw 		CH0SEXEV3
rw 		CH0SEXEV2
rw 		CH0SEXEV1
rw 		CH0SEXEV0
rw 		CH0SSTEV8
rw 		CH0SSTEV7
rw 		CH0SSTEV6
rw 		CH0SSTEV5
rw 		CH0SSTEV4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0SSTEV3
rw 		CH0SSTEV2
rw 		CH0SSTEV1
rw 		CH0SSTEV0
rw 		CH0SMTCMP3
rw 		CH0SMTCMP2
rw 		CH0SMTCMP1
rw 		CH0SMTCMP0
rw 		CH0SMTPER
rw 		CH0SCMP3
rw 		CH0SCMP2
rw 		CH0SCMP1
rw 		CH0SCMP0
rw 		CH0SPER
rw 		CH0SRST
rw 		CH0SSEV
rw
Toggle Fields.

CH0SSEV

Bit 0: Software event generates channel 0 .

CH0SRST

Bit 1: Slave_TIMERx reset event generates channel 0 .

CH0SPER

Bit 2: Slave_TIMERx period event generates channel 0 .

CH0SCMP0

Bit 3: Slave_TIMERx compare 0 event generates channel 0 .

CH0SCMP1

Bit 4: Slave_TIMERx compare 1 event generates channel 0 .

CH0SCMP2

Bit 5: Slave_TIMERx compare 2 event generates channel 0 .

CH0SCMP3

Bit 6: Slave_TIMERx compare 3 event generates channel 0 .

CH0SMTPER

Bit 7: Master_TIMER period event generates channel 0 .

CH0SMTCMP0

Bit 8: Master_TIMER compare 0 event generates channel 0 .

CH0SMTCMP1

Bit 9: Master_TIMER compare 1 event generates channel 0 .

CH0SMTCMP2

Bit 10: Master_TIMER compare 2 event generates channel 0 .

CH0SMTCMP3

Bit 11: Master_TIMER compare 3 event generates channel 0 .

CH0SSTEV0

Bit 12: Slave_TIMERx interconnection event 0 generates channel 0 .

CH0SSTEV1

Bit 13: Slave_TIMERx interconnection event 1 generates channel 0 .

CH0SSTEV2

Bit 14: Slave_TIMERx interconnection event 2 generates channel 0 .

CH0SSTEV3

Bit 15: Slave_TIMERx interconnection event 3 generates channel 0 .

CH0SSTEV4

Bit 16: Slave_TIMERx interconnection event 4 generates channel 0 .

CH0SSTEV5

Bit 17: Slave_TIMERx interconnection event 5 generates channel 0 .

CH0SSTEV6

Bit 18: Slave_TIMERx interconnection event 6 generates channel 0 .

CH0SSTEV7

Bit 19: Slave_TIMER1 interconnection event 7 generates channel 0 .

CH0SSTEV8

Bit 20: Slave_TIMERx interconnection event 8 generates channel 0 .

CH0SEXEV0

Bit 21: External event 0 generates channel 0 .

CH0SEXEV1

Bit 22: External event 1 generates channel 0 .

CH0SEXEV2

Bit 23: External event 2 generates channel 0 .

CH0SEXEV3

Bit 24: External event 3 generates channel 0 .

CH0SEXEV4

Bit 25: External event 4 generates channel 0 .

CH0SEXEV5

Bit 26: External event 5 generates channel 0 .

CH0SEXEV6

Bit 27: External event 6 generates channel 0 .

CH0SEXEV7

Bit 28: External event 7 generates channel 0 .

CH0SEXEV8

Bit 29: External event 8 generates channel 0 .

CH0SEXEV9

Bit 30: External event 9 generates channel 0 .

CH0SUP

Bit 31: Update event generates channel 0 .

ST2CH0RST

SHRTIMER Slave_TIMERx channel 0 reset request register

Offset: 0x40, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH0RSUP
rw 		CH0RSEXEV9
rw 		CH0RSEXEV8
rw 		CH0RSEXEV7
rw 		CH0RSEXEV6
rw 		CH0RSEXEV5
rw 		CH0RSEXEV4
rw 		CH0RSEXEV3
rw 		CH0RSEXEV2
rw 		CH0RSEXEV1
rw 		CH0RSEXEV0
rw 		CH0RSSTEV8
rw 		CH0RSSTEV7
rw 		CH0RSSTEV6
rw 		CH0RSSTEV5
rw 		CH0RSSTEV4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0RSSTEV3
rw 		CH0RSSTEV2
rw 		CH0RSSTEV1
rw 		CH0RSSTEV0
rw 		CH0RSMTCMP3
rw 		CH0RSMTCMP2
rw 		CH0RSMTCMP1
rw 		CH0RSMTCMP0
rw 		CH0RSMTPER
rw 		CH0RSCMP3
rw 		CH0RSCMP2
rw 		CH0RSCMP1
rw 		CH0RSCMP0
rw 		CH0RSPER
rw 		CH0RSRST
rw 		CH0RSSEV
rw
Toggle Fields.

CH0RSSEV

Bit 0: Software event generates channel 0 .

CH0RSRST

Bit 1: Slave_TIMERx reset event generates channel 0 .

CH0RSPER

Bit 2: Slave_TIMERx period event generates channel 0 .

CH0RSCMP0

Bit 3: Slave_TIMERx compare 0 event generates channel 0 .

CH0RSCMP1

Bit 4: Slave_TIMERx compare 1 event generates channel 0 .

CH0RSCMP2

Bit 5: Slave_TIMER1 compare 2 event generates channel 0 .

CH0RSCMP3

Bit 6: Slave_TIMERx compare 3 event generates channel 0 .

CH0RSMTPER

Bit 7: Master_TIMER period event generates channel 0 .

CH0RSMTCMP0

Bit 8: Master_TIMER compare 0 event generates channel 0 .

CH0RSMTCMP1

Bit 9: Master_TIMER compare 1 event generates channel 0 .

CH0RSMTCMP2

Bit 10: Master_TIMER compare 2 event generates channel 0 .

CH0RSMTCMP3

Bit 11: Master_TIMER compare 3 event generates channel 0 .

CH0RSSTEV0

Bit 12: Slave_TIMER1 interconnection event 0 generates channel 0 .

CH0RSSTEV1

Bit 13: Slave_TIMERx interconnection event 1 generates channel 0 .

CH0RSSTEV2

Bit 14: Slave_TIMERx interconnection event 2 generates channel 0 .

CH0RSSTEV3

Bit 15: Slave_TIMERx interconnection event 3 generates channel 0 .

CH0RSSTEV4

Bit 16: Slave_TIMER1 interconnection event 4 generates channel 0 .

CH0RSSTEV5

Bit 17: Slave_TIMERx interconnection event 5 generates channel 0 .

CH0RSSTEV6

Bit 18: Slave_TIMERx interconnection event 6 generates channel 0 .

CH0RSSTEV7

Bit 19: Slave_TIMERx interconnection event 7 generates channel 0 .

CH0RSSTEV8

Bit 20: Slave_TIMERx interconnection event 8 generates channel 0 .

CH0RSEXEV0

Bit 21: External event 0 generates channel 0 .

CH0RSEXEV1

Bit 22: External event 1 generates channel 0 .

CH0RSEXEV2

Bit 23: External event 2 generates channel 0 .

CH0RSEXEV3

Bit 24: External event 3 generates channel 0 .

CH0RSEXEV4

Bit 25: External event 4 generates channel 0 .

CH0RSEXEV5

Bit 26: External event 5 generates channel 0 .

CH0RSEXEV6

Bit 27: External event 6 generates channel 0 .

CH0RSEXEV7

Bit 28: External event 7 generates channel 0 .

CH0RSEXEV8

Bit 29: External event 8 generates channel 0 .

CH0RSEXEV9

Bit 30: External event 9 generates channel 0 .

CH0RSUP

Bit 31: Update event generates channel 0 .

ST2CH1SET

SHRTIMER Slave_TIMERx channel 1 set request register

Offset: 0x44, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1SUP
rw 		CH1SEXEV9
rw 		CH1SEXEV8
rw 		CH1SEXEV7
rw 		CH1SEXEV6
rw 		CH1SEXEV5
rw 		CH1SEXEV4
rw 		CH1SEXEV3
rw 		CH1SEXEV2
rw 		CH1SEXEV1
rw 		CH1SEXEV0
rw 		CH1SSTEV8
rw 		CH1SSTEV7
rw 		CH1SSTEV6
rw 		CH1SSTEV5
rw 		CH1SSTEV4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1SSTEV3
rw 		CH1SSTEV2
rw 		CH1SSTEV1
rw 		CH1SSTEV0
rw 		CH1SMTCMP3
rw 		CH1SMTCMP2
rw 		CH1SMTCMP1
rw 		CH1SMTCMP0
rw 		CH1SMTPER
rw 		CH1SCMP3
rw 		CH1SCMP2
rw 		CH1SCMP1
rw 		CH1SCMP0
rw 		CH1SPER
rw 		CH1SRST
rw 		CH1SSEV
rw
Toggle Fields.

CH1SSEV

Bit 0: Software event generates channel 1 .

CH1SRST

Bit 1: Slave_TIMERx reset event generates channel 1 .

CH1SPER

Bit 2: Slave_TIMERx period event generates channel 1 .

CH1SCMP0

Bit 3: Slave_TIMERx compare 0 event generates channel 1 .

CH1SCMP1

Bit 4: Slave_TIMERx compare 1 event generates channel 1 .

CH1SCMP2

Bit 5: Slave_TIMERx compare 2 event generates channel 1 .

CH1SCMP3

Bit 6: Slave_TIMERx compare 3 event generates channel 1 .

CH1SMTPER

Bit 7: Master_TIMER period event generates channel 1 .

CH1SMTCMP0

Bit 8: Master_TIMER compare 0 event generates channel 1 .

CH1SMTCMP1

Bit 9: Master_TIMER compare 1 event generates channel 1 .

CH1SMTCMP2

Bit 10: Master_TIMER compare 2 event generates channel 1 .

CH1SMTCMP3

Bit 11: Master_TIMER compare 3 event generates channel 1 .

CH1SSTEV0

Bit 12: Slave_TIMERx interconnection event 0 generates channel 1 .

CH1SSTEV1

Bit 13: Slave_TIMERx interconnection event 1 generates channel 1 .

CH1SSTEV2

Bit 14: Slave_TIMERx interconnection event 2 generates channel 1 .

CH1SSTEV3

Bit 15: Slave_TIMERx interconnection event 3 generates channel 1 .

CH1SSTEV4

Bit 16: Slave_TIMERx interconnection event 4 generates channel 1 .

CH1SSTEV5

Bit 17: Slave_TIMERx interconnection event 5 generates channel 1 .

CH1SSTEV6

Bit 18: Slave_TIMERx interconnection event 6 generates channel 1 .

CH1SSTEV7

Bit 19: Slave_TIMERx interconnection event 7 generates channel 1 .

CH1SSTEV8

Bit 20: Slave_TIMERx interconnection event 8 generates channel 1 .

CH1SEXEV0

Bit 21: External event 0 generates channel 1 .

CH1SEXEV1

Bit 22: External event 1 generates channel 1 .

CH1SEXEV2

Bit 23: External event 2 generates channel 1 .

CH1SEXEV3

Bit 24: External event 3 generates channel 1 .

CH1SEXEV4

Bit 25: External event 4 generates channel 1 .

CH1SEXEV5

Bit 26: External event 5 generates channel 1 .

CH1SEXEV6

Bit 27: External event 6 generates channel 1 .

CH1SEXEV7

Bit 28: External event 7 generates channel 1 .

CH1SEXEV8

Bit 29: External event 8 generates channel 1 .

CH1SEXEV9

Bit 30: External event 9 generates channel 1 .

CH1SUP

Bit 31: Update event generates channel 1 .

ST2CH1RST

SHRTIMER Slave_TIMERx channel 1 reset request register

Offset: 0x48, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1RSUP
rw 		CH1RSEXEV9
rw 		CH1RSEXEV8
rw 		CH1RSEXEV7
rw 		CH1RSEXEV6
rw 		CH1RSEXEV5
rw 		CH1RSEXEV4
rw 		CH1RSEXEV3
rw 		CH1RSEXEV2
rw 		CH1RSEXEV1
rw 		CH1RSEXEV0
rw 		CH1RSSTEV8
rw 		CH1RSSTEV7
rw 		CH1RSSTEV6
rw 		CH1RSSTEV5
rw 		CH1RSSTEV4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1RSSTEV3
rw 		CH1RSSTEV2
rw 		CH1RSSTEV1
rw 		CH1RSSTEV0
rw 		CH1RSMTCMP3
rw 		CH1RSMTCMP2
rw 		CH1RSMTCMP1
rw 		CH1RSMTCMP0
rw 		CH1RSMTPER
rw 		CH1RSCMP3
rw 		CH1RSCMP2
rw 		CH1RSCMP1
rw 		CH1RSCMP0
rw 		CH1RSPER
rw 		CH1RSRST
rw 		CH1RSSEV
rw
Toggle Fields.

CH1RSSEV

Bit 0: Software event generates channel 1 .

CH1RSRST

Bit 1: Slave_TIMERx reset event generates channel 1 .

CH1RSPER

Bit 2: Slave_TIMERx period event generates channel 1 .

CH1RSCMP0

Bit 3: Slave_TIMERx compare 0 event generates channel 1 .

CH1RSCMP1

Bit 4: Slave_TIMERx compare 1 event generates channel 1 .

CH1RSCMP2

Bit 5: Slave_TIMERx compare 2 event generates channel 1 .

CH1RSCMP3

Bit 6: Slave_TIMERx compare 3 event generates channel 1 .

CH1RSMTPER

Bit 7: Master_TIMER period event generates channel 1 .

CH1RSMTCMP0

Bit 8: Master_TIMER compare 0 event generates channel 1 .

CH1RSMTCMP1

Bit 9: Master_TIMER compare 1 event generates channel 1 .

CH1RSMTCMP2

Bit 10: Master_TIMER compare 2 event generates channel 1 .

CH1RSMTCMP3

Bit 11: Master_TIMER compare 3 event generates channel 1 .

CH1RSSTEV0

Bit 12: Slave_TIMERx interconnection event 0 generates channel 1 .

CH1RSSTEV1

Bit 13: Slave_TIMERx interconnection event 1 generates channel 1 .

CH1RSSTEV2

Bit 14: Slave_TIMERx interconnection event 2 generates channel 1 .

CH1RSSTEV3

Bit 15: Slave_TIMERx interconnection event 3 generates channel 1 .

CH1RSSTEV4

Bit 16: Slave_TIMERx interconnection event 4 generates channel 1 .

CH1RSSTEV5

Bit 17: Slave_TIMERx interconnection event 5 generates channel 1 .

CH1RSSTEV6

Bit 18: Slave_TIMERx interconnection event 6 generates channel 1 .

CH1RSSTEV7

Bit 19: Slave_TIMERx interconnection event 7 generates channel 1 .

CH1RSSTEV8

Bit 20: Slave_TIMERx interconnection event 8 generates channel 1 .

CH1RSEXEV0

Bit 21: External event 0 generates channel 1 .

CH1RSEXEV1

Bit 22: External event 1 generates channel 1 .

CH1RSEXEV2

Bit 23: External event 2 generates channel 1 .

CH1RSEXEV3

Bit 24: External event 3 generates channel 1 .

CH1RSEXEV4

Bit 25: External event 4 generates channel 1 .

CH1RSEXEV5

Bit 26: External event 5 generates channel 1 .

CH1RSEXEV6

Bit 27: External event 6 generates channel 1 .

CH1RSEXEV7

Bit 28: External event 7 generates channel 1 .

CH1RSEXEV8

Bit 29: External event 8 generates channel 1 .

CH1RSEXEV9

Bit 30: External event 9 generates channel 1 .

CH1RSUP

Bit 31: Update event generates channel 1 .

ST2EXEVFCFG0

SHRTIMER Slave_TIMERx external event filter configuration register 0

Offset: 0x4C, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXEV4FM
rw 		EXEV4MEEN
rw 		EXEV3FM
rw 		EXEV3MEEN
rw 		EXEV2FM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXEV2FM
rw 		EXEV2MEEN
rw 		EXEV1FM
rw 		EXEV1MEEN
rw 		EXEV0FM
rw 		EXEV0MEEN
rw
Toggle Fields.

EXEV0MEEN

Bit 0: External event 0 memorized enable.

EXEV0FM

Bits 1-4: External event 0 filter mode.

EXEV1MEEN

Bit 6: External event 1 memorized enable.

EXEV1FM

Bits 7-10: External event 1 filter mode.

EXEV2MEEN

Bit 12: External event 2 memorized enable.

EXEV2FM

Bits 13-16: External event 2 filter mode.

EXEV3MEEN

Bit 18: External event 3 memorized enable.

EXEV3FM

Bits 19-22: External event 3 filter mode.

EXEV4MEEN

Bit 24: External event 4 memorized enable.

EXEV4FM

Bits 25-28: External event 4 filter mode.

ST2EXEVFCFG1

SHRTIMER Slave_TIMERx external event filter configuration register 1

Offset: 0x50, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXEV9FM
rw 		EXEV9MEEN
rw 		EXEV8FM
rw 		EXEV8MEEN
rw 		EXEV7FM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXEV7FM
rw 		EXEV7MEEN
rw 		EXEV6FM
rw 		EXEV6MEEN
rw 		EXEV5FM
rw 		EXEV5MEEN
rw
Toggle Fields.

EXEV5MEEN

Bit 0: External event 5 memorized enable.

EXEV5FM

Bits 1-4: External event 5 filter mode.

EXEV6MEEN

Bit 6: External event 6 memorized enable.

EXEV6FM

Bits 7-10: External event 6 filter mode.

EXEV7MEEN

Bit 12: External event 7 memorized enable.

EXEV7FM

Bits 13-16: External event 7 filter mode.

EXEV8MEEN

Bit 18: External event 8 memorized enable.

EXEV8FM

Bits 19-22: External event 8 filter mode.

EXEV9MEEN

Bit 24: External event 9 memorized enable.

EXEV9FM

Bits 25-28: External event 9 filter mode.

ST2CNTRST

SHRTIMER Slave_TIMERx counter reset register

Offset: 0x54, reset: 0x00000000, access: read-write

0/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ST4CMP3RST
rw 		ST4CMP1RST
rw 		ST4CMP0RST
rw 		ST3CMP3RST
rw 		ST3CMP1RST
rw 		ST3CMP0RST
rw 		ST1CMP3RST
rw 		ST1CMP1RST
rw 		ST1CMP0RST
rw 		ST0CMP3RST
rw 		ST0CMP1RST
rw 		ST0CMP0RST
rw 		EXEV9RST
rw 		EXEV8RST
rw 		EXEV7RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXEV6RST
rw 		EXEV5RST
rw 		EXEV4RST
rw 		EXEV3RST
rw 		EXEV2RST
rw 		EXEV1RST
rw 		EXEV0RST
rw 		MTCMP3RST
rw 		MTCMP2RST
rw 		MTCMP1RST
rw 		MTCMP0RST
rw 		MTPERRST
rw 		CMP3RST
rw 		CMP1RST
rw 		UPRST
rw
Toggle Fields.

UPRST

Bit 1: Slave_TIMER2 update event resets counter.

CMP1RST

Bit 2: Slave_TIMER2 compare 1 event resets counter.

CMP3RST

Bit 3: Slave_TIMER2 compare 3 event resets counter.

MTPERRST

Bit 4: Master_TIMER period event resets counter.

MTCMP0RST

Bit 5: Master_TIMER compare 0 event resets counter.

MTCMP1RST

Bit 6: Master_TIMER compare 1 event resets counter.

MTCMP2RST

Bit 7: Master_TIMER compare 2 event resets counter.

MTCMP3RST

Bit 8: Master_TIMER compare 3 event resets counter.

EXEV0RST

Bit 9: External event 0 resets counter.

EXEV1RST

Bit 10: External event 1 resets counter.

EXEV2RST

Bit 11: External event 2 resets counter.

EXEV3RST

Bit 12: External event 3 resets counter.

EXEV4RST

Bit 13: External event 4 resets counter.

EXEV5RST

Bit 14: External event 5 resets counter.

EXEV6RST

Bit 15: External event 6 resets counter.

EXEV7RST

Bit 16: External event 7 resets counter.

EXEV8RST

Bit 17: External event 8 resets counter.

EXEV9RST

Bit 18: External event 9 resets counter.

ST0CMP0RST

Bit 19: Slave_TIMER0 compare 0 event resets counter.

ST0CMP1RST

Bit 20: Slave_TIMER0 compare 1 event resets counter.

ST0CMP3RST

Bit 21: Slave_TIMER0 compare 3 event resets counter.

ST1CMP0RST

Bit 22: Slave_TIMER1 compare 0 event resets counter.

ST1CMP1RST

Bit 23: Slave_TIMER1 compare 1 event resets counter.

ST1CMP3RST

Bit 24: Slave_TIMER1 compare 3 event resets counter.

ST3CMP0RST

Bit 25: Slave_TIMER3 compare 0 event resets counter.

ST3CMP1RST

Bit 26: Slave_TIMER3 compare 1 event resets counter.

ST3CMP3RST

Bit 27: Slave_TIMER3 compare 3 event resets counter.

ST4CMP0RST

Bit 28: Slave_TIMER4 compare 0 event resets counter.

ST4CMP1RST

Bit 29: Slave_TIMER4 compare 1 event resets counter.

ST4CMP3RST

Bit 30: Slave_TIMER4 compare 3 event resets counter.

ST2CSCTL

SHRTIMER Slave_TIMERx carrier-signal control register

Offset: 0x58, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSFSTPW
rw 		CSDTY
rw 		CSPRD
rw
Toggle Fields.

CSPRD

Bits 0-3: Carrier signal period.

CSDTY

Bits 4-6: Carrier signal duty cycle.

CSFSTPW

Bits 7-10: First carrier-signal pulse width.

ST2CAP0TRG

SHRTIMER Slave_TIMERx capture 0 trigger register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CP0BST2CMP1
rw 		CP0BST2CMP0
rw 		CP0BST2NA
rw 		CP0BST2A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CP0BEXEV9
rw 		CP0BEXEV8
rw 		CP0BEXEV7
rw 		CP0BEXEV6
rw 		CP0BEXEV5
rw 		CP0BEXEV4
rw 		CP0BEXEV3
rw 		CP0BEXEV2
rw 		CP0BEXEV1
rw 		CP0BEXEV0
rw 		CP0BUP
rw 		CP0BSW
rw
Toggle Fields.

CP0BSW

Bit 0: Capture 0 triggered by software.

CP0BUP

Bit 1: Capture 0 triggered by update event.

CP0BEXEV0

Bit 2: Capture 0 triggered by external event 0.

CP0BEXEV1

Bit 3: Capture 0 triggered by external event 1.

CP0BEXEV2

Bit 4: Capture 0 triggered by external event 2.

CP0BEXEV3

Bit 5: Capture 0 triggered by external event 3.

CP0BEXEV4

Bit 6: Capture 0 triggered by external event 4.

CP0BEXEV5

Bit 7: Capture 0 triggered by external event 5.

CP0BEXEV6

Bit 8: Capture 0 triggered by external event 6.

CP0BEXEV7

Bit 9: Capture 0 triggered by external event 7.

CP0BEXEV8

Bit 10: Capture 0 triggered by external event 8.

CP0BEXEV9

Bit 11: Capture 0 triggered by external event 9.

CP0BST2A

Bit 20: Capture 0 triggered by ST2CH0_O output inactive to active transition.

CP0BST2NA

Bit 21: Capture 0 triggered by ST2CH0_O output active to inactive transition.

CP0BST2CMP0

Bit 22: Capture 0 triggered by compare 0 event of Slave_TIMER2.

CP0BST2CMP1

Bit 23: Capture 0 triggered by compare 1 event of Slave_TIMER2.

ST2CAP1TRG

SHRTIMER Slave_TIMERx capture 1 trigger register

Offset: 0x60, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CP1BST2CMP1
rw 		CP1BST2CMP0
rw 		CP1BST2NA
rw 		CP1BST2A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CP1BEXEV9
rw 		CP1BEXEV8
rw 		CP1BEXEV7
rw 		CP1BEXEV6
rw 		CP1BEXEV5
rw 		CP1BEXEV4
rw 		CP1BEXEV3
rw 		CP1BEXEV2
rw 		CP1BEXEV1
rw 		CP1BEXEV0
rw 		CP1BUP
rw 		CP1BSW
rw
Toggle Fields.

CP1BSW

Bit 0: Capture 1 triggered by software.

CP1BUP

Bit 1: Capture 1 triggered by update event.

CP1BEXEV0

Bit 2: Capture 1 triggered by external event 0.

CP1BEXEV1

Bit 3: Capture 1 triggered by external event 1.

CP1BEXEV2

Bit 4: Capture 1 triggered by external event 2.

CP1BEXEV3

Bit 5: Capture 1 triggered by external event 3.

CP1BEXEV4

Bit 6: Capture 1 triggered by external event 4.

CP1BEXEV5

Bit 7: Capture 1 triggered by external event 5.

CP1BEXEV6

Bit 8: Capture 1 triggered by external event 6.

CP1BEXEV7

Bit 9: Capture 1 triggered by external event 7.

CP1BEXEV8

Bit 10: Capture 1 triggered by external event 8.

CP1BEXEV9

Bit 11: Capture 1 triggered by external event 9.

CP1BST2A

Bit 20: Capture 1 triggered by ST2CH0_O output inactive to active transition.

CP1BST2NA

Bit 21: Capture 1 triggered by ST2CH0_O output active to inactive transition.

CP1BST2CMP0

Bit 22: Capture 1 triggered by compare 0 event of Slave_TIMER2.

CP1BST2CMP1

Bit 23: Capture 1 triggered by compare 1 event of Slave_TIMER2.

ST2CHOCTL

SHRTIMER Slave_TIMERx channel output control register

Offset: 0x64, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BMCH1DTI
rw 		CH1CSEN
rw 		CH1FLTOS
rw 		ISO1
rw 		BMCH1IEN
rw 		CH1P
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYISCH
rw 		DLYISMEN
rw 		DTEN
rw 		BMCH0DTI
rw 		CH0CSEN
rw 		CH0FLTOS
rw 		ISO0
rw 		BMCH0IEN
rw 		CH0P
rw
Toggle Fields.

CH0P

Bit 1: Channel 0 output polarity.

BMCH0IEN

Bit 2: Channel 0 IDLE state enable in bunch mode.

ISO0

Bit 3: Channel 0 output idle state.

CH0FLTOS

Bits 4-5: Channel 0 Fault output state.

CH0CSEN

Bit 6: Channel 0 carrier-signal mode enable.

BMCH0DTI

Bit 7: Channel 0 dead-time insert in bunch mode.

DTEN

Bit 8: Dead time enable.

DLYISMEN

Bit 9: Delayed IDLE state mode enable.

DLYISCH

Bits 10-12: Delayed IDLE source and channel.

CH1P

Bit 17: Channel 1 output polarity.

BMCH1IEN

Bit 18: Channel 1 IDLE state enable in bunch mode.

ISO1

Bit 19: channel 1 output idle state.

CH1FLTOS

Bits 20-21: Channel 1 Fault output state.

CH1CSEN

Bit 22: Channel 1 carrier-signal mode enable.

BMCH1DTI

Bit 23: Channel 1 dead-time insert in bunch mode.

ST2FLTCTL

SHRTIMER Slave_TIMERx fault control register

Offset: 0x68, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTENPROT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT4EN
rw 		FLT3EN
rw 		FLT2EN
rw 		FLT1EN
rw 		FLT0EN
rw
Toggle Fields.

FLT0EN

Bit 0: Fault 0 enable.

FLT1EN

Bit 1: Fault 1 enable.

FLT2EN

Bit 2: Fault 2 enable.

FLT3EN

Bit 3: Fault 3 enable.

FLT4EN

Bit 4: Fault 4 enable.

FLTENPROT

Bit 31: Protect fault enable.

ST2ACTL

SHRTIMER Slave_TIMERx additional control register

Offset: 0x7C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFCFG_15_9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTRCFG_15_9
rw 		CNTCKDIV_3
rw
Toggle Fields.

CNTCKDIV_3

Bit 3: Counter clock division.

DTRCFG_15_9

Bits 9-15: Rising edge dead-time value configure.

DTFCFG_15_9

Bits 25-31: Falling edge dead-time value configure.

SLAVE_TIMER3

0x40017600: SHRTIMER Slave TIMER3 registers(

18/336 fields covered. Toggle Registers.

ST3CTL0

SHRTIMER Slave_TIMERx control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPSEL
rw 		SHWEN
rw 		DACTRGS
rw 		UPBMT
rw 		UPBST4
rw 		UPBST2
rw 		UPBST1
rw 		UPBST0
rw 		UPRST
rw 		UPREP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DELCMP3M
rw 		DELCMP1M
rw 		SYNISTRT
rw 		SYNIRST
rw 		BLNMEN
rw 		HALFM
rw 		CNTRSTM
rw 		CTNM
rw 		CNTCKDIV
rw
Toggle Fields.

CNTCKDIV

Bits 0-2: Counter clock division.

CTNM

Bit 3: Continuous mode.

CNTRSTM

Bit 4: Counter reset mode.

HALFM

Bit 5: Half mode.

BLNMEN

Bit 6: Balanced mode enable.

SYNIRST

Bit 10: Synchronization input reset counter.

SYNISTRT

Bit 11: Synchronization input start counter.

DELCMP1M

Bits 12-13: Compare 1 delayed mode.

DELCMP3M

Bits 14-15: Compare 3 delayed mode.

UPREP

Bit 17: Update event generated by repetition event.

UPRST

Bit 18: Update event generated by reset event.

UPBST0

Bit 19: Update by Slave_TIMER0 update event.

UPBST1

Bit 20: Update by Slave_TIMER1 update event.

UPBST2

Bit 21: Update by Slave_TIMER2 update event.

UPBST4

Bit 23: Update by Slave_TIMER4 update event.

UPBMT

Bit 24: Update by Master_TIMER update event.

DACTRGS

Bits 25-26: Trigger source to DAC.

SHWEN

Bit 27: Shadow registers enable.

UPSEL

Bits 28-31: Update event selection.

ST3INTF

SHRTIMER Slave_TIMERx interrupt flag register

Offset: 0x4, reset: 0x00000000, access: read-only

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1F
r 		CH0F
r 		BLNIF
r 		CBLNF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYIIF
r 		RSTIF
r 		CH1ONAIF
r 		CH1OAIF
r 		CH0ONAIF
r 		CH0OAIF
r 		CAP1IF
r 		CAP0IF
r 		UPIF
r 		REPIF
r 		CMP3IF
r 		CMP2IF
r 		CMP1IF
r 		CMP0IF
r
Toggle Fields.

CMP0IF

Bit 0: Compare 0 interrupt flag.

CMP1IF

Bit 1: Compare 1 interrupt flag.

CMP2IF

Bit 2: Compare 2 interrupt flag.

CMP3IF

Bit 3: Compare 3 interrupt flag.

REPIF

Bit 4: Repetition interrupt flag.

UPIF

Bit 6: Update interrupt flag.

CAP0IF

Bit 7: Capture 0 interrupt flag.

CAP1IF

Bit 8: Capture 1 interrupt flag.

CH0OAIF

Bit 9: Channel 0 output active interrupt flag.

CH0ONAIF

Bit 10: Channel 0 output inactive interrupt flag.

CH1OAIF

Bit 11: Channel 1 output active interrupt flag.

CH1ONAIF

Bit 12: Channel 1 output inactive interrupt flag.

RSTIF

Bit 13: Counter reset interrupt flag.

DLYIIF

Bit 14: Delayed IDLE mode entry interrupt flag.

CBLNF

Bit 16: Current balanced flag.

BLNIF

Bit 17: Balanced IDLE flag.

CH0F

Bit 20: Channel 0 output flag.

CH1F

Bit 21: Channel 1 output flag.

ST3INTC

SHRTIMER Slave_TIMERx interrupt flag clear register

Offset: 0x8, reset: 0x00000000, access: write-only

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYIIFC
w 		RSTIFC
w 		CH1ONAIFC
w 		CH1OAIFC
w 		CH0ONAIFC
w 		CH0OAIFC
w 		CAP1IFC
w 		CAP0IFC
w 		UPIFC
w 		REPIFC
w 		CMP3IFC
w 		CMP2IFC
w 		CMP1IFC
w 		CMP0IFC
w
Toggle Fields.

CMP0IFC

Bit 0: Clear compare 0 interrupt flag.

CMP1IFC

Bit 1: Clear compare 1 interrupt flag.

CMP2IFC

Bit 2: Clear compare 2 interrupt flag.

CMP3IFC

Bit 3: Clear compare 3 interrupt flag.

REPIFC

Bit 4: Clear repetition interrupt flag.

UPIFC

Bit 6: Clear update interrupt flag.

CAP0IFC

Bit 7: Clear capture 0 interrupt flag.

CAP1IFC

Bit 8: Clear capture 1 interrupt flag.

CH0OAIFC

Bit 9: Clear channel 0 output active interrupt flag.

CH0ONAIFC

Bit 10: Clear channel 0 output inactive interrupt flag.

CH1OAIFC

Bit 11: Clear channel 1 output active interrupt flag.

CH1ONAIFC

Bit 12: Clear channel 1 output inactive interrupt flag.

RSTIFC

Bit 13: Clear counter reset interrupt flag.

DLYIIFC

Bit 14: Clear delayed IDLE mode entry interrupt flag.

ST3DMAINTEN

SHRTIMER Slave_TIMERx DMA and interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYIDEN
rw 		RSTDEN
rw 		CH1ONADEN
rw 		CH1OADEN
rw 		CH0ONADEN
rw 		CH0ADEN
rw 		CAP1DEN
rw 		CAP0DEN
rw 		UPDEN
rw 		REPDEN
rw 		CMP3DEN
rw 		CMP2DEN
rw 		CMP1DEN
rw 		CMP0DEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYIIE
rw 		RSTIE
rw 		CH1ONAIE
rw 		CH1OAIE
rw 		CH0ONAIE
rw 		CH0OAIE
rw 		CAP1IE
rw 		CAP0IE
rw 		UPIE
rw 		REPIE
rw 		CMP3IE
rw 		CMP2IE
rw 		CMP1IE
rw 		CMP0IE
rw
Toggle Fields.

CMP0IE

Bit 0: Compare 0 interrupt enable.

CMP1IE

Bit 1: Compare 1 interrupt enable.

CMP2IE

Bit 2: Compare 2 interrupt enable.

CMP3IE

Bit 3: Compare 3 interrupt enable.

REPIE

Bit 4: Repetition interrupt enable.

UPIE

Bit 6: Update interrupt enable.

CAP0IE

Bit 7: Capture 0 interrupt enable.

CAP1IE

Bit 8: Capture 1 interrupt enable.

CH0OAIE

Bit 9: Channel 0 output active interrupt enable.

CH0ONAIE

Bit 10: Channel 0 output inactive interrupt enable.

CH1OAIE

Bit 11: Channel 1 output active interrupt enable.

CH1ONAIE

Bit 12: Channel 1 output inactive interrupt enable.

RSTIE

Bit 13: Counter reset interrupt enable.

DLYIIE

Bit 14: Delayed IDLE mode entry interrupt enable.

CMP0DEN

Bit 16: Compare 0 DMA request enable.

CMP1DEN

Bit 17: Compare 1 DMA request enable.

CMP2DEN

Bit 18: Compare 2 DMA request enable.

CMP3DEN

Bit 19: Compare 3 DMA request enable.

REPDEN

Bit 20: Repetition DMA request enable.

UPDEN

Bit 22: Update DMA request enable.

CAP0DEN

Bit 23: Capture 0 DMA request enable.

CAP1DEN

Bit 24: Capture 1 DMA request enable.

CH0ADEN

Bit 25: Channel 0 output active DMA request enable.

CH0ONADEN

Bit 26: Channel 0 output inactive DMA request enable.

CH1OADEN

Bit 27: Channel 1 output active DMA request enable.

CH1ONADEN

Bit 28: Channel 1 output inactive DMA request enable.

RSTDEN

Bit 29: Counter reset DMA request enable.

DLYIDEN

Bit 30: Delayed IDLE mode entry DMA request enable.

ST3CNT

SHRTIMER Slave_TIMERx counter register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: The current counter value.

ST3CAR

SHRTIMER Slave_TIMER3 counter auto reload register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARL
rw
Toggle Fields.

CARL

Bits 0-15: Counter auto reload value.

ST3CREP

SHRTIMER Slave_TIMER3 counter repetition register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CREP
rw
Toggle Fields.

CREP

Bits 0-7: Counter repetition value.

ST3CMP0V

SHRTIMER Slave_TIMER3 compare 0 value register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP0VAL
rw
Toggle Fields.

CMP0VAL

Bits 0-15: Compare 0 value.

ST3CMP0CP

SHRTIMER Slave_TIMERx compare 0 composite register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CREP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP0VAL
rw
Toggle Fields.

CMP0VAL

Bits 0-15: Compare 0 value.

CREP

Bits 16-23: Counter repetition value.

ST3CMP1V

SHRTIMER Slave_TIMERx compare 1 value register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP1VAL
rw
Toggle Fields.

CMP1VAL

Bits 0-15: Compare 1 value.

ST3CMP2V

SHRTIMER Slave_TIMERx compare 2 value register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP2VAL
rw
Toggle Fields.

CMP2VAL

Bits 0-15: Compare 2 value.

ST3CMP3V

SHRTIMER Slave_TIMERx compare 3 value register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP3VAL
rw
Toggle Fields.

CMP3VAL

Bits 0-15: Compare 3 value.

ST3CAP0V

SHRTIMER Slave_TIMERx capture 0 value register

Offset: 0x30, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAP0VAL
rw
Toggle Fields.

CAP0VAL

Bits 0-15: Capture 0 value.

ST3CAP1V

SHRTIMER Slave_TIMERx capture 1 value register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAP1VAL
rw
Toggle Fields.

CAP1VAL

Bits 0-15: Capture 1 value.

ST3DTCTL

SHRTIMER Slave_TIMERx dead-time control register

Offset: 0x38, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFSVPROT
rw 		DTFSPROT
rw 		DTFS
rw 		DTFCFG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTRSVPROT
rw 		DTRSPROT
rw 		DTGCKDIV
rw 		DTRS
rw 		DTRCFG
rw
Toggle Fields.

DTRCFG

Bits 0-8: Falling edge dead-time value.

DTRS

Bit 9: The sign of falling edge dead-time value.

DTGCKDIV

Bits 10-13: Dead time generator clock division.

DTRSPROT

Bit 14: Dead-time rising edge protection for sign.

DTRSVPROT

Bit 15: Dead-time rising edge protection for value and sign.

DTFCFG

Bits 16-24: Falling edge dead-time value.

DTFS

Bit 25: The sign of falling edge dead-time value.

DTFSPROT

Bit 30: Dead-time falling edge protection for sign.

DTFSVPROT

Bit 31: Dead-time falling edge protection for value and sign.

ST3CH0SET

SHRTIMER Slave_TIMERx channel 0 set request register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH0SUP
rw 		CH0SEXEV9
rw 		CH0SEXEV8
rw 		CH0SEXEV7
rw 		CH0SEXEV6
rw 		CH0SEXEV5
rw 		CH0SEXEV4
rw 		CH0SEXEV3
rw 		CH0SEXEV2
rw 		CH0SEXEV1
rw 		CH0SEXEV0
rw 		CH0SSTEV8
rw 		CH0SSTEV7
rw 		CH0SSTEV6
rw 		CH0SSTEV5
rw 		CH0SSTEV4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0SSTEV3
rw 		CH0SSTEV2
rw 		CH0SSTEV1
rw 		CH0SSTEV0
rw 		CH0SMTCMP3
rw 		CH0SMTCMP2
rw 		CH0SMTCMP1
rw 		CH0SMTCMP0
rw 		CH0SMTPER
rw 		CH0SCMP3
rw 		CH0SCMP2
rw 		CH0SCMP1
rw 		CH0SCMP0
rw 		CH0SPER
rw 		CH0SRST
rw 		CH0SSEV
rw
Toggle Fields.

CH0SSEV

Bit 0: Software event generates channel 0 .

CH0SRST

Bit 1: Slave_TIMERx reset event generates channel 0 .

CH0SPER

Bit 2: Slave_TIMERx period event generates channel 0 .

CH0SCMP0

Bit 3: Slave_TIMERx compare 0 event generates channel 0 .

CH0SCMP1

Bit 4: Slave_TIMERx compare 1 event generates channel 0 .

CH0SCMP2

Bit 5: Slave_TIMERx compare 2 event generates channel 0 .

CH0SCMP3

Bit 6: Slave_TIMERx compare 3 event generates channel 0 .

CH0SMTPER

Bit 7: Master_TIMER period event generates channel 0 .

CH0SMTCMP0

Bit 8: Master_TIMER compare 0 event generates channel 0 .

CH0SMTCMP1

Bit 9: Master_TIMER compare 1 event generates channel 0 .

CH0SMTCMP2

Bit 10: Master_TIMER compare 2 event generates channel 0 .

CH0SMTCMP3

Bit 11: Master_TIMER compare 3 event generates channel 0 .

CH0SSTEV0

Bit 12: Slave_TIMERx interconnection event 0 generates channel 0 .

CH0SSTEV1

Bit 13: Slave_TIMERx interconnection event 1 generates channel 0 .

CH0SSTEV2

Bit 14: Slave_TIMERx interconnection event 2 generates channel 0 .

CH0SSTEV3

Bit 15: Slave_TIMERx interconnection event 3 generates channel 0 .

CH0SSTEV4

Bit 16: Slave_TIMERx interconnection event 4 generates channel 0 .

CH0SSTEV5

Bit 17: Slave_TIMERx interconnection event 5 generates channel 0 .

CH0SSTEV6

Bit 18: Slave_TIMERx interconnection event 6 generates channel 0 .

CH0SSTEV7

Bit 19: Slave_TIMER1 interconnection event 7 generates channel 0 .

CH0SSTEV8

Bit 20: Slave_TIMERx interconnection event 8 generates channel 0 .

CH0SEXEV0

Bit 21: External event 0 generates channel 0 .

CH0SEXEV1

Bit 22: External event 1 generates channel 0 .

CH0SEXEV2

Bit 23: External event 2 generates channel 0 .

CH0SEXEV3

Bit 24: External event 3 generates channel 0 .

CH0SEXEV4

Bit 25: External event 4 generates channel 0 .

CH0SEXEV5

Bit 26: External event 5 generates channel 0 .

CH0SEXEV6

Bit 27: External event 6 generates channel 0 .

CH0SEXEV7

Bit 28: External event 7 generates channel 0 .

CH0SEXEV8

Bit 29: External event 8 generates channel 0 .

CH0SEXEV9

Bit 30: External event 9 generates channel 0 .

CH0SUP

Bit 31: Update event generates channel 0 .

ST3CH0RST

SHRTIMER Slave_TIMERx channel 0 reset request register

Offset: 0x40, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH0RSUP
rw 		CH0RSEXEV9
rw 		CH0RSEXEV8
rw 		CH0RSEXEV7
rw 		CH0RSEXEV6
rw 		CH0RSEXEV5
rw 		CH0RSEXEV4
rw 		CH0RSEXEV3
rw 		CH0RSEXEV2
rw 		CH0RSEXEV1
rw 		CH0RSEXEV0
rw 		CH0RSSTEV8
rw 		CH0RSSTEV7
rw 		CH0RSSTEV6
rw 		CH0RSSTEV5
rw 		CH0RSSTEV4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0RSSTEV3
rw 		CH0RSSTEV2
rw 		CH0RSSTEV1
rw 		CH0RSSTEV0
rw 		CH0RSMTCMP3
rw 		CH0RSMTCMP2
rw 		CH0RSMTCMP1
rw 		CH0RSMTCMP0
rw 		CH0RSMTPER
rw 		CH0RSCMP3
rw 		CH0RSCMP2
rw 		CH0RSCMP1
rw 		CH0RSCMP0
rw 		CH0RSPER
rw 		CH0RSRST
rw 		CH0RSSEV
rw
Toggle Fields.

CH0RSSEV

Bit 0: Software event generates channel 0 .

CH0RSRST

Bit 1: Slave_TIMERx reset event generates channel 0 .

CH0RSPER

Bit 2: Slave_TIMERx period event generates channel 0 .

CH0RSCMP0

Bit 3: Slave_TIMERx compare 0 event generates channel 0 .

CH0RSCMP1

Bit 4: Slave_TIMERx compare 1 event generates channel 0 .

CH0RSCMP2

Bit 5: Slave_TIMER1 compare 2 event generates channel 0 .

CH0RSCMP3

Bit 6: Slave_TIMERx compare 3 event generates channel 0 .

CH0RSMTPER

Bit 7: Master_TIMER period event generates channel 0 .

CH0RSMTCMP0

Bit 8: Master_TIMER compare 0 event generates channel 0 .

CH0RSMTCMP1

Bit 9: Master_TIMER compare 1 event generates channel 0 .

CH0RSMTCMP2

Bit 10: Master_TIMER compare 2 event generates channel 0 .

CH0RSMTCMP3

Bit 11: Master_TIMER compare 3 event generates channel 0 .

CH0RSSTEV0

Bit 12: Slave_TIMER1 interconnection event 0 generates channel 0 .

CH0RSSTEV1

Bit 13: Slave_TIMERx interconnection event 1 generates channel 0 .

CH0RSSTEV2

Bit 14: Slave_TIMERx interconnection event 2 generates channel 0 .

CH0RSSTEV3

Bit 15: Slave_TIMERx interconnection event 3 generates channel 0 .

CH0RSSTEV4

Bit 16: Slave_TIMER1 interconnection event 4 generates channel 0 .

CH0RSSTEV5

Bit 17: Slave_TIMERx interconnection event 5 generates channel 0 .

CH0RSSTEV6

Bit 18: Slave_TIMERx interconnection event 6 generates channel 0 .

CH0RSSTEV7

Bit 19: Slave_TIMERx interconnection event 7 generates channel 0 .

CH0RSSTEV8

Bit 20: Slave_TIMERx interconnection event 8 generates channel 0 .

CH0RSEXEV0

Bit 21: External event 0 generates channel 0 .

CH0RSEXEV1

Bit 22: External event 1 generates channel 0 .

CH0RSEXEV2

Bit 23: External event 2 generates channel 0 .

CH0RSEXEV3

Bit 24: External event 3 generates channel 0 .

CH0RSEXEV4

Bit 25: External event 4 generates channel 0 .

CH0RSEXEV5

Bit 26: External event 5 generates channel 0 .

CH0RSEXEV6

Bit 27: External event 6 generates channel 0 .

CH0RSEXEV7

Bit 28: External event 7 generates channel 0 .

CH0RSEXEV8

Bit 29: External event 8 generates channel 0 .

CH0RSEXEV9

Bit 30: External event 9 generates channel 0 .

CH0RSUP

Bit 31: Update event generates channel 0 .

ST3CH1SET

SHRTIMER Slave_TIMERx channel 1 set request register

Offset: 0x44, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1SUP
rw 		CH1SEXEV9
rw 		CH1SEXEV8
rw 		CH1SEXEV7
rw 		CH1SEXEV6
rw 		CH1SEXEV5
rw 		CH1SEXEV4
rw 		CH1SEXEV3
rw 		CH1SEXEV2
rw 		CH1SEXEV1
rw 		CH1SEXEV0
rw 		CH1SSTEV8
rw 		CH1SSTEV7
rw 		CH1SSTEV6
rw 		CH1SSTEV5
rw 		CH1SSTEV4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1SSTEV3
rw 		CH1SSTEV2
rw 		CH1SSTEV1
rw 		CH1SSTEV0
rw 		CH1SMTCMP3
rw 		CH1SMTCMP2
rw 		CH1SMTCMP1
rw 		CH1SMTCMP0
rw 		CH1SMTPER
rw 		CH1SCMP3
rw 		CH1SCMP2
rw 		CH1SCMP1
rw 		CH1SCMP0
rw 		CH1SPER
rw 		CH1SRST
rw 		CH1SSEV
rw
Toggle Fields.

CH1SSEV

Bit 0: Software event generates channel 1 .

CH1SRST

Bit 1: Slave_TIMERx reset event generates channel 1 .

CH1SPER

Bit 2: Slave_TIMERx period event generates channel 1 .

CH1SCMP0

Bit 3: Slave_TIMERx compare 0 event generates channel 1 .

CH1SCMP1

Bit 4: Slave_TIMERx compare 1 event generates channel 1 .

CH1SCMP2

Bit 5: Slave_TIMERx compare 2 event generates channel 1 .

CH1SCMP3

Bit 6: Slave_TIMERx compare 3 event generates channel 1 .

CH1SMTPER

Bit 7: Master_TIMER period event generates channel 1 .

CH1SMTCMP0

Bit 8: Master_TIMER compare 0 event generates channel 1 .

CH1SMTCMP1

Bit 9: Master_TIMER compare 1 event generates channel 1 .

CH1SMTCMP2

Bit 10: Master_TIMER compare 2 event generates channel 1 .

CH1SMTCMP3

Bit 11: Master_TIMER compare 3 event generates channel 1 .

CH1SSTEV0

Bit 12: Slave_TIMERx interconnection event 0 generates channel 1 .

CH1SSTEV1

Bit 13: Slave_TIMERx interconnection event 1 generates channel 1 .

CH1SSTEV2

Bit 14: Slave_TIMERx interconnection event 2 generates channel 1 .

CH1SSTEV3

Bit 15: Slave_TIMERx interconnection event 3 generates channel 1 .

CH1SSTEV4

Bit 16: Slave_TIMERx interconnection event 4 generates channel 1 .

CH1SSTEV5

Bit 17: Slave_TIMERx interconnection event 5 generates channel 1 .

CH1SSTEV6

Bit 18: Slave_TIMERx interconnection event 6 generates channel 1 .

CH1SSTEV7

Bit 19: Slave_TIMERx interconnection event 7 generates channel 1 .

CH1SSTEV8

Bit 20: Slave_TIMERx interconnection event 8 generates channel 1 .

CH1SEXEV0

Bit 21: External event 0 generates channel 1 .

CH1SEXEV1

Bit 22: External event 1 generates channel 1 .

CH1SEXEV2

Bit 23: External event 2 generates channel 1 .

CH1SEXEV3

Bit 24: External event 3 generates channel 1 .

CH1SEXEV4

Bit 25: External event 4 generates channel 1 .

CH1SEXEV5

Bit 26: External event 5 generates channel 1 .

CH1SEXEV6

Bit 27: External event 6 generates channel 1 .

CH1SEXEV7

Bit 28: External event 7 generates channel 1 .

CH1SEXEV8

Bit 29: External event 8 generates channel 1 .

CH1SEXEV9

Bit 30: External event 9 generates channel 1 .

CH1SUP

Bit 31: Update event generates channel 1 .

ST3CH1RST

SHRTIMER Slave_TIMERx channel 1 reset request register

Offset: 0x48, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1RSUP
rw 		CH1RSEXEV9
rw 		CH1RSEXEV8
rw 		CH1RSEXEV7
rw 		CH1RSEXEV6
rw 		CH1RSEXEV5
rw 		CH1RSEXEV4
rw 		CH1RSEXEV3
rw 		CH1RSEXEV2
rw 		CH1RSEXEV1
rw 		CH1RSEXEV0
rw 		CH1RSSTEV8
rw 		CH1RSSTEV7
rw 		CH1RSSTEV6
rw 		CH1RSSTEV5
rw 		CH1RSSTEV4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1RSSTEV3
rw 		CH1RSSTEV2
rw 		CH1RSSTEV1
rw 		CH1RSSTEV0
rw 		CH1RSMTCMP3
rw 		CH1RSMTCMP2
rw 		CH1RSMTCMP1
rw 		CH1RSMTCMP0
rw 		CH1RSMTPER
rw 		CH1RSCMP3
rw 		CH1RSCMP2
rw 		CH1RSCMP1
rw 		CH1RSCMP0
rw 		CH1RSPER
rw 		CH1RSRST
rw 		CH1RSSEV
rw
Toggle Fields.

CH1RSSEV

Bit 0: Software event generates channel 1 .

CH1RSRST

Bit 1: Slave_TIMERx reset event generates channel 1 .

CH1RSPER

Bit 2: Slave_TIMERx period event generates channel 1 .

CH1RSCMP0

Bit 3: Slave_TIMERx compare 0 event generates channel 1 .

CH1RSCMP1

Bit 4: Slave_TIMERx compare 1 event generates channel 1 .

CH1RSCMP2

Bit 5: Slave_TIMERx compare 2 event generates channel 1 .

CH1RSCMP3

Bit 6: Slave_TIMERx compare 3 event generates channel 1 .

CH1RSMTPER

Bit 7: Master_TIMER period event generates channel 1 .

CH1RSMTCMP0

Bit 8: Master_TIMER compare 0 event generates channel 1 .

CH1RSMTCMP1

Bit 9: Master_TIMER compare 1 event generates channel 1 .

CH1RSMTCMP2

Bit 10: Master_TIMER compare 2 event generates channel 1 .

CH1RSMTCMP3

Bit 11: Master_TIMER compare 3 event generates channel 1 .

CH1RSSTEV0

Bit 12: Slave_TIMERx interconnection event 0 generates channel 1 .

CH1RSSTEV1

Bit 13: Slave_TIMERx interconnection event 1 generates channel 1 .

CH1RSSTEV2

Bit 14: Slave_TIMERx interconnection event 2 generates channel 1 .

CH1RSSTEV3

Bit 15: Slave_TIMERx interconnection event 3 generates channel 1 .

CH1RSSTEV4

Bit 16: Slave_TIMERx interconnection event 4 generates channel 1 .

CH1RSSTEV5

Bit 17: Slave_TIMERx interconnection event 5 generates channel 1 .

CH1RSSTEV6

Bit 18: Slave_TIMERx interconnection event 6 generates channel 1 .

CH1RSSTEV7

Bit 19: Slave_TIMERx interconnection event 7 generates channel 1 .

CH1RSSTEV8

Bit 20: Slave_TIMERx interconnection event 8 generates channel 1 .

CH1RSEXEV0

Bit 21: External event 0 generates channel 1 .

CH1RSEXEV1

Bit 22: External event 1 generates channel 1 .

CH1RSEXEV2

Bit 23: External event 2 generates channel 1 .

CH1RSEXEV3

Bit 24: External event 3 generates channel 1 .

CH1RSEXEV4

Bit 25: External event 4 generates channel 1 .

CH1RSEXEV5

Bit 26: External event 5 generates channel 1 .

CH1RSEXEV6

Bit 27: External event 6 generates channel 1 .

CH1RSEXEV7

Bit 28: External event 7 generates channel 1 .

CH1RSEXEV8

Bit 29: External event 8 generates channel 1 .

CH1RSEXEV9

Bit 30: External event 9 generates channel 1 .

CH1RSUP

Bit 31: Update event generates channel 1 .

ST3EXEVFCFG0

SHRTIMER Slave_TIMERx external event filter configuration register 0

Offset: 0x4C, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXEV4FM
rw 		EXEV4MEEN
rw 		EXEV3FM
rw 		EXEV3MEEN
rw 		EXEV2FM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXEV2FM
rw 		EXEV2MEEN
rw 		EXEV1FM
rw 		EXEV1MEEN
rw 		EXEV0FM
rw 		EXEV0MEEN
rw
Toggle Fields.

EXEV0MEEN

Bit 0: External event 0 memorized enable.

EXEV0FM

Bits 1-4: External event 0 filter mode.

EXEV1MEEN

Bit 6: External event 1 memorized enable.

EXEV1FM

Bits 7-10: External event 1 filter mode.

EXEV2MEEN

Bit 12: External event 2 memorized enable.

EXEV2FM

Bits 13-16: External event 2 filter mode.

EXEV3MEEN

Bit 18: External event 3 memorized enable.

EXEV3FM

Bits 19-22: External event 3 filter mode.

EXEV4MEEN

Bit 24: External event 4 memorized enable.

EXEV4FM

Bits 25-28: External event 4 filter mode.

ST3EXEVFCFG1

SHRTIMER Slave_TIMERx external event filter configuration register 1

Offset: 0x50, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXEV9FM
rw 		EXEV9MEEN
rw 		EXEV8FM
rw 		EXEV8MEEN
rw 		EXEV7FM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXEV7FM
rw 		EXEV7MEEN
rw 		EXEV6FM
rw 		EXEV6MEEN
rw 		EXEV5FM
rw 		EXEV5MEEN
rw
Toggle Fields.

EXEV5MEEN

Bit 0: External event 5 memorized enable.

EXEV5FM

Bits 1-4: External event 5 filter mode.

EXEV6MEEN

Bit 6: External event 6 memorized enable.

EXEV6FM

Bits 7-10: External event 6 filter mode.

EXEV7MEEN

Bit 12: External event 7 memorized enable.

EXEV7FM

Bits 13-16: External event 7 filter mode.

EXEV8MEEN

Bit 18: External event 8 memorized enable.

EXEV8FM

Bits 19-22: External event 8 filter mode.

EXEV9MEEN

Bit 24: External event 9 memorized enable.

EXEV9FM

Bits 25-28: External event 9 filter mode.

ST3CNTRST

SHRTIMER Slave_TIMERx counter reset register

Offset: 0x54, reset: 0x00000000, access: read-write

0/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ST4CMP3RST
rw 		ST4CMP1RST
rw 		ST4CMP0RST
rw 		ST2CMP3RST
rw 		ST2CMP1RST
rw 		ST2CMP0RST
rw 		ST1CMP3RST
rw 		ST1CMP1RST
rw 		ST1CMP0RST
rw 		ST0CMP3RST
rw 		ST0CMP1RST
rw 		ST0CMP0RST
rw 		EXEV9RST
rw 		EXEV8RST
rw 		EXEV7RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXEV6RST
rw 		EXEV5RST
rw 		EXEV4RST
rw 		EXEV3RST
rw 		EXEV2RST
rw 		EXEV1RST
rw 		EXEV0RST
rw 		MTCMP3RST
rw 		MTCMP2RST
rw 		MTCMP1RST
rw 		MTCMP0RST
rw 		MTPERRST
rw 		CMP3RST
rw 		CMP1RST
rw 		UPRST
rw
Toggle Fields.

UPRST

Bit 1: Slave_TIMERx update event resets counter.

CMP1RST

Bit 2: Slave_TIMERx compare 1 event resets counter.

CMP3RST

Bit 3: Slave_TIMERx compare 3 event resets counter.

MTPERRST

Bit 4: Master_TIMER period event resets counter.

MTCMP0RST

Bit 5: Master_TIMER compare 0 event resets counter.

MTCMP1RST

Bit 6: Master_TIMER compare 1 event resets counter.

MTCMP2RST

Bit 7: Master_TIMER compare 2 event resets counter.

MTCMP3RST

Bit 8: Master_TIMER compare 3 event resets counter.

EXEV0RST

Bit 9: External event 0 resets counter.

EXEV1RST

Bit 10: External event 1 resets counter.

EXEV2RST

Bit 11: External event 2 resets counter.

EXEV3RST

Bit 12: External event 3 resets counter.

EXEV4RST

Bit 13: External event 4 resets counter.

EXEV5RST

Bit 14: External event 5 resets counter.

EXEV6RST

Bit 15: External event 6 resets counter.

EXEV7RST

Bit 16: External event 7 resets counter.

EXEV8RST

Bit 17: External event 8 resets counter.

EXEV9RST

Bit 18: External event 9 resets counter.

ST0CMP0RST

Bit 19: Slave_TIMER0 compare 0 event resets counter.

ST0CMP1RST

Bit 20: Slave_TIMER0 compare 1 event resets counter.

ST0CMP3RST

Bit 21: Slave_TIMER0 compare 3 event resets counter.

ST1CMP0RST

Bit 22: Slave_TIMER1 compare 0 event resets counter.

ST1CMP1RST

Bit 23: Slave_TIMER1 compare 1 event resets counter.

ST1CMP3RST

Bit 24: Slave_TIMER1 compare 3 event resets counter.

ST2CMP0RST

Bit 25: Slave_TIMER2 compare 0 event resets counter.

ST2CMP1RST

Bit 26: Slave_TIMER2 compare 1 event resets counter.

ST2CMP3RST

Bit 27: Slave_TIMER2 compare 3 event resets counter.

ST4CMP0RST

Bit 28: Slave_TIMER4 compare 0 event resets counter.

ST4CMP1RST

Bit 29: Slave_TIMER4 compare 1 event resets counter.

ST4CMP3RST

Bit 30: Slave_TIMER4 compare 3 event resets counter.

ST3CSCTL

SHRTIMER Slave_TIMERx carrier-signal control register

Offset: 0x58, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSFSTPW
rw 		CSDTY
rw 		CSPRD
rw
Toggle Fields.

CSPRD

Bits 0-3: Carrier signal period.

CSDTY

Bits 4-6: Carrier signal duty cycle.

CSFSTPW

Bits 7-10: First carrier-signal pulse width.

ST3CAP0TRG

SHRTIMER Slave_TIMERx capture 0 trigger register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CP0BST3CMP1
rw 		CP0BST3CMP0
rw 		CP0BST3NA
rw 		CP0BST3A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CP0BEXEV9
rw 		CP0BEXEV8
rw 		CP0BEXEV7
rw 		CP0BEXEV6
rw 		CP0BEXEV5
rw 		CP0BEXEV4
rw 		CP0BEXEV3
rw 		CP0BEXEV2
rw 		CP0BEXEV1
rw 		CP0BEXEV0
rw 		CP0BUP
rw 		CP0BSW
rw
Toggle Fields.

CP0BSW

Bit 0: Capture 0 triggered by software.

CP0BUP

Bit 1: Capture 0 triggered by update event.

CP0BEXEV0

Bit 2: Capture 0 triggered by external event 0.

CP0BEXEV1

Bit 3: Capture 0 triggered by external event 1.

CP0BEXEV2

Bit 4: Capture 0 triggered by external event 2.

CP0BEXEV3

Bit 5: Capture 0 triggered by external event 3.

CP0BEXEV4

Bit 6: Capture 0 triggered by external event 4.

CP0BEXEV5

Bit 7: Capture 0 triggered by external event 5.

CP0BEXEV6

Bit 8: Capture 0 triggered by external event 6.

CP0BEXEV7

Bit 9: Capture 0 triggered by external event 7.

CP0BEXEV8

Bit 10: Capture 0 triggered by external event 8.

CP0BEXEV9

Bit 11: Capture 0 triggered by external event 9.

CP0BST3A

Bit 24: Capture 0 triggered by ST3CH0_O output inactive to active transition.

CP0BST3NA

Bit 25: Capture 0 triggered by ST3CH0_O output active to inactive transition.

CP0BST3CMP0

Bit 26: Capture 0 triggered by compare 0 event of Slave_TIMER3.

CP0BST3CMP1

Bit 27: Capture 0 triggered by compare 1 event of Slave_TIMER3.

ST3CAP1TRG

SHRTIMER Slave_TIMERx capture 1 trigger register

Offset: 0x60, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CP1BST3CMP1
rw 		CP1BST3CMP0
rw 		CP1BST3NA
rw 		CP1BST3A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CP1BEXEV9
rw 		CP1BEXEV8
rw 		CP1BEXEV7
rw 		CP1BEXEV6
rw 		CP1BEXEV5
rw 		CP1BEXEV4
rw 		CP1BEXEV3
rw 		CP1BEXEV2
rw 		CP1BEXEV1
rw 		CP1BEXEV0
rw 		CP1BUP
rw 		CP1BSW
rw
Toggle Fields.

CP1BSW

Bit 0: Capture 1 triggered by software.

CP1BUP

Bit 1: Capture 1 triggered by update event.

CP1BEXEV0

Bit 2: Capture 1 triggered by external event 0.

CP1BEXEV1

Bit 3: Capture 1 triggered by external event 1.

CP1BEXEV2

Bit 4: Capture 1 triggered by external event 2.

CP1BEXEV3

Bit 5: Capture 1 triggered by external event 3.

CP1BEXEV4

Bit 6: Capture 1 triggered by external event 4.

CP1BEXEV5

Bit 7: Capture 1 triggered by external event 5.

CP1BEXEV6

Bit 8: Capture 1 triggered by external event 6.

CP1BEXEV7

Bit 9: Capture 1 triggered by external event 7.

CP1BEXEV8

Bit 10: Capture 1 triggered by external event 8.

CP1BEXEV9

Bit 11: Capture 1 triggered by external event 9.

CP1BST3A

Bit 24: Capture 1 triggered by ST3CH0_O output inactive to active transition.

CP1BST3NA

Bit 25: Capture 1 triggered by ST3CH0_O output active to inactive transition.

CP1BST3CMP0

Bit 26: Capture 1 triggered by compare 0 event of Slave_TIMER3.

CP1BST3CMP1

Bit 27: Capture 1 triggered by compare 1 event of Slave_TIMER3.

ST3CHOCTL

SHRTIMER Slave_TIMERx channel output control register

Offset: 0x64, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BMCH1DTI
rw 		CH1CSEN
rw 		CH1FLTOS
rw 		ISO1
rw 		BMCH1IEN
rw 		CH1P
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYISCH
rw 		DLYISMEN
rw 		DTEN
rw 		BMCH0DTI
rw 		CH0CSEN
rw 		CH0FLTOS
rw 		ISO0
rw 		BMCH0IEN
rw 		CH0P
rw
Toggle Fields.

CH0P

Bit 1: Channel 0 output polarity.

BMCH0IEN

Bit 2: Channel 0 IDLE state enable in bunch mode.

ISO0

Bit 3: Channel 0 output idle state.

CH0FLTOS

Bits 4-5: Channel 0 Fault output state.

CH0CSEN

Bit 6: Channel 0 carrier-signal mode enable.

BMCH0DTI

Bit 7: Channel 0 dead-time insert in bunch mode.

DTEN

Bit 8: Dead time enable.

DLYISMEN

Bit 9: Delayed IDLE state mode enable.

DLYISCH

Bits 10-12: Delayed IDLE source and channel.

CH1P

Bit 17: Channel 1 output polarity.

BMCH1IEN

Bit 18: Channel 1 IDLE state enable in bunch mode.

ISO1

Bit 19: channel 1 output idle state.

CH1FLTOS

Bits 20-21: Channel 1 Fault output state.

CH1CSEN

Bit 22: Channel 1 carrier-signal mode enable.

BMCH1DTI

Bit 23: Channel 1 dead-time insert in bunch mode.

ST3FLTCTL

SHRTIMER Slave_TIMERx fault control register

Offset: 0x68, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTENPROT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT4EN
rw 		FLT3EN
rw 		FLT2EN
rw 		FLT1EN
rw 		FLT0EN
rw
Toggle Fields.

FLT0EN

Bit 0: Fault 0 enable.

FLT1EN

Bit 1: Fault 1 enable.

FLT2EN

Bit 2: Fault 2 enable.

FLT3EN

Bit 3: Fault 3 enable.

FLT4EN

Bit 4: Fault 4 enable.

FLTENPROT

Bit 31: Protect fault enable.

ST3ACTL

SHRTIMER Slave_TIMERx additional control register

Offset: 0x7C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFCFG_15_9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTRCFG_15_9
rw 		CNTCKDIV_3
rw
Toggle Fields.

CNTCKDIV_3

Bit 3: Counter clock division.

DTRCFG_15_9

Bits 9-15: Rising edge dead-time value configure.

DTFCFG_15_9

Bits 25-31: Falling edge dead-time value configure.

SLAVE_TIMER4

0x40017680: SHRTIMER Slave TIMER4 registers(

18/336 fields covered. Toggle Registers.

ST3CTL0

SHRTIMER Slave_TIMERx control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UPSEL
rw 		SHWEN
rw 		DACTRGS
rw 		UPBMT
rw 		UPBST3
rw 		UPBST2
rw 		UPBST1
rw 		UPBST0
rw 		UPRST
rw 		UPREP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DELCMP3M
rw 		DELCMP1M
rw 		SYNISTRT
rw 		SYNIRST
rw 		BLNMEN
rw 		HALFM
rw 		CNTRSTM
rw 		CTNM
rw 		CNTCKDIV
rw
Toggle Fields.

CNTCKDIV

Bits 0-2: Counter clock division.

CTNM

Bit 3: Continuous mode.

CNTRSTM

Bit 4: Counter reset mode.

HALFM

Bit 5: Half mode.

BLNMEN

Bit 6: Balanced mode enable.

SYNIRST

Bit 10: Synchronization input reset counter.

SYNISTRT

Bit 11: Synchronization input start counter.

DELCMP1M

Bits 12-13: Compare 1 delayed mode.

DELCMP3M

Bits 14-15: Compare 3 delayed mode.

UPREP

Bit 17: Update event generated by repetition event.

UPRST

Bit 18: Update event generated by reset event.

UPBST0

Bit 19: Update by Slave_TIMER0 update event.

UPBST1

Bit 20: Update by Slave_TIMER1 update event.

UPBST2

Bit 21: Update by Slave_TIMER2 update event.

UPBST3

Bit 22: Update by Slave_TIMER3 update event.

UPBMT

Bit 24: Update by Master_TIMER update event.

DACTRGS

Bits 25-26: Trigger source to DAC.

SHWEN

Bit 27: Shadow registers enable.

UPSEL

Bits 28-31: Update event selection.

ST4INTF

SHRTIMER Slave_TIMERx interrupt flag register

Offset: 0x4, reset: 0x00000000, access: read-only

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1F
r 		CH0F
r 		BLNIF
r 		CBLNF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYIIF
r 		RSTIF
r 		CH1ONAIF
r 		CH1OAIF
r 		CH0ONAIF
r 		CH0OAIF
r 		CAP1IF
r 		CAP0IF
r 		UPIF
r 		REPIF
r 		CMP3IF
r 		CMP2IF
r 		CMP1IF
r 		CMP0IF
r
Toggle Fields.

CMP0IF

Bit 0: Compare 0 interrupt flag.

CMP1IF

Bit 1: Compare 1 interrupt flag.

CMP2IF

Bit 2: Compare 2 interrupt flag.

CMP3IF

Bit 3: Compare 3 interrupt flag.

REPIF

Bit 4: Repetition interrupt flag.

UPIF

Bit 6: Update interrupt flag.

CAP0IF

Bit 7: Capture 0 interrupt flag.

CAP1IF

Bit 8: Capture 1 interrupt flag.

CH0OAIF

Bit 9: Channel 0 output active interrupt flag.

CH0ONAIF

Bit 10: Channel 0 output inactive interrupt flag.

CH1OAIF

Bit 11: Channel 1 output active interrupt flag.

CH1ONAIF

Bit 12: Channel 1 output inactive interrupt flag.

RSTIF

Bit 13: Counter reset interrupt flag.

DLYIIF

Bit 14: Delayed IDLE mode entry interrupt flag.

CBLNF

Bit 16: Current balanced flag.

BLNIF

Bit 17: Balanced IDLE flag.

CH0F

Bit 20: Channel 0 output flag.

CH1F

Bit 21: Channel 1 output flag.

ST4INTC

SHRTIMER Slave_TIMERx interrupt flag clear register

Offset: 0x8, reset: 0x00000000, access: write-only

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYIIFC
w 		RSTIFC
w 		CH1ONAIFC
w 		CH1OAIFC
w 		CH0ONAIFC
w 		CH0OAIFC
w 		CAP1IFC
w 		CAP0IFC
w 		UPIFC
w 		REPIFC
w 		CMP3IFC
w 		CMP2IFC
w 		CMP1IFC
w 		CMP0IFC
w
Toggle Fields.

CMP0IFC

Bit 0: Clear compare 0 interrupt flag.

CMP1IFC

Bit 1: Clear compare 1 interrupt flag.

CMP2IFC

Bit 2: Clear compare 2 interrupt flag.

CMP3IFC

Bit 3: Clear compare 3 interrupt flag.

REPIFC

Bit 4: Clear repetition interrupt flag.

UPIFC

Bit 6: Clear update interrupt flag.

CAP0IFC

Bit 7: Clear capture 0 interrupt flag.

CAP1IFC

Bit 8: Clear capture 1 interrupt flag.

CH0OAIFC

Bit 9: Clear channel 0 output active interrupt flag.

CH0ONAIFC

Bit 10: Clear channel 0 output inactive interrupt flag.

CH1OAIFC

Bit 11: Clear channel 1 output active interrupt flag.

CH1ONAIFC

Bit 12: Clear channel 1 output inactive interrupt flag.

RSTIFC

Bit 13: Clear counter reset interrupt flag.

DLYIIFC

Bit 14: Clear delayed IDLE mode entry interrupt flag.

ST4DMAINTEN

SHRTIMER Slave_TIMERx DMA and interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYIDEN
rw 		RSTDEN
rw 		CH1ONADEN
rw 		CH1OADEN
rw 		CH0ONADEN
rw 		CH0ADEN
rw 		CAP1DEN
rw 		CAP0DEN
rw 		UPDEN
rw 		REPDEN
rw 		CMP3DEN
rw 		CMP2DEN
rw 		CMP1DEN
rw 		CMP0DEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYIIE
rw 		RSTIE
rw 		CH1ONAIE
rw 		CH1OAIE
rw 		CH0ONAIE
rw 		CH0OAIE
rw 		CAP1IE
rw 		CAP0IE
rw 		UPIE
rw 		REPIE
rw 		CMP3IE
rw 		CMP2IE
rw 		CMP1IE
rw 		CMP0IE
rw
Toggle Fields.

CMP0IE

Bit 0: Compare 0 interrupt enable.

CMP1IE

Bit 1: Compare 1 interrupt enable.

CMP2IE

Bit 2: Compare 2 interrupt enable.

CMP3IE

Bit 3: Compare 3 interrupt enable.

REPIE

Bit 4: Repetition interrupt enable.

UPIE

Bit 6: Update interrupt enable.

CAP0IE

Bit 7: Capture 0 interrupt enable.

CAP1IE

Bit 8: Capture 1 interrupt enable.

CH0OAIE

Bit 9: Channel 0 output active interrupt enable.

CH0ONAIE

Bit 10: Channel 0 output inactive interrupt enable.

CH1OAIE

Bit 11: Channel 1 output active interrupt enable.

CH1ONAIE

Bit 12: Channel 1 output inactive interrupt enable.

RSTIE

Bit 13: Counter reset interrupt enable.

DLYIIE

Bit 14: Delayed IDLE mode entry interrupt enable.

CMP0DEN

Bit 16: Compare 0 DMA request enable.

CMP1DEN

Bit 17: Compare 1 DMA request enable.

CMP2DEN

Bit 18: Compare 2 DMA request enable.

CMP3DEN

Bit 19: Compare 3 DMA request enable.

REPDEN

Bit 20: Repetition DMA request enable.

UPDEN

Bit 22: Update DMA request enable.

CAP0DEN

Bit 23: Capture 0 DMA request enable.

CAP1DEN

Bit 24: Capture 1 DMA request enable.

CH0ADEN

Bit 25: Channel 0 output active DMA request enable.

CH0ONADEN

Bit 26: Channel 0 output inactive DMA request enable.

CH1OADEN

Bit 27: Channel 1 output active DMA request enable.

CH1ONADEN

Bit 28: Channel 1 output inactive DMA request enable.

RSTDEN

Bit 29: Counter reset DMA request enable.

DLYIDEN

Bit 30: Delayed IDLE mode entry DMA request enable.

ST4CNT

SHRTIMER Slave_TIMERx counter register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: The current counter value.

ST4CAR

SHRTIMER Slave_TIMER4 counter auto reload register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARL
rw
Toggle Fields.

CARL

Bits 0-15: Counter auto reload value.

ST4CREP

SHRTIMER Slave_TIMER4 counter repetition register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CREP
rw
Toggle Fields.

CREP

Bits 0-7: Counter repetition value.

ST4CMP0V

SHRTIMER Slave_TIMER4 compare 0 value register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP0VAL
rw
Toggle Fields.

CMP0VAL

Bits 0-15: Compare 0 value.

ST4CMP0CP

SHRTIMER Slave_TIMERx compare 0 composite register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CREP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP0VAL
rw
Toggle Fields.

CMP0VAL

Bits 0-15: Compare 0 value.

CREP

Bits 16-23: Counter repetition value.

ST4CMP1V

SHRTIMER Slave_TIMERx compare 1 value register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP1VAL
rw
Toggle Fields.

CMP1VAL

Bits 0-15: Compare 1 value.

ST4CMP2V

SHRTIMER Slave_TIMERx compare 2 value register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP2VAL
rw
Toggle Fields.

CMP2VAL

Bits 0-15: Compare 2 value.

ST4CMP3V

SHRTIMER Slave_TIMERx compare 3 value register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP3VAL
rw
Toggle Fields.

CMP3VAL

Bits 0-15: Compare 3 value.

ST4CAP0V

SHRTIMER Slave_TIMERx capture 0 value register

Offset: 0x30, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAP0VAL
rw
Toggle Fields.

CAP0VAL

Bits 0-15: Capture 0 value.

ST4CAP1V

SHRTIMER Slave_TIMERx capture 1 value register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAP1VAL
rw
Toggle Fields.

CAP1VAL

Bits 0-15: Capture 1 value.

ST4DTCTL

SHRTIMER Slave_TIMERx dead-time control register

Offset: 0x38, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFSVPROT
rw 		DTFSPROT
rw 		DTFS
rw 		DTFCFG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTRSVPROT
rw 		DTRSPROT
rw 		DTGCKDIV
rw 		DTRS
rw 		DTRCFG
rw
Toggle Fields.

DTRCFG

Bits 0-8: Falling edge dead-time value.

DTRS

Bit 9: The sign of falling edge dead-time value.

DTGCKDIV

Bits 10-13: Dead time generator clock division.

DTRSPROT

Bit 14: Dead-time rising edge protection for sign.

DTRSVPROT

Bit 15: Dead-time rising edge protection for value and sign.

DTFCFG

Bits 16-24: Falling edge dead-time value.

DTFS

Bit 25: The sign of falling edge dead-time value.

DTFSPROT

Bit 30: Dead-time falling edge protection for sign.

DTFSVPROT

Bit 31: Dead-time falling edge protection for value and sign.

ST4CH0SET

SHRTIMER Slave_TIMERx channel 0 set request register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH0SUP
rw 		CH0SEXEV9
rw 		CH0SEXEV8
rw 		CH0SEXEV7
rw 		CH0SEXEV6
rw 		CH0SEXEV5
rw 		CH0SEXEV4
rw 		CH0SEXEV3
rw 		CH0SEXEV2
rw 		CH0SEXEV1
rw 		CH0SEXEV0
rw 		CH0SSTEV8
rw 		CH0SSTEV7
rw 		CH0SSTEV6
rw 		CH0SSTEV5
rw 		CH0SSTEV4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0SSTEV3
rw 		CH0SSTEV2
rw 		CH0SSTEV1
rw 		CH0SSTEV0
rw 		CH0SMTCMP3
rw 		CH0SMTCMP2
rw 		CH0SMTCMP1
rw 		CH0SMTCMP0
rw 		CH0SMTPER
rw 		CH0SCMP3
rw 		CH0SCMP2
rw 		CH0SCMP1
rw 		CH0SCMP0
rw 		CH0SPER
rw 		CH0SRST
rw 		CH0SSEV
rw
Toggle Fields.

CH0SSEV

Bit 0: Software event generates channel 0 .

CH0SRST

Bit 1: Slave_TIMERx reset event generates channel 0 .

CH0SPER

Bit 2: Slave_TIMERx period event generates channel 0 .

CH0SCMP0

Bit 3: Slave_TIMERx compare 0 event generates channel 0 .

CH0SCMP1

Bit 4: Slave_TIMERx compare 1 event generates channel 0 .

CH0SCMP2

Bit 5: Slave_TIMERx compare 2 event generates channel 0 .

CH0SCMP3

Bit 6: Slave_TIMERx compare 3 event generates channel 0 .

CH0SMTPER

Bit 7: Master_TIMER period event generates channel 0 .

CH0SMTCMP0

Bit 8: Master_TIMER compare 0 event generates channel 0 .

CH0SMTCMP1

Bit 9: Master_TIMER compare 1 event generates channel 0 .

CH0SMTCMP2

Bit 10: Master_TIMER compare 2 event generates channel 0 .

CH0SMTCMP3

Bit 11: Master_TIMER compare 3 event generates channel 0 .

CH0SSTEV0

Bit 12: Slave_TIMERx interconnection event 0 generates channel 0 .

CH0SSTEV1

Bit 13: Slave_TIMERx interconnection event 1 generates channel 0 .

CH0SSTEV2

Bit 14: Slave_TIMERx interconnection event 2 generates channel 0 .

CH0SSTEV3

Bit 15: Slave_TIMERx interconnection event 3 generates channel 0 .

CH0SSTEV4

Bit 16: Slave_TIMERx interconnection event 4 generates channel 0 .

CH0SSTEV5

Bit 17: Slave_TIMERx interconnection event 5 generates channel 0 .

CH0SSTEV6

Bit 18: Slave_TIMERx interconnection event 6 generates channel 0 .

CH0SSTEV7

Bit 19: Slave_TIMER1 interconnection event 7 generates channel 0 .

CH0SSTEV8

Bit 20: Slave_TIMERx interconnection event 8 generates channel 0 .

CH0SEXEV0

Bit 21: External event 0 generates channel 0 .

CH0SEXEV1

Bit 22: External event 1 generates channel 0 .

CH0SEXEV2

Bit 23: External event 2 generates channel 0 .

CH0SEXEV3

Bit 24: External event 3 generates channel 0 .

CH0SEXEV4

Bit 25: External event 4 generates channel 0 .

CH0SEXEV5

Bit 26: External event 5 generates channel 0 .

CH0SEXEV6

Bit 27: External event 6 generates channel 0 .

CH0SEXEV7

Bit 28: External event 7 generates channel 0 .

CH0SEXEV8

Bit 29: External event 8 generates channel 0 .

CH0SEXEV9

Bit 30: External event 9 generates channel 0 .

CH0SUP

Bit 31: Update event generates channel 0 .

ST4CH0RST

SHRTIMER Slave_TIMERx channel 0 reset request register

Offset: 0x40, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH0RSUP
rw 		CH0RSEXEV9
rw 		CH0RSEXEV8
rw 		CH0RSEXEV7
rw 		CH0RSEXEV6
rw 		CH0RSEXEV5
rw 		CH0RSEXEV4
rw 		CH0RSEXEV3
rw 		CH0RSEXEV2
rw 		CH0RSEXEV1
rw 		CH0RSEXEV0
rw 		CH0RSSTEV8
rw 		CH0RSSTEV7
rw 		CH0RSSTEV6
rw 		CH0RSSTEV5
rw 		CH0RSSTEV4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0RSSTEV3
rw 		CH0RSSTEV2
rw 		CH0RSSTEV1
rw 		CH0RSSTEV0
rw 		CH0RSMTCMP3
rw 		CH0RSMTCMP2
rw 		CH0RSMTCMP1
rw 		CH0RSMTCMP0
rw 		CH0RSMTPER
rw 		CH0RSCMP3
rw 		CH0RSCMP2
rw 		CH0RSCMP1
rw 		CH0RSCMP0
rw 		CH0RSPER
rw 		CH0RSRST
rw 		CH0RSSEV
rw
Toggle Fields.

CH0RSSEV

Bit 0: Software event generates channel 0 .

CH0RSRST

Bit 1: Slave_TIMERx reset event generates channel 0 .

CH0RSPER

Bit 2: Slave_TIMERx period event generates channel 0 .

CH0RSCMP0

Bit 3: Slave_TIMERx compare 0 event generates channel 0 .

CH0RSCMP1

Bit 4: Slave_TIMERx compare 1 event generates channel 0 .

CH0RSCMP2

Bit 5: Slave_TIMER1 compare 2 event generates channel 0 .

CH0RSCMP3

Bit 6: Slave_TIMERx compare 3 event generates channel 0 .

CH0RSMTPER

Bit 7: Master_TIMER period event generates channel 0 .

CH0RSMTCMP0

Bit 8: Master_TIMER compare 0 event generates channel 0 .

CH0RSMTCMP1

Bit 9: Master_TIMER compare 1 event generates channel 0 .

CH0RSMTCMP2

Bit 10: Master_TIMER compare 2 event generates channel 0 .

CH0RSMTCMP3

Bit 11: Master_TIMER compare 3 event generates channel 0 .

CH0RSSTEV0

Bit 12: Slave_TIMER1 interconnection event 0 generates channel 0 .

CH0RSSTEV1

Bit 13: Slave_TIMERx interconnection event 1 generates channel 0 .

CH0RSSTEV2

Bit 14: Slave_TIMERx interconnection event 2 generates channel 0 .

CH0RSSTEV3

Bit 15: Slave_TIMERx interconnection event 3 generates channel 0 .

CH0RSSTEV4

Bit 16: Slave_TIMER1 interconnection event 4 generates channel 0 .

CH0RSSTEV5

Bit 17: Slave_TIMERx interconnection event 5 generates channel 0 .

CH0RSSTEV6

Bit 18: Slave_TIMERx interconnection event 6 generates channel 0 .

CH0RSSTEV7

Bit 19: Slave_TIMERx interconnection event 7 generates channel 0 .

CH0RSSTEV8

Bit 20: Slave_TIMERx interconnection event 8 generates channel 0 .

CH0RSEXEV0

Bit 21: External event 0 generates channel 0 .

CH0RSEXEV1

Bit 22: External event 1 generates channel 0 .

CH0RSEXEV2

Bit 23: External event 2 generates channel 0 .

CH0RSEXEV3

Bit 24: External event 3 generates channel 0 .

CH0RSEXEV4

Bit 25: External event 4 generates channel 0 .

CH0RSEXEV5

Bit 26: External event 5 generates channel 0 .

CH0RSEXEV6

Bit 27: External event 6 generates channel 0 .

CH0RSEXEV7

Bit 28: External event 7 generates channel 0 .

CH0RSEXEV8

Bit 29: External event 8 generates channel 0 .

CH0RSEXEV9

Bit 30: External event 9 generates channel 0 .

CH0RSUP

Bit 31: Update event generates channel 0 .

ST4CH1SET

SHRTIMER Slave_TIMERx channel 1 set request register

Offset: 0x44, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1SUP
rw 		CH1SEXEV9
rw 		CH1SEXEV8
rw 		CH1SEXEV7
rw 		CH1SEXEV6
rw 		CH1SEXEV5
rw 		CH1SEXEV4
rw 		CH1SEXEV3
rw 		CH1SEXEV2
rw 		CH1SEXEV1
rw 		CH1SEXEV0
rw 		CH1SSTEV8
rw 		CH1SSTEV7
rw 		CH1SSTEV6
rw 		CH1SSTEV5
rw 		CH1SSTEV4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1SSTEV3
rw 		CH1SSTEV2
rw 		CH1SSTEV1
rw 		CH1SSTEV0
rw 		CH1SMTCMP3
rw 		CH1SMTCMP2
rw 		CH1SMTCMP1
rw 		CH1SMTCMP0
rw 		CH1SMTPER
rw 		CH1SCMP3
rw 		CH1SCMP2
rw 		CH1SCMP1
rw 		CH1SCMP0
rw 		CH1SPER
rw 		CH1SRST
rw 		CH1SSEV
rw
Toggle Fields.

CH1SSEV

Bit 0: Software event generates channel 1 .

CH1SRST

Bit 1: Slave_TIMERx reset event generates channel 1 .

CH1SPER

Bit 2: Slave_TIMERx period event generates channel 1 .

CH1SCMP0

Bit 3: Slave_TIMERx compare 0 event generates channel 1 .

CH1SCMP1

Bit 4: Slave_TIMERx compare 1 event generates channel 1 .

CH1SCMP2

Bit 5: Slave_TIMERx compare 2 event generates channel 1 .

CH1SCMP3

Bit 6: Slave_TIMERx compare 3 event generates channel 1 .

CH1SMTPER

Bit 7: Master_TIMER period event generates channel 1 .

CH1SMTCMP0

Bit 8: Master_TIMER compare 0 event generates channel 1 .

CH1SMTCMP1

Bit 9: Master_TIMER compare 1 event generates channel 1 .

CH1SMTCMP2

Bit 10: Master_TIMER compare 2 event generates channel 1 .

CH1SMTCMP3

Bit 11: Master_TIMER compare 3 event generates channel 1 .

CH1SSTEV0

Bit 12: Slave_TIMERx interconnection event 0 generates channel 1 .

CH1SSTEV1

Bit 13: Slave_TIMERx interconnection event 1 generates channel 1 .

CH1SSTEV2

Bit 14: Slave_TIMERx interconnection event 2 generates channel 1 .

CH1SSTEV3

Bit 15: Slave_TIMERx interconnection event 3 generates channel 1 .

CH1SSTEV4

Bit 16: Slave_TIMERx interconnection event 4 generates channel 1 .

CH1SSTEV5

Bit 17: Slave_TIMERx interconnection event 5 generates channel 1 .

CH1SSTEV6

Bit 18: Slave_TIMERx interconnection event 6 generates channel 1 .

CH1SSTEV7

Bit 19: Slave_TIMERx interconnection event 7 generates channel 1 .

CH1SSTEV8

Bit 20: Slave_TIMERx interconnection event 8 generates channel 1 .

CH1SEXEV0

Bit 21: External event 0 generates channel 1 .

CH1SEXEV1

Bit 22: External event 1 generates channel 1 .

CH1SEXEV2

Bit 23: External event 2 generates channel 1 .

CH1SEXEV3

Bit 24: External event 3 generates channel 1 .

CH1SEXEV4

Bit 25: External event 4 generates channel 1 .

CH1SEXEV5

Bit 26: External event 5 generates channel 1 .

CH1SEXEV6

Bit 27: External event 6 generates channel 1 .

CH1SEXEV7

Bit 28: External event 7 generates channel 1 .

CH1SEXEV8

Bit 29: External event 8 generates channel 1 .

CH1SEXEV9

Bit 30: External event 9 generates channel 1 .

CH1SUP

Bit 31: Update event generates channel 1 .

ST4CH1RST

SHRTIMER Slave_TIMERx channel 1 reset request register

Offset: 0x48, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1RSUP
rw 		CH1RSEXEV9
rw 		CH1RSEXEV8
rw 		CH1RSEXEV7
rw 		CH1RSEXEV6
rw 		CH1RSEXEV5
rw 		CH1RSEXEV4
rw 		CH1RSEXEV3
rw 		CH1RSEXEV2
rw 		CH1RSEXEV1
rw 		CH1RSEXEV0
rw 		CH1RSSTEV8
rw 		CH1RSSTEV7
rw 		CH1RSSTEV6
rw 		CH1RSSTEV5
rw 		CH1RSSTEV4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1RSSTEV3
rw 		CH1RSSTEV2
rw 		CH1RSSTEV1
rw 		CH1RSSTEV0
rw 		CH1RSMTCMP3
rw 		CH1RSMTCMP2
rw 		CH1RSMTCMP1
rw 		CH1RSMTCMP0
rw 		CH1RSMTPER
rw 		CH1RSCMP3
rw 		CH1RSCMP2
rw 		CH1RSCMP1
rw 		CH1RSCMP0
rw 		CH1RSPER
rw 		CH1RSRST
rw 		CH1RSSEV
rw
Toggle Fields.

CH1RSSEV

Bit 0: Software event generates channel 1 .

CH1RSRST

Bit 1: Slave_TIMERx reset event generates channel 1 .

CH1RSPER

Bit 2: Slave_TIMERx period event generates channel 1 .

CH1RSCMP0

Bit 3: Slave_TIMERx compare 0 event generates channel 1 .

CH1RSCMP1

Bit 4: Slave_TIMERx compare 1 event generates channel 1 .

CH1RSCMP2

Bit 5: Slave_TIMERx compare 2 event generates channel 1 .

CH1RSCMP3

Bit 6: Slave_TIMERx compare 3 event generates channel 1 .

CH1RSMTPER

Bit 7: Master_TIMER period event generates channel 1 .

CH1RSMTCMP0

Bit 8: Master_TIMER compare 0 event generates channel 1 .

CH1RSMTCMP1

Bit 9: Master_TIMER compare 1 event generates channel 1 .

CH1RSMTCMP2

Bit 10: Master_TIMER compare 2 event generates channel 1 .

CH1RSMTCMP3

Bit 11: Master_TIMER compare 3 event generates channel 1 .

CH1RSSTEV0

Bit 12: Slave_TIMERx interconnection event 0 generates channel 1 .

CH1RSSTEV1

Bit 13: Slave_TIMERx interconnection event 1 generates channel 1 .

CH1RSSTEV2

Bit 14: Slave_TIMERx interconnection event 2 generates channel 1 .

CH1RSSTEV3

Bit 15: Slave_TIMERx interconnection event 3 generates channel 1 .

CH1RSSTEV4

Bit 16: Slave_TIMERx interconnection event 4 generates channel 1 .

CH1RSSTEV5

Bit 17: Slave_TIMERx interconnection event 5 generates channel 1 .

CH1RSSTEV6

Bit 18: Slave_TIMERx interconnection event 6 generates channel 1 .

CH1RSSTEV7

Bit 19: Slave_TIMERx interconnection event 7 generates channel 1 .

CH1RSSTEV8

Bit 20: Slave_TIMERx interconnection event 8 generates channel 1 .

CH1RSEXEV0

Bit 21: External event 0 generates channel 1 .

CH1RSEXEV1

Bit 22: External event 1 generates channel 1 .

CH1RSEXEV2

Bit 23: External event 2 generates channel 1 .

CH1RSEXEV3

Bit 24: External event 3 generates channel 1 .

CH1RSEXEV4

Bit 25: External event 4 generates channel 1 .

CH1RSEXEV5

Bit 26: External event 5 generates channel 1 .

CH1RSEXEV6

Bit 27: External event 6 generates channel 1 .

CH1RSEXEV7

Bit 28: External event 7 generates channel 1 .

CH1RSEXEV8

Bit 29: External event 8 generates channel 1 .

CH1RSEXEV9

Bit 30: External event 9 generates channel 1 .

CH1RSUP

Bit 31: Update event generates channel 1 .

ST4EXEVFCFG0

SHRTIMER Slave_TIMERx external event filter configuration register 0

Offset: 0x4C, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXEV4FM
rw 		EXEV4MEEN
rw 		EXEV3FM
rw 		EXEV3MEEN
rw 		EXEV2FM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXEV2FM
rw 		EXEV2MEEN
rw 		EXEV1FM
rw 		EXEV1MEEN
rw 		EXEV0FM
rw 		EXEV0MEEN
rw
Toggle Fields.

EXEV0MEEN

Bit 0: External event 0 memorized enable.

EXEV0FM

Bits 1-4: External event 0 filter mode.

EXEV1MEEN

Bit 6: External event 1 memorized enable.

EXEV1FM

Bits 7-10: External event 1 filter mode.

EXEV2MEEN

Bit 12: External event 2 memorized enable.

EXEV2FM

Bits 13-16: External event 2 filter mode.

EXEV3MEEN

Bit 18: External event 3 memorized enable.

EXEV3FM

Bits 19-22: External event 3 filter mode.

EXEV4MEEN

Bit 24: External event 4 memorized enable.

EXEV4FM

Bits 25-28: External event 4 filter mode.

ST4EXEVFCFG1

SHRTIMER Slave_TIMERx external event filter configuration register 1

Offset: 0x50, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXEV9FM
rw 		EXEV9MEEN
rw 		EXEV8FM
rw 		EXEV8MEEN
rw 		EXEV7FM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXEV7FM
rw 		EXEV7MEEN
rw 		EXEV6FM
rw 		EXEV6MEEN
rw 		EXEV5FM
rw 		EXEV5MEEN
rw
Toggle Fields.

EXEV5MEEN

Bit 0: External event 5 memorized enable.

EXEV5FM

Bits 1-4: External event 5 filter mode.

EXEV6MEEN

Bit 6: External event 6 memorized enable.

EXEV6FM

Bits 7-10: External event 6 filter mode.

EXEV7MEEN

Bit 12: External event 7 memorized enable.

EXEV7FM

Bits 13-16: External event 7 filter mode.

EXEV8MEEN

Bit 18: External event 8 memorized enable.

EXEV8FM

Bits 19-22: External event 8 filter mode.

EXEV9MEEN

Bit 24: External event 9 memorized enable.

EXEV9FM

Bits 25-28: External event 9 filter mode.

ST4CNTRST

SHRTIMER Slave_TIMERx counter reset register

Offset: 0x54, reset: 0x00000000, access: read-write

0/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ST3CMP3RST
rw 		ST3CMP1RST
rw 		ST3CMP0RST
rw 		ST2CMP3RST
rw 		ST2CMP1RST
rw 		ST2CMP0RST
rw 		ST1CMP3RST
rw 		ST1CMP1RST
rw 		ST1CMP0RST
rw 		ST0CMP3RST
rw 		ST0CMP1RST
rw 		ST0CMP0RST
rw 		EXEV9RST
rw 		EXEV8RST
rw 		EXEV7RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXEV6RST
rw 		EXEV5RST
rw 		EXEV4RST
rw 		EXEV3RST
rw 		EXEV2RST
rw 		EXEV1RST
rw 		EXEV0RST
rw 		MTCMP3RST
rw 		MTCMP2RST
rw 		MTCMP1RST
rw 		MTCMP0RST
rw 		MTPERRST
rw 		CMP3RST
rw 		CMP1RST
rw 		UPRST
rw
Toggle Fields.

UPRST

Bit 1: Slave_TIMERx update event resets counter.

CMP1RST

Bit 2: Slave_TIMERx compare 1 event resets counter.

CMP3RST

Bit 3: Slave_TIMERx compare 3 event resets counter.

MTPERRST

Bit 4: Master_TIMER period event resets counter.

MTCMP0RST

Bit 5: Master_TIMER compare 0 event resets counter.

MTCMP1RST

Bit 6: Master_TIMER compare 1 event resets counter.

MTCMP2RST

Bit 7: Master_TIMER compare 2 event resets counter.

MTCMP3RST

Bit 8: Master_TIMER compare 3 event resets counter.

EXEV0RST

Bit 9: External event 0 resets counter.

EXEV1RST

Bit 10: External event 1 resets counter.

EXEV2RST

Bit 11: External event 2 resets counter.

EXEV3RST

Bit 12: External event 3 resets counter.

EXEV4RST

Bit 13: External event 4 resets counter.

EXEV5RST

Bit 14: External event 5 resets counter.

EXEV6RST

Bit 15: External event 6 resets counter.

EXEV7RST

Bit 16: External event 7 resets counter.

EXEV8RST

Bit 17: External event 8 resets counter.

EXEV9RST

Bit 18: External event 9 resets counter.

ST0CMP0RST

Bit 19: Slave_TIMER0 compare 0 event resets counter.

ST0CMP1RST

Bit 20: Slave_TIMER0 compare 1 event resets counter.

ST0CMP3RST

Bit 21: Slave_TIMER0 compare 3 event resets counter.

ST1CMP0RST

Bit 22: Slave_TIMER1 compare 0 event resets counter.

ST1CMP1RST

Bit 23: Slave_TIMER1 compare 1 event resets counter.

ST1CMP3RST

Bit 24: Slave_TIMER1 compare 3 event resets counter.

ST2CMP0RST

Bit 25: Slave_TIMER2 compare 0 event resets counter.

ST2CMP1RST

Bit 26: Slave_TIMER2 compare 1 event resets counter.

ST2CMP3RST

Bit 27: Slave_TIMER2 compare 3 event resets counter.

ST3CMP0RST

Bit 28: Slave_TIMER3 compare 0 event resets counter.

ST3CMP1RST

Bit 29: Slave_TIMER3 compare 1 event resets counter.

ST3CMP3RST

Bit 30: Slave_TIMER3 compare 3 event resets counter.

ST4CSCTL

SHRTIMER Slave_TIMERx carrier-signal control register

Offset: 0x58, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSFSTPW
rw 		CSDTY
rw 		CSPRD
rw
Toggle Fields.

CSPRD

Bits 0-3: Carrier signal period.

CSDTY

Bits 4-6: Carrier signal duty cycle.

CSFSTPW

Bits 7-10: First carrier-signal pulse width.

ST4CAP0TRG

SHRTIMER Slave_TIMERx capture 0 trigger register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CP0BST4CMP1
rw 		CP0BST4CMP0
rw 		CP0BST4NA
rw 		CP0BST4A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CP0BEXEV9
rw 		CP0BEXEV8
rw 		CP0BEXEV7
rw 		CP0BEXEV6
rw 		CP0BEXEV5
rw 		CP0BEXEV4
rw 		CP0BEXEV3
rw 		CP0BEXEV2
rw 		CP0BEXEV1
rw 		CP0BEXEV0
rw 		CP0BUP
rw 		CP0BSW
rw
Toggle Fields.

CP0BSW

Bit 0: Capture 0 triggered by software.

CP0BUP

Bit 1: Capture 0 triggered by update event.

CP0BEXEV0

Bit 2: Capture 0 triggered by external event 0.

CP0BEXEV1

Bit 3: Capture 0 triggered by external event 1.

CP0BEXEV2

Bit 4: Capture 0 triggered by external event 2.

CP0BEXEV3

Bit 5: Capture 0 triggered by external event 3.

CP0BEXEV4

Bit 6: Capture 0 triggered by external event 4.

CP0BEXEV5

Bit 7: Capture 0 triggered by external event 5.

CP0BEXEV6

Bit 8: Capture 0 triggered by external event 6.

CP0BEXEV7

Bit 9: Capture 0 triggered by external event 7.

CP0BEXEV8

Bit 10: Capture 0 triggered by external event 8.

CP0BEXEV9

Bit 11: Capture 0 triggered by external event 9.

CP0BST4A

Bit 28: Capture 0 triggered by ST4CH0_O output inactive to active transition.

CP0BST4NA

Bit 29: Capture 0 triggered by ST4CH0_O output active to inactive transition.

CP0BST4CMP0

Bit 30: Capture 0 triggered by compare 0 event of Slave_TIMER4.

CP0BST4CMP1

Bit 31: Capture 0 triggered by compare 1 event of Slave_TIMER4.

ST4CAP1TRG

SHRTIMER Slave_TIMERx capture 1 trigger register

Offset: 0x60, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CP1BST4CMP1
rw 		CP1BST4CMP0
rw 		CP1BST4NA
rw 		CP1BST4A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CP1BEXEV9
rw 		CP1BEXEV8
rw 		CP1BEXEV7
rw 		CP1BEXEV6
rw 		CP1BEXEV5
rw 		CP1BEXEV4
rw 		CP1BEXEV3
rw 		CP1BEXEV2
rw 		CP1BEXEV1
rw 		CP1BEXEV0
rw 		CP1BUP
rw 		CP1BSW
rw
Toggle Fields.

CP1BSW

Bit 0: Capture 1 triggered by software.

CP1BUP

Bit 1: Capture 1 triggered by update event.

CP1BEXEV0

Bit 2: Capture 1 triggered by external event 0.

CP1BEXEV1

Bit 3: Capture 1 triggered by external event 1.

CP1BEXEV2

Bit 4: Capture 1 triggered by external event 2.

CP1BEXEV3

Bit 5: Capture 1 triggered by external event 3.

CP1BEXEV4

Bit 6: Capture 1 triggered by external event 4.

CP1BEXEV5

Bit 7: Capture 1 triggered by external event 5.

CP1BEXEV6

Bit 8: Capture 1 triggered by external event 6.

CP1BEXEV7

Bit 9: Capture 1 triggered by external event 7.

CP1BEXEV8

Bit 10: Capture 1 triggered by external event 8.

CP1BEXEV9

Bit 11: Capture 1 triggered by external event 9.

CP1BST4A

Bit 28: Capture 1 triggered by ST4CH0_O output inactive to active transition.

CP1BST4NA

Bit 29: Capture 1 triggered by ST4CH0_O output active to inactive transition.

CP1BST4CMP0

Bit 30: Capture 1 triggered by compare 0 event of Slave_TIMER4.

CP1BST4CMP1

Bit 31: Capture 1 triggered by compare 1 event of Slave_TIMER4.

ST4CHOCTL

SHRTIMER Slave_TIMERx channel output control register

Offset: 0x64, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BMCH1DTI
rw 		CH1CSEN
rw 		CH1FLTOS
rw 		ISO1
rw 		BMCH1IEN
rw 		CH1P
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYISCH
rw 		DLYISMEN
rw 		DTEN
rw 		BMCH0DTI
rw 		CH0CSEN
rw 		CH0FLTOS
rw 		ISO0
rw 		BMCH0IEN
rw 		CH0P
rw
Toggle Fields.

CH0P

Bit 1: Channel 0 output polarity.

BMCH0IEN

Bit 2: Channel 0 IDLE state enable in bunch mode.

ISO0

Bit 3: Channel 0 output idle state.

CH0FLTOS

Bits 4-5: Channel 0 Fault output state.

CH0CSEN

Bit 6: Channel 0 carrier-signal mode enable.

BMCH0DTI

Bit 7: Channel 0 dead-time insert in bunch mode.

DTEN

Bit 8: Dead time enable.

DLYISMEN

Bit 9: Delayed IDLE state mode enable.

DLYISCH

Bits 10-12: Delayed IDLE source and channel.

CH1P

Bit 17: Channel 1 output polarity.

BMCH1IEN

Bit 18: Channel 1 IDLE state enable in bunch mode.

ISO1

Bit 19: channel 1 output idle state.

CH1FLTOS

Bits 20-21: Channel 1 Fault output state.

CH1CSEN

Bit 22: Channel 1 carrier-signal mode enable.

BMCH1DTI

Bit 23: Channel 1 dead-time insert in bunch mode.

ST4FLTCTL

SHRTIMER Slave_TIMERx fault control register

Offset: 0x68, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTENPROT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLT4EN
rw 		FLT3EN
rw 		FLT2EN
rw 		FLT1EN
rw 		FLT0EN
rw
Toggle Fields.

FLT0EN

Bit 0: Fault 0 enable.

FLT1EN

Bit 1: Fault 1 enable.

FLT2EN

Bit 2: Fault 2 enable.

FLT3EN

Bit 3: Fault 3 enable.

FLT4EN

Bit 4: Fault 4 enable.

FLTENPROT

Bit 31: Protect fault enable.

ST4ACTL

SHRTIMER Slave_TIMERx additional control register

Offset: 0x7C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTFCFG_15_9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTRCFG_15_9
rw 		CNTCKDIV_3
rw
Toggle Fields.

CNTCKDIV_3

Bit 3: Counter clock division.

DTRCFG_15_9

Bits 9-15: Rising edge dead-time value configure.

DTFCFG_15_9

Bits 25-31: Falling edge dead-time value configure.

SPI0

0x40013000: Serial peripheral interface

43/46 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDEN
rw 		BDOEN
rw 		CRCEN
rw 		CRCNT
rw 		FF16
rw 		RO
rw 		SWNSSEN
rw 		SWNSS
rw 		LF
rw 		SPIEN
rw 		PSC
rw 		MSTMOD
rw 		CKPL
rw 		CKPH
rw
Toggle Fields.

CKPH

Bit 0: Clock Phase Selection.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CKPL

Bit 1: Clock polarity Selection.

Allowed values:
0: IdleLow: CLK pulled low when idle
1: IdleHigh: CLK pulled high when idle

MSTMOD

Bit 2: Master Mode Enable.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

PSC

Bits 3-5: Master Clock Prescaler Selection.

Allowed values:
0: Div2: PCLK / 2
1: Div4: PCLK / 4
2: Div8: PCLK / 8
3: Div16: PCLK / 16
4: Div32: PCLK / 32
5: Div64: PCLK / 64
6: Div128: PCLK / 128
7: Div256: PCLK / 256

SPIEN

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LF

Bit 7: LSB First Mode.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SWNSS

Bit 8: NSS Pin Selection In NSS Software Mode.

Allowed values:
0: SlaveSelected: NSS is pulled low
1: SlaveNotSelected: NSS is pulled high

SWNSSEN

Bit 9: NSS Software Mode Selection.

Allowed values:
0: Hardware: Software slave management disabled
1: Software: Software slave management enabled

RO

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: ReceiveOnly: Output disabled (Receive-only mode)

FF16

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNT

Bit 12: CRC Next Transfer.

Allowed values:
0: Data: Next transmit value is data from Tx buffer
1: CRC: Next transmit value is CRC value from TCRC

CRCEN

Bit 13: CRC Calculation Enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BDOEN

Bit 14: Bidirectional Transmit output enable .

Allowed values:
0: ReceiveOnly: Receive-only mode
1: TransmitOnly: Transmit-only mode

BDEN

Bit 15: Bidirectional enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CTL1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

6/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBEIE
rw 		RBNEIE
rw 		ERRIE
rw 		TMOD
rw 		NSSP
rw 		NSSDRV
rw 		DMATEN
rw 		DMAREN
rw
Toggle Fields.

DMAREN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

DMATEN

Bit 1: Transmit Buffer DMA Enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

NSSDRV

Bit 2: Drive NSS Output.

Allowed values:
0: Disabled: NSS output is disabled in master mode
1: Enabled: NSS output is enabled in master mode

NSSP

Bit 3: SPI NSS pulse mode Enable.

TMOD

Bit 4: SPI TI Mode Enable.

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

RBNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Disabled: RBNE interrupt disabled
1: Enabled: RBNE interrupt enabled

TBEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Disabled: TBE interrupt disabled
1: Enabled: TBE interrupt enabled

STAT

status register

Offset: 0x8, reset: 0x00000002, access: Unspecified

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FERR
rw 		TRANS
r 		RXORERR
r 		CONFERR
r 		CRCERR
rw 		TXURERR
r 		I2SCH
r 		TBE
r 		RBNE
r
Toggle Fields.

RBNE

Bit 0: Receive Buffer Not Empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TBE

Bit 1: Transmit Buffer Empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

I2SCH

Bit 2: I2S channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

TXURERR

Bit 3: Transmission underrun error bit.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: SPI CRC Error Bit.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

CONFERR

Bit 5: SPI Configuration error.

Allowed values:
0: NoFault: No configuration fault occurred
1: Fault: Configuration fault occurred

RXORERR

Bit 6: Reception Overrun Error Bit.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

TRANS

Bit 7: Transmitting On-going Bit.

Allowed values:
0: Idle: SPI or I2S is idle
1: Busy: SPI or I2S is currently transmitting or receiving

FERR

Bit 8: Format Error.

DATA

data register

Offset: 0xC, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Data transfer register.

Allowed values: 0-65535

CRCPOLY

CRC polynomial register

Offset: 0x10, reset: 0x00000007, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0-65535

RCRC

RX CRC register

Offset: 0x14, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCRC
r
Toggle Fields.

RCRC

Bits 0-15: RX CRC register.

Allowed values: 0-65535

TCRC

TX CRC register

Offset: 0x18, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRC
r
Toggle Fields.

TCRC

Bits 0-15: Tx CRC register.

Allowed values: 0-65535

I2SCTL

I2S control register

Offset: 0x1C, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SSEL
rw 		I2SEN
rw 		I2SOPMOD
rw 		PCMSMOD
rw 		I2SSTD
rw 		CKPL
rw 		DTLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DTLEN

Bits 1-2: Data length.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPL

Bit 3: Idle state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSMOD

Bit 7: PCM frame synchronization mode.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SOPMOD

Bits 8-9: I2S operation mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SEN

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SSEL

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPSC

I2S prescaler register

Offset: 0x20, reset: 0x00000002, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOEN
rw 		OF
rw 		DIV
rw
Toggle Fields.

DIV

Bits 0-7: Dividing factor for the prescaler.

Allowed values: 1-255

OF

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is DIV * 2
1: Odd: Real divider value is (DIV * 2) + 1

MCKOEN

Bit 9: I2S_MCK output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

SPI1

0x40003800: Serial peripheral interface

43/46 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDEN
rw 		BDOEN
rw 		CRCEN
rw 		CRCNT
rw 		FF16
rw 		RO
rw 		SWNSSEN
rw 		SWNSS
rw 		LF
rw 		SPIEN
rw 		PSC
rw 		MSTMOD
rw 		CKPL
rw 		CKPH
rw
Toggle Fields.

CKPH

Bit 0: Clock Phase Selection.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CKPL

Bit 1: Clock polarity Selection.

Allowed values:
0: IdleLow: CLK pulled low when idle
1: IdleHigh: CLK pulled high when idle

MSTMOD

Bit 2: Master Mode Enable.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

PSC

Bits 3-5: Master Clock Prescaler Selection.

Allowed values:
0: Div2: PCLK / 2
1: Div4: PCLK / 4
2: Div8: PCLK / 8
3: Div16: PCLK / 16
4: Div32: PCLK / 32
5: Div64: PCLK / 64
6: Div128: PCLK / 128
7: Div256: PCLK / 256

SPIEN

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LF

Bit 7: LSB First Mode.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SWNSS

Bit 8: NSS Pin Selection In NSS Software Mode.

Allowed values:
0: SlaveSelected: NSS is pulled low
1: SlaveNotSelected: NSS is pulled high

SWNSSEN

Bit 9: NSS Software Mode Selection.

Allowed values:
0: Hardware: Software slave management disabled
1: Software: Software slave management enabled

RO

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: ReceiveOnly: Output disabled (Receive-only mode)

FF16

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNT

Bit 12: CRC Next Transfer.

Allowed values:
0: Data: Next transmit value is data from Tx buffer
1: CRC: Next transmit value is CRC value from TCRC

CRCEN

Bit 13: CRC Calculation Enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BDOEN

Bit 14: Bidirectional Transmit output enable .

Allowed values:
0: ReceiveOnly: Receive-only mode
1: TransmitOnly: Transmit-only mode

BDEN

Bit 15: Bidirectional enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CTL1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

6/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBEIE
rw 		RBNEIE
rw 		ERRIE
rw 		TMOD
rw 		NSSP
rw 		NSSDRV
rw 		DMATEN
rw 		DMAREN
rw
Toggle Fields.

DMAREN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

DMATEN

Bit 1: Transmit Buffer DMA Enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

NSSDRV

Bit 2: Drive NSS Output.

Allowed values:
0: Disabled: NSS output is disabled in master mode
1: Enabled: NSS output is enabled in master mode

NSSP

Bit 3: SPI NSS pulse mode Enable.

TMOD

Bit 4: SPI TI Mode Enable.

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

RBNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Disabled: RBNE interrupt disabled
1: Enabled: RBNE interrupt enabled

TBEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Disabled: TBE interrupt disabled
1: Enabled: TBE interrupt enabled

STAT

status register

Offset: 0x8, reset: 0x00000002, access: Unspecified

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FERR
rw 		TRANS
r 		RXORERR
r 		CONFERR
r 		CRCERR
rw 		TXURERR
r 		I2SCH
r 		TBE
r 		RBNE
r
Toggle Fields.

RBNE

Bit 0: Receive Buffer Not Empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TBE

Bit 1: Transmit Buffer Empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

I2SCH

Bit 2: I2S channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

TXURERR

Bit 3: Transmission underrun error bit.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: SPI CRC Error Bit.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

CONFERR

Bit 5: SPI Configuration error.

Allowed values:
0: NoFault: No configuration fault occurred
1: Fault: Configuration fault occurred

RXORERR

Bit 6: Reception Overrun Error Bit.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

TRANS

Bit 7: Transmitting On-going Bit.

Allowed values:
0: Idle: SPI or I2S is idle
1: Busy: SPI or I2S is currently transmitting or receiving

FERR

Bit 8: Format Error.

DATA

data register

Offset: 0xC, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Data transfer register.

Allowed values: 0-65535

CRCPOLY

CRC polynomial register

Offset: 0x10, reset: 0x00000007, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0-65535

RCRC

RX CRC register

Offset: 0x14, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCRC
r
Toggle Fields.

RCRC

Bits 0-15: RX CRC register.

Allowed values: 0-65535

TCRC

TX CRC register

Offset: 0x18, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRC
r
Toggle Fields.

TCRC

Bits 0-15: Tx CRC register.

Allowed values: 0-65535

I2SCTL

I2S control register

Offset: 0x1C, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SSEL
rw 		I2SEN
rw 		I2SOPMOD
rw 		PCMSMOD
rw 		I2SSTD
rw 		CKPL
rw 		DTLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DTLEN

Bits 1-2: Data length.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPL

Bit 3: Idle state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSMOD

Bit 7: PCM frame synchronization mode.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SOPMOD

Bits 8-9: I2S operation mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SEN

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SSEL

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPSC

I2S prescaler register

Offset: 0x20, reset: 0x00000002, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOEN
rw 		OF
rw 		DIV
rw
Toggle Fields.

DIV

Bits 0-7: Dividing factor for the prescaler.

Allowed values: 1-255

OF

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is DIV * 2
1: Odd: Real divider value is (DIV * 2) + 1

MCKOEN

Bit 9: I2S_MCK output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

SPI2

0x40003C00: Serial peripheral interface

43/49 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDEN
rw 		BDOEN
rw 		CRCEN
rw 		CRCNT
rw 		FF16
rw 		RO
rw 		SWNSSEN
rw 		SWNSS
rw 		LF
rw 		SPIEN
rw 		PSC
rw 		MSTMOD
rw 		CKPL
rw 		CKPH
rw
Toggle Fields.

CKPH

Bit 0: Clock Phase Selection.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CKPL

Bit 1: Clock polarity Selection.

Allowed values:
0: IdleLow: CLK pulled low when idle
1: IdleHigh: CLK pulled high when idle

MSTMOD

Bit 2: Master Mode Enable.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

PSC

Bits 3-5: Master Clock Prescaler Selection.

Allowed values:
0: Div2: PCLK / 2
1: Div4: PCLK / 4
2: Div8: PCLK / 8
3: Div16: PCLK / 16
4: Div32: PCLK / 32
5: Div64: PCLK / 64
6: Div128: PCLK / 128
7: Div256: PCLK / 256

SPIEN

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LF

Bit 7: LSB First Mode.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SWNSS

Bit 8: NSS Pin Selection In NSS Software Mode.

Allowed values:
0: SlaveSelected: NSS is pulled low
1: SlaveNotSelected: NSS is pulled high

SWNSSEN

Bit 9: NSS Software Mode Selection.

Allowed values:
0: Hardware: Software slave management disabled
1: Software: Software slave management enabled

RO

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: ReceiveOnly: Output disabled (Receive-only mode)

FF16

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNT

Bit 12: CRC Next Transfer.

Allowed values:
0: Data: Next transmit value is data from Tx buffer
1: CRC: Next transmit value is CRC value from TCRC

CRCEN

Bit 13: CRC Calculation Enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BDOEN

Bit 14: Bidirectional Transmit output enable .

Allowed values:
0: ReceiveOnly: Receive-only mode
1: TransmitOnly: Transmit-only mode

BDEN

Bit 15: Bidirectional enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CTL1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

6/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBEIE
rw 		RBNEIE
rw 		ERRIE
rw 		TMOD
rw 		NSSP
rw 		NSSDRV
rw 		DMATEN
rw 		DMAREN
rw
Toggle Fields.

DMAREN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

DMATEN

Bit 1: Transmit Buffer DMA Enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

NSSDRV

Bit 2: Drive NSS Output.

Allowed values:
0: Disabled: NSS output is disabled in master mode
1: Enabled: NSS output is enabled in master mode

NSSP

Bit 3: SPI NSS pulse mode Enable.

TMOD

Bit 4: SPI TI Mode Enable.

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

RBNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Disabled: RBNE interrupt disabled
1: Enabled: RBNE interrupt enabled

TBEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Disabled: TBE interrupt disabled
1: Enabled: TBE interrupt enabled

STAT

status register

Offset: 0x8, reset: 0x00000002, access: Unspecified

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FERR
rw 		TRANS
r 		RXORERR
r 		CONFERR
r 		CRCERR
rw 		TXURERR
r 		I2SCH
r 		TBE
r 		RBNE
r
Toggle Fields.

RBNE

Bit 0: Receive Buffer Not Empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TBE

Bit 1: Transmit Buffer Empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

I2SCH

Bit 2: I2S channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

TXURERR

Bit 3: Transmission underrun error bit.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: SPI CRC Error Bit.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

CONFERR

Bit 5: SPI Configuration error.

Allowed values:
0: NoFault: No configuration fault occurred
1: Fault: Configuration fault occurred

RXORERR

Bit 6: Reception Overrun Error Bit.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

TRANS

Bit 7: Transmitting On-going Bit.

Allowed values:
0: Idle: SPI or I2S is idle
1: Busy: SPI or I2S is currently transmitting or receiving

FERR

Bit 8: Format Error.

DATA

data register

Offset: 0xC, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Data transfer register.

Allowed values: 0-65535

CRCPOLY

CRC polynomial register

Offset: 0x10, reset: 0x00000007, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0-65535

RCRC

RX CRC register

Offset: 0x14, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCRC
r
Toggle Fields.

RCRC

Bits 0-15: RX CRC register.

Allowed values: 0-65535

TCRC

TX CRC register

Offset: 0x18, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRC
r
Toggle Fields.

TCRC

Bits 0-15: Tx CRC register.

Allowed values: 0-65535

I2SCTL

I2S control register

Offset: 0x1C, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SSEL
rw 		I2SEN
rw 		I2SOPMOD
rw 		PCMSMOD
rw 		I2SSTD
rw 		CKPL
rw 		DTLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DTLEN

Bits 1-2: Data length.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPL

Bit 3: Idle state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSMOD

Bit 7: PCM frame synchronization mode.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SOPMOD

Bits 8-9: I2S operation mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SEN

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SSEL

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPSC

I2S prescaler register

Offset: 0x20, reset: 0x00000002, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOEN
rw 		OF
rw 		DIV
rw
Toggle Fields.

DIV

Bits 0-7: Dividing factor for the prescaler.

Allowed values: 1-255

OF

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is DIV * 2
1: Odd: Real divider value is (DIV * 2) + 1

MCKOEN

Bit 9: I2S_MCK output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

QCTL

Quad-SPI mode control register

Offset: 0x80, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IO23_DRV
rw 		QRD
rw 		QMOD
rw
Toggle Fields.

QMOD

Bit 0: Quad-SPI mode enable.

QRD

Bit 1: Quad-SPI mode read select.

IO23_DRV

Bit 2: Drive IO2 and IO3 enable.

SQPI

0xA0001000: Serial/Quad Parallel Interface

2/15 fields covered. Toggle Registers.

INIT

SQPI Initial Register

Offset: 0x0, reset: 0x18010004, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQPI_PL
rw 		SQPI_IDLEN
rw 		SQPI_ADDRBIT
rw 		SQPI_CLKDIV
rw 		SQPI_CMDBIT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

SQPI_CMDBIT

Bits 16-17: Bit number of SQPI controller command phase.

SQPI_CLKDIV

Bits 18-23: Clock divider for SQPI output clock.

SQPI_ADDRBIT

Bits 24-28: Bit number of SPI PSRAM address phase..

SQPI_IDLEN

Bits 29-30: SQPI controller external memory ID length .

SQPI_PL

Bit 31: Read data sample polarity..

RCMD

SQPI Read Command Register

Offset: 0x4, reset: 0x00100000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQPI_RID
rw 		SQPI_RMODE
rw 		SQPI_RWAITCYCLE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQPI_RCMD
rw
Toggle Fields.

SQPI_RCMD

Bits 0-15: SQPI read command for AHB read transfer.

SQPI_RWAITCYCLE

Bits 16-19: SQPI read command waitcycle number after address phase.

SQPI_RMODE

Bits 20-22: SQPI controller read command mode.

SQPI_RID

Bit 31: Send read ID command.

WCMD

Write Command Register

Offset: 0x8, reset: 0x00010000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQPI_SC
rw 		SQPI_WMODE
rw 		SQPI_WWAITCYCLE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI_WCMD
rw
Toggle Fields.

SPI_WCMD

Bits 0-15: SQPI write command for AHB write transfer.

SQPI_WWAITCYCLE

Bits 16-19: SQPI write command waitcycle number after address phase.

SQPI_WMODE

Bits 20-22: SQPI controller write command mode.

SQPI_SC

Bit 31: Send special command .

IDL

ID Low Register

Offset: 0xC, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQPI_IDL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQPI_IDL
r
Toggle Fields.

SQPI_IDL

Bits 0-31: ID Low Data saved for SQPI Read ID Command.

IDH

ID High Register

Offset: 0x10, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQPI_IDH
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQPI_IDH
r
Toggle Fields.

SQPI_IDH

Bits 0-31: ID High Data saved for SQPI read ID command.

TIMER0

0x40012C00: Advanced-timers

127/129 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UPDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

UPS

Bit 2: Update source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UPG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

SPM

Bit 3: Single pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CAM

Bits 5-6: Counter aligns mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAlignedCountingDown: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAlignedCountingUp: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAlignedCountingUpDown: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:
0: Disabled: The shadow register for CAR is disabled
1: Enabled: The shadow register for CAR is enabled

CKDIV

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CTL1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISO3
rw 		ISO2N
rw 		ISO2
rw 		ISO1N
rw 		ISO1
rw 		ISO0N
rw 		ISO0
rw 		TI0S
rw 		MMC
rw 		DMAS
rw 		CCUC
rw 		CCSE
rw
Toggle Fields.

CCSE

Bit 0: Commutation control shadow enable.

Allowed values:
0: NotPreloaded: The shadow registers for CHxEN, CHxNEN and CHxCOMCTL bits are disabled
1: Preloaded: The shadow registers for CHxEN, CHxNEN and CHxCOMCTL bits are enabled

CCUC

Bit 2: Commutation control shadow register update control.

Allowed values:
0: Default: Capture/compare are updated only by setting the CMTG bit
1: WithRisingEdge: Capture/compare are updated by setting the CMTG bit or when an rising edge occurs on TRGI

DMAS

Bit 3: DMA request source selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMC

Bits 4-6: Master mode control.

Allowed values:
0: Reset: Use UPG bit from SWEVG register
1: Enable: Use CEN bit from CTL0 register
2: Update: Use the update event
3: CaptureComparePulse: The trigger output send a positive pulse when a capture or a compare match occurred in channel 0
4: CompareO0C: O0CPRE signal is used as trigger output
5: CompareO1C: O1CPRE signal is used as trigger output
6: CompareO2C: O2CPRE signal is used as trigger output
7: CompareO3C: O3CPRE signal is used as trigger output

TI0S

Bit 7: Channel 0 trigger input selection.

Allowed values:
0: Normal: The CH0 pin input is selected as channel 0 trigger input
1: XOR: The XOR of CH0, CH1 and CH2 pins are selected as channel 0 trigger input

ISO0

Bit 8: Idle state of channel 0 output.

Allowed values:
0: Low: CHn_O=0 (after a dead-time if CHn_ON is implemented) when POEN=0
1: High: CHn_O=1 (after a dead-time if CHn_ON is implemented) when POEN=0

ISO0N

Bit 9: Idle state of channel 0 complementary output.

Allowed values:
0: Low: CHn_ON=0 when POEN=0
1: High: CHn_ON=1 when POEN=0

ISO1

Bit 10: Idle state of channel 1 output.

Allowed values:

ISO1N

Bit 11: Idle state of channel 1 complementary output.

Allowed values:
0: Low: CHn_ON=0 when POEN=0
1: High: CHn_ON=1 when POEN=0

ISO2

Bit 12: Idle state of channel 2 output.

Allowed values:
0: Low: CHn_O=0 (after a dead-time if CHn_ON is implemented) when POEN=0
1: High: CHn_O=1 (after a dead-time if CHn_ON is implemented) when POEN=0

ISO2N

Bit 13: Idle state of channel 2 complementary output.

Allowed values:
0: Low: CHn_ON=0 when POEN=0
1: High: CHn_ON=1 when POEN=0

ISO3

Bit 14: Idle state of channel 3 output.

Allowed values:
0: Low: CHn_O=0 (after a dead-time if CHn_ON is implemented) when POEN=0
1: High: CHn_O=1 (after a dead-time if CHn_ON is implemented) when POEN=0

SMCFG

slave mode configuration register

Offset: 0x8, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.
1: QuadratureDecoderMode0: Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.
2: QuadratureDecoderMode1: Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.
3: QuadratureDecoderMode2: Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.
4: RestartMode: Restart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: PauseMode: Pause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: EventMode: Event Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: ExternalClockMode: External Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.

TRGS

Bits 4-6: Trigger selection.

Allowed values:
0: ITI0: Internal Trigger 0 (ITI0)
1: ITI1: Internal Trigger 1 (ITI1)
2: ITI2: Internal Trigger 2 (ITI2)
4: CI0F_ED: CI0 Edge Detector (CI0F_ED)
5: CI0FE0: Filtered Timer Input 0 (CI0FE0)
6: CI1FE1: Filtered Timer Input 1 (CI1FE1)
7: ETIFP: External Trigger input (ETIFP)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETFC

Bits 8-11: External trigger filter control.

Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8

ETPSC

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: External trigger prescaler disabled
1: Div2: ETI frequency divided by 2
2: Div4: ETI frequency divided by 4
3: Div8: ETI frequency divided by 8

SMC1

Bit 14: Part of SMC for enable External clock mode1.

Allowed values:
0: Disabled: External clock mode 1 disabled
1: Enabled: External clock mode 1 enabled. The counter is clocked by any active edge on the ETIF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETI is noninverted, active at high level or rising edge
1: Inverted: ETI is inverted, active at low level or falling edge

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CMTDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		BRKIE
rw 		TRGIE
rw 		CMTIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

Allowed values:
0: Disabled: Capture/compare interrupt disabled
1: Enabled: Capture/compare interrupt enabled

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

Allowed values:
0: Disabled: Capture/compare interrupt disabled
1: Enabled: Capture/compare interrupt enabled

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

Allowed values:
0: Disabled: Capture/compare interrupt disabled
1: Enabled: Capture/compare interrupt enabled

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

Allowed values:
0: Disabled: Capture/compare interrupt disabled
1: Enabled: Capture/compare interrupt enabled

CMTIE

Bit 5: commutation interrupt enable.

Allowed values:
0: Disabled: Commutation interrupt disabled
1: Enabled: Commutation interrupt enabled

TRGIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BRKIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CMTDEN

Bit 13: Commutation DMA request enable.

Allowed values:
0: Disabled: Commutation DMA request disabled
1: Enabled: Commutation DMA request enabled

TRGDEN

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

INTF

Interrupt flag register

Offset: 0x10, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		BRKIF
rw 		TRGIF
rw 		CMTIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update interrupt occurred
1: UpdatePending: Update interrupt pending.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

Allowed values:
0: Clear: No capture or compare interrupt occurred
1: CaptureCompare: A capture or compare event occurred

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

Allowed values:
0: Clear: No capture or compare interrupt occurred
1: CaptureCompare: A capture or compare event occurred

CH2IF

Bit 3: Channel 2 capture/compare interrupt flag.

Allowed values:
0: Clear: No capture or compare interrupt occurred
1: CaptureCompare: A capture or compare event occurred

CH3IF

Bit 4: Channel 3 capture/compare interrupt flag.

Allowed values:
0: Clear: No capture or compare interrupt occurred
1: CaptureCompare: A capture or compare event occurred

CMTIF

Bit 5: Channel commutation interrupt flag.

Allowed values:
0: Clear: No channel commutation event occured
1: Commutation: Channel commutation event occurred

TRGIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: Clear: No trigger event occured
1: Triggered: Trigger event occurred

BRKIF

Bit 7: Break interrupt flag.

Allowed values:
0: Clear: No active level break detected
1: Break: Active level detected

CH0OF

Bit 9: Channel 0 over capture flag.

Allowed values:
0: Clear: No over capture occurred
1: OverCapture: A capture event occured while CHnIF was already set

CH1OF

Bit 10: Channel 1 over capture flag.

Allowed values:
0: Clear: No over capture occurred
1: OverCapture: A capture event occured while CHnIF was already set

CH2OF

Bit 11: Channel 2 over capture flag.

Allowed values:
0: Clear: No over capture occurred
1: OverCapture: A capture event occured while CHnIF was already set

CH3OF

Bit 12: Channel 3 over capture flag.

Allowed values:
0: Clear: No over capture occurred
1: OverCapture: A capture event occured while CHnIF was already set

SWEVG

Software event generation register

Offset: 0x14, reset: 0x00000000, access: write-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRKG
w 		TRGG
w 		CMTG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update event generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CH0G

Bit 1: Channel 0 capture or compare event generation.

Allowed values:
1: CaptureCompare: Generate a capture or compare event

CH1G

Bit 2: Channel 1 capture or compare event generation.

Allowed values:
1: CaptureCompare: Generate a capture or compare event

CH2G

Bit 3: Channel 2 capture or compare event generation.

Allowed values:
1: CaptureCompare: Generate a capture or compare event

CH3G

Bit 4: Channel 3 capture or compare event generation.

Allowed values:
1: CaptureCompare: Generate a capture or compare event

CMTG

Bit 5: Channel commutation event generation.

Allowed values:
1: Update: Generate a channel commutation event, updating capture/compare control registers based on the value of CCSE

TRGG

Bit 6: Trigger event generation.

Allowed values:
1: Trigger: Generate a trigger event

BRKG

Bit 7: Break event generation.

Allowed values:
1: Break: Generate a break event

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

Allowed values:
0: Output: Channel is configured as output
1: CI0: Channel is configured as input, ISx is connected to CI0FEx
2: CI1: Channel is configured as input, ISx is connected to CI1FEx
3: ITS: Channel is configured as input, ISx is connected to ITS

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

Allowed values:
0: Div1: Prescaler disabled, capture on every edge
1: Div2: Capture every 2 edges
2: Div4: Capture every 4 edges
3: Div8: Capture every 8 edges

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8

CH1MS

Bits 8-9: Channel 1 mode selection.

Allowed values:

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

Allowed values:

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

Allowed values:

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

Allowed values:

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

Allowed values:

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

Allowed values:

CH3MS

Bits 8-9: Channel 3 mode selection.

Allowed values:

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

Allowed values:

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

Allowed values:

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2NEN
rw 		CH2P
rw 		CH2EN
rw 		CH1NP
rw 		CH1NEN
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0NEN
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

Allowed values:
0: Disabled: Channel output is disabled
1: Enabled: Channel output is enabled

CH0P

Bit 1: Channel 0 capture/compare function polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH0NEN

Bit 2: Channel 0 complementary output enable.

Allowed values:

CH0NP

Bit 3: Channel 0 complementary output polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH1EN

Bit 4: Channel 1 capture/compare function enable.

Allowed values:
0: Disabled: Channel output is disabled
1: Enabled: Channel output is enabled

CH1P

Bit 5: Channel 1 capture/compare function polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH1NEN

Bit 6: Channel 1 complementary output enable.

Allowed values:

CH1NP

Bit 7: Channel 1 complementary output polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH2EN

Bit 8: Channel 2 capture/compare function enable.

Allowed values:
0: Disabled: Channel output is disabled
1: Enabled: Channel output is enabled

CH2P

Bit 9: Channel 2 capture/compare function polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH2NEN

Bit 10: Channel 2 complementary output enable.

Allowed values:

CH2NP

Bit 11: Channel 2 complementary output polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH3EN

Bit 12: Channel 3 capture/compare function enable.

Allowed values:
0: Disabled: Channel output is disabled
1: Enabled: Channel output is enabled

CH3P

Bit 13: Channel 3 capture/compare function polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CREP

Counter repetition register

Offset: 0x30, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CREP
rw
Toggle Fields.

CREP

Bits 0-7: Counter repetition value.

Allowed values: 0-255

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel0.

Allowed values: 0-65535

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

Allowed values: 0-65535

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: Capture or compare value of channel 2.

Allowed values: 0-65535

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: Capture or compare value of channel 3.

Allowed values: 0-65535

CCHP

channel complementary protection register

Offset: 0x44, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POEN
rw 		OAEN
rw 		BRKP
rw 		BRKEN
rw 		ROS
rw 		IOS
rw 		PROT
rw 		DTCFG
rw
Toggle Fields.

DTCFG

Bits 0-7: Dead time configure.

Allowed values: 0-255

PROT

Bits 8-9: Complementary register protect control.

Allowed values:
0: Disabled: Write protection disabled
1: Mode0: Protection mode 0
2: Mode1: Protection mode 1
3: Mode2: Protection mode 2

IOS

Bit 10: Idle mode off-state configure.

Allowed values:
0: Disabled: When POEN is reset, the channel output signals are disabled
1: Enabled: When POEN is reset, the channel output signals are enabled

ROS

Bit 11: Run mode off-state configure.

Allowed values:
0: Disabled: When POEN is set, the channel output signals are disabled
1: Enabled: When POEN is set, the channel output signals are enabled

BRKEN

Bit 12: Break enable.

Allowed values:
0: Disabled: Break inputs disabled
1: Enabled: Break inputs enabled

BRKP

Bit 13: Break polarity.

Allowed values:
0: Inverted: BRKIN is active low
1: NotInverted: BRKIN is active high

OAEN

Bit 14: Output automatic enable.

Allowed values:
0: Manual: POEN cannot be set by hardware
1: Automatic: POEN can be set by hardware automatically at the next update event

POEN

Bit 15: Primary output enable.

Allowed values:
0: Disabled: Channel outputs are disabled
1: Enabled: Channel outputs are enabled

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

Allowed values: 0-31

DMATC

Bits 8-12: DMA transfer count.

Allowed values: 0-31

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

Allowed values: 0-65535

CFG

Configuration register

Offset: 0xFC, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw 		OUTSEL
rw
Toggle Fields.

OUTSEL

Bit 0: The output value selection.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER1

0x40000000: General-purpose-timers

100/101 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

SPM

Bit 3: Single pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:

CAM

Bits 5-6: Counter aligns mode selection.

Allowed values:

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

Allowed values:

CTL1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI0S
rw 		MMC
rw 		DMAS
rw
Toggle Fields.

DMAS

Bit 3: DMA request source selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMC

Bits 4-6: Master mode control.

Allowed values:
0: Reset: Use UPG bit from SWEVG register
1: Enable: Use CEN bit from CTL0 register
2: Update: Use the update event

TI0S

Bit 7: Channel 0 trigger input selection.

Allowed values:
0: Normal: The CH0 pin input is selected as channel 0 trigger input
1: XOR: The XOR of CH0, CH1 and CH2 pins are selected as channel 0 trigger input

SMCFG

slave mode control register

Offset: 0x8, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

Allowed values:
0: Disabled: Slave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.
1: QuadratureDecoderMode0: Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.
2: QuadratureDecoderMode1: Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.
3: QuadratureDecoderMode2: Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.
4: RestartMode: Restart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: PauseMode: Pause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: EventMode: Event Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: ExternalClockMode: External Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.

TRGS

Bits 4-6: Trigger selection.

Allowed values:
0: ITI0: Internal Trigger 0 (ITI0)
1: ITI1: Internal Trigger 1 (ITI1)
2: ITI2: Internal Trigger 2 (ITI2)
4: CI0F_ED: CI0 Edge Detector (CI0F_ED)
5: CI0FE0: Filtered Timer Input 0 (CI0FE0)
6: CI1FE1: Filtered Timer Input 1 (CI1FE1)
7: ETIFP: External Trigger input (ETIFP)

MSM

Bit 7: Master-slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETFC

Bits 8-11: External trigger filter control.

Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8

ETPSC

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: External trigger prescaler disabled
1: Div2: ETI frequency divided by 2
2: Div4: ETI frequency divided by 4
3: Div8: ETI frequency divided by 8

SMC1

Bit 14: Part of SMC for enable External clock mode1.

Allowed values:
0: Disabled: External clock mode 1 disabled
1: Enabled: External clock mode 1 enabled. The counter is clocked by any active edge on the ETIF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETI is noninverted, active at high level or rising edge
1: Inverted: ETI is inverted, active at low level or falling edge

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		TRGIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

Allowed values:

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

Allowed values:

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

Allowed values:

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

Allowed values:

TRGIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

TRGDEN

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

INTF

interrupt flag register

Offset: 0x10, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

Allowed values:

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

Allowed values:

CH2IF

Bit 3: Channel 2 capture/compare interrupt enable.

Allowed values:

CH3IF

Bit 4: Channel 3 capture/compare interrupt enable.

Allowed values:

TRGIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: Clear: No trigger event occured
1: Triggered: Trigger event occurred

CH0OF

Bit 9: Channel 0 over capture flag.

Allowed values:

CH1OF

Bit 10: Channel 1 over capture flag.

Allowed values:

CH2OF

Bit 11: Channel 2 over capture flag.

Allowed values:

CH3OF

Bit 12: Channel 3 over capture flag.

Allowed values:

SWEVG

event generation register

Offset: 0x14, reset: 0x00000000, access: write-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

Allowed values:

CH1G

Bit 2: Channel 1 capture or compare event generation.

Allowed values:

CH2G

Bit 3: Channel 2 capture or compare event generation.

Allowed values:

CH3G

Bit 4: Channel 3 capture or compare event generation.

Allowed values:

TRGG

Bit 6: Trigger event generation.

Allowed values:
1: Trigger: Generate a trigger event

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

Allowed values:

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

Allowed values:

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

Allowed values:

CH1MS

Bits 8-9: Channel 1 mode selection.

Allowed values:

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

Allowed values:

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

Allowed values:

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

Allowed values:

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

Allowed values:

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

Allowed values:

CH3MS

Bits 8-9: Channel 3 mode selection.

Allowed values:

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

Allowed values:

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

Allowed values:

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3NP
rw 		CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2P
rw 		CH2EN
rw 		CH1NP
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

Allowed values:

CH0P

Bit 1: Channel 0 capture/compare function polarity.

Allowed values:

CH0NP

Bit 3: Channel 0 complementary output polarity.

Allowed values:

CH1EN

Bit 4: Channel 1 capture/compare function enable.

Allowed values:

CH1P

Bit 5: Channel 1 capture/compare function polarity.

Allowed values:

CH1NP

Bit 7: Channel 1 complementary output polarity.

Allowed values:

CH2EN

Bit 8: Channel 2 capture/compare function enable.

Allowed values:

CH2P

Bit 9: Channel 2 capture/compare function polarity.

Allowed values:

CH2NP

Bit 11: Channel 2 complementary output polarity.

Allowed values:

CH3EN

Bit 12: Channel 3 capture/compare function enable.

Allowed values:

CH3P

Bit 13: Channel 3 capture/compare function polarity.

Allowed values:

CH3NP

Bit 15: Channel 3 complementary output polarity.

Allowed values:

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-31: counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-31: Counter auto reload value.

Allowed values: 0-65535

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH0VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-31: Capture or compare value of channel 0.

Allowed values: 0-65535

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-31: Capture or compare value of channel1.

Allowed values: 0-65535

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH2VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-31: Capture or compare value of channel 2.

Allowed values: 0-65535

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH3VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-31: Capture or compare value of channel 3.

Allowed values: 0-65535

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

Allowed values: 0-31

DMATC

Bits 8-12: DMA transfer count.

Allowed values: 0-31

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

Allowed values: 0-65535

CFG

Configuration

Offset: 0xFC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER10

0x40015400: General-purpose-timers

11/28 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMC
rw
Toggle Fields.

MMC

Bits 4-6: Master mode control.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0OF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x00000000, access: write-only

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

CHCTL0_Input

Channel control register 0 ( (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

Allowed values: 0-65535

CFG

configuration register

Offset: 0xFC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER11

0x40001800: General-purpose-timers

12/49 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

SPM

Bit 3: Single pulse mode.

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

SMCFG

slave mode configuration register

Offset: 0x8, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master-slave mode.

DMAINTEN

DMA and interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGIE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x00000000, access: read-write

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

TRGIF

Bit 6: Trigger interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x00000000, access: write-only

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

TRGG

Bit 6: Trigger event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1NP
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CH1NP

Bit 7: Channel 1 complementary output polarity.

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel0.

Allowed values: 0-65535

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

Allowed values: 0-65535

CFG

configuration register

Offset: 0xFC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER12

0x40001C00: General-purpose-timers

11/28 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMC
rw
Toggle Fields.

MMC

Bits 4-6: Master mode control.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0OF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x00000000, access: write-only

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

CHCTL0_Input

Channel control register 0 ( (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

Allowed values: 0-65535

CFG

configuration register

Offset: 0xFC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER13

0x40002000: General-purpose-timers

26/28 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

Allowed values:

CTL1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMC
rw
Toggle Fields.

MMC

Bits 4-6: Master mode control.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

Allowed values:

INTF

interrupt flag register

Offset: 0x10, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0OF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

Allowed values:

CH0OF

Bit 9: Channel 0 over capture flag.

Allowed values:

SWEVG

event generation register

Offset: 0x14, reset: 0x00000000, access: write-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

Allowed values:

CHCTL0_Input

Channel control register 0 ( (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

Allowed values:

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

Allowed values:

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

Allowed values:

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

Allowed values:

CH0P

Bit 1: Channel 0 capture/compare polarity.

Allowed values:

CH0NP

Bit 3: Channel 0 complementary output polarity.

Allowed values:

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

Allowed values: 0-65535

CFG

configuration register

Offset: 0xFC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER2

0x40000400: General-purpose-timers

100/101 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

SPM

Bit 3: Single pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:

CAM

Bits 5-6: Counter aligns mode selection.

Allowed values:

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

Allowed values:

CTL1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI0S
rw 		MMC
rw 		DMAS
rw
Toggle Fields.

DMAS

Bit 3: DMA request source selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMC

Bits 4-6: Master mode control.

Allowed values:
0: Reset: Use UPG bit from SWEVG register
1: Enable: Use CEN bit from CTL0 register
2: Update: Use the update event

TI0S

Bit 7: Channel 0 trigger input selection.

Allowed values:
0: Normal: The CH0 pin input is selected as channel 0 trigger input
1: XOR: The XOR of CH0, CH1 and CH2 pins are selected as channel 0 trigger input

SMCFG

slave mode control register

Offset: 0x8, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

Allowed values:
0: Disabled: Slave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.
1: QuadratureDecoderMode0: Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.
2: QuadratureDecoderMode1: Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.
3: QuadratureDecoderMode2: Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.
4: RestartMode: Restart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: PauseMode: Pause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: EventMode: Event Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: ExternalClockMode: External Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.

TRGS

Bits 4-6: Trigger selection.

Allowed values:
0: ITI0: Internal Trigger 0 (ITI0)
1: ITI1: Internal Trigger 1 (ITI1)
2: ITI2: Internal Trigger 2 (ITI2)
4: CI0F_ED: CI0 Edge Detector (CI0F_ED)
5: CI0FE0: Filtered Timer Input 0 (CI0FE0)
6: CI1FE1: Filtered Timer Input 1 (CI1FE1)
7: ETIFP: External Trigger input (ETIFP)

MSM

Bit 7: Master-slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETFC

Bits 8-11: External trigger filter control.

Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8

ETPSC

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: External trigger prescaler disabled
1: Div2: ETI frequency divided by 2
2: Div4: ETI frequency divided by 4
3: Div8: ETI frequency divided by 8

SMC1

Bit 14: Part of SMC for enable External clock mode1.

Allowed values:
0: Disabled: External clock mode 1 disabled
1: Enabled: External clock mode 1 enabled. The counter is clocked by any active edge on the ETIF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETI is noninverted, active at high level or rising edge
1: Inverted: ETI is inverted, active at low level or falling edge

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		TRGIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

Allowed values:

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

Allowed values:

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

Allowed values:

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

Allowed values:

TRGIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

TRGDEN

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

INTF

interrupt flag register

Offset: 0x10, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

Allowed values:

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

Allowed values:

CH2IF

Bit 3: Channel 2 capture/compare interrupt enable.

Allowed values:

CH3IF

Bit 4: Channel 3 capture/compare interrupt enable.

Allowed values:

TRGIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: Clear: No trigger event occured
1: Triggered: Trigger event occurred

CH0OF

Bit 9: Channel 0 over capture flag.

Allowed values:

CH1OF

Bit 10: Channel 1 over capture flag.

Allowed values:

CH2OF

Bit 11: Channel 2 over capture flag.

Allowed values:

CH3OF

Bit 12: Channel 3 over capture flag.

Allowed values:

SWEVG

event generation register

Offset: 0x14, reset: 0x00000000, access: write-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

Allowed values:

CH1G

Bit 2: Channel 1 capture or compare event generation.

Allowed values:

CH2G

Bit 3: Channel 2 capture or compare event generation.

Allowed values:

CH3G

Bit 4: Channel 3 capture or compare event generation.

Allowed values:

TRGG

Bit 6: Trigger event generation.

Allowed values:
1: Trigger: Generate a trigger event

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

Allowed values:

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

Allowed values:

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

Allowed values:

CH1MS

Bits 8-9: Channel 1 mode selection.

Allowed values:

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

Allowed values:

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

Allowed values:

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

Allowed values:

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

Allowed values:

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

Allowed values:

CH3MS

Bits 8-9: Channel 3 mode selection.

Allowed values:

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

Allowed values:

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

Allowed values:

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3NP
rw 		CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2P
rw 		CH2EN
rw 		CH1NP
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

Allowed values:

CH0P

Bit 1: Channel 0 capture/compare function polarity.

Allowed values:

CH0NP

Bit 3: Channel 0 complementary output polarity.

Allowed values:

CH1EN

Bit 4: Channel 1 capture/compare function enable.

Allowed values:

CH1P

Bit 5: Channel 1 capture/compare function polarity.

Allowed values:

CH1NP

Bit 7: Channel 1 complementary output polarity.

Allowed values:

CH2EN

Bit 8: Channel 2 capture/compare function enable.

Allowed values:

CH2P

Bit 9: Channel 2 capture/compare function polarity.

Allowed values:

CH2NP

Bit 11: Channel 2 complementary output polarity.

Allowed values:

CH3EN

Bit 12: Channel 3 capture/compare function enable.

Allowed values:

CH3P

Bit 13: Channel 3 capture/compare function polarity.

Allowed values:

CH3NP

Bit 15: Channel 3 complementary output polarity.

Allowed values:

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

Allowed values: 0-65535

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

Allowed values: 0-65535

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: Capture or compare value of channel 2.

Allowed values: 0-65535

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: Capture or compare value of channel 3.

Allowed values: 0-65535

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

Allowed values: 0-31

DMATC

Bits 8-12: DMA transfer count.

Allowed values: 0-31

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

Allowed values: 0-65535

CFG

Configuration

Offset: 0xFC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER3

0x40000800: General-purpose-timers

25/101 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

5/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

SPM

Bit 3: Single pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI0S
rw 		MMC
rw 		DMAS
rw
Toggle Fields.

DMAS

Bit 3: DMA request source selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMC

Bits 4-6: Master mode control.

Allowed values:
0: Reset: Use UPG bit from SWEVG register
1: Enable: Use CEN bit from CTL0 register
2: Update: Use the update event

TI0S

Bit 7: Channel 0 trigger input selection.

SMCFG

slave mode control register

Offset: 0x8, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master-slave mode.

ETFC

Bits 8-11: External trigger filter control.

ETPSC

Bits 12-13: External trigger prescaler.

SMC1

Bit 14: Part of SMC for enable External clock mode1.

ETP

Bit 15: External trigger polarity.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

6/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		TRGIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

TRGDEN

Bit 14: Trigger DMA request enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x00000000, access: read-write

1/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

CH2IF

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IF

Bit 4: Channel 3 capture/compare interrupt enable.

TRGIF

Bit 6: Trigger interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

CH2OF

Bit 11: Channel 2 over capture flag.

CH3OF

Bit 12: Channel 3 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x00000000, access: write-only

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

CH2G

Bit 3: Channel 2 capture or compare event generation.

CH3G

Bit 4: Channel 3 capture or compare event generation.

TRGG

Bit 6: Trigger event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

CH3MS

Bits 8-9: Channel 3 mode selection.

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3NP
rw 		CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2P
rw 		CH2EN
rw 		CH1NP
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CH1NP

Bit 7: Channel 1 complementary output polarity.

CH2EN

Bit 8: Channel 2 capture/compare function enable.

CH2P

Bit 9: Channel 2 capture/compare function polarity.

CH2NP

Bit 11: Channel 2 complementary output polarity.

CH3EN

Bit 12: Channel 3 capture/compare function enable.

CH3P

Bit 13: Channel 3 capture/compare function polarity.

CH3NP

Bit 15: Channel 3 complementary output polarity.

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

Allowed values: 0-65535

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

Allowed values: 0-65535

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: Capture or compare value of channel 2.

Allowed values: 0-65535

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: Capture or compare value of channel 3.

Allowed values: 0-65535

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

Allowed values: 0-31

DMATC

Bits 8-12: DMA transfer count.

Allowed values: 0-31

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

Allowed values: 0-65535

CFG

Configuration

Offset: 0xFC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER4

0x40000C00: General-purpose-timers

25/101 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

5/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

SPM

Bit 3: Single pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI0S
rw 		MMC
rw 		DMAS
rw
Toggle Fields.

DMAS

Bit 3: DMA request source selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMC

Bits 4-6: Master mode control.

Allowed values:
0: Reset: Use UPG bit from SWEVG register
1: Enable: Use CEN bit from CTL0 register
2: Update: Use the update event

TI0S

Bit 7: Channel 0 trigger input selection.

SMCFG

slave mode control register

Offset: 0x8, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master-slave mode.

ETFC

Bits 8-11: External trigger filter control.

ETPSC

Bits 12-13: External trigger prescaler.

SMC1

Bit 14: Part of SMC for enable External clock mode1.

ETP

Bit 15: External trigger polarity.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

6/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		TRGIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

TRGDEN

Bit 14: Trigger DMA request enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x00000000, access: read-write

1/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

CH2IF

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IF

Bit 4: Channel 3 capture/compare interrupt enable.

TRGIF

Bit 6: Trigger interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

CH2OF

Bit 11: Channel 2 over capture flag.

CH3OF

Bit 12: Channel 3 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x00000000, access: write-only

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

CH2G

Bit 3: Channel 2 capture or compare event generation.

CH3G

Bit 4: Channel 3 capture or compare event generation.

TRGG

Bit 6: Trigger event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

CH3MS

Bits 8-9: Channel 3 mode selection.

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3NP
rw 		CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2P
rw 		CH2EN
rw 		CH1NP
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CH1NP

Bit 7: Channel 1 complementary output polarity.

CH2EN

Bit 8: Channel 2 capture/compare function enable.

CH2P

Bit 9: Channel 2 capture/compare function polarity.

CH2NP

Bit 11: Channel 2 complementary output polarity.

CH3EN

Bit 12: Channel 3 capture/compare function enable.

CH3P

Bit 13: Channel 3 capture/compare function polarity.

CH3NP

Bit 15: Channel 3 complementary output polarity.

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

Allowed values: 0-65535

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

Allowed values: 0-65535

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: Capture or compare value of channel 2.

Allowed values: 0-65535

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: Capture or compare value of channel 3.

Allowed values: 0-65535

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

Allowed values: 0-31

DMATC

Bits 8-12: DMA transfer count.

Allowed values: 0-31

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

Allowed values: 0-65535

CFG

Configuration

Offset: 0xFC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER5

0x40001000: Basic-timers

13/13 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARSE
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

SPM

Bit 3: Single pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CTL1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMC
rw
Toggle Fields.

MMC

Bits 4-6: Master mode control.

Allowed values:
0: Reset: Use UPG bit from SWEVG register
1: Enable: Use CEN bit from CTL0 register
2: Update: Use the update event

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPDEN
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

INTF

Interrupt flag register

Offset: 0x10, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

SWEVG

event generation register

Offset: 0x14, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Low counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

TIMER6

0x40001400: Basic-timers

12/13 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARSE
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

SPM

Bit 3: Single pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CTL1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMC
rw
Toggle Fields.

MMC

Bits 4-6: Master mode control.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPDEN
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

INTF

Interrupt flag register

Offset: 0x10, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

SWEVG

event generation register

Offset: 0x14, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Low counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

TIMER7

0x40013400: Advanced-timers

24/129 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

5/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

SPM

Bit 3: Single pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

1/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISO3
rw 		ISO2N
rw 		ISO2
rw 		ISO1N
rw 		ISO1
rw 		ISO0N
rw 		ISO0
rw 		TI0S
rw 		MMC
rw 		DMAS
rw 		CCUC
rw 		CCSE
rw
Toggle Fields.

CCSE

Bit 0: Commutation control shadow enable.

CCUC

Bit 2: Commutation control shadow register update control.

DMAS

Bit 3: DMA request source selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMC

Bits 4-6: Master mode control.

TI0S

Bit 7: Channel 0 trigger input selection.

ISO0

Bit 8: Idle state of channel 0 output.

ISO0N

Bit 9: Idle state of channel 0 complementary output.

ISO1

Bit 10: Idle state of channel 1 output.

ISO1N

Bit 11: Idle state of channel 1 complementary output.

ISO2

Bit 12: Idle state of channel 2 output.

ISO2N

Bit 13: Idle state of channel 2 complementary output.

ISO3

Bit 14: Idle state of channel 3 output.

SMCFG

slave mode configuration register

Offset: 0x8, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode selection.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETFC

Bits 8-11: External trigger filter control.

ETPSC

Bits 12-13: External trigger prescaler.

SMC1

Bit 14: Part of SMC for enable External clock mode1.

ETP

Bit 15: External trigger polarity.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

6/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CMTDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		BRKIE
rw 		TRGIE
rw 		CMTIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

CMTIE

Bit 5: commutation interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

BRKIE

Bit 7: Break interrupt enable.

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CMTDEN

Bit 13: Commutation DMA request enable.

TRGDEN

Bit 14: Trigger DMA request enable.

INTF

Interrupt flag register

Offset: 0x10, reset: 0x00000000, access: read-write

1/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		BRKIF
rw 		TRGIF
rw 		CMTIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

CH2IF

Bit 3: Channel 2 capture/compare interrupt flag.

CH3IF

Bit 4: Channel 3 capture/compare interrupt flag.

CMTIF

Bit 5: Channel commutation interrupt flag.

TRGIF

Bit 6: Trigger interrupt flag.

BRKIF

Bit 7: Break interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

CH2OF

Bit 11: Channel 2 over capture flag.

CH3OF

Bit 12: Channel 3 over capture flag.

SWEVG

Software event generation register

Offset: 0x14, reset: 0x00000000, access: write-only

1/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRKG
w 		TRGG
w 		CMTG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update event generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

CH2G

Bit 3: Channel 2 capture or compare event generation.

CH3G

Bit 4: Channel 3 capture or compare event generation.

CMTG

Bit 5: Channel commutation event generation.

TRGG

Bit 6: Trigger event generation.

BRKG

Bit 7: Break event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

CH3MS

Bits 8-9: Channel 3 mode selection.

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2NEN
rw 		CH2P
rw 		CH2EN
rw 		CH1NP
rw 		CH1NEN
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0NEN
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH0NEN

Bit 2: Channel 0 complementary output enable.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CH1NEN

Bit 6: Channel 1 complementary output enable.

CH1NP

Bit 7: Channel 1 complementary output polarity.

CH2EN

Bit 8: Channel 2 capture/compare function enable.

CH2P

Bit 9: Channel 2 capture/compare function polarity.

CH2NEN

Bit 10: Channel 2 complementary output enable.

CH2NP

Bit 11: Channel 2 complementary output polarity.

CH3EN

Bit 12: Channel 3 capture/compare function enable.

CH3P

Bit 13: Channel 3 capture/compare function polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CREP

Counter repetition register

Offset: 0x30, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CREP
rw
Toggle Fields.

CREP

Bits 0-7: Counter repetition value.

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel0.

Allowed values: 0-65535

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

Allowed values: 0-65535

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: Capture or compare value of channel 2.

Allowed values: 0-65535

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: Capture or compare value of channel 3.

Allowed values: 0-65535

CCHP

channel complementary protection register

Offset: 0x44, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POEN
rw 		OAEN
rw 		BRKP
rw 		BRKEN
rw 		ROS
rw 		IOS
rw 		PROT
rw 		DTCFG
rw
Toggle Fields.

DTCFG

Bits 0-7: Dead time configure.

PROT

Bits 8-9: Complementary register protect control.

IOS

Bit 10: Idle mode off-state configure.

ROS

Bit 11: Run mode off-state configure.

BRKEN

Bit 12: Break enable.

BRKP

Bit 13: Break polarity.

OAEN

Bit 14: Output automatic enable.

POEN

Bit 15: Primary output enable.

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

Allowed values: 0-31

DMATC

Bits 8-12: DMA transfer count.

Allowed values: 0-31

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

Allowed values: 0-65535

CFG

Configuration register

Offset: 0xFC, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw 		OUTSEL
rw
Toggle Fields.

OUTSEL

Bit 0: The output value selection.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER8

0x40014c00: General-purpose-timers

12/49 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

SPM

Bit 3: Single pulse mode.

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

SMCFG

slave mode configuration register

Offset: 0x8, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master-slave mode.

DMAINTEN

DMA and interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGIE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x00000000, access: read-write

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

TRGIF

Bit 6: Trigger interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x00000000, access: write-only

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

TRGG

Bit 6: Trigger event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1NP
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CH1NP

Bit 7: Channel 1 complementary output polarity.

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel0.

Allowed values: 0-65535

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

Allowed values: 0-65535

CFG

configuration register

Offset: 0xFC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER9

0x40015000: General-purpose-timers

11/28 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMC
rw
Toggle Fields.

MMC

Bits 4-6: Master mode control.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x00000000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0OF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x00000000, access: write-only

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

CHCTL0_Input

Channel control register 0 ( (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

Allowed values: 0-65535

CFG

configuration register

Offset: 0xFC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

UART3

0x40004C00: Universal asynchronous receiver transmitter

9/44 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

INTDIV

Bits 4-15: Integer part of baud-rate divider.

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVSMOD
rw 		UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

RWU

Bit 1: Receiver wakeup from mute mode.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE line detected interrupt enable.

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

PERRIE

Bit 8: Parity error interrupt enable.

PM

Bit 9: Parity mode.

PCEN

Bit 10: Parity check function enable.

WM

Bit 11: Wakeup method in mute mode.

WL

Bit 12: Word length.

UEN

Bit 13: USART enable.

OVSMOD

Bit 15: Oversampe mode.

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

LBLEN

Bit 5: LIN break frame length.

LBDIE

Bit 6: LIN break detection interrupt enable.

STB

Bits 12-13: STOP bits length.

LMEN

Bit 14: LIN mode enable.

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSB
rw 		DENT
rw 		DENR
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDEN

Bit 3: Half-duplex selection.

DENR

Bit 6: DMA request enable for reception.

DENT

Bit 7: DMA request enable for transmission.

OSB

Bit 11: One sample bit method enable.

GP

Guard time and prescaler register

Offset: 0x18, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GUAT

Bits 8-15: Guard time value in Smartcard mode.

GDCTL

GD control register

Offset: 0xD0, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CD
w 		CDEN
rw
Toggle Fields.

CDEN

Bit 1: Collision detection enable.

CD

Bit 8: Collision detected status.

CDIE

Bit 16: Collision detected interrupt enable.

UART4

0x40005000: Universal asynchronous receiver transmitter

9/44 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

INTDIV

Bits 4-15: Integer part of baud-rate divider.

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVSMOD
rw 		UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

RWU

Bit 1: Receiver wakeup from mute mode.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE line detected interrupt enable.

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

PERRIE

Bit 8: Parity error interrupt enable.

PM

Bit 9: Parity mode.

PCEN

Bit 10: Parity check function enable.

WM

Bit 11: Wakeup method in mute mode.

WL

Bit 12: Word length.

UEN

Bit 13: USART enable.

OVSMOD

Bit 15: Oversampe mode.

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

LBLEN

Bit 5: LIN break frame length.

LBDIE

Bit 6: LIN break detection interrupt enable.

STB

Bits 12-13: STOP bits length.

LMEN

Bit 14: LIN mode enable.

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSB
rw 		DENT
rw 		DENR
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDEN

Bit 3: Half-duplex selection.

DENR

Bit 6: DMA request enable for reception.

DENT

Bit 7: DMA request enable for transmission.

OSB

Bit 11: One sample bit method enable.

GP

Guard time and prescaler register

Offset: 0x18, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GUAT

Bits 8-15: Guard time value in Smartcard mode.

GDCTL

GD control register

Offset: 0xD0, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CD
w 		CDEN
rw
Toggle Fields.

CDEN

Bit 1: Collision detection enable.

CD

Bit 8: Collision detected status.

CDIE

Bit 16: Collision detected interrupt enable.

USART0

0x40013800: Universal synchronous asynchronous receiver transmitter

11/67 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSF
r 		LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS change flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

INTDIV

Bits 4-15: Integer part of baud-rate divider.

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVSMOD
rw 		UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

RWU

Bit 1: Receiver wakeup from mute mode.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE line detected interrupt enable.

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

PERRIE

Bit 8: Parity error interrupt enable.

PM

Bit 9: Parity mode.

PCEN

Bit 10: Parity check function enable.

WM

Bit 11: Wakeup method in mute mode.

WL

Bit 12: Word length.

UEN

Bit 13: USART enable.

OVSMOD

Bit 15: Oversampe mode.

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

LBLEN

Bit 5: LIN break frame length.

LBDIE

Bit 6: LIN break detection interrupt enable.

CLEN

Bit 8: CK Length.

CPH

Bit 9: Clock phase.

CPL

Bit 10: Clock polarity.

CKEN

Bit 11: CK pin enable.

STB

Bits 12-13: STOP bits length.

LMEN

Bit 14: LIN mode enable.

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSB
rw 		CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDEN

Bit 3: Half-duplex selection.

NKEN

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DENR

Bit 6: DMA request enable for reception.

DENT

Bit 7: DMA request enable for transmission.

RTSEN

Bit 8: RTS enable.

CTSEN

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

OSB

Bit 11: One sample bit method.

GP

Guard time and prescaler register

Offset: 0x18, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GUAT

Bits 8-15: Guard time value in Smartcard mode.

CTL3

Control register 3

Offset: 0x80, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSBF
rw 		DINV
rw 		TINV
rw 		RINV
rw 		EBIE
rw 		RTIE
rw 		SCRTNUM
rw 		RTEN
rw
Toggle Fields.

RTEN

Bit 0: Receiver timeout enable.

SCRTNUM

Bits 1-3: Smartcard auto-retry number.

RTIE

Bit 4: Interrupt enable bit of receive timeout event.

EBIE

Bit 5: Interrupt enable bit of end of block event.

RINV

Bit 8: RX pin level inversion.

TINV

Bit 9: TX pin level inversion.

DINV

Bit 10: Data bit level inversion.

MSBF

Bit 11: Most significant bit first.

RT

Receiver timeout register

Offset: 0x84, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BL
rw 		RT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT
rw
Toggle Fields.

RT

Bits 0-23: Receiver timeout threshold.

BL

Bits 24-31: Block Length.

STAT1

Status register 1

Offset: 0x88, reset: 0x00000000, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBF
w 		RTF
w
Toggle Fields.

RTF

Bit 11: Receiver timeout flag.

EBF

Bit 12: End of block flag.

BSY

Bit 16: Busy flag.

GDCTL

GD control register

Offset: 0xD0, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CD
w 		CDEN
rw
Toggle Fields.

CDEN

Bit 1: Collision detection enable.

CD

Bit 8: Collision detected status.

CDIE

Bit 16: Collision detected interrupt enable.

USART1

0x40004400: Universal synchronous asynchronous receiver transmitter

11/67 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSF
r 		LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS change flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

INTDIV

Bits 4-15: Integer part of baud-rate divider.

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVSMOD
rw 		UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

RWU

Bit 1: Receiver wakeup from mute mode.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE line detected interrupt enable.

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

PERRIE

Bit 8: Parity error interrupt enable.

PM

Bit 9: Parity mode.

PCEN

Bit 10: Parity check function enable.

WM

Bit 11: Wakeup method in mute mode.

WL

Bit 12: Word length.

UEN

Bit 13: USART enable.

OVSMOD

Bit 15: Oversampe mode.

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

LBLEN

Bit 5: LIN break frame length.

LBDIE

Bit 6: LIN break detection interrupt enable.

CLEN

Bit 8: CK Length.

CPH

Bit 9: Clock phase.

CPL

Bit 10: Clock polarity.

CKEN

Bit 11: CK pin enable.

STB

Bits 12-13: STOP bits length.

LMEN

Bit 14: LIN mode enable.

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSB
rw 		CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDEN

Bit 3: Half-duplex selection.

NKEN

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DENR

Bit 6: DMA request enable for reception.

DENT

Bit 7: DMA request enable for transmission.

RTSEN

Bit 8: RTS enable.

CTSEN

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

OSB

Bit 11: One sample bit method.

GP

Guard time and prescaler register

Offset: 0x18, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GUAT

Bits 8-15: Guard time value in Smartcard mode.

CTL3

Control register 3

Offset: 0x80, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSBF
rw 		DINV
rw 		TINV
rw 		RINV
rw 		EBIE
rw 		RTIE
rw 		SCRTNUM
rw 		RTEN
rw
Toggle Fields.

RTEN

Bit 0: Receiver timeout enable.

SCRTNUM

Bits 1-3: Smartcard auto-retry number.

RTIE

Bit 4: Interrupt enable bit of receive timeout event.

EBIE

Bit 5: Interrupt enable bit of end of block event.

RINV

Bit 8: RX pin level inversion.

TINV

Bit 9: TX pin level inversion.

DINV

Bit 10: Data bit level inversion.

MSBF

Bit 11: Most significant bit first.

RT

Receiver timeout register

Offset: 0x84, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BL
rw 		RT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT
rw
Toggle Fields.

RT

Bits 0-23: Receiver timeout threshold.

BL

Bits 24-31: Block Length.

STAT1

Status register 1

Offset: 0x88, reset: 0x00000000, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBF
w 		RTF
w
Toggle Fields.

RTF

Bit 11: Receiver timeout flag.

EBF

Bit 12: End of block flag.

BSY

Bit 16: Busy flag.

GDCTL

GD control register

Offset: 0xD0, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CD
w 		CDEN
rw
Toggle Fields.

CDEN

Bit 1: Collision detection enable.

CD

Bit 8: Collision detected status.

CDIE

Bit 16: Collision detected interrupt enable.

USART2

0x40004800: Universal synchronous asynchronous receiver transmitter

11/67 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSF
r 		LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS change flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

INTDIV

Bits 4-15: Integer part of baud-rate divider.

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVSMOD
rw 		UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

RWU

Bit 1: Receiver wakeup from mute mode.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE line detected interrupt enable.

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

PERRIE

Bit 8: Parity error interrupt enable.

PM

Bit 9: Parity mode.

PCEN

Bit 10: Parity check function enable.

WM

Bit 11: Wakeup method in mute mode.

WL

Bit 12: Word length.

UEN

Bit 13: USART enable.

OVSMOD

Bit 15: Oversampe mode.

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

LBLEN

Bit 5: LIN break frame length.

LBDIE

Bit 6: LIN break detection interrupt enable.

CLEN

Bit 8: CK Length.

CPH

Bit 9: Clock phase.

CPL

Bit 10: Clock polarity.

CKEN

Bit 11: CK pin enable.

STB

Bits 12-13: STOP bits length.

LMEN

Bit 14: LIN mode enable.

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSB
rw 		CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDEN

Bit 3: Half-duplex selection.

NKEN

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DENR

Bit 6: DMA request enable for reception.

DENT

Bit 7: DMA request enable for transmission.

RTSEN

Bit 8: RTS enable.

CTSEN

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

OSB

Bit 11: One sample bit method.

GP

Guard time and prescaler register

Offset: 0x18, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GUAT

Bits 8-15: Guard time value in Smartcard mode.

CTL3

Control register 3

Offset: 0x80, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSBF
rw 		DINV
rw 		TINV
rw 		RINV
rw 		EBIE
rw 		RTIE
rw 		SCRTNUM
rw 		RTEN
rw
Toggle Fields.

RTEN

Bit 0: Receiver timeout enable.

SCRTNUM

Bits 1-3: Smartcard auto-retry number.

RTIE

Bit 4: Interrupt enable bit of receive timeout event.

EBIE

Bit 5: Interrupt enable bit of end of block event.

RINV

Bit 8: RX pin level inversion.

TINV

Bit 9: TX pin level inversion.

DINV

Bit 10: Data bit level inversion.

MSBF

Bit 11: Most significant bit first.

RT

Receiver timeout register

Offset: 0x84, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BL
rw 		RT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT
rw
Toggle Fields.

RT

Bits 0-23: Receiver timeout threshold.

BL

Bits 24-31: Block Length.

STAT1

Status register 1

Offset: 0x88, reset: 0x00000000, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBF
w 		RTF
w
Toggle Fields.

RTF

Bit 11: Receiver timeout flag.

EBF

Bit 12: End of block flag.

BSY

Bit 16: Busy flag.

GDCTL

GD control register

Offset: 0xD0, reset: 0x00000000, access: Unspecified

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CD
w 		CDEN
rw
Toggle Fields.

CDEN

Bit 1: Collision detection enable.

CD

Bit 8: Collision detected status.

CDIE

Bit 16: Collision detected interrupt enable.

USART5

0x40017000: Universal asynchronous receiver transmitter

24/103 fields covered. Toggle Registers.

CTL0

Control register 0

Offset: 0x0, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EBIE
rw 		RTIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVSMOD
rw 		AMIE
rw 		MEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		UESM
rw 		UEN
rw
Toggle Fields.

UEN

Bit 0: USART enable.

UESM

Bit 1: USART enable in Deep-sleep mode.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE line detected interrupt enable.

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TBEIE

Bit 7: Transmitter register empty interrupt enable.

PERRIE

Bit 8: Parity error interrupt enable.

PM

Bit 9: Parity mode.

PCEN

Bit 10: Parity control enable.

WM

Bit 11: Wakeup method in mute mode.

WL

Bit 12: Word length.

MEN

Bit 13: Mute mode enable.

AMIE

Bit 14: ADDR match interrupt enable.

OVSMOD

Bit 15: Oversample mode.

RTIE

Bit 26: Receiver timeout interrupt enable.

EBIE

Bit 27: End of Block interrupt enable.

CTL1

Control register 1

Offset: 0x4, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
rw 		RTEN
rw 		ABDM
rw 		ABDEN
rw 		MSBF
rw 		DINV
rw 		TINV
rw 		RINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRP
rw 		LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDM
rw
Toggle Fields.

ADDM

Bit 4: Address detection mode.

LBLEN

Bit 5: LIN break frame length.

LBDIE

Bit 6: LIN break detection interrupt enable.

CLEN

Bit 8: CK length.

CPH

Bit 9: Clock phase.

CPL

Bit 10: Clock polarity.

CKEN

Bit 11: CK pin enable.

STB

Bits 12-13: STOP bits length.

LMEN

Bit 14: LIN mode enable.

STRP

Bit 15: Swap TX/RX pins.

RINV

Bit 16: RX pin level inversion.

TINV

Bit 17: TX pin level inversion.

DINV

Bit 18: Data bit level inversion.

MSBF

Bit 19: Most significant bit first.

ABDEN

Bit 20: Auto baud rate enable.

ABDM

Bits 21-22: Auto baud rate mode.

RTEN

Bit 23: Receiver timeout enable.

ADDR

Bits 24-31: Address of the USART terminal.

CTL2

Control register 2

Offset: 0x8, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUIE
rw 		WUM
rw 		SCRTNUM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDRE
rw 		OVRD
rw 		OSB
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDEN

Bit 3: Half-duplex enable.

NKEN

Bit 4: NACK enable in Smartcard mode.

SCEN

Bit 5: Smartcard mode enable.

DENR

Bit 6: DMA enable for reception.

DENT

Bit 7: DMA enable for transmission.

OSB

Bit 11: One sample bit method.

OVRD

Bit 12: Overrun disable.

DDRE

Bit 13: Disable DMA on reception error.

SCRTNUM

Bits 17-19: Smartcard auto-retry number.

WUM

Bits 20-21: Wakeup mode from Deep-sleep mode.

WUIE

Bit 22: Wakeup from Deep-sleep mode interrupt enable.

BAUD

Baud rate generator register

Offset: 0xC, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR_4_15
rw 		BRR_0_3
rw
Toggle Fields.

BRR_0_3

Bits 0-3: Fraction of baud-rate divider.

BRR_4_15

Bits 4-15: Integer of baud-rate divider.

GP

Prescaler and guard time configuration register

Offset: 0x10, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value for dividing the system clock.

GUAT

Bits 8-15: Guard time value in smartcard mode.

RT

Receiver timeout register

Offset: 0x14, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BL
rw 		RT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT
rw
Toggle Fields.

RT

Bits 0-23: Receiver timeout threshold.

BL

Bits 24-31: Block Length.

CMD

Command register (USART_CMD)

Offset: 0x18, reset: 0x00000000, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFCMD
w 		RXFCMD
w 		MMCMD
w 		SBKCMD
w 		ABDCMD
w
Toggle Fields.

ABDCMD

Bit 0: Auto baudrate detection command.

SBKCMD

Bit 1: Send break command.

MMCMD

Bit 2: Mute mode command.

RXFCMD

Bit 3: Receive data flush command.

TXFCMD

Bit 4: Transmit data flush request.

STAT

Status register

Offset: 0x1C, reset: 0x000000C0, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REA
r 		TEA
r 		WUF
r 		RWU
r 		SBF
r 		AMF
r 		BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABDF
r 		ABDE
r 		EBF
r 		RTF
r 		LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE line detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission completed.

TBE

Bit 7: Transmit data register empty.

LBDF

Bit 8: LIN break detected flag.

RTF

Bit 11: Receiver timeout flag.

EBF

Bit 12: End of block flag.

ABDE

Bit 14: Auto baudrate detection error.

ABDF

Bit 15: Auto baudrate detection flag.

BSY

Bit 16: Busy flag.

AMF

Bit 17: ADDR match flag.

SBF

Bit 18: Send break flag.

RWU

Bit 19: Receiver wakeup from mute mode.

WUF

Bit 20: Wakeup from Deep-sleep mode flag.

TEA

Bit 21: Transmit enable acknowledge flag.

REA

Bit 22: Receive enable acknowledge flag.

INTC

Interrupt status clear register

Offset: 0x20, reset: 0x00000000, access: write-only

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUC
w 		AMC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBC
w 		RTC
w 		LBDC
w 		TCC
w 		IDLEC
w 		OREC
w 		NEC
w 		FEC
w 		PEC
w
Toggle Fields.

PEC

Bit 0: Parity error clear.

FEC

Bit 1: Frame error flag clear.

NEC

Bit 2: Noise detected clear.

OREC

Bit 3: Overrun error clear.

IDLEC

Bit 4: Idle line detected clear.

TCC

Bit 6: Transmission complete clear.

LBDC

Bit 8: LIN break detected clear.

RTC

Bit 11: Receiver timeout clear.

EBC

Bit 12: End of block clear.

AMC

Bit 17: ADDR match clear.

WUC

Bit 20: Wakeup from Deep-sleep mode clear.

RDATA

Receive data register (

Offset: 0x24, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle Fields.

RDATA

Bits 0-8: Receive Data value.

TDATA

Transmit data register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDATA
rw
Toggle Fields.

TDATA

Bits 0-8: Transmit Data value.

CHC

USART coherence control register

Offset: 0xC0, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPERR
rw 		HCM
rw
Toggle Fields.

HCM

Bit 0: Hardware flow control coherence mode.

EPERR

Bit 8: Early parity error flag.

RFCS

receive FIFO control and status register

Offset: 0xD0, reset: 0x00000400, access: Unspecified

3/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFFINT
rw 		RFCNT
r 		RFF
r 		RFE
r 		RFFIE
rw 		RFEN
rw 		ELNACK
rw
Toggle Fields.

ELNACK

Bit 0: Early NACK when smartcard mode is selected.

RFEN

Bit 8: Receive FIFO enable.

RFFIE

Bit 9: Receive FIFO full interrupt enable.

RFE

Bit 10: Receive FIFO empty flag.

RFF

Bit 11: Receive FIFO full flag.

RFCNT

Bits 12-14: Receive FIFO counter number.

RFFINT

Bit 15: Receive FIFO full interrupt flag.

USBD

0x40005C00: Universal serial bus full-speed device interface

5/118 fields covered. Toggle Registers.

EP0CS

endpoint 0 register

Offset: 0x0, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_ST
rw 		RX_DTG
rw 		RX_STA
rw 		SETUP
rw 		EP_CTL
rw 		EP_KCTL
rw 		TX_ST
rw 		TX_DTG
rw 		TX_STA
rw 		EP_AR
rw
Toggle Fields.

EP_AR

Bits 0-3: Endpoint address.

TX_STA

Bits 4-5: Status bits, for transmission transfers.

TX_DTG

Bit 6: Data PID Toggle, for transmission transfers.

TX_ST

Bit 7: Correct Transfer for transmission.

EP_KCTL

Bit 8: Endpoint kind.

EP_CTL

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

RX_STA

Bits 12-13: Status bits, for reception transfers.

RX_DTG

Bit 14: Data Toggle, for reception transfers.

RX_ST

Bit 15: Correct transfer for reception.

EP1CS

endpoint 1 register

Offset: 0x4, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_ST
rw 		RX_DTG
rw 		RX_STA
rw 		SETUP
rw 		EP_CTL
rw 		EP_KCTL
rw 		TX_ST
rw 		TX_DTG
rw 		TX_STA
rw 		EP_AR
rw
Toggle Fields.

EP_AR

Bits 0-3: Endpoint address.

TX_STA

Bits 4-5: Status bits, for transmission transfers.

TX_DTG

Bit 6: Data Toggle, for transmission transfers.

TX_ST

Bit 7: Correct Transfer for transmission.

EP_KCTL

Bit 8: Endpoint kind.

EP_CTL

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

RX_STA

Bits 12-13: Status bits, for reception transfers.

RX_DTG

Bit 14: Data Toggle, for reception transfers.

RX_ST

Bit 15: Correct transfer for reception.

EP2CS

endpoint 2 register

Offset: 0x8, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_ST
rw 		RX_DTG
rw 		RX_STA
rw 		SETUP
rw 		EP_CTL
rw 		EP_KCTL
rw 		TX_ST
rw 		TX_DTG
rw 		TX_STA
rw 		EP_AR
rw
Toggle Fields.

EP_AR

Bits 0-3: Endpoint address.

TX_STA

Bits 4-5: Status bits, for transmission transfers.

TX_DTG

Bit 6: Data Toggle, for transmission transfers.

TX_ST

Bit 7: Correct Transfer for transmission.

EP_KCTL

Bit 8: Endpoint kind.

EP_CTL

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

RX_STA

Bits 12-13: Status bits, for reception transfers.

RX_DTG

Bit 14: Data Toggle, for reception transfers.

RX_ST

Bit 15: Correct transfer for reception.

EP3CS

endpoint 3 register

Offset: 0xC, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_ST
rw 		RX_DTG
rw 		RX_STA
rw 		SETUP
rw 		EP_CTL
rw 		EP_KCTL
rw 		TX_ST
rw 		TX_DTG
rw 		TX_STA
rw 		EP_AR
rw
Toggle Fields.

EP_AR

Bits 0-3: Endpoint address.

TX_STA

Bits 4-5: Status bits, for transmission transfers.

TX_DTG

Bit 6: Data Toggle, for transmission transfers.

TX_ST

Bit 7: Correct Transfer for transmission.

EP_KCTL

Bit 8: Endpoint kind.

EP_CTL

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

RX_STA

Bits 12-13: Status bits, for reception transfers.

RX_DTG

Bit 14: Data Toggle, for reception transfers.

RX_ST

Bit 15: Correct transfer for reception.

EP4CS

endpoint 4 register

Offset: 0x10, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_ST
rw 		RX_DTG
rw 		RX_STA
rw 		SETUP
rw 		EP_CTL
rw 		EP_KCTL
rw 		TX_ST
rw 		TX_DTG
rw 		TX_STA
rw 		EP_AR
rw
Toggle Fields.

EP_AR

Bits 0-3: Endpoint address.

TX_STA

Bits 4-5: Status bits, for transmission transfers.

TX_DTG

Bit 6: Data Toggle, for transmission transfers.

TX_ST

Bit 7: Correct Transfer for transmission.

EP_KCTL

Bit 8: Endpoint kind.

EP_CTL

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

RX_STA

Bits 12-13: Status bits, for reception transfers.

RX_DTG

Bit 14: Data Toggle, for reception transfers.

RX_ST

Bit 15: Correct transfer for reception.

EP5CS

endpoint 5 register

Offset: 0x14, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_ST
rw 		RX_DTG
rw 		RX_STA
rw 		SETUP
rw 		EP_CTL
rw 		EP_KCTL
rw 		TX_ST
rw 		TX_DTG
rw 		TX_STA
rw 		EP_AR
rw
Toggle Fields.

EP_AR

Bits 0-3: Endpoint address.

TX_STA

Bits 4-5: Status bits, for transmission transfers.

TX_DTG

Bit 6: Data Toggle, for transmission transfers.

TX_ST

Bit 7: Correct Transfer for transmission.

EP_KCTL

Bit 8: Endpoint kind.

EP_CTL

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

RX_STA

Bits 12-13: Status bits, for reception transfers.

RX_DTG

Bit 14: Data Toggle, for reception transfers.

RX_ST

Bit 15: Correct transfer for reception.

EP6CS

endpoint 6 register

Offset: 0x18, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_ST
rw 		RX_DTG
rw 		RX_STA
rw 		SETUP
rw 		EP_CTL
rw 		EP_KCTL
rw 		TX_ST
rw 		TX_DTG
rw 		TX_STA
rw 		EP_AR
rw
Toggle Fields.

EP_AR

Bits 0-3: Endpoint address.

TX_STA

Bits 4-5: Status bits, for transmission transfers.

TX_DTG

Bit 6: Data Toggle, for transmission transfers.

TX_ST

Bit 7: Correct Transfer for transmission.

EP_KCTL

Bit 8: Endpoint kind.

EP_CTL

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

RX_STA

Bits 12-13: Status bits, for reception transfers.

RX_DTG

Bit 14: Data Toggle, for reception transfers.

RX_ST

Bit 15: Correct transfer for reception.

EP7CS

endpoint 7 register

Offset: 0x1C, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_ST
rw 		RX_DTG
rw 		RX_STA
rw 		SETUP
rw 		EP_CTL
rw 		EP_KCTL
rw 		TX_ST
rw 		TX_DTG
rw 		TX_STA
rw 		EP_AR
rw
Toggle Fields.

EP_AR

Bits 0-3: Endpoint address.

TX_STA

Bits 4-5: Status bits, for transmission transfers.

TX_DTG

Bit 6: Data Toggle, for transmission transfers.

TX_ST

Bit 7: Correct Transfer for transmission.

EP_KCTL

Bit 8: Endpoint kind.

EP_CTL

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

RX_STA

Bits 12-13: Status bits, for reception transfers.

RX_DTG

Bit 14: Data Toggle, for reception transfers.

RX_ST

Bit 15: Correct transfer for reception.

CTL

control register

Offset: 0x40, reset: 0x0003, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STIE
rw 		PMOUIE
rw 		ERRIE
rw 		WKUPIE
rw 		SPSIE
rw 		RSTIE
rw 		SOFIE
rw 		ESOFIE
rw 		L1REQIE
rw 		L1RSREQ
rw 		RSREQ
rw 		SETSPS
rw 		LOWM
rw 		CLOSE
rw 		SETRST
rw
Toggle Fields.

SETRST

Bit 0: Set reset.

CLOSE

Bit 1: Close state.

LOWM

Bit 2: Low-power mode.

SETSPS

Bit 3: Set suspend.

RSREQ

Bit 4: Resume request.

L1RSREQ

Bit 5: LPM L1 resume request.

L1REQIE

Bit 7: LPM L1 state request interrupt enable.

ESOFIE

Bit 8: Expected start of frame interrupt enable.

SOFIE

Bit 9: Start of frame interrupt mask.

RSTIE

Bit 10: USB reset interrupt mask.

SPSIE

Bit 11: Suspend mode interrupt mask.

WKUPIE

Bit 12: Wakeup interrupt enable.

ERRIE

Bit 13: Error interrupt mask.

PMOUIE

Bit 14: Packet memory area over / underrun interrupt enable.

STIE

Bit 15: Successful transfer interrupt enable.

INTF

interrupt flag register

Offset: 0x44, reset: 0x0000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STIF
rw 		PMOUIF
rw 		ERRIF
rw 		WKUPIF
rw 		SPSIF
rw 		RSTIF
rw 		SOFIF
rw 		ESOFIF
rw 		L1REQ
rw 		DIR
rw 		EPNUM
rw
Toggle Fields.

EPNUM

Bits 0-3: Endpoint Identifier.

DIR

Bit 4: Direction of transaction.

L1REQ

Bit 7: LPM L1 transaction is successful .

ESOFIF

Bit 8: Expected start of frame interrupt flag.

SOFIF

Bit 9: start of frame interrupt flag.

RSTIF

Bit 10: reset interrupt flag.

SPSIF

Bit 11: Suspend mode interrupt flag.

WKUPIF

Bit 12: Wakeup interrupt flag.

ERRIF

Bit 13: Error interrupt flag.

PMOUIF

Bit 14: Packet memory area over / underrun interrupt flag.

STIF

Bit 15: Successful transfer interrupt flag.

STAT

Status register

Offset: 0x48, reset: 0x0000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_DP
r 		RX_DM
r 		LOCK
r 		SOFLN
r 		FCNT
r
Toggle Fields.

FCNT

Bits 0-10: Frame number counter.

SOFLN

Bits 11-12: Lost SOF number.

LOCK

Bit 13: Locked the USB.

RX_DM

Bit 14: Receive data - line status.

RX_DP

Bit 15: Receive data + line status.

ADDR

device address register

Offset: 0x4C, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBEN
rw 		USBDAR
rw
Toggle Fields.

USBDAR

Bits 0-6: Device address.

USBEN

Bit 7: USB device enable.

BADDR

Buffer address register

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BAR
rw
Toggle Fields.

BAR

Bits 3-15: Buffer address.

LPMCS

USB LPM control and status register

Offset: 0x54, reset: 0x0000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BLSTAT
rw 		REMWK
rw 		LPMACK
rw 		LPMEN
rw
Toggle Fields.

LPMEN

Bit 0: LPM support enable.

LPMACK

Bit 1: LPM token acknowledge enable.

REMWK

Bit 3: bRemoteWake value.

BLSTAT

Bits 4-7: bLinkState value.

WWDGT

0x40002C00: Window watchdog timer

6/6 fields covered. Toggle Registers.

CTL

Control register

Offset: 0x0, reset: 0x0000007F, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGTEN
rw 		CNT
rw
Toggle Fields.

CNT

Bits 0-6: 7-bit counter.

Allowed values: 0-127

WDGTEN

Bit 7: Activation bit.

Allowed values:
0: Disabled: Watchdog disabled
1: Enabled: Watchdog enabled

CFG

Configuration register

Offset: 0x4, reset: 0x0000007F, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIE
rw 		PSC
rw 		WIN
rw
Toggle Fields.

WIN

Bits 0-6: 7-bit window value.

Allowed values: 0-127

PSC

Bits 7-8: Prescaler.

Allowed values:
0: Div1: Counter clock (PCLK1 div 4096) div 1
1: Div2: Counter clock (PCLK1 div 4096) div 2
2: Div4: Counter clock (PCLK1 div 4096) div 4
3: Div8: Counter clock (PCLK1 div 4096) div 8

EWIE

Bit 9: Early wakeup interrupt.

Allowed values:
1: Enable: interrupt occurs whenever the counter reaches the value 0x40

STAT

Status register

Offset: 0x8, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
rw
Toggle Fields.

EWIF

Bit 0: Early wakeup interrupt flag.

Allowed values:
1: Pending: The EWI Interrupt Service Routine has been triggered
0: Finished: The EWI Interrupt Service Routine has been serviced