Overall: 4052/9418 fields covered

ADC0

0x40012400: Analog to digital converter

87/88 fields covered. Toggle Registers.

STAT

status register

Offset: 0x0, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRC
rw 		STIC
rw 		EOIC
rw 		EOC
rw 		WDE
rw
Toggle Fields.

WDE

Bit 0: Analog watchdog event flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC

Bit 1: End of group conversion flag.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

EOIC

Bit 2: End of inserted group conversion flag.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

STIC

Bit 3: Start flag of inserted channel group.

Allowed values:
0: NotStarted: No inserted channel group conversion started
1: Started: Inserted channel group conversion has started

STRC

Bit 4: Start flag of regular channel group.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

CTL0

control register 0

Offset: 0x4, reset: 0x00000000, access: read-write

12/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RWDEN
rw 		IWDEN
rw 		SYNCM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISNUM
rw 		DISIC
rw 		DISRC
rw 		ICA
rw 		WDSC
rw 		SM
rw 		EOICIE
rw 		WDEIE
rw 		EOCIE
rw 		WDCHSEL
rw
Toggle Fields.

WDCHSEL

Bits 0-4: Analog watchdog channel select.

Allowed values: 0-18

EOCIE

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set

WDEIE

Bit 6: Interrupt enable for WDE.

Allowed values:
0: Disabled: WDE interrupt disabled
1: Enabled: WDE interrupt enabled. An interrupt is generated when the WDE bit is set

EOICIE

Bit 7: Interrupt enable for EOIC.

Allowed values:
0: Disabled: EOIC interrupt disabled
1: Enabled: EOIC interrupt enabled. An interrupt is generated when the EOIC bit is set

SM

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

WDSC

Bit 9: When in scan mode, analog watchdog is effective on a single channel.

Allowed values:
0: All: Analog watchdog enabled on all channels
1: Single: Analog watchdog enabled on a single channel

ICA

Bit 10: Inserted channel group convert automatically.

Allowed values:
0: Disabled: Automatic inserted group conversion disabled
1: Enabled: Automatic inserted group conversion enabled

DISRC

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

DISIC

Bit 12: Discontinuous mode on inserted channels.

Allowed values:
0: Disabled: Discontinuous mode on inserted channels disabled
1: Enabled: Discontinuous mode on inserted channels enabled

DISNUM

Bits 13-15: Number of conversions in discontinuous mode.

Allowed values: 0-7

SYNCM

Bits 16-19: sync mode selection.

IWDEN

Bit 22: Inserted channel analog watchdog enable.

Allowed values:
0: Disabled: Analog watchdog disabled on inserted channels
1: Enabled: Analog watchdog enabled on inserted channels

RWDEN

Bit 23: Regular channel analog watchdog enable.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

CTL1

control register 1

Offset: 0x8, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSVREN
rw 		SWRCST
rw 		SWICST
rw 		ETERC
rw 		ETSRC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETEIC
rw 		ETSIC
rw 		DAL
rw 		DMA
rw 		RSTCLB
rw 		CLB
rw 		CTN
rw 		ADCON
rw
Toggle Fields.

ADCON

Bit 0: ADC on.

Allowed values:
0: Disabled: Disable ADC conversion/calibration and go to power down mode
1: Enabled: Enable ADC and to start conversion

CTN

Bit 1: Continuous mode.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

CLB

Bit 2: ADC calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

RSTCLB

Bit 3: Reset calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

DMA

Bit 8: DMA request enable.

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

DAL

Bit 11: Data alignment.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

ETSIC

Bits 12-14: External trigger select for inserted channel.

Allowed values:
0: Timer0Trgo: Timer 0 TRGO event
1: Timer0Ch3: Timer 0 channel 3 event
2: Timer1Trgo: Timer 1 TRGO event
3: Timer1Ch0: Timer 1 channel 0 event
4: Timer2Ch2: Timer 2 channel 3 event
5: Timer14Trgo: Timer 14 TRGO event
6: Exti15: EXTI line 15
7: Swicst: SWICST

ETEIC

Bit 15: External trigger enable for inserted channel.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

ETSRC

Bits 17-19: External trigger select for regular channel.

Allowed values:
0: Timer0Ch0: Timer 0 channel 0 event
1: Timer0Ch1: Timer 0 channel 1 event
2: Timer0Ch2: Timer 0 channel 2 event
3: Timer1Ch1: Timer 1 channel 1 event
4: Timer2Trgo: Timer 2 TRGO event
5: Timer14Ch0: Timer 14 channel 0 event
6: Exti11: EXTI line 11
7: Swrcst: SWRCST

ETERC

Bit 20: External trigger enable for regular channel.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

SWICST

Bit 21: Start on inserted channel.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of inserted channels

SWRCST

Bit 22: Start on regular channel.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of regular channels

TSVREN

Bit 23: Channel 16 and 17 enable of ADC0.

Allowed values:
0: Disabled: Channel 16 and 17 disabled
1: Enabled: Channel 16 and 17 enabled

SAMPT0

Sample time register 0

Offset: 0xC, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT17
rw 		SPT16
rw 		SPT15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT15
rw 		SPT14
rw 		SPT13
rw 		SPT12
rw 		SPT11
rw 		SPT10
rw
Toggle Fields.

SPT10

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT11

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT12

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT13

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT14

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT15

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT16

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT17

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SAMPT1

Sample time register 1

Offset: 0x10, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT9
rw 		SPT8
rw 		SPT7
rw 		SPT6
rw 		SPT5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT5
rw 		SPT4
rw 		SPT3
rw 		SPT2
rw 		SPT1
rw 		SPT0
rw
Toggle Fields.

SPT0

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT1

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT2

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT3

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT4

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT5

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT6

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT7

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT8

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT9

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

IOFF0

Inserted channel data offset register 0

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 0.

Allowed values: 0-4095

IOFF1

Inserted channel data offset register 1

Offset: 0x18, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 1.

Allowed values: 0-4095

IOFF2

Inserted channel data offset register 2

Offset: 0x1C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 2.

Allowed values: 0-4095

IOFF3

Inserted channel data offset register 3

Offset: 0x20, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 3.

Allowed values: 0-4095

WDHT

watchdog higher threshold register

Offset: 0x24, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDHT
rw
Toggle Fields.

WDHT

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0-4095

WDLT

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDLT
rw
Toggle Fields.

WDLT

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0-4095

RSQ0

regular sequence register 0

Offset: 0x2C, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RL
rw 		RSQ15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ15
rw 		RSQ14
rw 		RSQ13
rw 		RSQ12
rw
Toggle Fields.

RSQ12

Bits 0-4: 13th conversion in regular sequence.

Allowed values: 0-18

RSQ13

Bits 5-9: 14th conversion in regular sequence.

Allowed values: 0-18

RSQ14

Bits 10-14: 15th conversion in regular sequence.

Allowed values: 0-18

RSQ15

Bits 15-19: 16th conversion in regular sequence.

Allowed values: 0-18

RL

Bits 20-23: Regular channel group length.

Allowed values: 0-15

RSQ1

regular sequence register 1

Offset: 0x30, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ11
rw 		RSQ10
rw 		RSQ9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ9
rw 		RSQ8
rw 		RSQ7
rw 		RSQ6
rw
Toggle Fields.

RSQ6

Bits 0-4: 7th conversion in regular sequence.

Allowed values: 0-18

RSQ7

Bits 5-9: 8th conversion in regular sequence.

Allowed values: 0-18

RSQ8

Bits 10-14: 9th conversion in regular sequence.

Allowed values: 0-18

RSQ9

Bits 15-19: 10th conversion in regular sequence.

Allowed values: 0-18

RSQ10

Bits 20-24: 11th conversion in regular sequence.

Allowed values: 0-18

RSQ11

Bits 25-29: 12th conversion in regular sequence.

Allowed values: 0-18

RSQ2

regular sequence register 2

Offset: 0x34, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ5
rw 		RSQ4
rw 		RSQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ3
rw 		RSQ2
rw 		RSQ1
rw 		RSQ0
rw
Toggle Fields.

RSQ0

Bits 0-4: 1st conversion in regular sequence.

Allowed values: 0-18

RSQ1

Bits 5-9: 2nd conversion in regular sequence.

Allowed values: 0-18

RSQ2

Bits 10-14: 3rd conversion in regular sequence.

Allowed values: 0-18

RSQ3

Bits 15-19: 4th conversion in regular sequence.

Allowed values: 0-18

RSQ4

Bits 20-24: 5th conversion in regular sequence.

Allowed values: 0-18

RSQ5

Bits 25-29: 6th conversion in regular sequence.

Allowed values: 0-18

ISQ

Inserted sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IL
rw 		ISQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISQ3
rw 		ISQ2
rw 		ISQ1
rw 		ISQ0
rw
Toggle Fields.

ISQ0

Bits 0-4: 1st conversion in inserted sequence.

Allowed values: 0-18

ISQ1

Bits 5-9: 2nd conversion in inserted sequence.

Allowed values: 0-18

ISQ2

Bits 10-14: 3rd conversion in inserted sequence.

Allowed values: 0-18

ISQ3

Bits 15-19: 4th conversion in inserted sequence.

Allowed values: 0-18

IL

Bits 20-21: Inserted channel group length.

Allowed values: 0-3

IDATA0

Inserted data register 0

Offset: 0x3C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

IDATA1

Inserted data register 1

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

IDATA2

Inserted data register 2

Offset: 0x44, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

IDATA3

Inserted data register 3

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

RDATA

regular data register

Offset: 0x4C, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADC1RDTR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle Fields.

RDATA

Bits 0-15: Regular channel data.

Allowed values: 0-65535

ADC1RDTR

Bits 16-31: ADC regular channel data.

OVSAMPCTL

Oversample control register

Offset: 0x80, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRES
rw 		TOVS
rw 		OVSS
rw 		OVSR
rw 		OVSEN
rw
Toggle Fields.

OVSEN

Bit 0: Oversampling Enable.

Allowed values:
0: Disabled: Oversampling disabled
1: Enabled: Oversampling enabled

OVSR

Bits 2-4: Oversampling ratio.

Allowed values:
0: Times2: 2x
1: Times4: 4x
2: Times8: 8x
3: Times16: 16x
4: Times32: 32x
5: Times64: 64x
6: Times128: 128x
7: Times256: 256x

OVSS

Bits 5-8: Oversampling shift.

Allowed values: 0-8

TOVS

Bit 9: Triggered Oversampling.

Allowed values:
0: Consecutive: All oversampled conversions are done consecutively
1: Individual: Each oversampled conversion needs a trigger

DRES

Bits 12-13: ADC resolution.

Allowed values:
0: Bits12: 12 bit resolution
1: Bits10: 10 bit resolution
2: Bits8: 8 bit resolution
3: Bits6: 6 bit resolution

ADC1

0x40012800: Analog to digital converter

87/88 fields covered. Toggle Registers.

STAT

status register

Offset: 0x0, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRC
rw 		STIC
rw 		EOIC
rw 		EOC
rw 		WDE
rw
Toggle Fields.

WDE

Bit 0: Analog watchdog event flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC

Bit 1: End of group conversion flag.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

EOIC

Bit 2: End of inserted group conversion flag.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

STIC

Bit 3: Start flag of inserted channel group.

Allowed values:
0: NotStarted: No inserted channel group conversion started
1: Started: Inserted channel group conversion has started

STRC

Bit 4: Start flag of regular channel group.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

CTL0

control register 0

Offset: 0x4, reset: 0x00000000, access: read-write

12/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RWDEN
rw 		IWDEN
rw 		SYNCM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISNUM
rw 		DISIC
rw 		DISRC
rw 		ICA
rw 		WDSC
rw 		SM
rw 		EOICIE
rw 		WDEIE
rw 		EOCIE
rw 		WDCHSEL
rw
Toggle Fields.

WDCHSEL

Bits 0-4: Analog watchdog channel select.

Allowed values: 0-18

EOCIE

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set

WDEIE

Bit 6: Interrupt enable for WDE.

Allowed values:
0: Disabled: WDE interrupt disabled
1: Enabled: WDE interrupt enabled. An interrupt is generated when the WDE bit is set

EOICIE

Bit 7: Interrupt enable for EOIC.

Allowed values:
0: Disabled: EOIC interrupt disabled
1: Enabled: EOIC interrupt enabled. An interrupt is generated when the EOIC bit is set

SM

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

WDSC

Bit 9: When in scan mode, analog watchdog is effective on a single channel.

Allowed values:
0: All: Analog watchdog enabled on all channels
1: Single: Analog watchdog enabled on a single channel

ICA

Bit 10: Inserted channel group convert automatically.

Allowed values:
0: Disabled: Automatic inserted group conversion disabled
1: Enabled: Automatic inserted group conversion enabled

DISRC

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

DISIC

Bit 12: Discontinuous mode on inserted channels.

Allowed values:
0: Disabled: Discontinuous mode on inserted channels disabled
1: Enabled: Discontinuous mode on inserted channels enabled

DISNUM

Bits 13-15: Number of conversions in discontinuous mode.

Allowed values: 0-7

SYNCM

Bits 16-19: sync mode selection.

IWDEN

Bit 22: Inserted channel analog watchdog enable.

Allowed values:
0: Disabled: Analog watchdog disabled on inserted channels
1: Enabled: Analog watchdog enabled on inserted channels

RWDEN

Bit 23: Regular channel analog watchdog enable.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

CTL1

control register 1

Offset: 0x8, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSVREN
rw 		SWRCST
rw 		SWICST
rw 		ETERC
rw 		ETSRC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETEIC
rw 		ETSIC
rw 		DAL
rw 		DMA
rw 		RSTCLB
rw 		CLB
rw 		CTN
rw 		ADCON
rw
Toggle Fields.

ADCON

Bit 0: ADC on.

Allowed values:
0: Disabled: Disable ADC conversion/calibration and go to power down mode
1: Enabled: Enable ADC and to start conversion

CTN

Bit 1: Continuous mode.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

CLB

Bit 2: ADC calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

RSTCLB

Bit 3: Reset calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

DMA

Bit 8: DMA request enable.

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

DAL

Bit 11: Data alignment.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

ETSIC

Bits 12-14: External trigger select for inserted channel.

Allowed values:
0: Timer0Trgo: Timer 0 TRGO event
1: Timer0Ch3: Timer 0 channel 3 event
2: Timer1Trgo: Timer 1 TRGO event
3: Timer1Ch0: Timer 1 channel 0 event
4: Timer2Ch2: Timer 2 channel 3 event
5: Timer14Trgo: Timer 14 TRGO event
6: Exti15: EXTI line 15
7: Swicst: SWICST

ETEIC

Bit 15: External trigger enable for inserted channel.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

ETSRC

Bits 17-19: External trigger select for regular channel.

Allowed values:
0: Timer0Ch0: Timer 0 channel 0 event
1: Timer0Ch1: Timer 0 channel 1 event
2: Timer0Ch2: Timer 0 channel 2 event
3: Timer1Ch1: Timer 1 channel 1 event
4: Timer2Trgo: Timer 2 TRGO event
5: Timer14Ch0: Timer 14 channel 0 event
6: Exti11: EXTI line 11
7: Swrcst: SWRCST

ETERC

Bit 20: External trigger enable for regular channel.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

SWICST

Bit 21: Start on inserted channel.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of inserted channels

SWRCST

Bit 22: Start on regular channel.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of regular channels

TSVREN

Bit 23: Channel 16 and 17 enable of ADC0.

Allowed values:
0: Disabled: Channel 16 and 17 disabled
1: Enabled: Channel 16 and 17 enabled

SAMPT0

Sample time register 0

Offset: 0xC, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT17
rw 		SPT16
rw 		SPT15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT15
rw 		SPT14
rw 		SPT13
rw 		SPT12
rw 		SPT11
rw 		SPT10
rw
Toggle Fields.

SPT10

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT11

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT12

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT13

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT14

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT15

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT16

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT17

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SAMPT1

Sample time register 1

Offset: 0x10, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT9
rw 		SPT8
rw 		SPT7
rw 		SPT6
rw 		SPT5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT5
rw 		SPT4
rw 		SPT3
rw 		SPT2
rw 		SPT1
rw 		SPT0
rw
Toggle Fields.

SPT0

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT1

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT2

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT3

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT4

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT5

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT6

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT7

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT8

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT9

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

IOFF0

Inserted channel data offset register 0

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 0.

Allowed values: 0-4095

IOFF1

Inserted channel data offset register 1

Offset: 0x18, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 1.

Allowed values: 0-4095

IOFF2

Inserted channel data offset register 2

Offset: 0x1C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 2.

Allowed values: 0-4095

IOFF3

Inserted channel data offset register 3

Offset: 0x20, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 3.

Allowed values: 0-4095

WDHT

watchdog higher threshold register

Offset: 0x24, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDHT
rw
Toggle Fields.

WDHT

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0-4095

WDLT

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDLT
rw
Toggle Fields.

WDLT

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0-4095

RSQ0

regular sequence register 0

Offset: 0x2C, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RL
rw 		RSQ15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ15
rw 		RSQ14
rw 		RSQ13
rw 		RSQ12
rw
Toggle Fields.

RSQ12

Bits 0-4: 13th conversion in regular sequence.

Allowed values: 0-18

RSQ13

Bits 5-9: 14th conversion in regular sequence.

Allowed values: 0-18

RSQ14

Bits 10-14: 15th conversion in regular sequence.

Allowed values: 0-18

RSQ15

Bits 15-19: 16th conversion in regular sequence.

Allowed values: 0-18

RL

Bits 20-23: Regular channel group length.

Allowed values: 0-15

RSQ1

regular sequence register 1

Offset: 0x30, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ11
rw 		RSQ10
rw 		RSQ9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ9
rw 		RSQ8
rw 		RSQ7
rw 		RSQ6
rw
Toggle Fields.

RSQ6

Bits 0-4: 7th conversion in regular sequence.

Allowed values: 0-18

RSQ7

Bits 5-9: 8th conversion in regular sequence.

Allowed values: 0-18

RSQ8

Bits 10-14: 9th conversion in regular sequence.

Allowed values: 0-18

RSQ9

Bits 15-19: 10th conversion in regular sequence.

Allowed values: 0-18

RSQ10

Bits 20-24: 11th conversion in regular sequence.

Allowed values: 0-18

RSQ11

Bits 25-29: 12th conversion in regular sequence.

Allowed values: 0-18

RSQ2

regular sequence register 2

Offset: 0x34, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ5
rw 		RSQ4
rw 		RSQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ3
rw 		RSQ2
rw 		RSQ1
rw 		RSQ0
rw
Toggle Fields.

RSQ0

Bits 0-4: 1st conversion in regular sequence.

Allowed values: 0-18

RSQ1

Bits 5-9: 2nd conversion in regular sequence.

Allowed values: 0-18

RSQ2

Bits 10-14: 3rd conversion in regular sequence.

Allowed values: 0-18

RSQ3

Bits 15-19: 4th conversion in regular sequence.

Allowed values: 0-18

RSQ4

Bits 20-24: 5th conversion in regular sequence.

Allowed values: 0-18

RSQ5

Bits 25-29: 6th conversion in regular sequence.

Allowed values: 0-18

ISQ

Inserted sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IL
rw 		ISQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISQ3
rw 		ISQ2
rw 		ISQ1
rw 		ISQ0
rw
Toggle Fields.

ISQ0

Bits 0-4: 1st conversion in inserted sequence.

Allowed values: 0-18

ISQ1

Bits 5-9: 2nd conversion in inserted sequence.

Allowed values: 0-18

ISQ2

Bits 10-14: 3rd conversion in inserted sequence.

Allowed values: 0-18

ISQ3

Bits 15-19: 4th conversion in inserted sequence.

Allowed values: 0-18

IL

Bits 20-21: Inserted channel group length.

Allowed values: 0-3

IDATA0

Inserted data register 0

Offset: 0x3C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

IDATA1

Inserted data register 1

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

IDATA2

Inserted data register 2

Offset: 0x44, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

IDATA3

Inserted data register 3

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

RDATA

regular data register

Offset: 0x4C, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADC1RDTR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle Fields.

RDATA

Bits 0-15: Regular channel data.

Allowed values: 0-65535

ADC1RDTR

Bits 16-31: ADC regular channel data.

OVSAMPCTL

Oversample control register

Offset: 0x80, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRES
rw 		TOVS
rw 		OVSS
rw 		OVSR
rw 		OVSEN
rw
Toggle Fields.

OVSEN

Bit 0: Oversampling Enable.

Allowed values:
0: Disabled: Oversampling disabled
1: Enabled: Oversampling enabled

OVSR

Bits 2-4: Oversampling ratio.

Allowed values:
0: Times2: 2x
1: Times4: 4x
2: Times8: 8x
3: Times16: 16x
4: Times32: 32x
5: Times64: 64x
6: Times128: 128x
7: Times256: 256x

OVSS

Bits 5-8: Oversampling shift.

Allowed values: 0-8

TOVS

Bit 9: Triggered Oversampling.

Allowed values:
0: Consecutive: All oversampled conversions are done consecutively
1: Individual: Each oversampled conversion needs a trigger

DRES

Bits 12-13: ADC resolution.

Allowed values:
0: Bits12: 12 bit resolution
1: Bits10: 10 bit resolution
2: Bits8: 8 bit resolution
3: Bits6: 6 bit resolution

ADC2

0x40013C00: Analog to digital converter

87/88 fields covered. Toggle Registers.

STAT

status register

Offset: 0x0, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRC
rw 		STIC
rw 		EOIC
rw 		EOC
rw 		WDE
rw
Toggle Fields.

WDE

Bit 0: Analog watchdog event flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC

Bit 1: End of group conversion flag.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

EOIC

Bit 2: End of inserted group conversion flag.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

STIC

Bit 3: Start flag of inserted channel group.

Allowed values:
0: NotStarted: No inserted channel group conversion started
1: Started: Inserted channel group conversion has started

STRC

Bit 4: Start flag of regular channel group.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

CTL0

control register 0

Offset: 0x4, reset: 0x00000000, access: read-write

12/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RWDEN
rw 		IWDEN
rw 		SYNCM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISNUM
rw 		DISIC
rw 		DISRC
rw 		ICA
rw 		WDSC
rw 		SM
rw 		EOICIE
rw 		WDEIE
rw 		EOCIE
rw 		WDCHSEL
rw
Toggle Fields.

WDCHSEL

Bits 0-4: Analog watchdog channel select.

Allowed values: 0-18

EOCIE

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set

WDEIE

Bit 6: Interrupt enable for WDE.

Allowed values:
0: Disabled: WDE interrupt disabled
1: Enabled: WDE interrupt enabled. An interrupt is generated when the WDE bit is set

EOICIE

Bit 7: Interrupt enable for EOIC.

Allowed values:
0: Disabled: EOIC interrupt disabled
1: Enabled: EOIC interrupt enabled. An interrupt is generated when the EOIC bit is set

SM

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

WDSC

Bit 9: When in scan mode, analog watchdog is effective on a single channel.

Allowed values:
0: All: Analog watchdog enabled on all channels
1: Single: Analog watchdog enabled on a single channel

ICA

Bit 10: Inserted channel group convert automatically.

Allowed values:
0: Disabled: Automatic inserted group conversion disabled
1: Enabled: Automatic inserted group conversion enabled

DISRC

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

DISIC

Bit 12: Discontinuous mode on inserted channels.

Allowed values:
0: Disabled: Discontinuous mode on inserted channels disabled
1: Enabled: Discontinuous mode on inserted channels enabled

DISNUM

Bits 13-15: Number of conversions in discontinuous mode.

Allowed values: 0-7

SYNCM

Bits 16-19: sync mode selection.

IWDEN

Bit 22: Inserted channel analog watchdog enable.

Allowed values:
0: Disabled: Analog watchdog disabled on inserted channels
1: Enabled: Analog watchdog enabled on inserted channels

RWDEN

Bit 23: Regular channel analog watchdog enable.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

CTL1

control register 1

Offset: 0x8, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSVREN
rw 		SWRCST
rw 		SWICST
rw 		ETERC
rw 		ETSRC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETEIC
rw 		ETSIC
rw 		DAL
rw 		DMA
rw 		RSTCLB
rw 		CLB
rw 		CTN
rw 		ADCON
rw
Toggle Fields.

ADCON

Bit 0: ADC on.

Allowed values:
0: Disabled: Disable ADC conversion/calibration and go to power down mode
1: Enabled: Enable ADC and to start conversion

CTN

Bit 1: Continuous mode.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

CLB

Bit 2: ADC calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

RSTCLB

Bit 3: Reset calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

DMA

Bit 8: DMA request enable.

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

DAL

Bit 11: Data alignment.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

ETSIC

Bits 12-14: External trigger select for inserted channel.

Allowed values:
0: Timer0Trgo: Timer 0 TRGO event
1: Timer0Ch3: Timer 0 channel 3 event
2: Timer1Trgo: Timer 1 TRGO event
3: Timer1Ch0: Timer 1 channel 0 event
4: Timer2Ch2: Timer 2 channel 3 event
5: Timer14Trgo: Timer 14 TRGO event
6: Exti15: EXTI line 15
7: Swicst: SWICST

ETEIC

Bit 15: External trigger enable for inserted channel.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

ETSRC

Bits 17-19: External trigger select for regular channel.

Allowed values:
0: Timer0Ch0: Timer 0 channel 0 event
1: Timer0Ch1: Timer 0 channel 1 event
2: Timer0Ch2: Timer 0 channel 2 event
3: Timer1Ch1: Timer 1 channel 1 event
4: Timer2Trgo: Timer 2 TRGO event
5: Timer14Ch0: Timer 14 channel 0 event
6: Exti11: EXTI line 11
7: Swrcst: SWRCST

ETERC

Bit 20: External trigger enable for regular channel.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

SWICST

Bit 21: Start on inserted channel.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of inserted channels

SWRCST

Bit 22: Start on regular channel.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of regular channels

TSVREN

Bit 23: Channel 16 and 17 enable of ADC0.

Allowed values:
0: Disabled: Channel 16 and 17 disabled
1: Enabled: Channel 16 and 17 enabled

SAMPT0

Sample time register 0

Offset: 0xC, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT17
rw 		SPT16
rw 		SPT15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT15
rw 		SPT14
rw 		SPT13
rw 		SPT12
rw 		SPT11
rw 		SPT10
rw
Toggle Fields.

SPT10

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT11

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT12

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT13

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT14

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT15

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT16

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT17

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SAMPT1

Sample time register 1

Offset: 0x10, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT9
rw 		SPT8
rw 		SPT7
rw 		SPT6
rw 		SPT5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT5
rw 		SPT4
rw 		SPT3
rw 		SPT2
rw 		SPT1
rw 		SPT0
rw
Toggle Fields.

SPT0

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT1

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT2

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT3

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT4

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT5

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT6

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT7

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT8

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT9

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

IOFF0

Inserted channel data offset register 0

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 0.

Allowed values: 0-4095

IOFF1

Inserted channel data offset register 1

Offset: 0x18, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 1.

Allowed values: 0-4095

IOFF2

Inserted channel data offset register 2

Offset: 0x1C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 2.

Allowed values: 0-4095

IOFF3

Inserted channel data offset register 3

Offset: 0x20, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 3.

Allowed values: 0-4095

WDHT

watchdog higher threshold register

Offset: 0x24, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDHT
rw
Toggle Fields.

WDHT

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0-4095

WDLT

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDLT
rw
Toggle Fields.

WDLT

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0-4095

RSQ0

regular sequence register 0

Offset: 0x2C, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RL
rw 		RSQ15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ15
rw 		RSQ14
rw 		RSQ13
rw 		RSQ12
rw
Toggle Fields.

RSQ12

Bits 0-4: 13th conversion in regular sequence.

Allowed values: 0-18

RSQ13

Bits 5-9: 14th conversion in regular sequence.

Allowed values: 0-18

RSQ14

Bits 10-14: 15th conversion in regular sequence.

Allowed values: 0-18

RSQ15

Bits 15-19: 16th conversion in regular sequence.

Allowed values: 0-18

RL

Bits 20-23: Regular channel group length.

Allowed values: 0-15

RSQ1

regular sequence register 1

Offset: 0x30, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ11
rw 		RSQ10
rw 		RSQ9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ9
rw 		RSQ8
rw 		RSQ7
rw 		RSQ6
rw
Toggle Fields.

RSQ6

Bits 0-4: 7th conversion in regular sequence.

Allowed values: 0-18

RSQ7

Bits 5-9: 8th conversion in regular sequence.

Allowed values: 0-18

RSQ8

Bits 10-14: 9th conversion in regular sequence.

Allowed values: 0-18

RSQ9

Bits 15-19: 10th conversion in regular sequence.

Allowed values: 0-18

RSQ10

Bits 20-24: 11th conversion in regular sequence.

Allowed values: 0-18

RSQ11

Bits 25-29: 12th conversion in regular sequence.

Allowed values: 0-18

RSQ2

regular sequence register 2

Offset: 0x34, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ5
rw 		RSQ4
rw 		RSQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ3
rw 		RSQ2
rw 		RSQ1
rw 		RSQ0
rw
Toggle Fields.

RSQ0

Bits 0-4: 1st conversion in regular sequence.

Allowed values: 0-18

RSQ1

Bits 5-9: 2nd conversion in regular sequence.

Allowed values: 0-18

RSQ2

Bits 10-14: 3rd conversion in regular sequence.

Allowed values: 0-18

RSQ3

Bits 15-19: 4th conversion in regular sequence.

Allowed values: 0-18

RSQ4

Bits 20-24: 5th conversion in regular sequence.

Allowed values: 0-18

RSQ5

Bits 25-29: 6th conversion in regular sequence.

Allowed values: 0-18

ISQ

Inserted sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IL
rw 		ISQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISQ3
rw 		ISQ2
rw 		ISQ1
rw 		ISQ0
rw
Toggle Fields.

ISQ0

Bits 0-4: 1st conversion in inserted sequence.

Allowed values: 0-18

ISQ1

Bits 5-9: 2nd conversion in inserted sequence.

Allowed values: 0-18

ISQ2

Bits 10-14: 3rd conversion in inserted sequence.

Allowed values: 0-18

ISQ3

Bits 15-19: 4th conversion in inserted sequence.

Allowed values: 0-18

IL

Bits 20-21: Inserted channel group length.

Allowed values: 0-3

IDATA0

Inserted data register 0

Offset: 0x3C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

IDATA1

Inserted data register 1

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

IDATA2

Inserted data register 2

Offset: 0x44, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

IDATA3

Inserted data register 3

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

RDATA

regular data register

Offset: 0x4C, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADC1RDTR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle Fields.

RDATA

Bits 0-15: Regular channel data.

Allowed values: 0-65535

ADC1RDTR

Bits 16-31: ADC regular channel data.

OVSAMPCTL

Oversample control register

Offset: 0x80, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRES
rw 		TOVS
rw 		OVSS
rw 		OVSR
rw 		OVSEN
rw
Toggle Fields.

OVSEN

Bit 0: Oversampling Enable.

Allowed values:
0: Disabled: Oversampling disabled
1: Enabled: Oversampling enabled

OVSR

Bits 2-4: Oversampling ratio.

Allowed values:
0: Times2: 2x
1: Times4: 4x
2: Times8: 8x
3: Times16: 16x
4: Times32: 32x
5: Times64: 64x
6: Times128: 128x
7: Times256: 256x

OVSS

Bits 5-8: Oversampling shift.

Allowed values: 0-8

TOVS

Bit 9: Triggered Oversampling.

Allowed values:
0: Consecutive: All oversampled conversions are done consecutively
1: Individual: Each oversampled conversion needs a trigger

DRES

Bits 12-13: ADC resolution.

Allowed values:
0: Bits12: 12 bit resolution
1: Bits10: 10 bit resolution
2: Bits8: 8 bit resolution
3: Bits6: 6 bit resolution

AFIO

0x40010000: Alternate-function I/Os

0/150 fields covered. Toggle Registers.

EC

Event control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOE
rw 		PORT
rw 		PIN
rw
Toggle Fields.

PIN

Bits 0-3: Event output pin selection.

PORT

Bits 4-6: Event output port selection.

EOE

Bit 7: Event output enable.

PCF0

AFIO port configuration register 0

Offset: 0x4, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTP_PPS_REMAP
rw 		TIMER1ITR0_REMAP
rw 		SPI2_REMAP
rw 		SWJ_CFG
rw 		ENET_PHY_SEL
rw 		CAN1_REMAP
rw 		ENET_REMAP
rw 		ADC1_ETRGREG_REMAP
rw 		ADC1_ETRGINS_REMAP
rw 		ADC0_ETRGREG_REMAP
rw 		ADC0_ETRGINS_REMAP
rw 		TIMER4CH3_IREMAP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD01_REMAP
rw 		CAN0_REMAP
rw 		TIMER3_REMAP
rw 		TIMER2_REMAP
rw 		TIMER1_REMAP
rw 		TIMER0_REMAP
rw 		USART2_REMAP
rw 		USART1_REMAP
rw 		USART0_REMAP
rw 		I2C0_REMAP
rw 		SPI0_REMAP
rw
Toggle Fields.

SPI0_REMAP

Bit 0: SPI0 remapping.

I2C0_REMAP

Bit 1: I2C0 remapping.

USART0_REMAP

Bit 2: USART0 remapping.

USART1_REMAP

Bit 3: USART1 remapping.

USART2_REMAP

Bits 4-5: USART2 remapping.

TIMER0_REMAP

Bits 6-7: TIMER0 remapping.

TIMER1_REMAP

Bits 8-9: TIMER1 remapping.

TIMER2_REMAP

Bits 10-11: TIMER2 remapping.

TIMER3_REMAP

Bit 12: TIMER3 remapping.

CAN0_REMAP

Bits 13-14: CAN0 alternate interface remapping.

PD01_REMAP

Bit 15: Port D0/Port D1 mapping on OSC_IN/OSC_OUT.

TIMER4CH3_IREMAP

Bit 16: TIMER4 channel3 internal remapping.

ADC0_ETRGINS_REMAP

Bit 17: ADC 0 external trigger inserted conversion remapping.

ADC0_ETRGREG_REMAP

Bit 18: ADC 0 external trigger regular conversion remapping.

ADC1_ETRGINS_REMAP

Bit 19: ADC 1 external trigger inserted conversion remapping.

ADC1_ETRGREG_REMAP

Bit 20: ADC 1 external trigger regular conversion remapping.

ENET_REMAP

Bit 21: Ethernet MAC I/O remapping.

CAN1_REMAP

Bit 22: CAN1 I/O remapping.

ENET_PHY_SEL

Bit 23: Ethernet MII or RMII PHY selection.

SWJ_CFG

Bits 24-26: Serial wire JTAG configuration.

SPI2_REMAP

Bit 28: SPI2/I2S2 remapping.

TIMER1ITR0_REMAP

Bit 29: TIMER1 internal trigger 0 remapping.

PTP_PPS_REMAP

Bit 30: Ethernet PTP PPS remapping.

EXTISS0

EXTI sources selection register 0

Offset: 0x8, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3_SS
rw 		EXTI2_SS
rw 		EXTI1_SS
rw 		EXTI0_SS
rw
Toggle Fields.

EXTI0_SS

Bits 0-3: EXTI 0 sources selection.

EXTI1_SS

Bits 4-7: EXTI 1 sources selection.

EXTI2_SS

Bits 8-11: EXTI 2 sources selection.

EXTI3_SS

Bits 12-15: EXTI 3 sources selection.

EXTISS1

EXTI sources selection register 1

Offset: 0xC, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7_SS
rw 		EXTI6_SS
rw 		EXTI5_SS
rw 		EXTI4_SS
rw
Toggle Fields.

EXTI4_SS

Bits 0-3: EXTI 4 sources selection.

EXTI5_SS

Bits 4-7: EXTI 5 sources selection.

EXTI6_SS

Bits 8-11: EXTI 6 sources selection.

EXTI7_SS

Bits 12-15: EXTI 7 sources selection.

EXTISS2

EXTI sources selection register 2

Offset: 0x10, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11_SS
rw 		EXTI10_SS
rw 		EXTI9_SS
rw 		EXTI8_SS
rw
Toggle Fields.

EXTI8_SS

Bits 0-3: EXTI 8 sources selection.

EXTI9_SS

Bits 4-7: EXTI 9 sources selection.

EXTI10_SS

Bits 8-11: EXTI 10 sources selection.

EXTI11_SS

Bits 12-15: EXTI 11 sources selection.

EXTISS3

EXTI sources selection register 3

Offset: 0x14, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15_SS
rw 		EXTI14_SS
rw 		EXTI13_SS
rw 		EXTI12_SS
rw
Toggle Fields.

EXTI12_SS

Bits 0-3: EXTI 12 sources selection.

EXTI13_SS

Bits 4-7: EXTI 13 sources selection.

EXTI14_SS

Bits 8-11: EXTI 14 sources selection.

EXTI15_SS

Bits 12-15: EXTI 15 sources selection.

PCF1

AFIO port configuration register 1

Offset: 0x1C, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMC_NADV
rw 		TIMER13_REMAP
rw 		TIMER12_REMAP
rw 		TIMER10_REMAP
rw 		TIMER9_REMAP
rw 		TIMER8_REMAP
rw
Toggle Fields.

TIMER8_REMAP

Bit 5: TIMER8 remapping.

TIMER9_REMAP

Bit 6: TIMER9 remapping.

TIMER10_REMAP

Bit 7: TIMER10 remapping.

TIMER12_REMAP

Bit 8: TIMER12 remapping.

TIMER13_REMAP

Bit 9: TIMER13 remapping.

EXMC_NADV

Bit 10: EXMC_NADV connect/disconnect.

PCF2

AFIO port configuration register 2

Offset: 0x3C, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PH01_REMAP
rw 		DCI_HSYNC_REMAP
rw 		DCI_D13_REMAP
rw 		DCI_D12_REMAP
rw 		DCI_D11_REMAP
rw 		DCI_D10_REMAP
rw 		DCI_D9_REMAP
rw 		DCI_D8_REMAP
rw 		DCI_D7_REMAP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCI_D6_REMAP
rw 		DCI_D5_REMAP
rw 		DCI_D4_REMAP
rw 		DCI_D3_REMAP
rw 		DCI_D2_REMAP
rw 		DCI_D1_REMAP
rw 		DCI_D0_REMAP
rw 		DCI_VSYNC_REMAP
rw
Toggle Fields.

DCI_VSYNC_REMAP

Bits 0-1: DCI_VSYNC remapping.

DCI_D0_REMAP

Bits 2-3: DCI_D0 remapping.

DCI_D1_REMAP

Bits 4-5: DCI_D1 remapping.

DCI_D2_REMAP

Bits 6-7: DCI_D2 remapping.

DCI_D3_REMAP

Bits 8-9: DCI_D3 remapping.

DCI_D4_REMAP

Bits 10-11: DCI_D4 remapping.

DCI_D5_REMAP

Bits 12-13: DCI_D5 remapping.

DCI_D6_REMAP

Bits 14-15: DCI_D6 remapping.

DCI_D7_REMAP

Bits 16-17: DCI_D7 remapping.

DCI_D8_REMAP

Bits 18-19: DCI_D8 remapping.

DCI_D9_REMAP

Bits 20-21: DCI_D9 remapping.

DCI_D10_REMAP

Bits 22-23: DCI_D10 remapping.

DCI_D11_REMAP

Bits 24-25: DCI_D11 remapping.

DCI_D12_REMAP

Bit 26: DCI_D12 remapping.

DCI_D13_REMAP

Bits 27-28: DCI_D13 remapping.

DCI_HSYNC_REMAP

Bit 29: DCI_HSYNC remapping.

PH01_REMAP

Bit 31: PH0/PH1 remapping.

PCF3

AFIO port configuration register 3

Offset: 0x40, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TLI_B3_PG11_REMAP
rw 		TLI_B2_PG10_REMAP
rw 		TLI_G3_PG10_REMAP
rw 		TLI_CLK_PG7_REMAP
rw 		TLI_R7_PG6_REMAP
rw 		TLI_DE_PF10_REMAP
rw 		TLI_R7_PE15_REMAP
rw 		TLI_CLK_PE14_REMAP
rw 		TLI_DE_PE13_REMAP
rw 		TLI_B4_PE12_REMAP
rw 		TLI_G3_PE11_REMAP
rw 		TLI_G1_PE6_REMAP
rw 		TLI_G0_PE5_REMAP
rw 		TLI_B0_PE4_REMAP
rw 		TLI_B3_PD10_REMAP
rw 		TLI_B2_PD6_REMAP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLI_G7_PD3_REMAP
rw 		TLI_R2_PC10_REMAP
rw 		TLI_G6_PC7_REMAP
rw 		TLI_HSYNC_PC6_REMAP
rw 		TLI_G5_PB11_REMAP
rw 		TLI_G4_PB10_REMAP
rw 		TLI_B7_PB9_REMAP
rw 		TLI_B6_PB8_REMAP
rw 		TLI_R6_PB1_REMAP
rw 		TLI_R3_PB0_REMAP
rw 		TLI_R5_PA12_REMAP
rw 		TLI_R4_PA11_REMAP
rw 		TLI_R6_PA8_REMAP
rw 		TLI_G2_PA6_REMAP
rw 		TLI_VSYNC_PA4_REMAP
rw 		TLI_B5_PA3_REMAP
rw
Toggle Fields.

TLI_B5_PA3_REMAP

Bit 0: TLI_B5_PA3 remapping.

TLI_VSYNC_PA4_REMAP

Bit 1: TLI_VSYNC_PA4 remapping.

TLI_G2_PA6_REMAP

Bit 2: TLI_G2_PA6 remapping.

TLI_R6_PA8_REMAP

Bit 3: TLI_R6_PA8 remapping.

TLI_R4_PA11_REMAP

Bit 4: TLI_R4_PA11 remapping.

TLI_R5_PA12_REMAP

Bit 5: TLI_R5_PA12 remapping.

TLI_R3_PB0_REMAP

Bit 6: TLI_R3_PB0 remapping.

TLI_R6_PB1_REMAP

Bit 7: TLI_R6_PB1 remapping.

TLI_B6_PB8_REMAP

Bit 8: TLI_B6_PB8 remapping.

TLI_B7_PB9_REMAP

Bit 9: TLI_B7_PB9 remapping.

TLI_G4_PB10_REMAP

Bit 10: TLI_G4_PB10 remapping.

TLI_G5_PB11_REMAP

Bit 11: TLI_G5_PB11 remapping.

TLI_HSYNC_PC6_REMAP

Bit 12: TLI_HSYNC_PC6 remapping.

TLI_G6_PC7_REMAP

Bit 13: TLI_G6_PC7 remapping.

TLI_R2_PC10_REMAP

Bit 14: TLI_R2_PC10 remapping.

TLI_G7_PD3_REMAP

Bit 15: TLI_G7_PD3 remapping.

TLI_B2_PD6_REMAP

Bit 16: TLI_B2_PD6 remapping.

TLI_B3_PD10_REMAP

Bit 17: TLI_B3_PD10 remapping.

TLI_B0_PE4_REMAP

Bit 18: TLI_B0_PE4 remapping.

TLI_G0_PE5_REMAP

Bit 19: TLI_G0_PE5 remapping.

TLI_G1_PE6_REMAP

Bit 20: TLI_G1_PE6 remapping.

TLI_G3_PE11_REMAP

Bit 21: TLI_G3_PE11 remapping.

TLI_B4_PE12_REMAP

Bit 22: TLI_B4_PE12 remapping.

TLI_DE_PE13_REMAP

Bit 23: TLI_DE_PE13 remapping.

TLI_CLK_PE14_REMAP

Bit 24: TLI_CLK_PE14 remapping.

TLI_R7_PE15_REMAP

Bit 25: TLI_R7_PE15 remapping.

TLI_DE_PF10_REMAP

Bit 26: TLI_DE_PF10 remapping.

TLI_R7_PG6_REMAP

Bit 27: TLI_R7_PG6 remapping.

TLI_CLK_PG7_REMAP

Bit 28: TLI_CLK_PG7 remapping.

TLI_G3_PG10_REMAP

Bit 29: TLI_G3_PG10 remapping.

TLI_B2_PG10_REMAP

Bit 30: TLI_B2_PG10 remapping.

TLI_B3_PG11_REMAP

Bit 31: TLI_B3_PG11 remapping.

PCF4

AFIO port configuration register 4

Offset: 0x44, reset: 0x00000000, access: read-write

0/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPI2_MOSI_REMAP
rw 		SPI1_SCK_REMAP
rw 		TLI_R1_PI3_REMAP
rw 		TLI_R0_PH4_REMAP
rw 		TLI_HSYNC_PI10_REMAP
rw 		TLI_VSYNC_PI9_REMAP
rw 		TLI_B7_PI7_REMAP
rw 		TLI_B6_PI6_REMAP
rw 		TLI_B5_PI5_REMAP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLI_B4_PI4_REMAP
rw 		TLI_G7_PI2_REMAP
rw 		TLI_G6_PI1_REMAP
rw 		TLI_G5_PI0_REMAP
rw 		TLI_G4_PH15_REMAP
rw 		TLI_G3_PH14_REMAP
rw 		TLI_G2_PH13_REMAP
rw 		TLI_R6_PH12_REMAP
rw 		TLI_R5_PH11_REMAP
rw 		TLI_R4_PH10_REMAP
rw 		TLI_R3_PH9_REMAP
rw 		TLI_R2_PH8_REMAP
rw 		TLI_R1_PH3_REMAP
rw 		TLI_R0_PH2_REMAP
rw 		TLI_B1_PG12_REMAP
rw 		TLI_B4_PG12_REMAP
rw
Toggle Fields.

TLI_B4_PG12_REMAP

Bit 0: TLI_B4_PG12 remapping.

TLI_B1_PG12_REMAP

Bit 1: TLI_B1_PG12 remapping.

TLI_R0_PH2_REMAP

Bit 2: TLI_R0_PH2 remapping.

TLI_R1_PH3_REMAP

Bit 3: TLI_R1_PH3 remapping.

TLI_R2_PH8_REMAP

Bit 4: TLI_R2_PH8 remapping.

TLI_R3_PH9_REMAP

Bit 5: TLI_R3_PH9 remapping.

TLI_R4_PH10_REMAP

Bit 6: TLI_R4_PH10 remapping.

TLI_R5_PH11_REMAP

Bit 7: TLI_R5_PH11 remapping.

TLI_R6_PH12_REMAP

Bit 8: TLI_R6_PH12 remapping.

TLI_G2_PH13_REMAP

Bit 9: TLI_G2_PH13 remapping.

TLI_G3_PH14_REMAP

Bit 10: TLI_G3_PH14 remapping.

TLI_G4_PH15_REMAP

Bit 11: TLI_G4_PH15 remapping.

TLI_G5_PI0_REMAP

Bit 12: TLI_G5_PI0 remapping.

TLI_G6_PI1_REMAP

Bit 13: TLI_G6_PI1 remapping.

TLI_G7_PI2_REMAP

Bit 14: TLI_G7_PI2 remapping.

TLI_B4_PI4_REMAP

Bit 15: TLI_B4_PI4 remapping.

TLI_B5_PI5_REMAP

Bit 16: TLI_B5_PI5 remapping.

TLI_B6_PI6_REMAP

Bit 17: TLI_B6_PI6 remapping.

TLI_B7_PI7_REMAP

Bit 18: TLI_B7_PI7 remapping.

TLI_VSYNC_PI9_REMAP

Bit 19: TLI_VSYNC_PI9 remapping.

TLI_HSYNC_PI10_REMAP

Bit 20: TLI_HSYNC_PI10 remapping.

TLI_R0_PH4_REMAP

Bit 21: TLI_R0_PH4 remapping.

TLI_R1_PI3_REMAP

Bit 22: TLI_R1_PI3 remapping.

SPI1_SCK_REMAP

Bit 23: SPI1_SCK remapping.

SPI2_MOSI_REMAP

Bit 24: SPI2_MOSI remapping.

PCF5

AFIO port configuration register 5

Offset: 0x48, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMC_SDNE1_REMAP
rw 		EXMC_SDNE0_REMAP
rw 		EXMC_SDCKE1_REMAP
rw 		EXMC_SDCKE0_REMAP
rw 		EXMC_SDNWE_REMAP
rw 		USART5_RX_REMAP
rw 		USART5_TX_REMAP
rw 		USART5_CTS_REMAP
rw 		USART5_RTS_REMAP
rw 		USART5_CK_REMAP
rw 		UART6_REMAP
rw 		ENET_RX_HI_REMAP
rw 		ENET_CRSCOL_REMAP
rw 		ENET_TXD01_REMAP
rw 		PPS_HI_REMAP
rw 		ENET_TXD3_REMAP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAN0_ADD_REMAP
rw 		TIMER11_REMAP
rw 		UART3_REMAP
rw 		SPI1_IO_REMAP
rw 		SPI1_NSCK_REMAP
rw 		I2C1_REMAP
rw 		TIMER7_CH_REMAP
rw 		TIMER7_CHON_REMAP
rw 		TIMER4_REMAP
rw 		TIMER1_CH0_REMAP
rw 		I2C2_REMAP1
rw 		I2C2_REMAP0
rw
Toggle Fields.

I2C2_REMAP0

Bit 0: I2C2 remapping 0.

I2C2_REMAP1

Bit 1: I2C2 remapping 1.

TIMER1_CH0_REMAP

Bit 2: TIMER1_CH0 remapping.

TIMER4_REMAP

Bit 3: TIMER4 remapping.

TIMER7_CHON_REMAP

Bits 4-5: TIMER7_CHON remapping.

TIMER7_CH_REMAP

Bit 6: TIMER7_CH remapping.

I2C1_REMAP

Bits 7-8: I2C1 remapping.

SPI1_NSCK_REMAP

Bits 9-10: SPI1_NSCK remapping.

SPI1_IO_REMAP

Bits 11-12: SPI1_IO remapping.

UART3_REMAP

Bit 13: UART3 remapping.

TIMER11_REMAP

Bit 14: TIMER11 remapping.

CAN0_ADD_REMAP

Bit 15: CAN0_ADD remapping.

ENET_TXD3_REMAP

Bit 16: ENET _TXD3 remapping.

PPS_HI_REMAP

Bit 17: PPS_HI remapping.

ENET_TXD01_REMAP

Bit 18: ENET_TXD01 remapping.

ENET_CRSCOL_REMAP

Bit 19: ENET_CRSCOL remapping.

ENET_RX_HI_REMAP

Bit 20: ENET _RX_HI remapping.

UART6_REMAP

Bit 21: UART6 remapping.

USART5_CK_REMAP

Bit 22: USART5_CK remapping.

USART5_RTS_REMAP

Bit 23: USART5_RTS remapping.

USART5_CTS_REMAP

Bit 24: USART5_CTS remapping.

USART5_TX_REMAP

Bit 25: USART5_TX remapping.

USART5_RX_REMAP

Bit 26: USART5_RX remapping.

EXMC_SDNWE_REMAP

Bit 27: EXMC_SDNWE remapping.

EXMC_SDCKE0_REMAP

Bit 28: EXMC_SDCKE0 remapping.

EXMC_SDCKE1_REMAP

Bit 29: EXMC_SDCKE1 remapping.

EXMC_SDNE0_REMAP

Bit 30: EXMC_SDNE0 remapping.

EXMC_SDNE1_REMAP

Bit 31: EXMC_SDNE1 remapping.

BKP

0x40006C00: Backup registers

0/64 fields covered. Toggle Registers.

DATA0

Backup data register 0

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA1

Backup data register 1

Offset: 0x8, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA2

Backup data register 2

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA3

Backup data register 3

Offset: 0x10, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA4

Backup data register 4

Offset: 0x14, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA5

Backup data register 5

Offset: 0x18, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA6

Backup data register 6

Offset: 0x1C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA7

Backup data register 7

Offset: 0x20, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA8

Backup data register 8

Offset: 0x24, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA9

Backup data register 9

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

OCTL

RTC signal output control register

Offset: 0x2C, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALDIR
rw 		CCOSEL
rw 		ROSEL
rw 		ASOEN
rw 		COEN
rw 		RCCV
rw
Toggle Fields.

RCCV

Bits 0-6: RTC clock calibration value.

COEN

Bit 7: RTC clock calibration output enable.

ASOEN

Bit 8: RTC alarm or second signal output enable.

ROSEL

Bit 9: RTC output selection.

CCOSEL

Bit 14: RTC clock output selection.

CALDIR

Bit 15: RTC clock calibration direction.

TPCTL0

Tamper pin control register 0

Offset: 0x30, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPAL0
rw 		TPEN0
rw
Toggle Fields.

TPEN0

Bit 0: TAMPER0 detection enable.

TPAL0

Bit 1: TAMPER0 pin active level.

TPCS

Tamper control and status register

Offset: 0x34, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIF1
rw 		TEF1
rw 		TIF0
rw 		TEF0
rw 		TPIE1
rw 		TIR1
rw 		TER1
rw 		TPIE0
rw 		TIR0
rw 		TER0
rw
Toggle Fields.

TER0

Bit 0: Tamper0 event reset.

TIR0

Bit 1: Tamper0 interrupt reset.

TPIE0

Bit 2: Tamper0 interrupt enable.

TER1

Bit 5: Tamper1 event reset.

TIR1

Bit 6: Tamper1 interrupt reset.

TPIE1

Bit 7: Tamper1interrupt enable.

TEF0

Bit 8: Tamper0 event flag.

TIF0

Bit 9: Tamper0 interrupt flag.

TEF1

Bit 14: Tamper1 event flag.

TIF1

Bit 15: Tamper1 interrupt flag.

TPCTL1

Tamper pin control register 1

Offset: 0x38, reset: 0x0000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPM1
rw 		TPM2
rw 		TPAL1
rw 		TPEN1
rw
Toggle Fields.

TPEN1

Bit 8: TAMPER1 detection enable.

TPAL1

Bit 9: TAMPER1 pin active level.

TPM2

Bit 14: The second waveform detection enable.

TPM1

Bit 15: The first waveform detection enable.

DATA10

Backup data register 10

Offset: 0x40, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA11

Backup data register 11

Offset: 0x44, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA12

Backup data register 12

Offset: 0x48, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA13

Backup data register 13

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA14

Backup data register 14

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA15

Backup data register 15

Offset: 0x54, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA16

Backup data register 16

Offset: 0x58, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA17

Backup data register 17

Offset: 0x5C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA18

Backup data register 18

Offset: 0x60, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA19

Backup data register 19

Offset: 0x64, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA20

Backup data register 20

Offset: 0x68, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA21

Backup data register 21

Offset: 0x6C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA22

Backup data register 22

Offset: 0x70, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA23

Backup data register 23

Offset: 0x74, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA24

Backup data register 24

Offset: 0x78, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA25

Backup data register 25

Offset: 0x7C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA26

Backup data register 26

Offset: 0x80, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA27

Backup data register 27

Offset: 0x84, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA28

Backup data register 28

Offset: 0x88, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA29

Backup data register 29

Offset: 0x8C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA30

Backup data register 30

Offset: 0x90, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA31

Backup data register 31

Offset: 0x94, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA32

Backup data register 32

Offset: 0x98, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA33

Backup data register 33

Offset: 0x9C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA34

Backup data register 34

Offset: 0xA0, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA35

Backup data register 35

Offset: 0xA4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA36

Backup data register 36

Offset: 0xA8, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA37

Backup data register 37

Offset: 0xAC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA38

Backup data register 38

Offset: 0xB0, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA39

Backup data register 39

Offset: 0xB4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA40

Backup data register 40

Offset: 0xB8, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA41

Backup data register 41

Offset: 0xBC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

CAN0

0x40006400: Controller area network

261/2059 fields covered. Toggle Registers.

CTL

Control register

Offset: 0x0, reset: 0x00010002, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
rw 		TTC
rw 		ABOR
rw 		AWU
rw 		ARD
rw 		RFOD
rw 		TFO
rw 		SLPWMOD
rw 		IWMOD
rw
Toggle Fields.

IWMOD

Bit 0: Initial working mode.

Allowed values:
0: Disabled: Disable initial working mode
1: Enabled: Enable initial working mode

SLPWMOD

Bit 1: Sleep working mode.

Allowed values:
0: Active: Disable sleep mode, bus activity detected
1: Sleep: Enable sleep mode

TFO

Bit 2: Transmit FIFO order.

Allowed values:
0: Identifier: Order by identifier of the frame
1: FIFO: First in first out order

RFOD

Bit 3: Receive FIFO overwrite disable.

Allowed values:
0: Overwrite: Overwrite full receive FIFO with incoming frame
1: Discard: Discard incoming frame when receive FIFO is full

ARD

Bit 4: Automatic retransmission disable.

Allowed values:
0: Enabled: Enable automatic retransmission
1: Disabled: Disable automatic retransmission

AWU

Bit 5: Automatic wakeup.

Allowed values:
0: Manual: Sleep state is set by software
1: Automatic: Sleep state is set automatically by hardware

ABOR

Bit 6: Automatic bus-off recovery.

Allowed values:
0: Manual: Bus off state is set by software
1: Automatic: Bus off state is set automatically by hardware

TTC

Bit 7: Time-triggered communication.

Allowed values:
0: Disabled: Disable time-triggered communication
1: Enabled: Enable time-triggered communication

SWRST

Bit 15: Software reset.

Allowed values:
0: NotResetting: Finished resetting
1: Resetting: Reset in progress

DFZ

Bit 16: Debug freeze.

Allowed values:
0: Continue: Continue running CAN during debug
1: Stop: Stop CAN reception and transmission during debug hold

STAT

Status register

Offset: 0x4, reset: 0x00000C02, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXL
r 		LASTRX
r 		RS
r 		TS
r 		SLPIF
rw 		WUIF
rw 		ERRIF
rw 		SLPWS
r 		IWS
r
Toggle Fields.

IWS

Bit 0: Initial working state.

Allowed values:
0: Normal: CAN is not in initial working mode
1: Initial: CAN is in initial working mode

SLPWS

Bit 1: Sleep working state.

Allowed values:
0: Normal: CAN is not in sleep working mode
1: Sleeping: CAN is in sleep working mode

ERRIF

Bit 2: Error interrupt flag.

Allowed values:
0: NoError: There was no error
1: Error: An error was detected

WUIF

Bit 3: Status change interrupt flag of wakeup from sleep working mode.

Allowed values:
0: NoWakeup: No wakeup event
1: Wakeup: Wakeup event

SLPIF

Bit 4: Status change interrupt flag of sleep working mode entering.

Allowed values:
0: Awake: CAN is not entering sleep working mode
1: Sleeping: CAN is entering sleep working mode

TS

Bit 8: Transmitting state.

Allowed values:
0: NotWorking: CAN is not working in transmitting state
1: Working: CAN is working in transmitting state

RS

Bit 9: Receiving state.

Allowed values:
0: NotWorking: CAN is not working in receiving state
1: Working: CAN is working in receiving state

LASTRX

Bit 10: Last sample value of RX pin.

RXL

Bit 11: RX level.

TSTAT

Transmit status register

Offset: 0x8, reset: 0x1C000000, access: Unspecified

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TMLS2
r 		TMLS1
r 		TMLS0
r 		TME2
r 		TME1
r 		TME0
r 		NUM
r 		MST2
rw 		MTE2
rw 		MAL2
rw 		MTFNERR2
rw 		MTF2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MST1
rw 		MTE1
rw 		MAL1
rw 		MTFNERR1
rw 		MTF1
rw 		MST0
rw 		MTE0
rw 		MAL0
rw 		MTFNERR0
rw 		MTF0
rw
Toggle Fields.

MTF0

Bit 0: Mailbox 0 transmit finished.

Allowed values:
0: InProgress: Mailbox transmission still in progress
1: Finished: Mailbox transmission finished

MTFNERR0

Bit 1: Mailbox 0 transmit finished and no error.

Allowed values:
0: FinishedWithError: Mailbox transmission finished with an error
1: FinishedNoError: Mailbox transmission finished with no error

MAL0

Bit 2: Mailbox 0 arbitration lost.

Allowed values:
0: NoArbitrationLost: Arbitration was not lost
1: ArbitrationLost: Arbitration lost

MTE0

Bit 3: Mailbox 0 transmit error.

Allowed values:
0: NoError: There was no error
1: Error: An error was detected

MST0

Bit 7: Mailbox 0 stop transmitting.

Allowed values:
0: NotStop: Mailbox is not stopped, or is empty
1: Stop: Stop mailbox transmitting

MTF1

Bit 8: Mailbox 1 transmit finished.

Allowed values:
0: InProgress: Mailbox transmission still in progress
1: Finished: Mailbox transmission finished

MTFNERR1

Bit 9: Mailbox 1 transmit finished and no error.

Allowed values:
0: FinishedWithError: Mailbox transmission finished with an error
1: FinishedNoError: Mailbox transmission finished with no error

MAL1

Bit 10: Mailbox 1 arbitration lost.

Allowed values:
0: NoArbitrationLost: Arbitration was not lost
1: ArbitrationLost: Arbitration lost

MTE1

Bit 11: Mailbox 1 transmit error.

Allowed values:
0: NoError: There was no error
1: Error: An error was detected

MST1

Bit 15: Mailbox 1 stop transmitting.

Allowed values:
0: NotStop: Mailbox is not stopped, or is empty
1: Stop: Stop mailbox transmitting

MTF2

Bit 16: Mailbox 2 transmit finished.

Allowed values:
0: InProgress: Mailbox transmission still in progress
1: Finished: Mailbox transmission finished

MTFNERR2

Bit 17: Mailbox 2 transmit finished and no error.

Allowed values:
0: FinishedWithError: Mailbox transmission finished with an error
1: FinishedNoError: Mailbox transmission finished with no error

MAL2

Bit 18: Mailbox 2 arbitration lost.

Allowed values:
0: NoArbitrationLost: Arbitration was not lost
1: ArbitrationLost: Arbitration lost

MTE2

Bit 19: Mailbox 2 transmit error.

Allowed values:
0: NoError: There was no error
1: Error: An error was detected

MST2

Bit 23: Mailbox 2 stop transmitting.

Allowed values:
0: NotStop: Mailbox is not stopped, or is empty
1: Stop: Stop mailbox transmitting

NUM

Bits 24-25: number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty.

Allowed values: 0-2

TME0

Bit 26: Transmit mailbox 0 empty.

Allowed values:
0: NotEmpty: Transmit mailbox not empty
1: Empty: Transmit mailbox is empty

TME1

Bit 27: Transmit mailbox 1 empty.

Allowed values:
0: NotEmpty: Transmit mailbox not empty
1: Empty: Transmit mailbox is empty

TME2

Bit 28: Transmit mailbox 2 empty.

Allowed values:
0: NotEmpty: Transmit mailbox not empty
1: Empty: Transmit mailbox is empty

TMLS0

Bit 29: Transmit mailbox 0 last sending in transmit FIFO.

Allowed values:
0: NotLast: The mailbox doesn't have the last sending order
1: Last: The mailbox has the last sending order with at least two frames pending

TMLS1

Bit 30: Transmit mailbox 1 last sending in transmit FIFO.

Allowed values:
0: NotLast: The mailbox doesn't have the last sending order
1: Last: The mailbox has the last sending order with at least two frames pending

TMLS2

Bit 31: Transmit mailbox 2 last sending in transmit FIFO.

Allowed values:
0: NotLast: The mailbox doesn't have the last sending order
1: Last: The mailbox has the last sending order with at least two frames pending

RFIFO0

Receive message FIFO0 register

Offset: 0xC, reset: 0x00000000, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFD0
rw 		RFO0
rw 		RFF0
rw 		RFL0
r
Toggle Fields.

RFL0

Bits 0-1: Receive FIFO0 length.

Allowed values: 0-3

RFF0

Bit 3: Receive FIFO0 full.

Allowed values:
0: NotFull: Receive FIFO is not full
1: Full: Receive FIFO is full

RFO0

Bit 4: Receive FIFO0 overfull.

Allowed values:
0: NotOverfull: Receive FIFO is not overfull
1: Overfull: Receive FIFO is overfull

RFD0

Bit 5: Receive FIFO0 dequeue.

Allowed values:
0: Finished: Dequeuing done
1: InProgress: Dequeuing in progress

RFIFO1

Receive message FIFO1 register

Offset: 0x10, reset: 0x00000000, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFD1
rw 		RFO1
rw 		RFF1
rw 		RFL1
r
Toggle Fields.

RFL1

Bits 0-1: Receive FIFO1 length.

Allowed values: 0-3

RFF1

Bit 3: Receive FIFO1 full.

Allowed values:
0: NotFull: Receive FIFO is not full
1: Full: Receive FIFO is full

RFO1

Bit 4: Receive FIFO1 overfull.

Allowed values:
0: NotOverfull: Receive FIFO is not overfull
1: Overfull: Receive FIFO is overfull

RFD1

Bit 5: Receive FIFO1 dequeue.

Allowed values:
0: Finished: Dequeuing done
1: InProgress: Dequeuing in progress

INTEN

Interrupt enable register

Offset: 0x14, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLPWIE
rw 		WIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE
rw 		ERRNIE
rw 		BOIE
rw 		PERRIE
rw 		WERRIE
rw 		RFOIE1
rw 		RFFIE1
rw 		RFNEIE1
rw 		RFOIE0
rw 		RFFIE0
rw 		RFNEIE0
rw 		TMEIE
rw
Toggle Fields.

TMEIE

Bit 0: Transmit mailbox empty interrupt enable.

Allowed values:
0: Disabled: Transmit mailbox empty interrupt is disabled
1: Enabled: Transmit mailbox empty interrupt is enabled

RFNEIE0

Bit 1: Receive FIFO0 not empty interrupt enable.

Allowed values:
0: Disabled: Receive FIFO not empty interrupt is disabled
1: Enabled: Receive FIFO not empty interrupt is enabled

RFFIE0

Bit 2: Receive FIFO0 full interrupt enable.

Allowed values:
0: Disabled: Receive FIFO full interrupt is disabled
1: Enabled: Receive FIFO full interrupt is enabled

RFOIE0

Bit 3: Receive FIFO0 overfull interrupt enable.

Allowed values:
0: Disabled: Receive FIFO overfull interrupt is disabled
1: Enabled: Receive FIFO overfull interrupt is enabled

RFNEIE1

Bit 4: Receive FIFO1 not empty interrupt enable.

Allowed values:
0: Disabled: Receive FIFO not empty interrupt is disabled
1: Enabled: Receive FIFO not empty interrupt is enabled

RFFIE1

Bit 5: Receive FIFO1 full interrupt enable.

Allowed values:
0: Disabled: Receive FIFO full interrupt is disabled
1: Enabled: Receive FIFO full interrupt is enabled

RFOIE1

Bit 6: Receive FIFO1 overfull interrupt enable.

Allowed values:
0: Disabled: Receive FIFO overfull interrupt is disabled
1: Enabled: Receive FIFO overfull interrupt is enabled

WERRIE

Bit 8: Warning error interrupt enable.

Allowed values:
0: Disabled: Warning error interrupt is disabled
1: Enabled: Warning error interrupt is enabled

PERRIE

Bit 9: Passive error interrupt enable.

Allowed values:
0: Disabled: Passive error interrupt is disabled
1: Enabled: Passive error interrupt is enabled

BOIE

Bit 10: Bus-off interrupt enable.

Allowed values:
0: Disabled: Bus-off interrupt is disabled
1: Enabled: Bus-off interrupt is enabled

ERRNIE

Bit 11: Error number interrupt enable.

Allowed values:
0: Disabled: Error number interrupt is disabled
1: Enabled: Error number interrupt is enabled

ERRIE

Bit 15: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt is disabled
1: Enabled: Error interrupt is enabled

WIE

Bit 16: Wakeup interrupt enable.

Allowed values:
0: Disabled: Wakeup interrupt is disabled
1: Enabled: Wakeup interrupt is enabled

SLPWIE

Bit 17: Sleep working interrupt enable.

Allowed values:
0: Disabled: Sleep working interrupt is disabled
1: Enabled: Sleep working interrupt is enabled

ERR

Error register

Offset: 0x18, reset: 0x00000000, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECNT
r 		TECNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRN
rw 		BOERR
r 		PERR
r 		WERR
r
Toggle Fields.

WERR

Bit 0: Warning error.

Allowed values:
0: NoError: No warning error
1: Error: Warning error

PERR

Bit 1: Passive error.

Allowed values:
0: NoError: No passive error
1: Error: Passive error

BOERR

Bit 2: Bus-off error.

Allowed values:
0: NoError: No bus-off error
1: Error: Bus-off error

ERRN

Bits 4-6: Error number.

Allowed values:
0: NoError: No Error
1: Stuff: Stuff Error
2: Form: Form Error
3: Ack: Acknowledgment Error
4: BitRecessive: Bit recessive Error
5: BitDominant: Bit dominant Error
6: Crc: CRC Error
7: Custom: Set by software

TECNT

Bits 16-23: Transmit Error Count defined by the CAN standard.

Allowed values: 0-255

RECNT

Bits 24-31: Receive Error Count defined by the CAN standard.

Allowed values: 0-255

BT

Bit timing register

Offset: 0x1C, reset: 0x01230000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCMOD
rw 		LCMOD
rw 		SJW
rw 		BS2
rw 		BS1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BAUDPSC
rw
Toggle Fields.

BAUDPSC

Bits 0-9: Baud rate prescaler.

Allowed values: 0-1023

BS1

Bits 16-19: Bit segment 1.

Allowed values: 0-3

BS2

Bits 20-22: Bit segment 2.

Allowed values: 0-3

SJW

Bits 24-25: Resynchronization jump width.

Allowed values: 0-3

LCMOD

Bit 30: Loopback communication mode.

Allowed values:
0: Disabled: Loop Back Mode disabled
1: Enabled: Loop Back Mode enabled

SCMOD

Bit 31: Silent communication mode.

Allowed values:
0: Normal: Normal operation
1: Silent: Silent Mode

TMI0

Transmit mailbox identifier register 0

Offset: 0x180, reset: 0x00000000, access: read-write

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

Allowed values:
0: Disabled: Transmit disabled
1: Enabled: Transmit enabled

FT

Bit 1: Frame type.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

FF

Bit 2: Frame format.

Allowed values:
0: Standard: Standard format frame
1: Extended: Extended format frame

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP0

Transmit mailbox property register 0

Offset: 0x184, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

Allowed values: 0-15

TSEN

Bit 8: Time stamp enable.

Allowed values:
0: Disabled: Timestamp disabled
1: Enabled: Timestamp enabled

TS

Bits 16-31: Time stamp.

Allowed values: 0-65535

TMDATA00

Transmit mailbox data0 register

Offset: 0x188, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

Allowed values: 0-255

DB1

Bits 8-15: Data byte 1.

Allowed values: 0-255

DB2

Bits 16-23: Data byte 2.

Allowed values: 0-255

DB3

Bits 24-31: Data byte 3.

Allowed values: 0-255

TMDATA10

Transmit mailbox data1 register

Offset: 0x18C, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

Allowed values: 0-255

DB5

Bits 8-15: Data byte 5.

Allowed values: 0-255

DB6

Bits 16-23: Data byte 6.

Allowed values: 0-255

DB7

Bits 24-31: Data byte 7.

Allowed values: 0-255

TMI1

Transmit mailbox identifier register 1

Offset: 0x190, reset: 0x00000000, access: read-write

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

Allowed values:
0: Disabled: Transmit disabled
1: Enabled: Transmit enabled

FT

Bit 1: Frame type.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

FF

Bit 2: Frame format.

Allowed values:
0: Standard: Standard format frame
1: Extended: Extended format frame

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP1

Transmit mailbox property register 1

Offset: 0x194, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

Allowed values: 0-15

TSEN

Bit 8: Time stamp enable.

Allowed values:
0: Disabled: Timestamp disabled
1: Enabled: Timestamp enabled

TS

Bits 16-31: Time stamp.

Allowed values: 0-65535

TMDATA01

Transmit mailbox data0 register

Offset: 0x198, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

Allowed values: 0-255

DB1

Bits 8-15: Data byte 1.

Allowed values: 0-255

DB2

Bits 16-23: Data byte 2.

Allowed values: 0-255

DB3

Bits 24-31: Data byte 3.

Allowed values: 0-255

TMDATA11

Transmit mailbox data1 register

Offset: 0x19C, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

Allowed values: 0-255

DB5

Bits 8-15: Data byte 5.

Allowed values: 0-255

DB6

Bits 16-23: Data byte 6.

Allowed values: 0-255

DB7

Bits 24-31: Data byte 7.

Allowed values: 0-255

TMI2

Transmit mailbox identifier register 2

Offset: 0x1A0, reset: 0x00000000, access: read-write

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

Allowed values:
0: Disabled: Transmit disabled
1: Enabled: Transmit enabled

FT

Bit 1: Frame type.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

FF

Bit 2: Frame format.

Allowed values:
0: Standard: Standard format frame
1: Extended: Extended format frame

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP2

Transmit mailbox property register 2

Offset: 0x1A4, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

Allowed values: 0-15

TSEN

Bit 8: Time stamp enable.

Allowed values:
0: Disabled: Timestamp disabled
1: Enabled: Timestamp enabled

TS

Bits 16-31: Time stamp.

Allowed values: 0-65535

TMDATA02

Transmit mailbox data0 register

Offset: 0x1A8, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

Allowed values: 0-255

DB1

Bits 8-15: Data byte 1.

Allowed values: 0-255

DB2

Bits 16-23: Data byte 2.

Allowed values: 0-255

DB3

Bits 24-31: Data byte 3.

Allowed values: 0-255

TMDATA12

Transmit mailbox data1 register

Offset: 0x1AC, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

Allowed values: 0-255

DB5

Bits 8-15: Data byte 5.

Allowed values: 0-255

DB6

Bits 16-23: Data byte 6.

Allowed values: 0-255

DB7

Bits 24-31: Data byte 7.

Allowed values: 0-255

RFIFOMI0

Receive FIFO mailbox identifier register

Offset: 0x1B0, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
r 		EFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
r 		FF
r 		FT
r
Toggle Fields.

FT

Bit 1: Frame type.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

FF

Bit 2: Frame format.

Allowed values:
0: Standard: Standard format frame
1: Extended: Extended format frame

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

RFIFOMP0

Receive FIFO0 mailbox property register

Offset: 0x1B4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FI
r 		DLENC
r
Toggle Fields.

DLENC

Bits 0-3: Data length code.

Allowed values: 0-15

FI

Bits 8-15: Filtering index.

Allowed values: 0-255

TS

Bits 16-31: Time stamp.

Allowed values: 0-65535

RFIFOMDATA00

Receive FIFO0 mailbox data0 register

Offset: 0x1B8, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
r 		DB2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
r 		DB0
r
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

Allowed values: 0-255

DB1

Bits 8-15: Data byte 1.

Allowed values: 0-255

DB2

Bits 16-23: Data byte 2.

Allowed values: 0-255

DB3

Bits 24-31: Data byte 3.

Allowed values: 0-255

RFIFOMDATA10

Receive FIFO0 mailbox data1 register

Offset: 0x1BC, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
r 		DB6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
r 		DB4
r
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

Allowed values: 0-255

DB5

Bits 8-15: Data byte 5.

Allowed values: 0-255

DB6

Bits 16-23: Data byte 6.

Allowed values: 0-255

DB7

Bits 24-31: Data byte 7.

Allowed values: 0-255

RFIFOMI1

Receive FIFO1 mailbox identifier register

Offset: 0x1C0, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
r 		EFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
r 		FF
r 		FT
r
Toggle Fields.

FT

Bit 1: Frame type.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

FF

Bit 2: Frame format.

Allowed values:
0: Standard: Standard format frame
1: Extended: Extended format frame

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

RFIFOMP1

Receive FIFO1 mailbox property register

Offset: 0x1C4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FI
r 		DLENC
r
Toggle Fields.

DLENC

Bits 0-3: Data length code.

Allowed values: 0-15

FI

Bits 8-15: Filtering index.

Allowed values: 0-255

TS

Bits 16-31: Time stamp.

Allowed values: 0-65535

RFIFOMDATA01

Receive FIFO1 mailbox data0 register

Offset: 0x1C8, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
r 		DB2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
r 		DB0
r
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

Allowed values: 0-255

DB1

Bits 8-15: Data byte 1.

Allowed values: 0-255

DB2

Bits 16-23: Data byte 2.

Allowed values: 0-255

DB3

Bits 24-31: Data byte 3.

Allowed values: 0-255

RFIFOMDATA11

Receive FIFO1 mailbox data1 register

Offset: 0x1CC, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
r 		DB6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
r 		DB4
r
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

Allowed values: 0-255

DB5

Bits 8-15: Data byte 5.

Allowed values: 0-255

DB6

Bits 16-23: Data byte 6.

Allowed values: 0-255

DB7

Bits 24-31: Data byte 7.

Allowed values: 0-255

FCTL

Filter control register

Offset: 0x200, reset: 0x2A1C0E01, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HBC1F
rw 		FLD
rw
Toggle Fields.

FLD

Bit 0: Filter lock disable.

Allowed values:
0: Disabled: Filter lock disabled
1: Enabled: Filter lock enabled

HBC1F

Bits 8-13: Header bank of CAN1 filter.

Allowed values: 0-28

FMCFG

Filter mode configuration register

Offset: 0x204, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FMOD27
rw 		FMOD26
rw 		FMOD25
rw 		FMOD24
rw 		FMOD23
rw 		FMOD22
rw 		FMOD21
rw 		FMOD20
rw 		FMOD19
rw 		FMOD18
rw 		FMOD17
rw 		FMOD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMOD15
rw 		FMOD14
rw 		FMOD13
rw 		FMOD12
rw 		FMOD11
rw 		FMOD10
rw 		FMOD9
rw 		FMOD8
rw 		FMOD7
rw 		FMOD6
rw 		FMOD5
rw 		FMOD4
rw 		FMOD3
rw 		FMOD2
rw 		FMOD1
rw 		FMOD0
rw
Toggle Fields.

FMOD0

Bit 0: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD1

Bit 1: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD2

Bit 2: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD3

Bit 3: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD4

Bit 4: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD5

Bit 5: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD6

Bit 6: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD7

Bit 7: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD8

Bit 8: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD9

Bit 9: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD10

Bit 10: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD11

Bit 11: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD12

Bit 12: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD13

Bit 13: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD14

Bit 14: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD15

Bit 15: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD16

Bit 16: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD17

Bit 17: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD18

Bit 18: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD19

Bit 19: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD20

Bit 20: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD21

Bit 21: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD22

Bit 22: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD23

Bit 23: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD24

Bit 24: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD25

Bit 25: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD26

Bit 26: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD27

Bit 27: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FSCFG

Filter scale configuration register

Offset: 0x20C, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FS27
rw 		FS26
rw 		FS25
rw 		FS24
rw 		FS23
rw 		FS22
rw 		FS21
rw 		FS20
rw 		FS19
rw 		FS18
rw 		FS17
rw 		FS16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FS15
rw 		FS14
rw 		FS13
rw 		FS12
rw 		FS11
rw 		FS10
rw 		FS9
rw 		FS8
rw 		FS7
rw 		FS6
rw 		FS5
rw 		FS4
rw 		FS3
rw 		FS2
rw 		FS1
rw 		FS0
rw
Toggle Fields.

FS0

Bit 0: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS1

Bit 1: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS2

Bit 2: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS3

Bit 3: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS4

Bit 4: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS5

Bit 5: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS6

Bit 6: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS7

Bit 7: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS8

Bit 8: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS9

Bit 9: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS10

Bit 10: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS11

Bit 11: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS12

Bit 12: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS13

Bit 13: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS14

Bit 14: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS15

Bit 15: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS16

Bit 16: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS17

Bit 17: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS18

Bit 18: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS19

Bit 19: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS20

Bit 20: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS21

Bit 21: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS22

Bit 22: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS23

Bit 23: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS24

Bit 24: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS25

Bit 25: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS26

Bit 26: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS27

Bit 27: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FAFIFO

Filter associated FIFO register

Offset: 0x214, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FAF27
rw 		FAF26
rw 		FAF25
rw 		FAF24
rw 		FAF23
rw 		FAF22
rw 		FAF21
rw 		FAF20
rw 		FAF19
rw 		FAF18
rw 		FAF17
rw 		FAF16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAF15
rw 		FAF14
rw 		FAF13
rw 		FAF12
rw 		FAF11
rw 		FAF10
rw 		FAF9
rw 		FAF8
rw 		FAF7
rw 		FAF6
rw 		FAF5
rw 		FAF4
rw 		FAF3
rw 		FAF2
rw 		FAF1
rw 		FAF0
rw
Toggle Fields.

FAF0

Bit 0: Filter 0 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF1

Bit 1: Filter 1 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF2

Bit 2: Filter 2 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF3

Bit 3: Filter 3 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF4

Bit 4: Filter 4 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF5

Bit 5: Filter 5 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF6

Bit 6: Filter 6 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF7

Bit 7: Filter 7 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF8

Bit 8: Filter 8 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF9

Bit 9: Filter 9 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF10

Bit 10: Filter 10 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF11

Bit 11: Filter 11 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF12

Bit 12: Filter 12 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF13

Bit 13: Filter 13 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF14

Bit 14: Filter 14 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF15

Bit 15: Filter 15 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF16

Bit 16: Filter 16 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF17

Bit 17: Filter 17 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF18

Bit 18: Filter 18 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF19

Bit 19: Filter 19 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF20

Bit 20: Filter 20 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF21

Bit 21: Filter 21 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF22

Bit 22: Filter 22 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF23

Bit 23: Filter 23 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF24

Bit 24: Filter 24 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF25

Bit 25: Filter 25 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF26

Bit 26: Filter 26 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF27

Bit 27: Filter 27 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FW

Filter working register

Offset: 0x21C, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FW27
rw 		FW26
rw 		FW25
rw 		FW24
rw 		FW23
rw 		FW22
rw 		FW21
rw 		FW20
rw 		FW19
rw 		FW18
rw 		FW17
rw 		FW16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FW15
rw 		FW14
rw 		FW13
rw 		FW12
rw 		FW11
rw 		FW10
rw 		FW9
rw 		FW8
rw 		FW7
rw 		FW6
rw 		FW5
rw 		FW4
rw 		FW3
rw 		FW2
rw 		FW1
rw 		FW0
rw
Toggle Fields.

FW0

Bit 0: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW1

Bit 1: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW2

Bit 2: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW3

Bit 3: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW4

Bit 4: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW5

Bit 5: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW6

Bit 6: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW7

Bit 7: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW8

Bit 8: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW9

Bit 9: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW10

Bit 10: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW11

Bit 11: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW12

Bit 12: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW13

Bit 13: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW14

Bit 14: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW15

Bit 15: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW16

Bit 16: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW17

Bit 17: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW18

Bit 18: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW19

Bit 19: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW20

Bit 20: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW21

Bit 21: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW22

Bit 22: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW23

Bit 23: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW24

Bit 24: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW25

Bit 25: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW26

Bit 26: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW27

Bit 27: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

F0DATA0

Filter 0 data 0 register

Offset: 0x240, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F0DATA1

Filter 0 data 1 register

Offset: 0x244, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F1DATA0

Filter 1 data 0 register

Offset: 0x248, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F1DATA1

Filter 1 data 1 register

Offset: 0x24C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F2DATA0

Filter 2 data 0 register

Offset: 0x250, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F2DATA1

Filter 2 data 1 register

Offset: 0x254, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F3DATA0

Filter 3 data 0 register

Offset: 0x258, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F3DATA1

Filter 3 data 1 register

Offset: 0x25C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F4DATA0

Filter 4 data 0 register

Offset: 0x260, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F4DATA1

Filter 4 data 1 register

Offset: 0x264, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F5DATA0

Filter 5 data 0 register

Offset: 0x268, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F5DATA1

Filter 5 data 1 register

Offset: 0x26C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F6DATA0

Filter 6 data 0 register

Offset: 0x270, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F6DATA1

Filter 6 data 1 register

Offset: 0x274, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F7DATA0

Filter 7 data 0 register

Offset: 0x278, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F7DATA1

Filter 7 data 1 register

Offset: 0x27C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F8DATA0

Filter 8 data 0 register

Offset: 0x280, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F8DATA1

Filter 8 data 1 register

Offset: 0x284, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F9DATA0

Filter 9 data 0 register

Offset: 0x288, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F9DATA1

Filter 9 data 1 register

Offset: 0x28C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F10DATA0

Filter 10 data 0 register

Offset: 0x290, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F10DATA1

Filter 10 data 1 register

Offset: 0x294, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F11DATA0

Filter 11 data 0 register

Offset: 0x298, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F11DATA1

Filter 11 data 1 register

Offset: 0x29C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F12DATA0

Filter 12 data 0 register

Offset: 0x2A0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F12DATA1

Filter 12 data 1 register

Offset: 0x2A4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F13DATA0

Filter 13 data 0 register

Offset: 0x2A8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F13DATA1

Filter 13 data 1 register

Offset: 0x2AC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F14DATA0

Filter 14 data 0 register

Offset: 0x2B0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F14DATA1

Filter 14 data 1 register

Offset: 0x2B4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F15DATA0

Filter 15 data 0 register

Offset: 0x2B8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F15DATA1

Filter 15 data 1 register

Offset: 0x2BC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F16DATA0

Filter 16 data 0 register

Offset: 0x2C0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F16DATA1

Filter 16 data 1 register

Offset: 0x2C4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F17DATA0

Filter 17 data 0 register

Offset: 0x2C8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F17DATA1

Filter 17 data 1 register

Offset: 0x2CC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F18DATA0

Filter 18 data 0 register

Offset: 0x2D0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F18DATA1

Filter 18 data 1 register

Offset: 0x2D4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F19DATA0

Filter 19 data 0 register

Offset: 0x2D8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F19DATA1

Filter 19 data 1 register

Offset: 0x2DC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F20DATA0

Filter 20 data 0 register

Offset: 0x2E0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F20DATA1

Filter 20 data 1 register

Offset: 0x2E4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F21DATA0

Filter 21 data 0 register

Offset: 0x2E8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F21DATA1

Filter 21 data 1 register

Offset: 0x2EC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F22DATA0

Filter 22 data 0 register

Offset: 0x2F0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F22DATA1

Filter 22 data 1 register

Offset: 0x2F4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F23DATA0

Filter 23 data 0 register

Offset: 0x2F8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F23DATA1

Filter 23 data 1 register

Offset: 0x2FC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F24DATA0

Filter 24 data 0 register

Offset: 0x300, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F24DATA1

Filter 24 data 1 register

Offset: 0x304, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F25DATA0

Filter 25 data 0 register

Offset: 0x308, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F25DATA1

Filter 25 data 1 register

Offset: 0x30C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F26DATA0

Filter 26 data 0 register

Offset: 0x310, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F26DATA1

Filter 26 data 1 register

Offset: 0x314, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F27DATA0

Filter 27 data 0 register

Offset: 0x318, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F27DATA1

Filter 27 data 1 register

Offset: 0x31C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

CAN1

0x40006800: Controller area network

261/2059 fields covered. Toggle Registers.

CTL

Control register

Offset: 0x0, reset: 0x00010002, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
rw 		TTC
rw 		ABOR
rw 		AWU
rw 		ARD
rw 		RFOD
rw 		TFO
rw 		SLPWMOD
rw 		IWMOD
rw
Toggle Fields.

IWMOD

Bit 0: Initial working mode.

Allowed values:
0: Disabled: Disable initial working mode
1: Enabled: Enable initial working mode

SLPWMOD

Bit 1: Sleep working mode.

Allowed values:
0: Active: Disable sleep mode, bus activity detected
1: Sleep: Enable sleep mode

TFO

Bit 2: Transmit FIFO order.

Allowed values:
0: Identifier: Order by identifier of the frame
1: FIFO: First in first out order

RFOD

Bit 3: Receive FIFO overwrite disable.

Allowed values:
0: Overwrite: Overwrite full receive FIFO with incoming frame
1: Discard: Discard incoming frame when receive FIFO is full

ARD

Bit 4: Automatic retransmission disable.

Allowed values:
0: Enabled: Enable automatic retransmission
1: Disabled: Disable automatic retransmission

AWU

Bit 5: Automatic wakeup.

Allowed values:
0: Manual: Sleep state is set by software
1: Automatic: Sleep state is set automatically by hardware

ABOR

Bit 6: Automatic bus-off recovery.

Allowed values:
0: Manual: Bus off state is set by software
1: Automatic: Bus off state is set automatically by hardware

TTC

Bit 7: Time-triggered communication.

Allowed values:
0: Disabled: Disable time-triggered communication
1: Enabled: Enable time-triggered communication

SWRST

Bit 15: Software reset.

Allowed values:
0: NotResetting: Finished resetting
1: Resetting: Reset in progress

DFZ

Bit 16: Debug freeze.

Allowed values:
0: Continue: Continue running CAN during debug
1: Stop: Stop CAN reception and transmission during debug hold

STAT

Status register

Offset: 0x4, reset: 0x00000C02, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXL
r 		LASTRX
r 		RS
r 		TS
r 		SLPIF
rw 		WUIF
rw 		ERRIF
rw 		SLPWS
r 		IWS
r
Toggle Fields.

IWS

Bit 0: Initial working state.

Allowed values:
0: Normal: CAN is not in initial working mode
1: Initial: CAN is in initial working mode

SLPWS

Bit 1: Sleep working state.

Allowed values:
0: Normal: CAN is not in sleep working mode
1: Sleeping: CAN is in sleep working mode

ERRIF

Bit 2: Error interrupt flag.

Allowed values:
0: NoError: There was no error
1: Error: An error was detected

WUIF

Bit 3: Status change interrupt flag of wakeup from sleep working mode.

Allowed values:
0: NoWakeup: No wakeup event
1: Wakeup: Wakeup event

SLPIF

Bit 4: Status change interrupt flag of sleep working mode entering.

Allowed values:
0: Awake: CAN is not entering sleep working mode
1: Sleeping: CAN is entering sleep working mode

TS

Bit 8: Transmitting state.

Allowed values:
0: NotWorking: CAN is not working in transmitting state
1: Working: CAN is working in transmitting state

RS

Bit 9: Receiving state.

Allowed values:
0: NotWorking: CAN is not working in receiving state
1: Working: CAN is working in receiving state

LASTRX

Bit 10: Last sample value of RX pin.

RXL

Bit 11: RX level.

TSTAT

Transmit status register

Offset: 0x8, reset: 0x1C000000, access: Unspecified

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TMLS2
r 		TMLS1
r 		TMLS0
r 		TME2
r 		TME1
r 		TME0
r 		NUM
r 		MST2
rw 		MTE2
rw 		MAL2
rw 		MTFNERR2
rw 		MTF2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MST1
rw 		MTE1
rw 		MAL1
rw 		MTFNERR1
rw 		MTF1
rw 		MST0
rw 		MTE0
rw 		MAL0
rw 		MTFNERR0
rw 		MTF0
rw
Toggle Fields.

MTF0

Bit 0: Mailbox 0 transmit finished.

Allowed values:
0: InProgress: Mailbox transmission still in progress
1: Finished: Mailbox transmission finished

MTFNERR0

Bit 1: Mailbox 0 transmit finished and no error.

Allowed values:
0: FinishedWithError: Mailbox transmission finished with an error
1: FinishedNoError: Mailbox transmission finished with no error

MAL0

Bit 2: Mailbox 0 arbitration lost.

Allowed values:
0: NoArbitrationLost: Arbitration was not lost
1: ArbitrationLost: Arbitration lost

MTE0

Bit 3: Mailbox 0 transmit error.

Allowed values:
0: NoError: There was no error
1: Error: An error was detected

MST0

Bit 7: Mailbox 0 stop transmitting.

Allowed values:
0: NotStop: Mailbox is not stopped, or is empty
1: Stop: Stop mailbox transmitting

MTF1

Bit 8: Mailbox 1 transmit finished.

Allowed values:
0: InProgress: Mailbox transmission still in progress
1: Finished: Mailbox transmission finished

MTFNERR1

Bit 9: Mailbox 1 transmit finished and no error.

Allowed values:
0: FinishedWithError: Mailbox transmission finished with an error
1: FinishedNoError: Mailbox transmission finished with no error

MAL1

Bit 10: Mailbox 1 arbitration lost.

Allowed values:
0: NoArbitrationLost: Arbitration was not lost
1: ArbitrationLost: Arbitration lost

MTE1

Bit 11: Mailbox 1 transmit error.

Allowed values:
0: NoError: There was no error
1: Error: An error was detected

MST1

Bit 15: Mailbox 1 stop transmitting.

Allowed values:
0: NotStop: Mailbox is not stopped, or is empty
1: Stop: Stop mailbox transmitting

MTF2

Bit 16: Mailbox 2 transmit finished.

Allowed values:
0: InProgress: Mailbox transmission still in progress
1: Finished: Mailbox transmission finished

MTFNERR2

Bit 17: Mailbox 2 transmit finished and no error.

Allowed values:
0: FinishedWithError: Mailbox transmission finished with an error
1: FinishedNoError: Mailbox transmission finished with no error

MAL2

Bit 18: Mailbox 2 arbitration lost.

Allowed values:
0: NoArbitrationLost: Arbitration was not lost
1: ArbitrationLost: Arbitration lost

MTE2

Bit 19: Mailbox 2 transmit error.

Allowed values:
0: NoError: There was no error
1: Error: An error was detected

MST2

Bit 23: Mailbox 2 stop transmitting.

Allowed values:
0: NotStop: Mailbox is not stopped, or is empty
1: Stop: Stop mailbox transmitting

NUM

Bits 24-25: number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty.

Allowed values: 0-2

TME0

Bit 26: Transmit mailbox 0 empty.

Allowed values:
0: NotEmpty: Transmit mailbox not empty
1: Empty: Transmit mailbox is empty

TME1

Bit 27: Transmit mailbox 1 empty.

Allowed values:
0: NotEmpty: Transmit mailbox not empty
1: Empty: Transmit mailbox is empty

TME2

Bit 28: Transmit mailbox 2 empty.

Allowed values:
0: NotEmpty: Transmit mailbox not empty
1: Empty: Transmit mailbox is empty

TMLS0

Bit 29: Transmit mailbox 0 last sending in transmit FIFO.

Allowed values:
0: NotLast: The mailbox doesn't have the last sending order
1: Last: The mailbox has the last sending order with at least two frames pending

TMLS1

Bit 30: Transmit mailbox 1 last sending in transmit FIFO.

Allowed values:
0: NotLast: The mailbox doesn't have the last sending order
1: Last: The mailbox has the last sending order with at least two frames pending

TMLS2

Bit 31: Transmit mailbox 2 last sending in transmit FIFO.

Allowed values:
0: NotLast: The mailbox doesn't have the last sending order
1: Last: The mailbox has the last sending order with at least two frames pending

RFIFO0

Receive message FIFO0 register

Offset: 0xC, reset: 0x00000000, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFD0
rw 		RFO0
rw 		RFF0
rw 		RFL0
r
Toggle Fields.

RFL0

Bits 0-1: Receive FIFO0 length.

Allowed values: 0-3

RFF0

Bit 3: Receive FIFO0 full.

Allowed values:
0: NotFull: Receive FIFO is not full
1: Full: Receive FIFO is full

RFO0

Bit 4: Receive FIFO0 overfull.

Allowed values:
0: NotOverfull: Receive FIFO is not overfull
1: Overfull: Receive FIFO is overfull

RFD0

Bit 5: Receive FIFO0 dequeue.

Allowed values:
0: Finished: Dequeuing done
1: InProgress: Dequeuing in progress

RFIFO1

Receive message FIFO1 register

Offset: 0x10, reset: 0x00000000, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFD1
rw 		RFO1
rw 		RFF1
rw 		RFL1
r
Toggle Fields.

RFL1

Bits 0-1: Receive FIFO1 length.

Allowed values: 0-3

RFF1

Bit 3: Receive FIFO1 full.

Allowed values:
0: NotFull: Receive FIFO is not full
1: Full: Receive FIFO is full

RFO1

Bit 4: Receive FIFO1 overfull.

Allowed values:
0: NotOverfull: Receive FIFO is not overfull
1: Overfull: Receive FIFO is overfull

RFD1

Bit 5: Receive FIFO1 dequeue.

Allowed values:
0: Finished: Dequeuing done
1: InProgress: Dequeuing in progress

INTEN

Interrupt enable register

Offset: 0x14, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLPWIE
rw 		WIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE
rw 		ERRNIE
rw 		BOIE
rw 		PERRIE
rw 		WERRIE
rw 		RFOIE1
rw 		RFFIE1
rw 		RFNEIE1
rw 		RFOIE0
rw 		RFFIE0
rw 		RFNEIE0
rw 		TMEIE
rw
Toggle Fields.

TMEIE

Bit 0: Transmit mailbox empty interrupt enable.

Allowed values:
0: Disabled: Transmit mailbox empty interrupt is disabled
1: Enabled: Transmit mailbox empty interrupt is enabled

RFNEIE0

Bit 1: Receive FIFO0 not empty interrupt enable.

Allowed values:
0: Disabled: Receive FIFO not empty interrupt is disabled
1: Enabled: Receive FIFO not empty interrupt is enabled

RFFIE0

Bit 2: Receive FIFO0 full interrupt enable.

Allowed values:
0: Disabled: Receive FIFO full interrupt is disabled
1: Enabled: Receive FIFO full interrupt is enabled

RFOIE0

Bit 3: Receive FIFO0 overfull interrupt enable.

Allowed values:
0: Disabled: Receive FIFO overfull interrupt is disabled
1: Enabled: Receive FIFO overfull interrupt is enabled

RFNEIE1

Bit 4: Receive FIFO1 not empty interrupt enable.

Allowed values:
0: Disabled: Receive FIFO not empty interrupt is disabled
1: Enabled: Receive FIFO not empty interrupt is enabled

RFFIE1

Bit 5: Receive FIFO1 full interrupt enable.

Allowed values:
0: Disabled: Receive FIFO full interrupt is disabled
1: Enabled: Receive FIFO full interrupt is enabled

RFOIE1

Bit 6: Receive FIFO1 overfull interrupt enable.

Allowed values:
0: Disabled: Receive FIFO overfull interrupt is disabled
1: Enabled: Receive FIFO overfull interrupt is enabled

WERRIE

Bit 8: Warning error interrupt enable.

Allowed values:
0: Disabled: Warning error interrupt is disabled
1: Enabled: Warning error interrupt is enabled

PERRIE

Bit 9: Passive error interrupt enable.

Allowed values:
0: Disabled: Passive error interrupt is disabled
1: Enabled: Passive error interrupt is enabled

BOIE

Bit 10: Bus-off interrupt enable.

Allowed values:
0: Disabled: Bus-off interrupt is disabled
1: Enabled: Bus-off interrupt is enabled

ERRNIE

Bit 11: Error number interrupt enable.

Allowed values:
0: Disabled: Error number interrupt is disabled
1: Enabled: Error number interrupt is enabled

ERRIE

Bit 15: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt is disabled
1: Enabled: Error interrupt is enabled

WIE

Bit 16: Wakeup interrupt enable.

Allowed values:
0: Disabled: Wakeup interrupt is disabled
1: Enabled: Wakeup interrupt is enabled

SLPWIE

Bit 17: Sleep working interrupt enable.

Allowed values:
0: Disabled: Sleep working interrupt is disabled
1: Enabled: Sleep working interrupt is enabled

ERR

Error register

Offset: 0x18, reset: 0x00000000, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECNT
r 		TECNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRN
rw 		BOERR
r 		PERR
r 		WERR
r
Toggle Fields.

WERR

Bit 0: Warning error.

Allowed values:
0: NoError: No warning error
1: Error: Warning error

PERR

Bit 1: Passive error.

Allowed values:
0: NoError: No passive error
1: Error: Passive error

BOERR

Bit 2: Bus-off error.

Allowed values:
0: NoError: No bus-off error
1: Error: Bus-off error

ERRN

Bits 4-6: Error number.

Allowed values:
0: NoError: No Error
1: Stuff: Stuff Error
2: Form: Form Error
3: Ack: Acknowledgment Error
4: BitRecessive: Bit recessive Error
5: BitDominant: Bit dominant Error
6: Crc: CRC Error
7: Custom: Set by software

TECNT

Bits 16-23: Transmit Error Count defined by the CAN standard.

Allowed values: 0-255

RECNT

Bits 24-31: Receive Error Count defined by the CAN standard.

Allowed values: 0-255

BT

Bit timing register

Offset: 0x1C, reset: 0x01230000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCMOD
rw 		LCMOD
rw 		SJW
rw 		BS2
rw 		BS1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BAUDPSC
rw
Toggle Fields.

BAUDPSC

Bits 0-9: Baud rate prescaler.

Allowed values: 0-1023

BS1

Bits 16-19: Bit segment 1.

Allowed values: 0-3

BS2

Bits 20-22: Bit segment 2.

Allowed values: 0-3

SJW

Bits 24-25: Resynchronization jump width.

Allowed values: 0-3

LCMOD

Bit 30: Loopback communication mode.

Allowed values:
0: Disabled: Loop Back Mode disabled
1: Enabled: Loop Back Mode enabled

SCMOD

Bit 31: Silent communication mode.

Allowed values:
0: Normal: Normal operation
1: Silent: Silent Mode

TMI0

Transmit mailbox identifier register 0

Offset: 0x180, reset: 0x00000000, access: read-write

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

Allowed values:
0: Disabled: Transmit disabled
1: Enabled: Transmit enabled

FT

Bit 1: Frame type.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

FF

Bit 2: Frame format.

Allowed values:
0: Standard: Standard format frame
1: Extended: Extended format frame

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP0

Transmit mailbox property register 0

Offset: 0x184, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

Allowed values: 0-15

TSEN

Bit 8: Time stamp enable.

Allowed values:
0: Disabled: Timestamp disabled
1: Enabled: Timestamp enabled

TS

Bits 16-31: Time stamp.

Allowed values: 0-65535

TMDATA00

Transmit mailbox data0 register

Offset: 0x188, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

Allowed values: 0-255

DB1

Bits 8-15: Data byte 1.

Allowed values: 0-255

DB2

Bits 16-23: Data byte 2.

Allowed values: 0-255

DB3

Bits 24-31: Data byte 3.

Allowed values: 0-255

TMDATA10

Transmit mailbox data1 register

Offset: 0x18C, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

Allowed values: 0-255

DB5

Bits 8-15: Data byte 5.

Allowed values: 0-255

DB6

Bits 16-23: Data byte 6.

Allowed values: 0-255

DB7

Bits 24-31: Data byte 7.

Allowed values: 0-255

TMI1

Transmit mailbox identifier register 1

Offset: 0x190, reset: 0x00000000, access: read-write

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

Allowed values:
0: Disabled: Transmit disabled
1: Enabled: Transmit enabled

FT

Bit 1: Frame type.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

FF

Bit 2: Frame format.

Allowed values:
0: Standard: Standard format frame
1: Extended: Extended format frame

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP1

Transmit mailbox property register 1

Offset: 0x194, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

Allowed values: 0-15

TSEN

Bit 8: Time stamp enable.

Allowed values:
0: Disabled: Timestamp disabled
1: Enabled: Timestamp enabled

TS

Bits 16-31: Time stamp.

Allowed values: 0-65535

TMDATA01

Transmit mailbox data0 register

Offset: 0x198, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

Allowed values: 0-255

DB1

Bits 8-15: Data byte 1.

Allowed values: 0-255

DB2

Bits 16-23: Data byte 2.

Allowed values: 0-255

DB3

Bits 24-31: Data byte 3.

Allowed values: 0-255

TMDATA11

Transmit mailbox data1 register

Offset: 0x19C, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

Allowed values: 0-255

DB5

Bits 8-15: Data byte 5.

Allowed values: 0-255

DB6

Bits 16-23: Data byte 6.

Allowed values: 0-255

DB7

Bits 24-31: Data byte 7.

Allowed values: 0-255

TMI2

Transmit mailbox identifier register 2

Offset: 0x1A0, reset: 0x00000000, access: read-write

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

Allowed values:
0: Disabled: Transmit disabled
1: Enabled: Transmit enabled

FT

Bit 1: Frame type.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

FF

Bit 2: Frame format.

Allowed values:
0: Standard: Standard format frame
1: Extended: Extended format frame

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP2

Transmit mailbox property register 2

Offset: 0x1A4, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

Allowed values: 0-15

TSEN

Bit 8: Time stamp enable.

Allowed values:
0: Disabled: Timestamp disabled
1: Enabled: Timestamp enabled

TS

Bits 16-31: Time stamp.

Allowed values: 0-65535

TMDATA02

Transmit mailbox data0 register

Offset: 0x1A8, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

Allowed values: 0-255

DB1

Bits 8-15: Data byte 1.

Allowed values: 0-255

DB2

Bits 16-23: Data byte 2.

Allowed values: 0-255

DB3

Bits 24-31: Data byte 3.

Allowed values: 0-255

TMDATA12

Transmit mailbox data1 register

Offset: 0x1AC, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

Allowed values: 0-255

DB5

Bits 8-15: Data byte 5.

Allowed values: 0-255

DB6

Bits 16-23: Data byte 6.

Allowed values: 0-255

DB7

Bits 24-31: Data byte 7.

Allowed values: 0-255

RFIFOMI0

Receive FIFO mailbox identifier register

Offset: 0x1B0, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
r 		EFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
r 		FF
r 		FT
r
Toggle Fields.

FT

Bit 1: Frame type.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

FF

Bit 2: Frame format.

Allowed values:
0: Standard: Standard format frame
1: Extended: Extended format frame

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

RFIFOMP0

Receive FIFO0 mailbox property register

Offset: 0x1B4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FI
r 		DLENC
r
Toggle Fields.

DLENC

Bits 0-3: Data length code.

Allowed values: 0-15

FI

Bits 8-15: Filtering index.

Allowed values: 0-255

TS

Bits 16-31: Time stamp.

Allowed values: 0-65535

RFIFOMDATA00

Receive FIFO0 mailbox data0 register

Offset: 0x1B8, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
r 		DB2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
r 		DB0
r
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

Allowed values: 0-255

DB1

Bits 8-15: Data byte 1.

Allowed values: 0-255

DB2

Bits 16-23: Data byte 2.

Allowed values: 0-255

DB3

Bits 24-31: Data byte 3.

Allowed values: 0-255

RFIFOMDATA10

Receive FIFO0 mailbox data1 register

Offset: 0x1BC, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
r 		DB6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
r 		DB4
r
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

Allowed values: 0-255

DB5

Bits 8-15: Data byte 5.

Allowed values: 0-255

DB6

Bits 16-23: Data byte 6.

Allowed values: 0-255

DB7

Bits 24-31: Data byte 7.

Allowed values: 0-255

RFIFOMI1

Receive FIFO1 mailbox identifier register

Offset: 0x1C0, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
r 		EFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
r 		FF
r 		FT
r
Toggle Fields.

FT

Bit 1: Frame type.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

FF

Bit 2: Frame format.

Allowed values:
0: Standard: Standard format frame
1: Extended: Extended format frame

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

RFIFOMP1

Receive FIFO1 mailbox property register

Offset: 0x1C4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FI
r 		DLENC
r
Toggle Fields.

DLENC

Bits 0-3: Data length code.

Allowed values: 0-15

FI

Bits 8-15: Filtering index.

Allowed values: 0-255

TS

Bits 16-31: Time stamp.

Allowed values: 0-65535

RFIFOMDATA01

Receive FIFO1 mailbox data0 register

Offset: 0x1C8, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
r 		DB2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
r 		DB0
r
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

Allowed values: 0-255

DB1

Bits 8-15: Data byte 1.

Allowed values: 0-255

DB2

Bits 16-23: Data byte 2.

Allowed values: 0-255

DB3

Bits 24-31: Data byte 3.

Allowed values: 0-255

RFIFOMDATA11

Receive FIFO1 mailbox data1 register

Offset: 0x1CC, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
r 		DB6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
r 		DB4
r
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

Allowed values: 0-255

DB5

Bits 8-15: Data byte 5.

Allowed values: 0-255

DB6

Bits 16-23: Data byte 6.

Allowed values: 0-255

DB7

Bits 24-31: Data byte 7.

Allowed values: 0-255

FCTL

Filter control register

Offset: 0x200, reset: 0x2A1C0E01, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HBC1F
rw 		FLD
rw
Toggle Fields.

FLD

Bit 0: Filter lock disable.

Allowed values:
0: Disabled: Filter lock disabled
1: Enabled: Filter lock enabled

HBC1F

Bits 8-13: Header bank of CAN1 filter.

Allowed values: 0-28

FMCFG

Filter mode configuration register

Offset: 0x204, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FMOD27
rw 		FMOD26
rw 		FMOD25
rw 		FMOD24
rw 		FMOD23
rw 		FMOD22
rw 		FMOD21
rw 		FMOD20
rw 		FMOD19
rw 		FMOD18
rw 		FMOD17
rw 		FMOD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMOD15
rw 		FMOD14
rw 		FMOD13
rw 		FMOD12
rw 		FMOD11
rw 		FMOD10
rw 		FMOD9
rw 		FMOD8
rw 		FMOD7
rw 		FMOD6
rw 		FMOD5
rw 		FMOD4
rw 		FMOD3
rw 		FMOD2
rw 		FMOD1
rw 		FMOD0
rw
Toggle Fields.

FMOD0

Bit 0: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD1

Bit 1: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD2

Bit 2: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD3

Bit 3: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD4

Bit 4: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD5

Bit 5: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD6

Bit 6: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD7

Bit 7: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD8

Bit 8: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD9

Bit 9: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD10

Bit 10: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD11

Bit 11: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD12

Bit 12: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD13

Bit 13: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD14

Bit 14: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD15

Bit 15: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD16

Bit 16: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD17

Bit 17: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD18

Bit 18: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD19

Bit 19: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD20

Bit 20: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD21

Bit 21: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD22

Bit 22: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD23

Bit 23: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD24

Bit 24: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD25

Bit 25: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD26

Bit 26: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD27

Bit 27: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FSCFG

Filter scale configuration register

Offset: 0x20C, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FS27
rw 		FS26
rw 		FS25
rw 		FS24
rw 		FS23
rw 		FS22
rw 		FS21
rw 		FS20
rw 		FS19
rw 		FS18
rw 		FS17
rw 		FS16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FS15
rw 		FS14
rw 		FS13
rw 		FS12
rw 		FS11
rw 		FS10
rw 		FS9
rw 		FS8
rw 		FS7
rw 		FS6
rw 		FS5
rw 		FS4
rw 		FS3
rw 		FS2
rw 		FS1
rw 		FS0
rw
Toggle Fields.

FS0

Bit 0: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS1

Bit 1: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS2

Bit 2: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS3

Bit 3: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS4

Bit 4: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS5

Bit 5: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS6

Bit 6: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS7

Bit 7: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS8

Bit 8: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS9

Bit 9: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS10

Bit 10: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS11

Bit 11: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS12

Bit 12: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS13

Bit 13: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS14

Bit 14: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS15

Bit 15: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS16

Bit 16: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS17

Bit 17: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS18

Bit 18: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS19

Bit 19: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS20

Bit 20: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS21

Bit 21: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS22

Bit 22: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS23

Bit 23: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS24

Bit 24: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS25

Bit 25: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS26

Bit 26: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS27

Bit 27: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FAFIFO

Filter associated FIFO register

Offset: 0x214, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FAF27
rw 		FAF26
rw 		FAF25
rw 		FAF24
rw 		FAF23
rw 		FAF22
rw 		FAF21
rw 		FAF20
rw 		FAF19
rw 		FAF18
rw 		FAF17
rw 		FAF16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAF15
rw 		FAF14
rw 		FAF13
rw 		FAF12
rw 		FAF11
rw 		FAF10
rw 		FAF9
rw 		FAF8
rw 		FAF7
rw 		FAF6
rw 		FAF5
rw 		FAF4
rw 		FAF3
rw 		FAF2
rw 		FAF1
rw 		FAF0
rw
Toggle Fields.

FAF0

Bit 0: Filter 0 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF1

Bit 1: Filter 1 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF2

Bit 2: Filter 2 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF3

Bit 3: Filter 3 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF4

Bit 4: Filter 4 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF5

Bit 5: Filter 5 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF6

Bit 6: Filter 6 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF7

Bit 7: Filter 7 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF8

Bit 8: Filter 8 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF9

Bit 9: Filter 9 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF10

Bit 10: Filter 10 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF11

Bit 11: Filter 11 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF12

Bit 12: Filter 12 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF13

Bit 13: Filter 13 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF14

Bit 14: Filter 14 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF15

Bit 15: Filter 15 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF16

Bit 16: Filter 16 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF17

Bit 17: Filter 17 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF18

Bit 18: Filter 18 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF19

Bit 19: Filter 19 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF20

Bit 20: Filter 20 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF21

Bit 21: Filter 21 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF22

Bit 22: Filter 22 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF23

Bit 23: Filter 23 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF24

Bit 24: Filter 24 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF25

Bit 25: Filter 25 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF26

Bit 26: Filter 26 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF27

Bit 27: Filter 27 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FW

Filter working register

Offset: 0x21C, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FW27
rw 		FW26
rw 		FW25
rw 		FW24
rw 		FW23
rw 		FW22
rw 		FW21
rw 		FW20
rw 		FW19
rw 		FW18
rw 		FW17
rw 		FW16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FW15
rw 		FW14
rw 		FW13
rw 		FW12
rw 		FW11
rw 		FW10
rw 		FW9
rw 		FW8
rw 		FW7
rw 		FW6
rw 		FW5
rw 		FW4
rw 		FW3
rw 		FW2
rw 		FW1
rw 		FW0
rw
Toggle Fields.

FW0

Bit 0: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW1

Bit 1: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW2

Bit 2: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW3

Bit 3: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW4

Bit 4: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW5

Bit 5: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW6

Bit 6: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW7

Bit 7: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW8

Bit 8: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW9

Bit 9: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW10

Bit 10: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW11

Bit 11: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW12

Bit 12: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW13

Bit 13: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW14

Bit 14: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW15

Bit 15: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW16

Bit 16: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW17

Bit 17: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW18

Bit 18: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW19

Bit 19: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW20

Bit 20: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW21

Bit 21: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW22

Bit 22: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW23

Bit 23: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW24

Bit 24: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW25

Bit 25: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW26

Bit 26: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW27

Bit 27: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

F0DATA0

Filter 0 data 0 register

Offset: 0x240, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F0DATA1

Filter 0 data 1 register

Offset: 0x244, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F1DATA0

Filter 1 data 0 register

Offset: 0x248, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F1DATA1

Filter 1 data 1 register

Offset: 0x24C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F2DATA0

Filter 2 data 0 register

Offset: 0x250, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F2DATA1

Filter 2 data 1 register

Offset: 0x254, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F3DATA0

Filter 3 data 0 register

Offset: 0x258, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F3DATA1

Filter 3 data 1 register

Offset: 0x25C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F4DATA0

Filter 4 data 0 register

Offset: 0x260, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F4DATA1

Filter 4 data 1 register

Offset: 0x264, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F5DATA0

Filter 5 data 0 register

Offset: 0x268, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F5DATA1

Filter 5 data 1 register

Offset: 0x26C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F6DATA0

Filter 6 data 0 register

Offset: 0x270, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F6DATA1

Filter 6 data 1 register

Offset: 0x274, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F7DATA0

Filter 7 data 0 register

Offset: 0x278, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F7DATA1

Filter 7 data 1 register

Offset: 0x27C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F8DATA0

Filter 8 data 0 register

Offset: 0x280, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F8DATA1

Filter 8 data 1 register

Offset: 0x284, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F9DATA0

Filter 9 data 0 register

Offset: 0x288, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F9DATA1

Filter 9 data 1 register

Offset: 0x28C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F10DATA0

Filter 10 data 0 register

Offset: 0x290, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F10DATA1

Filter 10 data 1 register

Offset: 0x294, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F11DATA0

Filter 11 data 0 register

Offset: 0x298, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F11DATA1

Filter 11 data 1 register

Offset: 0x29C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F12DATA0

Filter 12 data 0 register

Offset: 0x2A0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F12DATA1

Filter 12 data 1 register

Offset: 0x2A4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F13DATA0

Filter 13 data 0 register

Offset: 0x2A8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F13DATA1

Filter 13 data 1 register

Offset: 0x2AC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F14DATA0

Filter 14 data 0 register

Offset: 0x2B0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F14DATA1

Filter 14 data 1 register

Offset: 0x2B4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F15DATA0

Filter 15 data 0 register

Offset: 0x2B8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F15DATA1

Filter 15 data 1 register

Offset: 0x2BC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F16DATA0

Filter 16 data 0 register

Offset: 0x2C0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F16DATA1

Filter 16 data 1 register

Offset: 0x2C4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F17DATA0

Filter 17 data 0 register

Offset: 0x2C8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F17DATA1

Filter 17 data 1 register

Offset: 0x2CC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F18DATA0

Filter 18 data 0 register

Offset: 0x2D0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F18DATA1

Filter 18 data 1 register

Offset: 0x2D4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F19DATA0

Filter 19 data 0 register

Offset: 0x2D8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F19DATA1

Filter 19 data 1 register

Offset: 0x2DC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F20DATA0

Filter 20 data 0 register

Offset: 0x2E0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F20DATA1

Filter 20 data 1 register

Offset: 0x2E4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F21DATA0

Filter 21 data 0 register

Offset: 0x2E8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F21DATA1

Filter 21 data 1 register

Offset: 0x2EC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F22DATA0

Filter 22 data 0 register

Offset: 0x2F0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F22DATA1

Filter 22 data 1 register

Offset: 0x2F4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F23DATA0

Filter 23 data 0 register

Offset: 0x2F8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F23DATA1

Filter 23 data 1 register

Offset: 0x2FC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F24DATA0

Filter 24 data 0 register

Offset: 0x300, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F24DATA1

Filter 24 data 1 register

Offset: 0x304, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F25DATA0

Filter 25 data 0 register

Offset: 0x308, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F25DATA1

Filter 25 data 1 register

Offset: 0x30C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F26DATA0

Filter 26 data 0 register

Offset: 0x310, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F26DATA1

Filter 26 data 1 register

Offset: 0x314, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F27DATA0

Filter 27 data 0 register

Offset: 0x318, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F27DATA1

Filter 27 data 1 register

Offset: 0x31C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

CRC

0x40023000: CRC calculation unit

3/3 fields covered. Toggle Registers.

DATA

Data register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: CRC calculation result bits.

Allowed values: 0-4294967295

FDATA

Independent Data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDATA
rw
Toggle Fields.

FDATA

Bits 0-7: Free Data Register bits.

Allowed values: 0-255

CTL

Control register

Offset: 0x8, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RST
w
Toggle Fields.

RST

Bit 0: Reset bit.

Allowed values:
1: Reset: Resets the DATA register to IDATA, with no effect on FDATA

DAC

0x40007400: Digital to analog converter

26/30 fields covered. Toggle Registers.

CTL

control register

Offset: 0x0, reset: 0x00000000, access: read-write

10/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DDMAEN1
rw 		DWBW1
rw 		DWM1
rw 		DTSEL1
rw 		DTEN1
rw 		DBOFF1
rw 		DEN1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDMAEN0
rw 		DWBW0
rw 		DWM0
rw 		DTSEL0
rw 		DTEN0
rw 		DBOFF0
rw 		DEN0
rw
Toggle Fields.

DEN0

Bit 0: DAC0 enable.

Allowed values:
0: Disabled: DAC channel disabled
1: Enabled: DAC channel enabled

DBOFF0

Bit 1: DAC0 output buffer turn off.

Allowed values:
0: Enabled: DAC X output buffer enabled
1: Disabled: DAC X output buffer disabled

DTEN0

Bit 2: DAC0 trigger enable.

Allowed values:
0: Disabled: DAC trigger disabled
1: Enabled: DAC trigger enabled

DTSEL0

Bits 3-5: DAC0 trigger selection.

Allowed values:
0: TIMER5_TRGO: Timer 5 TRGO event
1: TIMER2_TRGO: Timer 2 TRGO event
3: TIMER14_TRGO: Timer 14 TRGO event
4: TIMER1_TRGO: Timer 1 TRGO event
6: EXTERNAL9: External line9
7: SOFTWARE: Software trigger

DWM0

Bits 6-7: DAC0 noise wave mode.

DWBW0

Bits 8-11: DAC0 noise wave bit width.

DDMAEN0

Bit 12: DAC0 DMA enable.

Allowed values:
0: Disabled: DAC DMA mode disabled
1: Enabled: DAC DMA mode enabled

DEN1

Bit 16: DAC1 enable.

Allowed values:
0: Disabled: DAC channel disabled
1: Enabled: DAC channel enabled

DBOFF1

Bit 17: DAC1 output buffer turn off.

Allowed values:
0: Enabled: DAC X output buffer enabled
1: Disabled: DAC X output buffer disabled

DTEN1

Bit 18: DAC1 trigger enable.

Allowed values:
0: Disabled: DAC trigger disabled
1: Enabled: DAC trigger enabled

DTSEL1

Bits 19-21: DAC1 trigger selection.

Allowed values:
0: TIMER5_TRGO: Timer 5 TRGO event
1: TIMER2_TRGO: Timer 2 TRGO event
3: TIMER14_TRGO: Timer 14 TRGO event
4: TIMER1_TRGO: Timer 1 TRGO event
6: EXTERNAL9: External line9
7: SOFTWARE: Software trigger

DWM1

Bits 22-23: DAC1 noise wave mode.

DWBW1

Bits 24-27: DAC1 noise wave bit width.

DDMAEN1

Bit 28: DAC1 DMA enable.

Allowed values:
0: Disabled: DAC DMA mode disabled
1: Enabled: DAC DMA mode enabled

SWT

software trigger register

Offset: 0x4, reset: 0x00000000, access: write-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTR1
w 		SWTR0
w
Toggle Fields.

SWTR0

Bit 0: DAC0 software trigger.

Allowed values:
0: Disabled: DAC channel X software trigger disabled
1: Enabled: DAC channel X software trigger enabled

SWTR1

Bit 1: DAC1 software trigger.

Allowed values:
0: Disabled: DAC channel X software trigger disabled
1: Enabled: DAC channel X software trigger enabled

DAC0_R12DH

DAC0 12-bit right-aligned data holding register

Offset: 0x8, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC0_DH
rw
Toggle Fields.

DAC0_DH

Bits 0-11: DAC0 12-bit right-aligned data.

Allowed values: 0-4095

DAC0_L12DH

DAC0 12-bit left-aligned data holding register

Offset: 0xC, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC0_DH
rw
Toggle Fields.

DAC0_DH

Bits 4-15: DAC0 12-bit left-aligned data.

Allowed values: 0-4095

DAC0_R8DH

DAC0 8-bit right aligned data holding register

Offset: 0x10, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC0_DH
rw
Toggle Fields.

DAC0_DH

Bits 0-7: DAC0 8-bit right-aligned data.

Allowed values: 0-255

DAC1_R12DH

DAC1 12-bit right-aligned data holding register

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC1_DH
rw
Toggle Fields.

DAC1_DH

Bits 0-11: DAC1 12-bit right-aligned data.

Allowed values: 0-4095

DAC1_L12DH

DAC1 12-bit left aligned data holding register

Offset: 0x18, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC1_DH
rw
Toggle Fields.

DAC1_DH

Bits 4-15: DAC1 12-bit left-aligned data.

Allowed values: 0-4095

DAC1_R8DH

DAC1 8-bit right aligned data holding register

Offset: 0x1C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC1_DH
rw
Toggle Fields.

DAC1_DH

Bits 0-7: DAC1 8-bit right-aligned data.

Allowed values: 0-255

DACC_R12DH

DAC concurrent mode 12-bit right-aligned data holding register

Offset: 0x20, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAC1_DH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC0_DH
rw
Toggle Fields.

DAC0_DH

Bits 0-11: DAC0 12-bit right-aligned data.

Allowed values: 0-4095

DAC1_DH

Bits 16-27: DAC1 12-bit right-aligned data.

Allowed values: 0-4095

DACC_L12DH

DAC concurrent mode 12-bit left aligned data holding register

Offset: 0x24, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAC1_DH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC0_DH
rw
Toggle Fields.

DAC0_DH

Bits 4-15: DAC0 12-bit left-aligned data.

Allowed values: 0-4095

DAC1_DH

Bits 20-31: DAC1 12-bit left-aligned data.

Allowed values: 0-4095

DACC_R8DH

DAC concurrent mode 8-bit right aligned data holding register

Offset: 0x28, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC1_DH
rw 		DAC0_DH
rw
Toggle Fields.

DAC0_DH

Bits 0-7: DAC0 8-bit right-aligned data.

Allowed values: 0-255

DAC1_DH

Bits 8-15: DAC1 8-bit right-aligned data.

Allowed values: 0-255

DAC0_DO

DAC0 data output register

Offset: 0x2C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC0_DO
r
Toggle Fields.

DAC0_DO

Bits 0-11: DAC0 data output.

Allowed values: 0-4095

DAC1_DO

DAC1 data output register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC1_DO
r
Toggle Fields.

DAC1_DO

Bits 0-11: DAC1 data output.

Allowed values: 0-4095

DBG

0xE0042000: Debug support

24/26 fields covered. Toggle Registers.

ID

ID code register

Offset: 0x0, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID_CODE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID_CODE
r
Toggle Fields.

ID_CODE

Bits 0-31: DBG ID code register.

Allowed values: 0-4294967295

CTL0

Control register

Offset: 0x4, reset: 0x00000000, access: read-write

23/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIMER10_HOLD
rw 		TIMER9_HOLD
rw 		TIMER8_HOLD
rw 		TIMER13_HOLD
rw 		TIMER12_HOLD
rw 		TIMER11_HOLD
rw 		CAN1_HOLD
rw 		TIMER7_HOLD
rw 		TIMER6_HOLD
rw 		TIMER5_HOLD
rw 		TIMER4_HOLD
rw 		I2C1_HOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C0_HOLD
rw 		CAN0_HOLD
rw 		TIMER3_HOLD
rw 		TIMER2_HOLD
rw 		TIMER1_HOLD
rw 		TIMER0_HOLD
rw 		WWDGT_HOLD
rw 		FWDGT_HOLD
rw 		TRACE_MODE
rw 		TRACE_IOEN
rw 		STB_HOLD
rw 		DSLP_HOLD
rw 		SLP_HOLD
rw
Toggle Fields.

SLP_HOLD

Bit 0: Sleep mode hold register.

Allowed values:
0: Disabled: No effect
1: Enabled: In sleep mode the AHB clock is on

DSLP_HOLD

Bit 1: Deep-sleep mode hold register.

Allowed values:
0: Disabled: No effect
1: Enabled: In deep-sleep mode the AHB clock and system clock are provided by IRC8M

STB_HOLD

Bit 2: Standby mode hold register.

Allowed values:
0: Disabled: No effect
1: Enabled: In standby mode the AHB clock and system clock are provided by IRC8M

TRACE_IOEN

Bit 5: Trace pin allocation enable.

TRACE_MODE

Bits 6-7: Trace pin allocation mode.

FWDGT_HOLD

Bit 8: FWDGT hold bit.

Allowed values:
0: Continue: Continue running the watchdog timer as usual
1: Stop: Hold the watchdog timer for debug when the core is halted

WWDGT_HOLD

Bit 9: WWDGT hold bit.

Allowed values:
0: Continue: Continue running the watchdog timer as usual
1: Stop: Hold the watchdog timer for debug when the core is halted

TIMER0_HOLD

Bit 10: TIMER 0 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER1_HOLD

Bit 11: TIMER 1 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER2_HOLD

Bit 12: TIMER 2 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER3_HOLD

Bit 13: TIMER 23 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

CAN0_HOLD

Bit 14: CAN0 hold bit.

Allowed values:
0: Continue: Continue running CAN as usual
1: Stop: Hold the CAN for debug when the core is halted

I2C0_HOLD

Bit 15: I2C0 hold bit.

Allowed values:
0: Continue: Continue running I2C as usual
1: Stop: Hold the I2C timeout for debug when the core is halted

I2C1_HOLD

Bit 16: I2C1 hold bit.

Allowed values:
0: Continue: Continue running I2C as usual
1: Stop: Hold the I2C timeout for debug when the core is halted

TIMER4_HOLD

Bit 17: TIMER 4 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER5_HOLD

Bit 18: TIMER 5 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER6_HOLD

Bit 19: TIMER 6 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER7_HOLD

Bit 20: TIMER 7 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

CAN1_HOLD

Bit 21: CAN1 hold bit.

Allowed values:
0: Continue: Continue running CAN as usual
1: Stop: Hold the CAN for debug when the core is halted

TIMER11_HOLD

Bit 25: TIMER 11 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER12_HOLD

Bit 26: TIMER 12 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER13_HOLD

Bit 27: TIMER 13 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER8_HOLD

Bit 28: TIMER 8 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER9_HOLD

Bit 29: TIMER 9 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER10_HOLD

Bit 30: TIMER 10 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

DCI

0x50050000: Digital Camera Interface

17/50 fields covered. Toggle Registers.

CTL

DCI Control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCIEN
rw 		DCIF
rw 		FR
rw 		VPS
rw 		HPS
rw 		CKS
rw 		ESM
rw 		JM
rw 		WDEN
rw 		SNAP
rw 		CAP
rw
Toggle Fields.

CAP

Bit 0: Capture Enable.

SNAP

Bit 1: Snapshot mode.

WDEN

Bit 2: Window Enable.

JM

Bit 3: JPEG mode.

ESM

Bit 4: Embedded synchronous mode.

CKS

Bit 5: Clock Polarity Selection.

HPS

Bit 6: Horizontal Polarity Selection.

VPS

Bit 7: Vertical Polarity Selection.

FR

Bits 8-9: Frame rate.

DCIF

Bits 10-11: Digital camera interface format.

DCIEN

Bit 14: DCI Enable.

STAT0

DCI Status register 0

Offset: 0x4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FV
r 		VS
r 		HS
r
Toggle Fields.

HS

Bit 0: HS line status.

VS

Bit 1: VS line status.

FV

Bit 2: FIFO Valid.

STAT1

DCI Status register1

Offset: 0x8, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ELF
r 		VSF
r 		ESEF
r 		OVRF
r 		EFF
r
Toggle Fields.

EFF

Bit 0: End of Frame Flag.

OVRF

Bit 1: FIFO Overrun flag.

ESEF

Bit 2: Embedded Synchronous Error Flag.

VSF

Bit 3: Vsync Flag.

ELF

Bit 4: End of line flag.

INTEN

DCI inrerrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ELIE
rw 		VSIE
rw 		ESEIE
rw 		OVRIE
rw 		EFIE
rw
Toggle Fields.

EFIE

Bit 0: End of Frame Interrupt Enable.

OVRIE

Bit 1: FIFO Overrun interrupt Enable.

ESEIE

Bit 2: Embedded Synchronous Error Interrupt Enable.

VSIE

Bit 3: Vsync Interrupt Enable.

ELIE

Bit 4: End of line interrupt Enable.

INTF

DCI Interrupt flag register

Offset: 0x10, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ELIF
r 		VSIF
r 		ESEIF
r 		OVRIF
r 		EFIF
r
Toggle Fields.

EFIF

Bit 0: End of Frame Interrupt Flag.

OVRIF

Bit 1: FIFO Overrun Interrupt Flag.

ESEIF

Bit 2: Embedded Synchronous Error Interrupt Flag.

VSIF

Bit 3: Vsync Interrupt Flag.

ELIF

Bit 4: End of Line Interrupt Flag.

INTC

DCI Interrupt flag clear register

Offset: 0x14, reset: 0x00000000, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ELFC
w 		VSFC
w 		ESEFC
w 		OVRFC
w 		EFFC
w
Toggle Fields.

EFFC

Bit 0: Clear End of Frame Flag.

OVRFC

Bit 1: Clear FIFO Overrun Flag.

ESEFC

Bit 2: Clear embedded synchronous Error Flag.

VSFC

Bit 3: Vsync flag clear.

ELFC

Bit 4: End of Line Flag Clear.

SC

DCI Synchronization codes register

Offset: 0x18, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FE
rw 		LE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LS
rw 		FS
rw
Toggle Fields.

FS

Bits 0-7: Frame start code in embedded synchronous mode.

LS

Bits 8-15: Line start code in embedded synchronous mode.

LE

Bits 16-23: Line end code in embedded synchronous mode.

FE

Bits 24-31: Frame end code in embedded synchronous mode.

SCUMSK

DCI Synchronization codes unmask register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEM
rw 		LEM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSM
rw 		FSM
rw
Toggle Fields.

FSM

Bits 0-7: Frame start code mask bits in embedded synchronous mode.

LSM

Bits 8-15: Line start code mask bits in embedded synchronous mode.

LEM

Bits 16-23: Line end code mask bits in embedded synchronous mode.

FEM

Bits 24-31: Frame end code mask bits in embedded synchronous mode.

CWSPOS

DCI Cropping window start position register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WVSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WHSP
rw
Toggle Fields.

WHSP

Bits 0-13: Window horizontal start position.

WVSP

Bits 16-28: Window Vertical start position.

CWSZ

DCI Cropping window size register

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WVSZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WHSZ
rw
Toggle Fields.

WHSZ

Bits 0-13: Window horizontal Size.

WVSZ

Bits 16-29: Window Vertical Size.

DATA

DCI DATA register

Offset: 0x28, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DT3
r 		DT2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DT1
r 		DT0
r
Toggle Fields.

DT0

Bits 0-7: Pixel Data 0.

DT1

Bits 8-15: Pixel Data 1.

DT2

Bits 16-23: Pixel Data 2.

DT3

Bits 24-31: Pixel Data 3 .

DMA0

0x40020000: DMA controller

147/161 fields covered. Toggle Registers.

INTF

Interrupt flag register

Offset: 0x0, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERRIF6
r 		HTFIF6
r 		FTFIF6
r 		GIF6
r 		ERRIF5
r 		HTFIF5
r 		FTFIF5
r 		GIF5
r 		ERRIF4
r 		HTFIF4
r 		FTFIF4
r 		GIF4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIF3
r 		HTFIF3
r 		FTFIF3
r 		GIF3
r 		ERRIF2
r 		HTFIF2
r 		FTFIF2
r 		GIF2
r 		ERRIF1
r 		HTFIF1
r 		FTFIF1
r 		GIF1
r 		ERRIF0
r 		HTFIF0
r 		FTFIF0
r 		GIF0
r
Toggle Fields.

GIF0

Bit 0: Global interrupt flag of channel 0.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF0

Bit 1: Full Transfer finish flag of channe 0.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF0

Bit 2: Half transfer finish flag of channel 0.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF0

Bit 3: Error flag of channel 0.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF1

Bit 4: Global interrupt flag of channel 1.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF1

Bit 5: Full Transfer finish flag of channe 1.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF1

Bit 6: Half transfer finish flag of channel 1.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF1

Bit 7: Error flag of channel 1.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF2

Bit 8: Global interrupt flag of channel 2.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF2

Bit 9: Full Transfer finish flag of channe 2.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF2

Bit 10: Half transfer finish flag of channel 2.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF2

Bit 11: Error flag of channel 2.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF3

Bit 12: Global interrupt flag of channel 3.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF3

Bit 13: Full Transfer finish flag of channe 3.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF3

Bit 14: Half transfer finish flag of channel 3.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF3

Bit 15: Error flag of channel 3.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF4

Bit 16: Global interrupt flag of channel 4.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF4

Bit 17: Full Transfer finish flag of channe 4.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF4

Bit 18: Half transfer finish flag of channel 4.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF4

Bit 19: Error flag of channel 4.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF5

Bit 20: Global interrupt flag of channel 5.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF5

Bit 21: Full Transfer finish flag of channe 5.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF5

Bit 22: Half transfer finish flag of channel 5.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF5

Bit 23: Error flag of channel 5.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF6

Bit 24: Global interrupt flag of channel 6.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF6

Bit 25: Full Transfer finish flag of channe 6.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF6

Bit 26: Half transfer finish flag of channel 6.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF6

Bit 27: Error flag of channel 6.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

INTC

Interrupt flag clear register

Offset: 0x4, reset: 0x00000000, access: write-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERRIFC6
w 		HTFIFC6
w 		FTFIFC6
w 		GIFC6
w 		ERRIFC5
w 		HTFIFC5
w 		FTFIFC5
w 		GIFC5
w 		ERRIFC4
w 		HTFIFC4
w 		FTFIFC4
w 		GIFC4
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIFC3
w 		HTFIFC3
w 		FTFIFC3
w 		GIFC3
w 		ERRIFC2
w 		HTFIFC2
w 		FTFIFC2
w 		GIFC2
w 		ERRIFC1
w 		HTFIFC1
w 		FTFIFC1
w 		GIFC1
w 		ERRIFC0
w 		HTFIFC0
w 		FTFIFC0
w 		GIFC0
w
Toggle Fields.

GIFC0

Bit 0: Clear global interrupt flag of channel 0.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC0

Bit 1: Clear bit for full transfer finish flag of channel 0.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC0

Bit 2: Clear bit for half transfer finish flag of channel 0.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC0

Bit 3: Clear bit for error flag of channel 0.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC1

Bit 4: Clear global interrupt flag of channel 1.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC1

Bit 5: Clear bit for full transfer finish flag of channel 1.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC1

Bit 6: Clear bit for half transfer finish flag of channel 1.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC1

Bit 7: Clear bit for error flag of channel 1.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC2

Bit 8: Clear global interrupt flag of channel 2.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC2

Bit 9: Clear bit for full transfer finish flag of channel 2.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC2

Bit 10: Clear bit for half transfer finish flag of channel 2.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC2

Bit 11: Clear bit for error flag of channel 2.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC3

Bit 12: Clear global interrupt flag of channel 3.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC3

Bit 13: Clear bit for full transfer finish flag of channel 3.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC3

Bit 14: Clear bit for half transfer finish flag of channel 3.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC3

Bit 15: Clear bit for error flag of channel 3.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC4

Bit 16: Clear global interrupt flag of channel 4.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC4

Bit 17: Clear bit for full transfer finish flag of channel 4.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC4

Bit 18: Clear bit for half transfer finish flag of channel 4.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC4

Bit 19: Clear bit for error flag of channel 4.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC5

Bit 20: Clear global interrupt flag of channel 5.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC5

Bit 21: Clear bit for full transfer finish flag of channel 5.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC5

Bit 22: Clear bit for half transfer finish flag of channel 5.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC5

Bit 23: Clear bit for error flag of channel 5.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC6

Bit 24: Clear global interrupt flag of channel 6.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC6

Bit 25: Clear bit for full transfer finish flag of channel 6.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC6

Bit 26: Clear bit for half transfer finish flag of channel 6.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC6

Bit 27: Clear bit for error flag of channel 6.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

CH0CTL

Channel 0 control register

Offset: 0x8, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH0CNT

Channel 0 counter register

Offset: 0xC, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH0PADDR

Channel 0 peripheral base address register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH0MADDR

Channel 0 memory base address register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH1CTL

Channel 1 control register

Offset: 0x1C, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH1CNT

Channel 1 counter register

Offset: 0x20, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH1PADDR

Channel 1 peripheral base address register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH1MADDR

Channel 1 memory base address register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH2CTL

Channel 2 control register

Offset: 0x30, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH2CNT

Channel 2 counter register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH2PADDR

Channel 2 peripheral base address register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH2MADDR

Channel 2 memory base address register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH3CTL

Channel 3 control register

Offset: 0x44, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH3CNT

Channel 3 counter register

Offset: 0x48, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH3PADDR

Channel 3 peripheral base address register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH3MADDR

Channel 3 memory base address register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH4CTL

Channel 4 control register

Offset: 0x58, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH4CNT

Channel 4 counter register

Offset: 0x5C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH4PADDR

Channel 4 peripheral base address register

Offset: 0x60, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH4MADDR

Channel 4 memory base address register

Offset: 0x64, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH5CTL

Channel 5 control register

Offset: 0x6C, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH5CNT

Channel 5 counter register

Offset: 0x70, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH5PADDR

Channel 5 peripheral base address register

Offset: 0x74, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH5MADDR

Channel 5 memory base address register

Offset: 0x78, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH6CTL

Channel 6 control register

Offset: 0x80, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH6CNT

Channel 6 counter register

Offset: 0x84, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH6PADDR

Channel 6 peripheral base address register

Offset: 0x88, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH6MADDR

Channel 6 memory base address register

Offset: 0x8C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

DMA1

0x40020400: DMA controller

147/162 fields covered. Toggle Registers.

INTF

Interrupt flag register

Offset: 0x0, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERRIF6
r 		HTFIF6
r 		FTFIF6
r 		GIF6
r 		ERRIF5
r 		HTFIF5
r 		FTFIF5
r 		GIF5
r 		ERRIF4
r 		HTFIF4
r 		FTFIF4
r 		GIF4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIF3
r 		HTFIF3
r 		FTFIF3
r 		GIF3
r 		ERRIF2
r 		HTFIF2
r 		FTFIF2
r 		GIF2
r 		ERRIF1
r 		HTFIF1
r 		FTFIF1
r 		GIF1
r 		ERRIF0
r 		HTFIF0
r 		FTFIF0
r 		GIF0
r
Toggle Fields.

GIF0

Bit 0: Global interrupt flag of channel 0.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF0

Bit 1: Full Transfer finish flag of channe 0.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF0

Bit 2: Half transfer finish flag of channel 0.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF0

Bit 3: Error flag of channel 0.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF1

Bit 4: Global interrupt flag of channel 1.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF1

Bit 5: Full Transfer finish flag of channe 1.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF1

Bit 6: Half transfer finish flag of channel 1.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF1

Bit 7: Error flag of channel 1.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF2

Bit 8: Global interrupt flag of channel 2.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF2

Bit 9: Full Transfer finish flag of channe 2.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF2

Bit 10: Half transfer finish flag of channel 2.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF2

Bit 11: Error flag of channel 2.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF3

Bit 12: Global interrupt flag of channel 3.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF3

Bit 13: Full Transfer finish flag of channe 3.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF3

Bit 14: Half transfer finish flag of channel 3.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF3

Bit 15: Error flag of channel 3.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF4

Bit 16: Global interrupt flag of channel 4.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF4

Bit 17: Full Transfer finish flag of channe 4.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF4

Bit 18: Half transfer finish flag of channel 4.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF4

Bit 19: Error flag of channel 4.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF5

Bit 20: Global interrupt flag of channel 5.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF5

Bit 21: Full Transfer finish flag of channe 5.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF5

Bit 22: Half transfer finish flag of channel 5.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF5

Bit 23: Error flag of channel 5.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF6

Bit 24: Global interrupt flag of channel 6.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF6

Bit 25: Full Transfer finish flag of channe 6.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF6

Bit 26: Half transfer finish flag of channel 6.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF6

Bit 27: Error flag of channel 6.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

INTC

Interrupt flag clear register

Offset: 0x4, reset: 0x00000000, access: write-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERRIFC6
w 		HTFIFC6
w 		FTFIFC6
w 		GIFC6
w 		ERRIFC5
w 		HTFIFC5
w 		FTFIFC5
w 		GIFC5
w 		ERRIFC4
w 		HTFIFC4
w 		FTFIFC4
w 		GIFC4
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIFC3
w 		HTFIFC3
w 		FTFIFC3
w 		GIFC3
w 		ERRIFC2
w 		HTFIFC2
w 		FTFIFC2
w 		GIFC2
w 		ERRIFC1
w 		HTFIFC1
w 		FTFIFC1
w 		GIFC1
w 		ERRIFC0
w 		HTFIFC0
w 		FTFIFC0
w 		GIFC0
w
Toggle Fields.

GIFC0

Bit 0: Clear global interrupt flag of channel 0.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC0

Bit 1: Clear bit for full transfer finish flag of channel 0.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC0

Bit 2: Clear bit for half transfer finish flag of channel 0.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC0

Bit 3: Clear bit for error flag of channel 0.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC1

Bit 4: Clear global interrupt flag of channel 1.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC1

Bit 5: Clear bit for full transfer finish flag of channel 1.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC1

Bit 6: Clear bit for half transfer finish flag of channel 1.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC1

Bit 7: Clear bit for error flag of channel 1.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC2

Bit 8: Clear global interrupt flag of channel 2.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC2

Bit 9: Clear bit for full transfer finish flag of channel 2.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC2

Bit 10: Clear bit for half transfer finish flag of channel 2.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC2

Bit 11: Clear bit for error flag of channel 2.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC3

Bit 12: Clear global interrupt flag of channel 3.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC3

Bit 13: Clear bit for full transfer finish flag of channel 3.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC3

Bit 14: Clear bit for half transfer finish flag of channel 3.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC3

Bit 15: Clear bit for error flag of channel 3.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC4

Bit 16: Clear global interrupt flag of channel 4.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC4

Bit 17: Clear bit for full transfer finish flag of channel 4.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC4

Bit 18: Clear bit for half transfer finish flag of channel 4.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC4

Bit 19: Clear bit for error flag of channel 4.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC5

Bit 20: Clear global interrupt flag of channel 5.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC5

Bit 21: Clear bit for full transfer finish flag of channel 5.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC5

Bit 22: Clear bit for half transfer finish flag of channel 5.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC5

Bit 23: Clear bit for error flag of channel 5.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC6

Bit 24: Clear global interrupt flag of channel 6.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC6

Bit 25: Clear bit for full transfer finish flag of channel 6.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC6

Bit 26: Clear bit for half transfer finish flag of channel 6.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC6

Bit 27: Clear bit for error flag of channel 6.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

CH0CTL

Channel 0 control register

Offset: 0x8, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH0CNT

Channel 0 counter register

Offset: 0xC, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH0PADDR

Channel 0 peripheral base address register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH0MADDR

Channel 0 memory base address register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH1CTL

Channel 1 control register

Offset: 0x1C, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH1CNT

Channel 1 counter register

Offset: 0x20, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH1PADDR

Channel 1 peripheral base address register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH1MADDR

Channel 1 memory base address register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH2CTL

Channel 2 control register

Offset: 0x30, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH2CNT

Channel 2 counter register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH2PADDR

Channel 2 peripheral base address register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH2MADDR

Channel 2 memory base address register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH3CTL

Channel 3 control register

Offset: 0x44, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH3CNT

Channel 3 counter register

Offset: 0x48, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH3PADDR

Channel 3 peripheral base address register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH3MADDR

Channel 3 memory base address register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH4CTL

Channel 4 control register

Offset: 0x58, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH4CNT

Channel 4 counter register

Offset: 0x5C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH4PADDR

Channel 4 peripheral base address register

Offset: 0x60, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH4MADDR

Channel 4 memory base address register

Offset: 0x64, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH5CTL

Channel 5 control register

Offset: 0x6C, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH5CNT

Channel 5 counter register

Offset: 0x70, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH5PADDR

Channel 5 peripheral base address register

Offset: 0x74, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH5MADDR

Channel 5 memory base address register

Offset: 0x78, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH6CTL

Channel 6 control register

Offset: 0x80, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH6CNT

Channel 6 counter register

Offset: 0x84, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH6PADDR

Channel 6 peripheral base address register

Offset: 0x88, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH6MADDR

Channel 6 memory base address register

Offset: 0x8C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

ACFG

DMA additional configuration register

Offset: 0x300, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD_CH5EN
rw
Toggle Fields.

FD_CH5EN

Bit 5: Enable bit for channel 5 Full_Data transfer mode.

ENET_DMA

0x40029000: Ethernet: DMA controller operation

13/69 fields covered. Toggle Registers.

DMA_BCTL

Ethernet DMA bus control register

Offset: 0x0, reset: 0x00002101, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AA
rw 		FPBL
rw 		UIP
rw 		RXDP
rw 		FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTPR
rw 		PGBL
rw 		DPSL
rw 		DAB
rw 		SWR
rw
Toggle Fields.

SWR

Bit 0: Software reset.

DAB

Bit 1: DMA Arbitration.

DPSL

Bits 2-6: Descriptor skip length.

PGBL

Bits 8-13: Programmable burst length.

RTPR

Bits 14-15: RxDMA and TxDMA transfer priority ratio.

FB

Bit 16: Fixed burst.

RXDP

Bits 17-22: Rx DMA PGBL.

UIP

Bit 23: Use independent PGBL.

FPBL

Bit 24: Four times PGBL mode.

AA

Bit 25: Address-aligned .

DMA_TPEN

Ethernet DMA transmit poll enable register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TPE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPE
rw
Toggle Fields.

TPE

Bits 0-31: Transmit poll enable.

DMA_RPEN

Ethernet DMA receive poll enable register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPE
rw
Toggle Fields.

RPE

Bits 0-31: Receive poll enable.

DMA_RDTADDR

Ethernet DMA receive descriptor table address register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRT
rw
Toggle Fields.

SRT

Bits 0-31: Start address of receive table.

DMA_TDTADDR

Ethernet DMA transmit descriptor table address register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STT
rw
Toggle Fields.

STT

Bits 0-31: Start address of transmit table.

DMA_STAT

Ethernet DMA status register

Offset: 0x14, reset: 0x00000000, access: Unspecified

6/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TST
r 		WUM
r 		MSC
r 		EB
r 		TP
r 		RP
r 		NI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AI
rw 		ER
rw 		FBE
rw 		ET
rw 		RWT
rw 		RPS
rw 		RBU
rw 		RS
rw 		TU
rw 		RO
rw 		TJT
rw 		TBU
rw 		TPS
rw 		TS
rw
Toggle Fields.

TS

Bit 0: Transmit status.

TPS

Bit 1: Transmit process stopped status.

TBU

Bit 2: Transmit buffer unavailable status.

TJT

Bit 3: Transmit jabber timeout status.

RO

Bit 4: Receive overflow status.

TU

Bit 5: Transmit underflow status.

RS

Bit 6: Receive status.

RBU

Bit 7: Receive buffer unavailable status.

RPS

Bit 8: Receive process stopped status.

RWT

Bit 9: Receive watchdog timeout status.

ET

Bit 10: Early transmit status.

FBE

Bit 13: Fatal bus error status.

ER

Bit 14: Early receive status.

AI

Bit 15: Abnormal interrupt summary.

NI

Bit 16: Normal interrupt summary.

RP

Bits 17-19: Receive process state.

TP

Bits 20-22: Transmit process state.

EB

Bits 23-25: Error bits status.

MSC

Bit 27: MSC status.

WUM

Bit 28: WUM status.

TST

Bit 29: Time stamp trigger status.

DMA_CTL

Ethernet DMA control register

Offset: 0x18, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTCERFD
rw 		RSFD
rw 		DAFRF
rw 		TSFD
rw 		FTF
rw 		TTHC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTHC
rw 		STE
rw 		FERF
rw 		FUF
rw 		RTHC
rw 		OSF
rw 		SRE
rw
Toggle Fields.

SRE

Bit 1: Start/stop receive enable.

OSF

Bit 2: Operate on second frame.

RTHC

Bits 3-4: Receive threshold control.

FUF

Bit 6: Forward undersized good frames.

FERF

Bit 7: Forward error frames.

STE

Bit 13: Start/stop transmission enable.

TTHC

Bits 14-16: Transmit threshold control.

FTF

Bit 20: Flush transmit FIFO.

TSFD

Bit 21: Transmit Store-and-Forward.

DAFRF

Bit 24: Disable flushing of received frames.

RSFD

Bit 25: Receive Store-and-Forward.

DTCERFD

Bit 26: Dropping of TCP/IP checksum error frames disable.

DMA_INTEN

Ethernet DMA interrupt enable register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AIE
rw 		ERIE
rw 		FBEIE
rw 		ETIE
rw 		RWTIE
rw 		RPSIE
rw 		RBUIE
rw 		RIE
rw 		TUIE
rw 		ROIE
rw 		TJTIE
rw 		TBUIE
rw 		TPSIE
rw 		TIE
rw
Toggle Fields.

TIE

Bit 0: Transmit interrupt enable.

TPSIE

Bit 1: Transmit process stopped interrupt enable.

TBUIE

Bit 2: Transmit buffer unavailable interrupt enable.

TJTIE

Bit 3: Transmit jabber timeout interrupt enable.

ROIE

Bit 4: Receive overflow interrupt enable.

TUIE

Bit 5: Transmit underflow interrupt enable.

RIE

Bit 6: Receive interrupt enable.

RBUIE

Bit 7: Receive buffer unavailable interrupt enable.

RPSIE

Bit 8: Receive process stopped interrupt enable.

RWTIE

Bit 9: receive watchdog timeout interrupt enable.

ETIE

Bit 10: Early transmit interrupt enable.

FBEIE

Bit 13: Fatal bus error interrupt enable.

ERIE

Bit 14: Early receive interrupt enable.

AIE

Bit 15: Abnormal interrupt summary enable.

NIE

Bit 16: Normal interrupt summary enable.

DMA_MFBOCNT

Ethernet DMA missed frame and buffer overflow counter register

Offset: 0x20, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OBFOC
r 		MSFA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSFC
r
Toggle Fields.

MSFC

Bits 0-15: Missed frames by the controller.

MSFA

Bits 17-27: Missed frames by the application.

OBFOC

Bit 28: Overflow bit for FIFO overflow counter bit.

DMA_CTDADDR

DMA current transmit descriptor address register

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDAP
r
Toggle Fields.

TDAP

Bits 0-31: transmit descriptor address pointer.

DMA_CRDADDR

Ethernet DMA current receive descriptor address register

Offset: 0x4C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDAP
r
Toggle Fields.

RDAP

Bits 0-31: Receive descriptor address pointer.

DMA_CTBADDR

Ethernet DMA current transmit buffer address register

Offset: 0x50, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TBAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBAP
r
Toggle Fields.

TBAP

Bits 0-31: Transmit buffer address pointer.

DMA_CRBADDR

Ethernet DMA current receive buffer address register

Offset: 0x54, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RBAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RBAP
r
Toggle Fields.

RBAP

Bits 0-31: receive buffer address pointer.

ENET_MAC

0x40028000: Ethernet: media access control

5/78 fields covered. Toggle Registers.

MAC_CFG

Ethernet MAC configuration register (MAC_CFG)

Offset: 0x0, reset: 0x00008000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDD
rw 		JBD
rw 		IGBS
rw 		CSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPD
rw 		ROD
rw 		LBM
rw 		DPM
rw 		IPFCO
rw 		RTD
rw 		APCD
rw 		BOL
rw 		DFC
rw 		TEN
rw 		REN
rw
Toggle Fields.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

DFC

Bit 4: Deferral check.

BOL

Bits 5-6: Back-off limit.

APCD

Bit 7: Automatic pad/CRC drop.

RTD

Bit 9: Retry disable.

IPFCO

Bit 10: IP frame checksum offload.

DPM

Bit 11: Duplex mode.

LBM

Bit 12: Loopback mode.

ROD

Bit 13: Receive own disable.

SPD

Bit 14: Fast Ethernet speed.

CSD

Bit 16: Carrier sense disable.

IGBS

Bits 17-19: Inter frame gap bit selection.

JBD

Bit 22: Jabber disable.

WDD

Bit 23: Watchdog disable.

MAC_FRMF

Ethernet MAC frame filter register (MAC_FRMF)

Offset: 0x4, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HPFLT
rw 		SAFLT
rw 		SAIFLT
rw 		PCFRM
rw 		BFRMD
rw 		MFD
rw 		DAIFLT
rw 		HMF
rw 		HUF
rw 		PM
rw
Toggle Fields.

PM

Bit 0: Promiscuous mode.

HUF

Bit 1: Hash unicast filter.

HMF

Bit 2: Hash multicast filter.

DAIFLT

Bit 3: Destination address inverse filtering.

MFD

Bit 4: multicast filter disable.

BFRMD

Bit 5: Broadcast frames disable.

PCFRM

Bits 6-7: Pass control frames.

SAIFLT

Bit 8: Source address inverse filtering.

SAFLT

Bit 9: Source address filter.

HPFLT

Bit 10: Hash or perfect filter.

FAR

Bit 31: Frames all receive.

MAC_HLH

Ethernet MAC hash list high register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HLH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HLH
rw
Toggle Fields.

HLH

Bits 0-31: Hash list high.

MAC_HLL

Ethernet MAC hash list low register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HLL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HLL
rw
Toggle Fields.

HLL

Bits 0-31: Hash list low.

MAC_PHY_CTL

Ethernet MAC PHY control register (MAC_PHY_CTL)

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw 		PR
rw 		CLR
rw 		PW
rw 		PB
rw
Toggle Fields.

PB

Bit 0: PHY busy.

PW

Bit 1: PHY write.

CLR

Bits 2-4: Clock range.

PR

Bits 6-10: PHY register.

PA

Bits 11-15: PHY address.

MAC_PHY_DATA

Ethernet MAC MII data register (MAC_PHY_DATA)

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD
rw
Toggle Fields.

PD

Bits 0-15: PHY data.

MAC_FCTL

Ethernet MAC flow control register (MAC_FCTL)

Offset: 0x18, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DZQP
rw 		PLTS
rw 		UPFDT
rw 		RFCEN
rw 		TFCEN
rw 		FLCB_BKPA
rw
Toggle Fields.

FLCB_BKPA

Bit 0: Flow control busy/back pressure activate.

TFCEN

Bit 1: Transmit flow control enable.

RFCEN

Bit 2: Receive flow control enable.

UPFDT

Bit 3: Unicast pause frame detect.

PLTS

Bits 4-5: Pause low threshold.

DZQP

Bit 7: Disable Zero-quanta pause.

PTM

Bits 16-31: Pause time.

MAC_VLT

Ethernet MAC VLAN tag register (MAC_VLT)

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VLTC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VLTI
rw
Toggle Fields.

VLTI

Bits 0-15: VLAN tag identifier (for receive frames).

VLTC

Bit 16: 12-bit VLAN tag comparison.

MAC_RWFF

Ethernet MAC remote wakeup frame filter register (MAC_RWFF)

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

MAC_WUM

Ethernet MAC wakeup management register (MAC_WUM)

Offset: 0x2C, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUFFRPR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GU
rw 		WUFR
rw 		MPKR
rw 		WFEN
rw 		MPEN
rw 		PWD
rw
Toggle Fields.

PWD

Bit 0: Power down.

MPEN

Bit 1: Magic Packet enable.

WFEN

Bit 2: Wakeup frame enable.

MPKR

Bit 5: Magic packet received.

WUFR

Bit 6: Wakeup frame received.

GU

Bit 9: Global unicast.

WUFFRPR

Bit 31: Wakeup frame filter register pointer reset.

MAC_INTF

Ethernet MAC interrupt flag register (MAC_INTF)

Offset: 0x38, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMST
r 		MSCT
r 		MSCR
r 		MSC
r 		WUM
r
Toggle Fields.

WUM

Bit 3: WUM status.

MSC

Bit 4: MSC status.

MSCR

Bit 5: MSC receive status.

MSCT

Bit 6: MSC transmit status.

TMST

Bit 9: Time stamp trigger status.

MAC_INTMSK

Ethernet MAC interrupt mask register (MAC_INTMSK)

Offset: 0x3C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMSTIM
rw 		WUMIM
rw
Toggle Fields.

WUMIM

Bit 3: WUM interrupt mask.

TMSTIM

Bit 9: Time stamp trigger interrupt mask.

MAC_ADDR0H

Ethernet MAC address 0 high register (MAC_ADDR0H)

Offset: 0x40, reset: 0x8000FFFF, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR0H
rw
Toggle Fields.

ADDR0H

Bits 0-15: MAC address0 high.

MO

Bit 31: Always 1.

MAC_ADDR0L

Ethernet MAC address 0 low register

Offset: 0x44, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR0L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR0L
rw
Toggle Fields.

ADDR0L

Bits 0-31: MAC address0 low.

MAC_ADDR1H

Ethernet MAC address 1 high register (MAC_ADDR1H)

Offset: 0x48, reset: 0x0000FFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFE
rw 		SAF
rw 		MB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR1H
rw
Toggle Fields.

ADDR1H

Bits 0-15: MAC address1 high.

MB

Bits 24-29: Mask byte.

SAF

Bit 30: Source address filter.

AFE

Bit 31: Address filter enable.

MAC_ADDR1L

Ethernet MAC address1 low register

Offset: 0x4C, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR1L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR1L
rw
Toggle Fields.

ADDR1L

Bits 0-31: MAC address1 low.

MAC_ADDR2H

Ethernet MAC address 2 high register (MAC_ADDR2H)

Offset: 0x50, reset: 0x0000FFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFE
rw 		SAF
rw 		MB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR2H
rw
Toggle Fields.

ADDR2H

Bits 0-15: Ethernet MAC address 2 high register.

MB

Bits 24-29: Mask byte.

SAF

Bit 30: Source address filter.

AFE

Bit 31: Address filter enable .

MAC_ADDR2L

Ethernet MAC address 2 low register

Offset: 0x54, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR2L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR2L
rw
Toggle Fields.

ADDR2L

Bits 0-31: MAC address2 low.

MAC_ADDR3H

Ethernet MAC address 3 high register (MAC_ADDR3H)

Offset: 0x58, reset: 0x0000FFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFE
rw 		SAF
rw 		MB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR3H
rw
Toggle Fields.

ADDR3H

Bits 0-15: MAC address3 high.

MB

Bits 24-29: Mask byte.

SAF

Bit 30: Source address filter.

AFE

Bit 31: Address filter enable.

MAC_ADDR3L

Ethernet MAC address 3 low register

Offset: 0x5C, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR3L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR3L
rw
Toggle Fields.

ADDR3L

Bits 0-31: MAC address3 low.

MAC_FCTH

Ethernet MAC flow control threshold register

Offset: 0x1080, reset: 0x00000015, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFD
rw 		RFA
rw
Toggle Fields.

RFA

Bits 0-2: Threshold of active flow control.

RFD

Bits 4-6: Threshold of deactive flow control.

ENET_MSC

0x40028100: Ethernet: MAC statistics counters

12/22 fields covered. Toggle Registers.

MSC_CTL

Ethernet MSC control register (MSC_CTL)

Offset: 0x0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCFZ
rw 		RTOR
rw 		CTSR
rw 		CTR
rw
Toggle Fields.

CTR

Bit 0: Counter reset.

CTSR

Bit 1: Counter stop rollover.

RTOR

Bit 2: Reset on read.

MCFZ

Bit 3: MSC counter freeze.

MSC_RINTF

Ethernet MSC receive interrupt flag register (MSC_RINTF)

Offset: 0x4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RGUF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFAE
r 		RFCE
r
Toggle Fields.

RFCE

Bit 5: Received frames CRC error.

RFAE

Bit 6: Received frames alignment error.

RGUF

Bit 17: Received Good Unicast Frames.

MSC_TINTF

Ethernet MSC transmit interrupt flag register (MSC_TINTF)

Offset: 0x8, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFMSC
r 		TGFSC
r
Toggle Fields.

TGFSC

Bit 14: Transmitted good frames single collision.

TGFMSC

Bit 15: Transmitted good frames more single collision .

TGF

Bit 21: Transmitted good frames.

MSC_RINTMSK

Ethernet MSC receive interrupt mask register (MSC_RINTMSK)

Offset: 0xC, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RGUFIM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFAEIM
rw 		RFCEIM
rw
Toggle Fields.

RFCEIM

Bit 5: Received frame CRC error interrupt mask.

RFAEIM

Bit 6: Received frames alignment error interrupt mask.

RGUFIM

Bit 17: Received good unicast frames interrupt mask.

MSC_TINTMSK

Ethernet MSC transmit interrupt mask register (MSC_TINTMSK)

Offset: 0x10, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGFIM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFMSCIM
rw 		TGFSCIM
rw
Toggle Fields.

TGFSCIM

Bit 14: Transmitted good frames single collision interrupt mask.

TGFMSCIM

Bit 15: Transmitted good frames more single interrupt collision mask.

TGFIM

Bit 21: Transmitted good frames interrupt mask.

MSC_SCCNT

Ethernet MSC transmitted good frames after a single collision counter

Offset: 0x4C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCC
r
Toggle Fields.

SCC

Bits 0-31: Transmitted good frames after a single collision counter.

MSC_MSCCNT

Ethernet MSC transmitted good frames after more than a single collision

Offset: 0x50, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSCC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSCC
r
Toggle Fields.

MSCC

Bits 0-31: Transmitted good frames after more than a single collision counter.

MSC_TGFCNT

Ethernet MSC transmitted good frames counter register

Offset: 0x68, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGF
r
Toggle Fields.

TGF

Bits 0-31: Transmitted good frames counter.

MSC_RFCECNT

Ethernet MSC received frames with CRC error counter register

Offset: 0x94, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RFCER
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFCER
r
Toggle Fields.

RFCER

Bits 0-31: Received frames with CRC error counter.

MSC_RFAECNT

Ethernet MSC received frames with alignment error counter register

Offset: 0x98, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RFAER
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFAER
r
Toggle Fields.

RFAER

Bits 0-31: Received frames with alignment error counter.

MSC_RGUFCNT

MSC received good unicast frames counter register

Offset: 0xC4, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RGUF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGUF
r
Toggle Fields.

RGUF

Bits 0-31: Received good unicast frames counter.

ENET_PTP

0x40028700: Ethernet: Precision time protocol

3/16 fields covered. Toggle Registers.

PTP_TSCTL

Ethernet PTP time stamp control register (PTP_TSCTL)

Offset: 0x0, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMSARU
rw 		TMSITEN
rw 		TMSSTU
rw 		TMSSTI
rw 		TMSFCU
rw 		TMSEN
rw
Toggle Fields.

TMSEN

Bit 0: Time stamp enable.

TMSFCU

Bit 1: Time stamp fine or coarse update.

TMSSTI

Bit 2: Time stamp system time initialize.

TMSSTU

Bit 3: Time stamp system time update.

TMSITEN

Bit 4: Time stamp interrupt trigger enable.

TMSARU

Bit 5: Time stamp addend register update.

PTP_SSINC

Ethernet PTP subsecond increment register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STMSSI
rw
Toggle Fields.

STMSSI

Bits 0-7: System time subsecond increment.

PTP_TSH

Ethernet PTP time stamp high register

Offset: 0x8, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STMS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STMS
r
Toggle Fields.

STMS

Bits 0-31: System time second.

PTP_TSL

Ethernet PTP time stamp low register (PTP_TSL)

Offset: 0xC, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STS
r 		STMSS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STMSS
r
Toggle Fields.

STMSS

Bits 0-30: System time subseconds.

STS

Bit 31: System time sign.

PTP_TSUH

Ethernet PTP time stamp high update register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TMSUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMSUS
rw
Toggle Fields.

TMSUS

Bits 0-31: Time stamp update second.

PTP_TSUL

Ethernet PTP time stamp low update register (PTP_TSUL)

Offset: 0x14, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TMSUPNS
rw 		TMSUSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMSUSS
rw
Toggle Fields.

TMSUSS

Bits 0-30: Time stamp update subseconds.

TMSUPNS

Bit 31: Time stamp update positive or negative sign.

PTP_TSADDEND

Ethernet PTP time stamp addend register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TMSA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMSA
rw
Toggle Fields.

TMSA

Bits 0-31: Time stamp addend.

PTP_ETH

Ethernet PTP expected time high register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETSH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETSH
rw
Toggle Fields.

ETSH

Bits 0-31: Expected time stamp high.

PTP_ETL

Ethernet PTP expected time low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETSL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETSL
rw
Toggle Fields.

ETSL

Bits 0-31: Expected time stamp low.

EXMC

0xA0000000: External memory controller

5/183 fields covered. Toggle Registers.

SNCTL0

SRAM/NOR flash control register 0

Offset: 0x0, reset: 0x000030DB, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCWR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXMODEN
rw 		NRWTEN
rw 		WREN
rw 		NRWTCFG
rw 		WRAPEN
rw 		NRWTPOL
rw 		SBRSTEN
rw 		NREN
rw 		NRW
rw 		NRTP
rw 		NRMUX
rw 		NRBKEN
rw
Toggle Fields.

NRBKEN

Bit 0: NOR bank enable.

NRMUX

Bit 1: NOR bank memory address/data multiplexing.

NRTP

Bits 2-3: NOR bank memory type.

NRW

Bits 4-5: NOR bank memory data bus width.

NREN

Bit 6: NOR Flash access enable.

SBRSTEN

Bit 8: Synchronous burst enable.

NRWTPOL

Bit 9: NWAIT signal polarity.

WRAPEN

Bit 10: Wrapped burst mode enable.

NRWTCFG

Bit 11: NWAIT signal configuration, only work in synchronous mode.

WREN

Bit 12: Write enable.

NRWTEN

Bit 13: NWAIT signal enable.

EXMODEN

Bit 14: Extended mode enable.

ASYNCWAIT

Bit 15: Asynchronous wait.

SYNCWR

Bit 19: Synchronous write.

SNTCFG0

SRAM/NOR flash timing configuration register 0

Offset: 0x4, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ASYNCMOD
rw 		DLAT
rw 		CKDIV
rw 		BUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSET
rw 		AHLD
rw 		ASET
rw
Toggle Fields.

ASET

Bits 0-3: Address setup time.

AHLD

Bits 4-7: Address hold time.

DSET

Bits 8-15: Data setup time.

BUSLAT

Bits 16-19: Bus latency.

CKDIV

Bits 20-23: Synchronous clock divide ratio.

DLAT

Bits 24-27: Data latency for NOR Flash.

ASYNCMOD

Bits 28-29: Asynchronous access mode.

SNCTL1

SRAM/NOR flash control register 1

Offset: 0x8, reset: 0x000030D2, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCWR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXMODEN
rw 		NRWTEN
rw 		WREN
rw 		NRWTCFG
rw 		WRAPEN
rw 		NRWTPOL
rw 		SBRSTEN
rw 		NREN
rw 		NRW
rw 		NRTP
rw 		NRMUX
rw 		NRBKEN
rw
Toggle Fields.

NRBKEN

Bit 0: NOR bank enable.

NRMUX

Bit 1: NOR bank memory address/data multiplexing.

NRTP

Bits 2-3: NOR bank memory type.

NRW

Bits 4-5: NOR bank memory data bus width.

NREN

Bit 6: NOR Flash access enable.

SBRSTEN

Bit 8: Synchronous burst enable.

NRWTPOL

Bit 9: NWAIT signal polarity.

WRAPEN

Bit 10: Wrapped burst mode enable.

NRWTCFG

Bit 11: NWAIT signal configuration, only work in synchronous mode.

WREN

Bit 12: Write enable.

NRWTEN

Bit 13: NWAIT signal enable.

EXMODEN

Bit 14: Extended mode enable.

ASYNCWAIT

Bit 15: Asynchronous wait.

SYNCWR

Bit 19: Synchronous write.

SNTCFG1

SRAM/NOR flash timing configuration register 1

Offset: 0xC, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ASYNCMOD
rw 		DLAT
rw 		CKDIV
rw 		BUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSET
rw 		AHLD
rw 		ASET
rw
Toggle Fields.

ASET

Bits 0-3: Address setup time.

AHLD

Bits 4-7: Address hold time.

DSET

Bits 8-15: Data setup time.

BUSLAT

Bits 16-19: Bus latency.

CKDIV

Bits 20-23: Synchronous clock divide ratio.

DLAT

Bits 24-27: Data latency for NOR Flash.

ASYNCMOD

Bits 28-29: Asynchronous access mode.

SNCTL2

SRAM/NOR flash control register 2

Offset: 0x10, reset: 0x000030D2, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCWR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXMODEN
rw 		NRWTEN
rw 		WREN
rw 		NRWTCFG
rw 		WRAPEN
rw 		NRWTPOL
rw 		SBRSTEN
rw 		NREN
rw 		NRW
rw 		NRTP
rw 		NRMUX
rw 		NRBKEN
rw
Toggle Fields.

NRBKEN

Bit 0: NOR bank enable.

NRMUX

Bit 1: NOR bank memory address/data multiplexing.

NRTP

Bits 2-3: NOR bank memory type.

NRW

Bits 4-5: NOR bank memory data bus width.

NREN

Bit 6: NOR Flash access enable.

SBRSTEN

Bit 8: Synchronous burst enable.

NRWTPOL

Bit 9: NWAIT signal polarity.

WRAPEN

Bit 10: Wrapped burst mode enable.

NRWTCFG

Bit 11: NWAIT signal configuration, only work in synchronous mode.

WREN

Bit 12: Write enable.

NRWTEN

Bit 13: NWAIT signal enable.

EXMODEN

Bit 14: Extended mode enable.

ASYNCWAIT

Bit 15: Asynchronous wait.

SYNCWR

Bit 19: Synchronous write.

SNTCFG2

SRAM/NOR flash timing configuration register 2

Offset: 0x14, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ASYNCMOD
rw 		DLAT
rw 		CKDIV
rw 		BUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSET
rw 		AHLD
rw 		ASET
rw
Toggle Fields.

ASET

Bits 0-3: Address setup time.

AHLD

Bits 4-7: Address hold time.

DSET

Bits 8-15: Data setup time.

BUSLAT

Bits 16-19: Bus latency.

CKDIV

Bits 20-23: Synchronous clock divide ratio.

DLAT

Bits 24-27: Data latency for NOR Flash.

ASYNCMOD

Bits 28-29: Asynchronous access mode.

SNCTL3

SRAM/NOR flash control register 3

Offset: 0x18, reset: 0x000030D2, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCWR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXMODEN
rw 		NRWTEN
rw 		WREN
rw 		NRWTCFG
rw 		WRAPEN
rw 		NRWTPOL
rw 		SBRSTEN
rw 		NREN
rw 		NRW
rw 		NRTP
rw 		NRMUX
rw 		NRBKEN
rw
Toggle Fields.

NRBKEN

Bit 0: NOR bank enable.

NRMUX

Bit 1: NOR bank memory address/data multiplexing.

NRTP

Bits 2-3: NOR bank memory type.

NRW

Bits 4-5: NOR bank memory data bus width.

NREN

Bit 6: NOR Flash access enable.

SBRSTEN

Bit 8: Synchronous burst enable.

NRWTPOL

Bit 9: NWAIT signal polarity.

WRAPEN

Bit 10: Wrapped burst mode enable.

NRWTCFG

Bit 11: NWAIT signal configuration, only work in synchronous mode.

WREN

Bit 12: Write enable.

NRWTEN

Bit 13: NWAIT signal enable.

EXMODEN

Bit 14: Extended mode enable.

ASYNCWAIT

Bit 15: Asynchronous wait.

SYNCWR

Bit 19: Synchronous write.

SNTCFG3

SRAM/NOR flash timing configuration register 3

Offset: 0x1C, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ASYNCMOD
rw 		DLAT
rw 		CKDIV
rw 		BUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSET
rw 		AHLD
rw 		ASET
rw
Toggle Fields.

ASET

Bits 0-3: Address setup time.

AHLD

Bits 4-7: Address hold time.

DSET

Bits 8-15: Data setup time.

BUSLAT

Bits 16-19: Bus latency.

CKDIV

Bits 20-23: Synchronous clock divide ratio.

DLAT

Bits 24-27: Data latency for NOR Flash.

ASYNCMOD

Bits 28-29: Asynchronous access mode.

NPCTL1

NAND flash/PC card control register 1

Offset: 0x60, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCSZ
rw 		ATR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATR
rw 		CTR
rw 		ECCEN
rw 		NDW
rw 		NDTP
rw 		NDBKEN
rw 		NDWTEN
rw
Toggle Fields.

NDWTEN

Bit 1: Wait feature enable.

NDBKEN

Bit 2: NAND bank enable.

NDTP

Bit 3: NAND bank memory type.

NDW

Bits 4-5: NAND bank memory data bus width.

ECCEN

Bit 6: ECC enable.

CTR

Bits 9-12: CLE to RE delay.

ATR

Bits 13-16: ALE to RE delay.

ECCSZ

Bits 17-19: ECC size.

NPINTEN1

NAND flash/PC card interrupt enable register 1

Offset: 0x64, reset: 0x00000040, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFEPT
r 		INTFEN
rw 		INTHEN
rw 		INTREN
rw 		INTFS
rw 		INTHS
rw 		INTRS
rw
Toggle Fields.

INTRS

Bit 0: Interrupt rising edge status.

INTHS

Bit 1: Interrupt high-level status.

INTFS

Bit 2: Interrupt falling edge status.

INTREN

Bit 3: Interrupt rising edge detection enable bit.

INTHEN

Bit 4: Interrupt high-level detection enable.

INTFEN

Bit 5: Interrupt falling edge detection enable.

FFEPT

Bit 6: FIFO empty flag.

NPCTCFG1

NAND flash/PC card common space timing configuration register 1

Offset: 0x68, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMHIZ
rw 		COMHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMWAIT
rw 		COMSET
rw
Toggle Fields.

COMSET

Bits 0-7: Common memory setup time.

COMWAIT

Bits 8-15: Common memory wait time.

COMHLD

Bits 16-23: Common memory hold time.

COMHIZ

Bits 24-31: Common memory data bus HiZ time.

NPATCFG1

NAND flash/PC card attribute space timing configuration register 1

Offset: 0x6C, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw 		ATTHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw 		ATTSET
rw
Toggle Fields.

ATTSET

Bits 0-7: Attribute memory setup time.

ATTWAIT

Bits 8-15: Attribute memory wait time.

ATTHLD

Bits 16-23: Attribute memory hold time.

ATTHIZ

Bits 24-31: Attribute memory data bus HiZ time.

NECC1

NAND flash ECC register 1

Offset: 0x74, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC
r
Toggle Fields.

ECC

Bits 0-31: ECC result.

NPCTL2

NAND flash/PC card control register 2

Offset: 0x80, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCSZ
rw 		ATR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATR
rw 		CTR
rw 		ECCEN
rw 		NDW
rw 		NDTP
rw 		NDBKEN
rw 		NDWTEN
rw
Toggle Fields.

NDWTEN

Bit 1: Wait feature enable.

NDBKEN

Bit 2: NAND bank enable.

NDTP

Bit 3: NAND bank memory type.

NDW

Bits 4-5: NAND bank memory data bus width.

ECCEN

Bit 6: ECC enable.

CTR

Bits 9-12: CLE to RE delay.

ATR

Bits 13-16: ALE to RE delay.

ECCSZ

Bits 17-19: ECC size.

NPINTEN2

NAND flash/PC card interrupt enable register 2

Offset: 0x84, reset: 0x00000040, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFEPT
r 		INTFEN
rw 		INTHEN
rw 		INTREN
rw 		INTFS
rw 		INTHS
rw 		INTRS
rw
Toggle Fields.

INTRS

Bit 0: Interrupt rising edge status.

INTHS

Bit 1: Interrupt high-level status.

INTFS

Bit 2: Interrupt falling edge status.

INTREN

Bit 3: Interrupt rising edge detection enable bit.

INTHEN

Bit 4: Interrupt high-level detection enable.

INTFEN

Bit 5: Interrupt falling edge detection enable.

FFEPT

Bit 6: FIFO empty flag.

NPCTCFG2

NAND flash/PC card common space timing configuration register 2

Offset: 0x88, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMHIZ
rw 		COMHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMWAIT
rw 		COMSET
rw
Toggle Fields.

COMSET

Bits 0-7: Common memory setup time.

COMWAIT

Bits 8-15: Common memory wait time.

COMHLD

Bits 16-23: Common memory hold time.

COMHIZ

Bits 24-31: Common memory data bus HiZ time.

NPATCFG2

NAND flash/PC card attribute space timing configuration register 2

Offset: 0x8C, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw 		ATTHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw 		ATTSET
rw
Toggle Fields.

ATTSET

Bits 0-7: Attribute memory setup time.

ATTWAIT

Bits 8-15: Attribute memory wait time.

ATTHLD

Bits 16-23: Attribute memory hold time.

ATTHIZ

Bits 24-31: Attribute memory data bus HiZ time.

NECC2

NAND flash ECC register 2

Offset: 0x94, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC
r
Toggle Fields.

ECC

Bits 0-31: ECC result.

NPCTL3

NAND flash/PC card control register 3

Offset: 0xA0, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCSZ
rw 		ATR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATR
rw 		CTR
rw 		ECCEN
rw 		NDW
rw 		NDTP
rw 		NDBKEN
rw 		NDWTEN
rw
Toggle Fields.

NDWTEN

Bit 1: Wait feature enable.

NDBKEN

Bit 2: NAND bank enable.

NDTP

Bit 3: NAND bank memory type.

NDW

Bits 4-5: NAND bank memory data bus width.

ECCEN

Bit 6: ECC enable.

CTR

Bits 9-12: CLE to RE delay.

ATR

Bits 13-16: ALE to RE delay.

ECCSZ

Bits 17-19: ECC size.

NPINTEN3

NAND flash/PC card interrupt enable register 3

Offset: 0xA4, reset: 0x00000040, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFEPT
r 		INTFEN
rw 		INTHEN
rw 		INTREN
rw 		INTFS
rw 		INTHS
rw 		INTRS
rw
Toggle Fields.

INTRS

Bit 0: Interrupt rising edge status.

INTHS

Bit 1: Interrupt high-level status.

INTFS

Bit 2: Interrupt falling edge status.

INTREN

Bit 3: Interrupt rising edge detection enable bit.

INTHEN

Bit 4: Interrupt high-level detection enable.

INTFEN

Bit 5: Interrupt falling edge detection enable.

FFEPT

Bit 6: FIFO empty flag.

NPCTCFG3

NAND flash/PC card common space timing configuration register 3

Offset: 0xA8, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMHIZ
rw 		COMHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMWAIT
rw 		COMSET
rw
Toggle Fields.

COMSET

Bits 0-7: Common memory setup time.

COMWAIT

Bits 8-15: Common memory wait time.

COMHLD

Bits 16-23: Common memory hold time.

COMHIZ

Bits 24-31: Common memory data bus HiZ time.

NPATCFG3

NAND flash/PC card attribute space timing configuration register 3

Offset: 0xAC, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw 		ATTHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw 		ATTSET
rw
Toggle Fields.

ATTSET

Bits 0-7: Attribute memory setup time.

ATTWAIT

Bits 8-15: Attribute memory wait time.

ATTHLD

Bits 16-23: Attribute memory hold time.

ATTHIZ

Bits 24-31: Attribute memory data bus HiZ time.

PIOTCFG3

PC card I/O space timing configuration register

Offset: 0xB0, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOHIZ
rw 		IOHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOWAIT
rw 		IOSET
rw
Toggle Fields.

IOSET

Bits 0-7: IO space setup time.

IOWAIT

Bits 8-15: IO space wait time.

IOHLD

Bits 16-23: IO space hold time.

IOHIZ

Bits 24-31: IO space data bus HiZ time.

SNWTCFG0

SRAM/NOR flash write timing configuration register 0

Offset: 0x104, reset: 0x0FFFFFFF, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WASYNCMOD
rw 		DLAT
rw 		CKDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDSET
rw 		WAHLD
rw 		WASET
rw
Toggle Fields.

WASET

Bits 0-3: Address setup time.

WAHLD

Bits 4-7: Address hold time.

WDSET

Bits 8-15: Data setup time.

CKDIV

Bits 20-23: Synchronous clock divide ratio.

DLAT

Bits 24-27: Data latency for NOR Flash.

WASYNCMOD

Bits 28-29: Asynchronous access mode.

SNWTCFG1

SRAM/NOR flash write timing configuration register 1

Offset: 0x10C, reset: 0x0FFFFFFF, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WASYNCMOD
rw 		DLAT
rw 		CKDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDSET
rw 		WAHLD
rw 		WASET
rw
Toggle Fields.

WASET

Bits 0-3: Address setup time.

WAHLD

Bits 4-7: Address hold time.

WDSET

Bits 8-15: Data setup time.

CKDIV

Bits 20-23: Synchronous clock divide ratio.

DLAT

Bits 24-27: Data latency for NOR Flash.

WASYNCMOD

Bits 28-29: Asynchronous access mode.

SNWTCFG2

SRAM/NOR flash write timing configuration register 2

Offset: 0x114, reset: 0x0FFFFFFF, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WASYNCMOD
rw 		DLAT
rw 		CKDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDSET
rw 		WAHLD
rw 		WASET
rw
Toggle Fields.

WASET

Bits 0-3: Address setup time.

WAHLD

Bits 4-7: Address hold time.

WDSET

Bits 8-15: Data setup time.

CKDIV

Bits 20-23: Synchronous clock divide ratio.

DLAT

Bits 24-27: Data latency for NOR Flash.

WASYNCMOD

Bits 28-29: Asynchronous access mode.

SNWTCFG3

SRAM/NOR flash write timing configuration register 3

Offset: 0x11C, reset: 0x0FFFFFFF, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WASYNCMOD
rw 		DLAT
rw 		CKDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDSET
rw 		WAHLD
rw 		WASET
rw
Toggle Fields.

WASET

Bits 0-3: Address setup time.

WAHLD

Bits 4-7: Address hold time.

WDSET

Bits 8-15: Data setup time.

CKDIV

Bits 20-23: Synchronous clock divide ratio.

DLAT

Bits 24-27: Data latency for NOR Flash.

WASYNCMOD

Bits 28-29: Asynchronous access mode.

EXTI

0x40010400: External interrupt/event controller

120/120 fields covered. Toggle Registers.

INTEN

Interrupt enable register (EXTI_INTEN)

Offset: 0x0, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INTEN19
rw 		INTEN18
rw 		INTEN17
rw 		INTEN16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTEN15
rw 		INTEN14
rw 		INTEN13
rw 		INTEN12
rw 		INTEN11
rw 		INTEN10
rw 		INTEN9
rw 		INTEN8
rw 		INTEN7
rw 		INTEN6
rw 		INTEN5
rw 		INTEN4
rw 		INTEN3
rw 		INTEN2
rw 		INTEN1
rw 		INTEN0
rw
Toggle Fields.

INTEN0

Bit 0: Enable Interrupt on line 0.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN1

Bit 1: Enable Interrupt on line 1.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN2

Bit 2: Enable Interrupt on line 2.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN3

Bit 3: Enable Interrupt on line 3.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN4

Bit 4: Enable Interrupt on line 4.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN5

Bit 5: Enable Interrupt on line 5.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN6

Bit 6: Enable Interrupt on line 6.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN7

Bit 7: Enable Interrupt on line 7.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN8

Bit 8: Enable Interrupt on line 8.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN9

Bit 9: Enable Interrupt on line 9.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN10

Bit 10: Enable Interrupt on line 10.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN11

Bit 11: Enable Interrupt on line 11.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN12

Bit 12: Enable Interrupt on line 12.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN13

Bit 13: Enable Interrupt on line 13.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN14

Bit 14: Enable Interrupt on line 14.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN15

Bit 15: Enable Interrupt on line 15.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN16

Bit 16: Enable Interrupt on line 16.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN17

Bit 17: Enable Interrupt on line 17.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN18

Bit 18: Enable Interrupt on line 18.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN19

Bit 19: Enable Interrupt on line 19.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

EVEN

Event enable register (EXTI_EVEN)

Offset: 0x4, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EVEN19
rw 		EVEN18
rw 		EVEN17
rw 		EVEN16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EVEN15
rw 		EVEN14
rw 		EVEN13
rw 		EVEN12
rw 		EVEN11
rw 		EVEN10
rw 		EVEN9
rw 		EVEN8
rw 		EVEN7
rw 		EVEN6
rw 		EVEN5
rw 		EVEN4
rw 		EVEN3
rw 		EVEN2
rw 		EVEN1
rw 		EVEN0
rw
Toggle Fields.

EVEN0

Bit 0: Enable Event on line 0.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN1

Bit 1: Enable Event on line 1.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN2

Bit 2: Enable Event on line 2.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN3

Bit 3: Enable Event on line 3.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN4

Bit 4: Enable Event on line 4.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN5

Bit 5: Enable Event on line 5.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN6

Bit 6: Enable Event on line 6.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN7

Bit 7: Enable Event on line 7.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN8

Bit 8: Enable Event on line 8.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN9

Bit 9: Enable Event on line 9.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN10

Bit 10: Enable Event on line 10.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN11

Bit 11: Enable Event on line 11.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN12

Bit 12: Enable Event on line 12.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN13

Bit 13: Enable Event on line 13.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN14

Bit 14: Enable Event on line 14.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN15

Bit 15: Enable Event on line 15.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN16

Bit 16: Enable Event on line 16.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN17

Bit 17: Enable Event on line 17.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN18

Bit 18: Enable Event on line 18.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN19

Bit 19: Enable Event on line 19.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

RTEN

Rising Edge Trigger Enable register (EXTI_RTEN)

Offset: 0x8, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTEN19
rw 		RTEN18
rw 		RTEN17
rw 		RTEN16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTEN15
rw 		RTEN14
rw 		RTEN13
rw 		RTEN12
rw 		RTEN11
rw 		RTEN10
rw 		RTEN9
rw 		RTEN8
rw 		RTEN7
rw 		RTEN6
rw 		RTEN5
rw 		RTEN4
rw 		RTEN3
rw 		RTEN2
rw 		RTEN1
rw 		RTEN0
rw
Toggle Fields.

RTEN0

Bit 0: Rising edge trigger enable of line 0.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN1

Bit 1: Rising edge trigger enable of line 1.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN2

Bit 2: Rising edge trigger enable of line 2.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN3

Bit 3: Rising edge trigger enable of line 3.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN4

Bit 4: Rising edge trigger enable of line 4.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN5

Bit 5: Rising edge trigger enable of line 5.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN6

Bit 6: Rising edge trigger enable of line 6.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN7

Bit 7: Rising edge trigger enable of line 7.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN8

Bit 8: Rising edge trigger enable of line 8.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN9

Bit 9: Rising edge trigger enable of line 9.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN10

Bit 10: Rising edge trigger enable of line 10.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN11

Bit 11: Rising edge trigger enable of line 11.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN12

Bit 12: Rising edge trigger enable of line 12.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN13

Bit 13: Rising edge trigger enable of line 13.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN14

Bit 14: Rising edge trigger enable of line 14.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN15

Bit 15: Rising edge trigger enable of line 15.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN16

Bit 16: Rising edge trigger enable of line 16.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN17

Bit 17: Rising edge trigger enable of line 17.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN18

Bit 18: Rising edge trigger enable of line 18.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN19

Bit 19: Rising edge trigger enable of line 19.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTEN

Falling Egde Trigger Enable register (EXTI_FTEN)

Offset: 0xC, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTEN19
rw 		FTEN18
rw 		FTEN17
rw 		FTEN16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTEN15
rw 		FTEN14
rw 		FTEN13
rw 		FTEN12
rw 		FTEN11
rw 		FTEN10
rw 		FTEN9
rw 		FTEN8
rw 		FTEN7
rw 		FTEN6
rw 		FTEN5
rw 		FTEN4
rw 		FTEN3
rw 		FTEN2
rw 		FTEN1
rw 		FTEN0
rw
Toggle Fields.

FTEN0

Bit 0: Falling edge trigger enable of line 0.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN1

Bit 1: Falling edge trigger enable of line 1.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN2

Bit 2: Falling edge trigger enable of line 2.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN3

Bit 3: Falling edge trigger enable of line 3.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN4

Bit 4: Falling edge trigger enable of line 4.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN5

Bit 5: Falling edge trigger enable of line 5.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN6

Bit 6: Falling edge trigger enable of line 6.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN7

Bit 7: Falling edge trigger enable of line 7.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN8

Bit 8: Falling edge trigger enable of line 8.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN9

Bit 9: Falling edge trigger enable of line 9.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN10

Bit 10: Falling edge trigger enable of line 10.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN11

Bit 11: Falling edge trigger enable of line 11.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN12

Bit 12: Falling edge trigger enable of line 12.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN13

Bit 13: Falling edge trigger enable of line 13.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN14

Bit 14: Falling edge trigger enable of line 14.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN15

Bit 15: Falling edge trigger enable of line 15.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN16

Bit 16: Falling edge trigger enable of line 16.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN17

Bit 17: Falling edge trigger enable of line 17.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN18

Bit 18: Falling edge trigger enable of line 18.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN19

Bit 19: Falling edge trigger enable of line 19.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIEV

Software interrupt event register (EXTI_SWIEV)

Offset: 0x10, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWIEV19
rw 		SWIEV18
rw 		SWIEV17
rw 		SWIEV16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWIEV15
rw 		SWIEV14
rw 		SWIEV13
rw 		SWIEV12
rw 		SWIEV11
rw 		SWIEV10
rw 		SWIEV9
rw 		SWIEV8
rw 		SWIEV7
rw 		SWIEV6
rw 		SWIEV5
rw 		SWIEV4
rw 		SWIEV3
rw 		SWIEV2
rw 		SWIEV1
rw 		SWIEV0
rw
Toggle Fields.

SWIEV0

Bit 0: Interrupt/Event software trigger on line 0.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV1

Bit 1: Interrupt/Event software trigger on line 1.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV2

Bit 2: Interrupt/Event software trigger on line 2.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV3

Bit 3: Interrupt/Event software trigger on line 3.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV4

Bit 4: Interrupt/Event software trigger on line 4.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV5

Bit 5: Interrupt/Event software trigger on line 5.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV6

Bit 6: Interrupt/Event software trigger on line 6.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV7

Bit 7: Interrupt/Event software trigger on line 7.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV8

Bit 8: Interrupt/Event software trigger on line 8.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV9

Bit 9: Interrupt/Event software trigger on line 9.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV10

Bit 10: Interrupt/Event software trigger on line 10.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV11

Bit 11: Interrupt/Event software trigger on line 11.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV12

Bit 12: Interrupt/Event software trigger on line 12.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV13

Bit 13: Interrupt/Event software trigger on line 13.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV14

Bit 14: Interrupt/Event software trigger on line 14.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV15

Bit 15: Interrupt/Event software trigger on line 15.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV16

Bit 16: Interrupt/Event software trigger on line 16.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV17

Bit 17: Interrupt/Event software trigger on line 17.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV18

Bit 18: Interrupt/Event software trigger on line 18.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV19

Bit 19: Interrupt/Event software trigger on line 19.

Allowed values:
1: Pend: Generates an interrupt request

PD

Pending register (EXTI_PD)

Offset: 0x14, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PD19
rw 		PD18
rw 		PD17
rw 		PD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle Fields.

PD0

Bit 0: Interrupt pending status of line 0.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD1

Bit 1: Interrupt pending status of line 1.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD2

Bit 2: Interrupt pending status of line 2.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD3

Bit 3: Interrupt pending status of line 3.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD4

Bit 4: Interrupt pending status of line 4.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD5

Bit 5: Interrupt pending status of line 5.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD6

Bit 6: Interrupt pending status of line 6.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD7

Bit 7: Interrupt pending status of line 7.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD8

Bit 8: Interrupt pending status of line 8.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD9

Bit 9: Interrupt pending status of line 9.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD10

Bit 10: Interrupt pending status of line 10.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD11

Bit 11: Interrupt pending status of line 11.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD12

Bit 12: Interrupt pending status of line 12.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD13

Bit 13: Interrupt pending status of line 13.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD14

Bit 14: Interrupt pending status of line 14.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD15

Bit 15: Interrupt pending status of line 15.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD16

Bit 16: Interrupt pending status of line 16.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD17

Bit 17: Interrupt pending status of line 17.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD18

Bit 18: Interrupt pending status of line 18.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD19

Bit 19: Interrupt pending status of line 19.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FMC

0x40022000: FMC

38/38 fields covered. Toggle Registers.

WS

wait state counter register

Offset: 0x0, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WSCNT
rw
Toggle Fields.

WSCNT

Bits 0-2: WSCNT.

Allowed values:
0: WS0: 0 wait states added
1: WS1: 1 wait state added
2: WS2: 2 wait states added

KEY0

Flash unlock key register

Offset: 0x4, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-31: FMC_CTL0 unlock key.

Allowed values: 0-4294967295

OBKEY

Option byte unlock key register

Offset: 0x8, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OBKEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OBKEY
w
Toggle Fields.

OBKEY

Bits 0-31: FMC_CTL0 option bytes operation unlock key.

Allowed values: 0-4294967295

STAT0

Status register 0

Offset: 0xC, reset: 0x00000000, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENDF
rw 		WPERR
rw 		PGERR
rw 		BUSY
r
Toggle Fields.

BUSY

Bit 0: The flash is busy bit.

Allowed values:
0: Inactive: No operation is in progress
1: Active: An operation is in progress

PGERR

Bit 2: Program error flag bit.

Allowed values:
0: NoError: There was no error
1: Error: There was an error programming flash

WPERR

Bit 4: Erase/Program protection error flag bit.

Allowed values:
0: NoError: There was no error
1: Error: There was an error erasing/programming protected pages

ENDF

Bit 5: End of operation flag bit.

Allowed values:
0: NoEvent: No end of operation occurred
1: Event: An end of operation event occurred

CTL0

Control register 0

Offset: 0x10, reset: 0x00000080, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENDIE
rw 		ERRIE
rw 		OBWEN
rw 		LK
rw 		START
rw 		OBER
rw 		OBPG
rw 		MER
rw 		PER
rw 		PG
rw
Toggle Fields.

PG

Bit 0: Main flash program for bank0 command bit.

Allowed values:
1: Program: Flash programming activated

PER

Bit 1: Main flash page erase for bank0 command bit.

Allowed values:
1: PageErase: Erase activated for selected page

MER

Bit 2: Main flash mass erase for bank0 command bit.

Allowed values:
1: MassErase: Erase activated for all user sectors

OBPG

Bit 4: Option byte programming.

Allowed values:
1: OptionByteProgramming: Program option byte activated

OBER

Bit 5: Option byte erase.

Allowed values:
1: OptionByteErase: Erase option byte activated

START

Bit 6: Send erase command to FMC bit.

Allowed values:
1: Start: Trigger an erase operation

LK

Bit 7: FMC_CTL0 lock bit.

Allowed values:
0: Unlocked: CTL register is unlocked
1: Locked: CTL register is locked

OBWEN

Bit 9: Option byte erase/program enable bit.

Allowed values:
0: Disabled: Option byte write disabled
1: Enabled: Option byte write enabled

ERRIE

Bit 10: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt generation disabled
1: Enabled: Error interrupt generation enabled

ENDIE

Bit 12: End of operation interrupt enable.

Allowed values:
0: Disabled: End of operation interrupt disabled
1: Enabled: End of operation interrupt enabled

ADDR0

Address register 0

Offset: 0x14, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
w
Toggle Fields.

ADDR

Bits 0-31: Flash erase/program command address bits.

Allowed values: 0-4294967295

OBSTAT

Option byte register

Offset: 0x1C, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r 		USER
r 		SPC
r 		OBERR
r
Toggle Fields.

OBERR

Bit 0: Option bytes read error bit.

SPC

Bit 1: Option bytes security protection code.

USER

Bits 2-9: Store USER of option bytes block after system reset.

DATA

Bits 10-25: Store DATA of option bytes block after system reset.

WP

Erase/Program Protection register

Offset: 0x20, reset: 0x000000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WP
r
Toggle Fields.

WP

Bits 0-31: Store WP of option bytes block after system reset.

KEY1

Unlock key register 1

Offset: 0x44, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-31: FMC_CTL1 unlock register .

Allowed values: 0-4294967295

STAT1

Status register 1

Offset: 0x4C, reset: 0x00000000, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENDF
rw 		WPERR
rw 		PGERR
rw 		BUSY
r
Toggle Fields.

BUSY

Bit 0: Busy.

Allowed values:
0: Inactive: No operation is in progress
1: Active: An operation is in progress

PGERR

Bit 2: Programming error.

Allowed values:
0: NoError: There was no error
1: Error: There was an error programming flash

WPERR

Bit 4: Erase/Program protection error flag bit.

Allowed values:
0: NoError: There was no error
1: Error: There was an error erasing/programming protected pages

ENDF

Bit 5: End of operation.

Allowed values:
0: NoEvent: No end of operation occurred
1: Event: An end of operation event occurred

CTL1

Control register 1

Offset: 0x50, reset: 0x00000080, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENDIE
rw 		ERRIE
rw 		LK
rw 		START
rw 		MER
rw 		PER
rw 		PG
rw
Toggle Fields.

PG

Bit 0: Main flash program for bank1 command bit.

Allowed values:
1: Program: Flash programming activated

PER

Bit 1: Main flash page erase for bank1 command bit.

Allowed values:
1: PageErase: Erase activated for selected page

MER

Bit 2: Main flash mass erase for bank1 command bit.

Allowed values:
1: MassErase: Erase activated for all user sectors

START

Bit 6: Send erase command to FMC bit.

Allowed values:
1: Start: Trigger an erase operation

LK

Bit 7: FMC_CTL1 lock bit.

Allowed values:
0: Unlocked: CTL register is unlocked
1: Locked: CTL register is locked

ERRIE

Bit 10: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt generation disabled
1: Enabled: Error interrupt generation enabled

ENDIE

Bit 12: End of operation interrupt enable.

Allowed values:
0: Disabled: End of operation interrupt disabled
1: Enabled: End of operation interrupt enabled

ADDR1

Address register 1

Offset: 0x54, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
w
Toggle Fields.

ADDR

Bits 0-31: Flash erase/program command address bits.

Allowed values: 0-4294967295

WSEN

Wait state enable register

Offset: 0xFC, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WSEN
rw
Toggle Fields.

WSEN

Bit 0: FMC wait state enable.

Allowed values:
0: NoWaitState: No wait state added
1: WaitState: Wait state added

PID

Product ID register

Offset: 0x100, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PID
r
Toggle Fields.

PID

Bits 0-31: Product reserved ID code register.

Allowed values: 0-4294967295

FWDGT

0x40003000: free watchdog timer

5/5 fields covered. Toggle Registers.

CTL

Control register

Offset: 0x0, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMD
w
Toggle Fields.

CMD

Bits 0-15: Key value.

Allowed values:
21845: Enable: Enable access to PR, RLR and WINR registers (0x5555)
43690: Reset: Reset the watchdog value (0xAAAA)
52428: Start: Start the watchdog (0xCCCC)

PSC

Prescaler register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-2: Free watchdog timer prescaler selection.

Allowed values:
0: DivideBy4: Divider /4
1: DivideBy8: Divider /8
2: DivideBy16: Divider /16
3: DivideBy32: Divider /32
4: DivideBy64: Divider /64
5: DivideBy128: Divider /128
6: DivideBy256: Divider /256
7: DivideBy256bis: Divider /256

RLD

Reload register

Offset: 0x8, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RLD
rw
Toggle Fields.

RLD

Bits 0-11: Free watchdog timer counter reload value.

Allowed values: 0-4095

STAT

Status register

Offset: 0xC, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RUD
r 		PUD
r
Toggle Fields.

PUD

Bit 0: Free watchdog timer prescaler value update.

Allowed values:
0: Valid: The value read from the PSC register is valid
1: Ongoing: A write operation to to the PSC register is ongoing, so the value read is invalid

RUD

Bit 1: Free watchdog timer counter reload value update.

Allowed values:
0: Valid: The value read from the RLD register is valid
1: Ongoing: A write operation to to the RLD register is ongoing, so the value read is invalid

GPIOA

0x40010800: General-purpose I/Os

129/129 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK1

Bit 1: Port Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK2

Bit 2: Port Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK3

Bit 3: Port Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK4

Bit 4: Port Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK5

Bit 5: Port Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK6

Bit 6: Port Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK7

Bit 7: Port Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK8

Bit 8: Port Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK9

Bit 9: Port Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK10

Bit 10: Port Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK11

Bit 11: Port Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK12

Bit 12: Port Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK13

Bit 13: Port Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK14

Bit 14: Port Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK15

Bit 15: Port Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LKK

Bit 16: Lock sequence key .

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

GPIOB

0x40010C00: General-purpose I/Os

129/129 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK1

Bit 1: Port Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK2

Bit 2: Port Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK3

Bit 3: Port Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK4

Bit 4: Port Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK5

Bit 5: Port Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK6

Bit 6: Port Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK7

Bit 7: Port Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK8

Bit 8: Port Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK9

Bit 9: Port Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK10

Bit 10: Port Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK11

Bit 11: Port Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK12

Bit 12: Port Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK13

Bit 13: Port Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK14

Bit 14: Port Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK15

Bit 15: Port Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LKK

Bit 16: Lock sequence key .

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

GPIOC

0x40011000: General-purpose I/Os

129/129 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK1

Bit 1: Port Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK2

Bit 2: Port Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK3

Bit 3: Port Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK4

Bit 4: Port Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK5

Bit 5: Port Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK6

Bit 6: Port Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK7

Bit 7: Port Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK8

Bit 8: Port Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK9

Bit 9: Port Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK10

Bit 10: Port Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK11

Bit 11: Port Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK12

Bit 12: Port Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK13

Bit 13: Port Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK14

Bit 14: Port Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK15

Bit 15: Port Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LKK

Bit 16: Lock sequence key .

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

GPIOD

0x40011400: General-purpose I/Os

129/129 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK1

Bit 1: Port Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK2

Bit 2: Port Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK3

Bit 3: Port Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK4

Bit 4: Port Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK5

Bit 5: Port Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK6

Bit 6: Port Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK7

Bit 7: Port Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK8

Bit 8: Port Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK9

Bit 9: Port Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK10

Bit 10: Port Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK11

Bit 11: Port Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK12

Bit 12: Port Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK13

Bit 13: Port Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK14

Bit 14: Port Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK15

Bit 15: Port Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LKK

Bit 16: Lock sequence key .

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

GPIOE

0x40011800: General-purpose I/Os

129/129 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK1

Bit 1: Port Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK2

Bit 2: Port Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK3

Bit 3: Port Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK4

Bit 4: Port Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK5

Bit 5: Port Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK6

Bit 6: Port Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK7

Bit 7: Port Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK8

Bit 8: Port Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK9

Bit 9: Port Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK10

Bit 10: Port Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK11

Bit 11: Port Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK12

Bit 12: Port Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK13

Bit 13: Port Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK14

Bit 14: Port Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK15

Bit 15: Port Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LKK

Bit 16: Lock sequence key .

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

GPIOF

0x40011C00: General-purpose I/Os

129/129 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK1

Bit 1: Port Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK2

Bit 2: Port Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK3

Bit 3: Port Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK4

Bit 4: Port Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK5

Bit 5: Port Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK6

Bit 6: Port Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK7

Bit 7: Port Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK8

Bit 8: Port Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK9

Bit 9: Port Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK10

Bit 10: Port Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK11

Bit 11: Port Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK12

Bit 12: Port Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK13

Bit 13: Port Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK14

Bit 14: Port Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK15

Bit 15: Port Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LKK

Bit 16: Lock sequence key .

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

GPIOG

0x40012000: General-purpose I/Os

129/129 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK1

Bit 1: Port Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK2

Bit 2: Port Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK3

Bit 3: Port Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK4

Bit 4: Port Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK5

Bit 5: Port Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK6

Bit 6: Port Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK7

Bit 7: Port Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK8

Bit 8: Port Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK9

Bit 9: Port Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK10

Bit 10: Port Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK11

Bit 11: Port Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK12

Bit 12: Port Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK13

Bit 13: Port Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK14

Bit 14: Port Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK15

Bit 15: Port Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LKK

Bit 16: Lock sequence key .

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

GPIOH

0x40017400: General-purpose I/Os

129/129 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK1

Bit 1: Port Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK2

Bit 2: Port Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK3

Bit 3: Port Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK4

Bit 4: Port Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK5

Bit 5: Port Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK6

Bit 6: Port Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK7

Bit 7: Port Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK8

Bit 8: Port Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK9

Bit 9: Port Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK10

Bit 10: Port Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK11

Bit 11: Port Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK12

Bit 12: Port Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK13

Bit 13: Port Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK14

Bit 14: Port Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK15

Bit 15: Port Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LKK

Bit 16: Lock sequence key .

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

GPIOI

0x40017800: General-purpose I/Os

129/129 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK1

Bit 1: Port Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK2

Bit 2: Port Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK3

Bit 3: Port Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK4

Bit 4: Port Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK5

Bit 5: Port Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK6

Bit 6: Port Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK7

Bit 7: Port Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK8

Bit 8: Port Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK9

Bit 9: Port Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK10

Bit 10: Port Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK11

Bit 11: Port Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK12

Bit 12: Port Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK13

Bit 13: Port Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK14

Bit 14: Port Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK15

Bit 15: Port Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LKK

Bit 16: Lock sequence key .

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

I2C0

0x40005400: Inter integrated circuit

49/51 fields covered. Toggle Registers.

CTL0

Control register 0

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRESET
rw 		SALT
rw 		PECTRANS
rw 		POAP
rw 		ACKEN
rw 		STOP
rw 		START
rw 		SS
rw 		GCEN
rw 		PECEN
rw 		ARPEN
rw 		SMBSEL
rw 		SMBEN
rw 		I2CEN
rw
Toggle Fields.

I2CEN

Bit 0: I2C peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

SMBEN

Bit 1: SMBus/I2C mode switch.

Allowed values:
0: I2C: I2C Mode
1: SMBus: SMBus

SMBSEL

Bit 3: SMBusType Selection.

Allowed values:
0: Device: SMBus Device
1: Host: SMBus Host

ARPEN

Bit 4: ARP protocol in SMBus switch.

Allowed values:
0: Disabled: ARP disabled
1: Enabled: ARP enabled

PECEN

Bit 5: PEC Calculation Switch.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

GCEN

Bit 6: Whether or not to response to a General Call (0x00).

Allowed values:
0: NotRespond: Slave won't respond to General Call
1: Respond: Slave will respond to General Call

SS

Bit 7: Whether to stretch SCL low when data is not ready in slave mode.

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

START

Bit 8: Generate a START condition on I2C bus.

Allowed values:
0: NoStart: START will not be sent
1: Start: START will be sent

STOP

Bit 9: Generate a STOP condition on I2C bus.

Allowed values:
0: NoStop: STOP will not be sent
1: Stop: STOP will be sent

ACKEN

Bit 10: Whether or not to send an ACK.

Allowed values:
0: NAK: No acknowledge returned
1: ACK: Acknowledge returned after a byte is received

POAP

Bit 11: Position of ACK and PEC when receiving.

Allowed values:
0: Current: ACK bit controls the (N)ACK of the current byte being received
1: Next: ACK bit controls the (N)ACK of the next byte to be received

PECTRANS

Bit 12: PEC Transfer.

Allowed values:
0: Disabled: No PEC transfer
1: Enabled: PEC transfer

SALT

Bit 13: SMBus alert.

Allowed values:
0: Release: SMBA pin released high
1: Drive: SMBA pin driven low

SRESET

Bit 15: Software reset.

Allowed values:
0: NotReset: I2C peripheral not under reset
1: Reset: I2C peripheral under reset

CTL1

Control register 1

Offset: 0x4, reset: 0x0000, access: read-write

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMALST
rw 		DMAON
rw 		BUFIE
rw 		EVIE
rw 		ERRIE
rw 		I2CCLK
rw
Toggle Fields.

I2CCLK

Bits 0-5: I2C Peripheral clock frequency.

ERRIE

Bit 8: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

EVIE

Bit 9: Event interrupt enable.

Allowed values:
0: Disabled: Event interrupt disabled
1: Enabled: Event interrupt enabled

BUFIE

Bit 10: Buffer interrupt enable.

Allowed values:
0: Disabled: TBE=1 or RBNE=1 does not generate any interrupt
1: Enabled: TBE=1 or RBNE=1 generates Event interrupt

DMAON

Bit 11: DMA mode switch.

Allowed values:
0: Disabled: DMA requests disabled
1: Enabled: DMA requests enabled

DMALST

Bit 12: Flag indicating DMA last transfer.

Allowed values:
0: NotLast: Next DMA EOT is not the last transfer
1: Last: Next DMA EOT is the last transfer

SADDR0

Slave address register 0

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDFORMAT
rw 		ADDRESS
rw
Toggle Fields.

ADDRESS

Bits 0-9: Highest two bits of a 10-bit address.

Allowed values: 0-1023

ADDFORMAT

Bit 15: Address mode for the I2C slave.

Allowed values:
0: Add7: 7-bit slave address (note that you'll need to shift the address by 1b)
1: Add10: 10-bit slave address

SADDR1

Slave address register 1

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS2
rw 		DUADEN
rw
Toggle Fields.

DUADEN

Bit 0: Dual-Address mode switch.

Allowed values:
0: Single: Single addressing mode
1: Dual: Dual addressing mode

ADDRESS2

Bits 1-7: Second I2C address for the slave in Dual-Address mode.

Allowed values: 0-127

DATA

Transfer buffer register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRB
rw
Toggle Fields.

TRB

Bits 0-7: Transmission or reception data buffer.

Allowed values: 0-255

STAT0

Transfer status register 0

Offset: 0x14, reset: 0x0000, access: Unspecified

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALT
rw 		SMBTO
rw 		PECERR
rw 		OUERR
rw 		AERR
rw 		LOSTARB
rw 		BERR
rw 		TBE
r 		RBNE
r 		STPDET
r 		ADD10SEND
r 		BTC
r 		ADDSEND
r 		SBSEND
r
Toggle Fields.

SBSEND

Bit 0: START condition sent out in master mode.

Allowed values:
0: NoStart: No Start condition
1: Start: Start condition generated

ADDSEND

Bit 1: Address is sent in master mode or received and matches in slave mode.

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

BTC

Bit 2: Byte transmission completed.

Allowed values:
0: NotFinished: Data byte transfer not done
1: Finished: Data byte transfer successful

ADD10SEND

Bit 3: Header of 10-bit address is sent in master mode.

Allowed values:
0: NoHeader: No header of 10-bit address is sent
1: Header: Header of 10-bit address is sent

STPDET

Bit 4: STOP condition detected in slave mode.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

RBNE

Bit 6: I2C_DATA is not Empty during receiving.

Allowed values:
0: Empty: Data register empty
1: NotEmpty: Data register not empty, software can read

TBE

Bit 7: I2C_DATA is Empty during transmitting.

Allowed values:
0: NotEmpty: Data register not empty
1: Empty: Data register empty, software can write

BERR

Bit 8: A bus error occurs indication a unexpected START or STOP condition on I2C bus.

Allowed values:
0: NoError: No misplaced Start or Stop condition
1: Error: Misplaced Start or Stop condition

LOSTARB

Bit 9: Arbitration Lost in master mode.

Allowed values:
0: NoLost: No Arbitration Lost detected
1: Lost: Arbitration Lost detected

AERR

Bit 10: Acknowledge error.

Allowed values:
0: NoError: No acknowledge error
1: Error: Acknowledge error

OUERR

Bit 11: Over-run or under-run situation occurs in slave mode.

Allowed values:
0: NoOverrun: No overrun/underrun occured
1: Overrun: Overrun/underrun occured

PECERR

Bit 12: PEC error when receiving data.

Allowed values:
0: NoError: No PEC error
1: Error: PEC error

SMBTO

Bit 14: Timeout signal in SMBus mode.

Allowed values:
0: NoTimeout: No Timeout error
1: Timeout: SCL remained low for 25 ms

SMBALT

Bit 15: SMBus Alert status.

Allowed values:
0: NoAlert: SMBA not pulled down or no alert occured
1: Alert: SMBA pulled down or alert occurred

STAT1

Transfer status register 1

Offset: 0x18, reset: 0x0000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PECV
r 		DUMODF
r 		HSTSMB
r 		DEFSMB
r 		RXGC
r 		TR
r 		I2CBSY
r 		MASTER
r
Toggle Fields.

MASTER

Bit 0: A flag indicating whether I2C block is in master or slave mode.

Allowed values:
0: Slave: Slave mode
1: Master: Master mode

I2CBSY

Bit 1: Busy flag.

Allowed values:
0: NotBusy: No I2C communication
1: Busy: I2C communication active

TR

Bit 2: Whether the I2C is a transmitter or a receiver.

Allowed values:
0: Receiver: Receiver
1: Transmitter: Transmitter

RXGC

Bit 4: General call address (00h) received.

Allowed values:
0: NotReceived: No general call address received
1: Received: General call address received

DEFSMB

Bit 5: Default address of SMBusDevice.

Allowed values:
0: NotReceived: Default address has not been received
1: Received: Default address has been received

HSTSMB

Bit 6: SMBus Host Header detected in slave mode.

Allowed values:
0: NoHeader: No SMBus host header detected
1: Header: SMBus host header detected

DUMODF

Bit 7: Dual Flag in slave mode.

Allowed values:
0: SADDR0: The address matches SADDR0
1: SADDR1: The address matches SADDR1

PECV

Bits 8-15: Packet Error Checking Value that calculated by hardware when PEC is enabled.

Allowed values: 0-127

CKCFG

Clock configure register

Offset: 0x1C, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAST
rw 		DTCY
rw 		CLKC
rw
Toggle Fields.

CLKC

Bits 0-11: I2C Clock control in master mode.

Allowed values: 0-4095

DTCY

Bit 14: Duty cycle in fast mode.

Allowed values:
0: Duty2: Duty cycle t_low/t_high = 2
1: Duty16_9: Duty cycle t_low/t_high = 16/9

FAST

Bit 15: I2C speed selection in master mode.

Allowed values:
0: Standard: Standard mode I2C
1: Fast: Fast mode I2C

RT

Rise time register

Offset: 0x20, reset: 0x0002, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RISETIME
rw
Toggle Fields.

RISETIME

Bits 0-5: Maximum rise time in master mode.

I2C1

0x40005800: Inter integrated circuit

49/51 fields covered. Toggle Registers.

CTL0

Control register 0

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRESET
rw 		SALT
rw 		PECTRANS
rw 		POAP
rw 		ACKEN
rw 		STOP
rw 		START
rw 		SS
rw 		GCEN
rw 		PECEN
rw 		ARPEN
rw 		SMBSEL
rw 		SMBEN
rw 		I2CEN
rw
Toggle Fields.

I2CEN

Bit 0: I2C peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

SMBEN

Bit 1: SMBus/I2C mode switch.

Allowed values:
0: I2C: I2C Mode
1: SMBus: SMBus

SMBSEL

Bit 3: SMBusType Selection.

Allowed values:
0: Device: SMBus Device
1: Host: SMBus Host

ARPEN

Bit 4: ARP protocol in SMBus switch.

Allowed values:
0: Disabled: ARP disabled
1: Enabled: ARP enabled

PECEN

Bit 5: PEC Calculation Switch.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

GCEN

Bit 6: Whether or not to response to a General Call (0x00).

Allowed values:
0: NotRespond: Slave won't respond to General Call
1: Respond: Slave will respond to General Call

SS

Bit 7: Whether to stretch SCL low when data is not ready in slave mode.

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

START

Bit 8: Generate a START condition on I2C bus.

Allowed values:
0: NoStart: START will not be sent
1: Start: START will be sent

STOP

Bit 9: Generate a STOP condition on I2C bus.

Allowed values:
0: NoStop: STOP will not be sent
1: Stop: STOP will be sent

ACKEN

Bit 10: Whether or not to send an ACK.

Allowed values:
0: NAK: No acknowledge returned
1: ACK: Acknowledge returned after a byte is received

POAP

Bit 11: Position of ACK and PEC when receiving.

Allowed values:
0: Current: ACK bit controls the (N)ACK of the current byte being received
1: Next: ACK bit controls the (N)ACK of the next byte to be received

PECTRANS

Bit 12: PEC Transfer.

Allowed values:
0: Disabled: No PEC transfer
1: Enabled: PEC transfer

SALT

Bit 13: SMBus alert.

Allowed values:
0: Release: SMBA pin released high
1: Drive: SMBA pin driven low

SRESET

Bit 15: Software reset.

Allowed values:
0: NotReset: I2C peripheral not under reset
1: Reset: I2C peripheral under reset

CTL1

Control register 1

Offset: 0x4, reset: 0x0000, access: read-write

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMALST
rw 		DMAON
rw 		BUFIE
rw 		EVIE
rw 		ERRIE
rw 		I2CCLK
rw
Toggle Fields.

I2CCLK

Bits 0-5: I2C Peripheral clock frequency.

ERRIE

Bit 8: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

EVIE

Bit 9: Event interrupt enable.

Allowed values:
0: Disabled: Event interrupt disabled
1: Enabled: Event interrupt enabled

BUFIE

Bit 10: Buffer interrupt enable.

Allowed values:
0: Disabled: TBE=1 or RBNE=1 does not generate any interrupt
1: Enabled: TBE=1 or RBNE=1 generates Event interrupt

DMAON

Bit 11: DMA mode switch.

Allowed values:
0: Disabled: DMA requests disabled
1: Enabled: DMA requests enabled

DMALST

Bit 12: Flag indicating DMA last transfer.

Allowed values:
0: NotLast: Next DMA EOT is not the last transfer
1: Last: Next DMA EOT is the last transfer

SADDR0

Slave address register 0

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDFORMAT
rw 		ADDRESS
rw
Toggle Fields.

ADDRESS

Bits 0-9: Highest two bits of a 10-bit address.

Allowed values: 0-1023

ADDFORMAT

Bit 15: Address mode for the I2C slave.

Allowed values:
0: Add7: 7-bit slave address (note that you'll need to shift the address by 1b)
1: Add10: 10-bit slave address

SADDR1

Slave address register 1

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS2
rw 		DUADEN
rw
Toggle Fields.

DUADEN

Bit 0: Dual-Address mode switch.

Allowed values:
0: Single: Single addressing mode
1: Dual: Dual addressing mode

ADDRESS2

Bits 1-7: Second I2C address for the slave in Dual-Address mode.

Allowed values: 0-127

DATA

Transfer buffer register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRB
rw
Toggle Fields.

TRB

Bits 0-7: Transmission or reception data buffer.

Allowed values: 0-255

STAT0

Transfer status register 0

Offset: 0x14, reset: 0x0000, access: Unspecified

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALT
rw 		SMBTO
rw 		PECERR
rw 		OUERR
rw 		AERR
rw 		LOSTARB
rw 		BERR
rw 		TBE
r 		RBNE
r 		STPDET
r 		ADD10SEND
r 		BTC
r 		ADDSEND
r 		SBSEND
r
Toggle Fields.

SBSEND

Bit 0: START condition sent out in master mode.

Allowed values:
0: NoStart: No Start condition
1: Start: Start condition generated

ADDSEND

Bit 1: Address is sent in master mode or received and matches in slave mode.

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

BTC

Bit 2: Byte transmission completed.

Allowed values:
0: NotFinished: Data byte transfer not done
1: Finished: Data byte transfer successful

ADD10SEND

Bit 3: Header of 10-bit address is sent in master mode.

Allowed values:
0: NoHeader: No header of 10-bit address is sent
1: Header: Header of 10-bit address is sent

STPDET

Bit 4: STOP condition detected in slave mode.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

RBNE

Bit 6: I2C_DATA is not Empty during receiving.

Allowed values:
0: Empty: Data register empty
1: NotEmpty: Data register not empty, software can read

TBE

Bit 7: I2C_DATA is Empty during transmitting.

Allowed values:
0: NotEmpty: Data register not empty
1: Empty: Data register empty, software can write

BERR

Bit 8: A bus error occurs indication a unexpected START or STOP condition on I2C bus.

Allowed values:
0: NoError: No misplaced Start or Stop condition
1: Error: Misplaced Start or Stop condition

LOSTARB

Bit 9: Arbitration Lost in master mode.

Allowed values:
0: NoLost: No Arbitration Lost detected
1: Lost: Arbitration Lost detected

AERR

Bit 10: Acknowledge error.

Allowed values:
0: NoError: No acknowledge error
1: Error: Acknowledge error

OUERR

Bit 11: Over-run or under-run situation occurs in slave mode.

Allowed values:
0: NoOverrun: No overrun/underrun occured
1: Overrun: Overrun/underrun occured

PECERR

Bit 12: PEC error when receiving data.

Allowed values:
0: NoError: No PEC error
1: Error: PEC error

SMBTO

Bit 14: Timeout signal in SMBus mode.

Allowed values:
0: NoTimeout: No Timeout error
1: Timeout: SCL remained low for 25 ms

SMBALT

Bit 15: SMBus Alert status.

Allowed values:
0: NoAlert: SMBA not pulled down or no alert occured
1: Alert: SMBA pulled down or alert occurred

STAT1

Transfer status register 1

Offset: 0x18, reset: 0x0000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PECV
r 		DUMODF
r 		HSTSMB
r 		DEFSMB
r 		RXGC
r 		TR
r 		I2CBSY
r 		MASTER
r
Toggle Fields.

MASTER

Bit 0: A flag indicating whether I2C block is in master or slave mode.

Allowed values:
0: Slave: Slave mode
1: Master: Master mode

I2CBSY

Bit 1: Busy flag.

Allowed values:
0: NotBusy: No I2C communication
1: Busy: I2C communication active

TR

Bit 2: Whether the I2C is a transmitter or a receiver.

Allowed values:
0: Receiver: Receiver
1: Transmitter: Transmitter

RXGC

Bit 4: General call address (00h) received.

Allowed values:
0: NotReceived: No general call address received
1: Received: General call address received

DEFSMB

Bit 5: Default address of SMBusDevice.

Allowed values:
0: NotReceived: Default address has not been received
1: Received: Default address has been received

HSTSMB

Bit 6: SMBus Host Header detected in slave mode.

Allowed values:
0: NoHeader: No SMBus host header detected
1: Header: SMBus host header detected

DUMODF

Bit 7: Dual Flag in slave mode.

Allowed values:
0: SADDR0: The address matches SADDR0
1: SADDR1: The address matches SADDR1

PECV

Bits 8-15: Packet Error Checking Value that calculated by hardware when PEC is enabled.

Allowed values: 0-127

CKCFG

Clock configure register

Offset: 0x1C, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAST
rw 		DTCY
rw 		CLKC
rw
Toggle Fields.

CLKC

Bits 0-11: I2C Clock control in master mode.

Allowed values: 0-4095

DTCY

Bit 14: Duty cycle in fast mode.

Allowed values:
0: Duty2: Duty cycle t_low/t_high = 2
1: Duty16_9: Duty cycle t_low/t_high = 16/9

FAST

Bit 15: I2C speed selection in master mode.

Allowed values:
0: Standard: Standard mode I2C
1: Fast: Fast mode I2C

RT

Rise time register

Offset: 0x20, reset: 0x0002, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RISETIME
rw
Toggle Fields.

RISETIME

Bits 0-5: Maximum rise time in master mode.

I2C2

0x4000C000: Inter integrated circuit

49/51 fields covered. Toggle Registers.

CTL0

Control register 0

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRESET
rw 		SALT
rw 		PECTRANS
rw 		POAP
rw 		ACKEN
rw 		STOP
rw 		START
rw 		SS
rw 		GCEN
rw 		PECEN
rw 		ARPEN
rw 		SMBSEL
rw 		SMBEN
rw 		I2CEN
rw
Toggle Fields.

I2CEN

Bit 0: I2C peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

SMBEN

Bit 1: SMBus/I2C mode switch.

Allowed values:
0: I2C: I2C Mode
1: SMBus: SMBus

SMBSEL

Bit 3: SMBusType Selection.

Allowed values:
0: Device: SMBus Device
1: Host: SMBus Host

ARPEN

Bit 4: ARP protocol in SMBus switch.

Allowed values:
0: Disabled: ARP disabled
1: Enabled: ARP enabled

PECEN

Bit 5: PEC Calculation Switch.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

GCEN

Bit 6: Whether or not to response to a General Call (0x00).

Allowed values:
0: NotRespond: Slave won't respond to General Call
1: Respond: Slave will respond to General Call

SS

Bit 7: Whether to stretch SCL low when data is not ready in slave mode.

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

START

Bit 8: Generate a START condition on I2C bus.

Allowed values:
0: NoStart: START will not be sent
1: Start: START will be sent

STOP

Bit 9: Generate a STOP condition on I2C bus.

Allowed values:
0: NoStop: STOP will not be sent
1: Stop: STOP will be sent

ACKEN

Bit 10: Whether or not to send an ACK.

Allowed values:
0: NAK: No acknowledge returned
1: ACK: Acknowledge returned after a byte is received

POAP

Bit 11: Position of ACK and PEC when receiving.

Allowed values:
0: Current: ACK bit controls the (N)ACK of the current byte being received
1: Next: ACK bit controls the (N)ACK of the next byte to be received

PECTRANS

Bit 12: PEC Transfer.

Allowed values:
0: Disabled: No PEC transfer
1: Enabled: PEC transfer

SALT

Bit 13: SMBus alert.

Allowed values:
0: Release: SMBA pin released high
1: Drive: SMBA pin driven low

SRESET

Bit 15: Software reset.

Allowed values:
0: NotReset: I2C peripheral not under reset
1: Reset: I2C peripheral under reset

CTL1

Control register 1

Offset: 0x4, reset: 0x0000, access: read-write

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMALST
rw 		DMAON
rw 		BUFIE
rw 		EVIE
rw 		ERRIE
rw 		I2CCLK
rw
Toggle Fields.

I2CCLK

Bits 0-5: I2C Peripheral clock frequency.

ERRIE

Bit 8: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

EVIE

Bit 9: Event interrupt enable.

Allowed values:
0: Disabled: Event interrupt disabled
1: Enabled: Event interrupt enabled

BUFIE

Bit 10: Buffer interrupt enable.

Allowed values:
0: Disabled: TBE=1 or RBNE=1 does not generate any interrupt
1: Enabled: TBE=1 or RBNE=1 generates Event interrupt

DMAON

Bit 11: DMA mode switch.

Allowed values:
0: Disabled: DMA requests disabled
1: Enabled: DMA requests enabled

DMALST

Bit 12: Flag indicating DMA last transfer.

Allowed values:
0: NotLast: Next DMA EOT is not the last transfer
1: Last: Next DMA EOT is the last transfer

SADDR0

Slave address register 0

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDFORMAT
rw 		ADDRESS
rw
Toggle Fields.

ADDRESS

Bits 0-9: Highest two bits of a 10-bit address.

Allowed values: 0-1023

ADDFORMAT

Bit 15: Address mode for the I2C slave.

Allowed values:
0: Add7: 7-bit slave address (note that you'll need to shift the address by 1b)
1: Add10: 10-bit slave address

SADDR1

Slave address register 1

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS2
rw 		DUADEN
rw
Toggle Fields.

DUADEN

Bit 0: Dual-Address mode switch.

Allowed values:
0: Single: Single addressing mode
1: Dual: Dual addressing mode

ADDRESS2

Bits 1-7: Second I2C address for the slave in Dual-Address mode.

Allowed values: 0-127

DATA

Transfer buffer register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRB
rw
Toggle Fields.

TRB

Bits 0-7: Transmission or reception data buffer.

Allowed values: 0-255

STAT0

Transfer status register 0

Offset: 0x14, reset: 0x0000, access: Unspecified

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALT
rw 		SMBTO
rw 		PECERR
rw 		OUERR
rw 		AERR
rw 		LOSTARB
rw 		BERR
rw 		TBE
r 		RBNE
r 		STPDET
r 		ADD10SEND
r 		BTC
r 		ADDSEND
r 		SBSEND
r
Toggle Fields.

SBSEND

Bit 0: START condition sent out in master mode.

Allowed values:
0: NoStart: No Start condition
1: Start: Start condition generated

ADDSEND

Bit 1: Address is sent in master mode or received and matches in slave mode.

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

BTC

Bit 2: Byte transmission completed.

Allowed values:
0: NotFinished: Data byte transfer not done
1: Finished: Data byte transfer successful

ADD10SEND

Bit 3: Header of 10-bit address is sent in master mode.

Allowed values:
0: NoHeader: No header of 10-bit address is sent
1: Header: Header of 10-bit address is sent

STPDET

Bit 4: STOP condition detected in slave mode.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

RBNE

Bit 6: I2C_DATA is not Empty during receiving.

Allowed values:
0: Empty: Data register empty
1: NotEmpty: Data register not empty, software can read

TBE

Bit 7: I2C_DATA is Empty during transmitting.

Allowed values:
0: NotEmpty: Data register not empty
1: Empty: Data register empty, software can write

BERR

Bit 8: A bus error occurs indication a unexpected START or STOP condition on I2C bus.

Allowed values:
0: NoError: No misplaced Start or Stop condition
1: Error: Misplaced Start or Stop condition

LOSTARB

Bit 9: Arbitration Lost in master mode.

Allowed values:
0: NoLost: No Arbitration Lost detected
1: Lost: Arbitration Lost detected

AERR

Bit 10: Acknowledge error.

Allowed values:
0: NoError: No acknowledge error
1: Error: Acknowledge error

OUERR

Bit 11: Over-run or under-run situation occurs in slave mode.

Allowed values:
0: NoOverrun: No overrun/underrun occured
1: Overrun: Overrun/underrun occured

PECERR

Bit 12: PEC error when receiving data.

Allowed values:
0: NoError: No PEC error
1: Error: PEC error

SMBTO

Bit 14: Timeout signal in SMBus mode.

Allowed values:
0: NoTimeout: No Timeout error
1: Timeout: SCL remained low for 25 ms

SMBALT

Bit 15: SMBus Alert status.

Allowed values:
0: NoAlert: SMBA not pulled down or no alert occured
1: Alert: SMBA pulled down or alert occurred

STAT1

Transfer status register 1

Offset: 0x18, reset: 0x0000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PECV
r 		DUMODF
r 		HSTSMB
r 		DEFSMB
r 		RXGC
r 		TR
r 		I2CBSY
r 		MASTER
r
Toggle Fields.

MASTER

Bit 0: A flag indicating whether I2C block is in master or slave mode.

Allowed values:
0: Slave: Slave mode
1: Master: Master mode

I2CBSY

Bit 1: Busy flag.

Allowed values:
0: NotBusy: No I2C communication
1: Busy: I2C communication active

TR

Bit 2: Whether the I2C is a transmitter or a receiver.

Allowed values:
0: Receiver: Receiver
1: Transmitter: Transmitter

RXGC

Bit 4: General call address (00h) received.

Allowed values:
0: NotReceived: No general call address received
1: Received: General call address received

DEFSMB

Bit 5: Default address of SMBusDevice.

Allowed values:
0: NotReceived: Default address has not been received
1: Received: Default address has been received

HSTSMB

Bit 6: SMBus Host Header detected in slave mode.

Allowed values:
0: NoHeader: No SMBus host header detected
1: Header: SMBus host header detected

DUMODF

Bit 7: Dual Flag in slave mode.

Allowed values:
0: SADDR0: The address matches SADDR0
1: SADDR1: The address matches SADDR1

PECV

Bits 8-15: Packet Error Checking Value that calculated by hardware when PEC is enabled.

Allowed values: 0-127

CKCFG

Clock configure register

Offset: 0x1C, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAST
rw 		DTCY
rw 		CLKC
rw
Toggle Fields.

CLKC

Bits 0-11: I2C Clock control in master mode.

Allowed values: 0-4095

DTCY

Bit 14: Duty cycle in fast mode.

Allowed values:
0: Duty2: Duty cycle t_low/t_high = 2
1: Duty16_9: Duty cycle t_low/t_high = 16/9

FAST

Bit 15: I2C speed selection in master mode.

Allowed values:
0: Standard: Standard mode I2C
1: Fast: Fast mode I2C

RT

Rise time register

Offset: 0x20, reset: 0x0002, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RISETIME
rw
Toggle Fields.

RISETIME

Bits 0-5: Maximum rise time in master mode.

NVIC

0xE000E000: Nested Vectored Interrupt Controller

4/113 fields covered. Toggle Registers.

ICTR

Interrupt Controller Type Register

Offset: 0x4, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTLINESNUM
r
Toggle Fields.

INTLINESNUM

Bits 0-3: Total number of interrupt lines in groups.

ISER0

Interrupt Set-Enable Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER1

Interrupt Set-Enable Register

Offset: 0x104, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER2

Interrupt Set-Enable Register

Offset: 0x108, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ICER0

Interrupt Clear-Enable Register

Offset: 0x180, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER1

Interrupt Clear-Enable Register

Offset: 0x184, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER2

Interrupt Clear-Enable Register

Offset: 0x188, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ISPR0

Interrupt Set-Pending Register

Offset: 0x200, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR1

Interrupt Set-Pending Register

Offset: 0x204, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR2

Interrupt Set-Pending Register

Offset: 0x208, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ICPR0

Interrupt Clear-Pending Register

Offset: 0x280, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR1

Interrupt Clear-Pending Register

Offset: 0x284, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR2

Interrupt Clear-Pending Register

Offset: 0x288, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

IABR0

Interrupt Active Bit Register

Offset: 0x300, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle Fields.

ACTIVE

Bits 0-31: ACTIVE.

IABR1

Interrupt Active Bit Register

Offset: 0x304, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle Fields.

ACTIVE

Bits 0-31: ACTIVE.

IABR2

Interrupt Active Bit Register

Offset: 0x308, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle Fields.

ACTIVE

Bits 0-31: ACTIVE.

IPR0

Interrupt Priority Register

Offset: 0x400, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR1

Interrupt Priority Register

Offset: 0x404, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR2

Interrupt Priority Register

Offset: 0x408, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR3

Interrupt Priority Register

Offset: 0x40C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR4

Interrupt Priority Register

Offset: 0x410, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR5

Interrupt Priority Register

Offset: 0x414, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR6

Interrupt Priority Register

Offset: 0x418, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR7

Interrupt Priority Register

Offset: 0x41C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR8

Interrupt Priority Register

Offset: 0x420, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR9

Interrupt Priority Register

Offset: 0x424, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR10

Interrupt Priority Register

Offset: 0x428, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR11

Interrupt Priority Register

Offset: 0x42C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR12

Interrupt Priority Register

Offset: 0x430, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR13

Interrupt Priority Register

Offset: 0x434, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR14

Interrupt Priority Register

Offset: 0x438, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR15

Interrupt Priority Register

Offset: 0x43C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR16

Interrupt Priority Register

Offset: 0x440, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR17

Interrupt Priority Register

Offset: 0x444, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR18

Interrupt Priority Register

Offset: 0x448, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR19

Interrupt Priority Register

Offset: 0x44C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR20

Interrupt Priority Register

Offset: 0x450, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR21

Interrupt Priority Register

Offset: 0x454, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR22

Interrupt Priority Register

Offset: 0x458, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR23

Interrupt Priority Register

Offset: 0x45C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

STIR

Software Triggered Interrupt Register

Offset: 0xF00, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTID
w
Toggle Fields.

INTID

Bits 0-8: interrupt to be triggered.

PMU

0x40007000: Power management unit

11/11 fields covered. Toggle Registers.

CTL

power control register

Offset: 0x0, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKPWEN
rw 		LVDT
rw 		LVDEN
rw 		STBRST
rw 		WURST
rw 		STBMOD
rw 		LDOLP
rw
Toggle Fields.

LDOLP

Bit 0: LDO Low Power Mode.

Allowed values:
0: Normal: LDO operates normally during Deepsleep mode
1: LowPower: LDO in low-power mode during Deepsleep mode

STBMOD

Bit 1: Standby Mode.

Allowed values:
0: DeepSleep: Enter Deep-sleep mode when the CPU enters deepsleep
1: Standby: Enter Standby mode when the CPU enters deepsleep

WURST

Bit 2: Wakeup Flag Reset.

Allowed values:
1: Clear: Clear the wakeup flag

STBRST

Bit 3: Standby Flag Reset.

Allowed values:
1: Clear: Clear the standby flag

LVDEN

Bit 4: Low Voltage Detector Enable.

Allowed values:
0: Disabled: Low voltage detector disabled
1: Enabled: Low voltage detector enabled

LVDT

Bits 5-7: Low Voltage Detector Threshold.

Allowed values:
0: V2_2: 2.2 V
1: V2_3: 2.3 V
2: V2_4: 2.4 V
3: V2_5: 2.5 V
4: V2_6: 2.6 V
5: V2_7: 2.7 V
6: V2_8: 2.8 V
7: V2_9: 2.9 V

BKPWEN

Bit 8: Backup Domain Write Enable.

Allowed values:
0: Disabled: Access to backup domain registers disabled
1: Enabled: Access to backup domain registers enabled

CS

power control/status register

Offset: 0x4, reset: 0x00000000, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUPEN0
rw 		LVDF
r 		STBF
r 		WUF
r
Toggle Fields.

WUF

Bit 0: Wakeup flag.

Allowed values:
0: NoWakeupEvent: No wakeup event occurred
1: WakeupEvent: A wakeup event was received from the WKUP pin or from the RTC wakeup event (RTC Tamper event, RTC TimeStamp event or RTC alarm)

STBF

Bit 1: Standby flag.

Allowed values:
0: NoStandbyEvent: Device has not been in Standby mode
1: StandbyEvent: Device has been in Standby mode

LVDF

Bit 2: Low Voltage Detector Status Flag.

Allowed values:
0: AboveThreshold: VDD is higher than the LVD threshold
1: BelowThreshold: VDD is lower than or equal to the LVD threshold

WUPEN0

Bit 8: Enable WKUP pin.

Allowed values:
0: Disabled: WKUP pin 0 is used for general purpose I/Os. An event on the WKUP pin 0 does not wakeup the device from Standby mode
1: Enabled: WKUP pin 0 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 0 wakes-up the system from Standby mode)

RCU

0x40021000: Reset and clock unit

157/203 fields covered. Toggle Registers.

CTL0

Control register

Offset: 0x0, reset: 0x00000083, access: Unspecified

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL2STB
r 		PLL2EN
rw 		PLL1STB
r 		PLL1EN
rw 		PLLSTB
r 		PLLEN
rw 		CKMEN
rw 		HXTALBPS
rw 		HXTALSTB
r 		HXTALEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRC8MCALIB
r 		IRC8MADJ
rw 		IRC8MSTB
r 		IRC8MEN
rw
Toggle Fields.

IRC8MEN

Bit 0: Internal 8MHz RC oscillator Enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

IRC8MSTB

Bit 1: IRC8M Internal 8MHz RC Oscillator stabilization Flag.

Allowed values:
0: NotReady: IRC8M is not stable
1: Ready: IRC8M is stable

IRC8MADJ

Bits 3-7: Internal 8MHz RC Oscillator clock trim adjust value.

Allowed values: 0-31

IRC8MCALIB

Bits 8-15: Internal 8MHz RC Oscillator calibration value register.

Allowed values: 0-255

HXTALEN

Bit 16: External High Speed oscillator Enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

HXTALSTB

Bit 17: External crystal oscillator (HXTAL) clock stabilization flag.

Allowed values:
0: NotReady: HXTAL is not stable
1: Ready: HXTAL is stable

HXTALBPS

Bit 18: External crystal oscillator (HXTAL) clock bypass mode enable.

Allowed values:
0: NotBypassed: HXTAL crystal oscillator not bypassed
1: Bypassed: HXTAL crystal oscillator bypassed with external clock

CKMEN

Bit 19: HXTAL Clock Monitor Enable.

Allowed values:
0: Off: Clock monitor disabled
1: On: Clock monitor enabled

PLLEN

Bit 24: PLL enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

PLLSTB

Bit 25: PLL Clock Stabilization Flag.

Allowed values:
0: NotReady: PLL is not stable
1: Ready: PLL is stable

PLL1EN

Bit 26: PLL1 enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

PLL1STB

Bit 27: PLL1 Clock Stabilization Flag.

Allowed values:
0: NotReady: PLL is not stable
1: Ready: PLL is stable

PLL2EN

Bit 28: PLL2 enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

PLL2STB

Bit 29: PLL2 Clock Stabilization Flag.

Allowed values:
0: NotReady: PLL is not stable
1: Ready: PLL is stable

CFG0

Clock configuration register 0 (RCU_CFG0)

Offset: 0x4, reset: 0x00000000, access: Unspecified

11/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLMF_MSB
rw 		CKOUTSEL
rw 		USBFSPSC
rw 		PLLMF
rw 		PLLPREDV
rw 		ADCPSC
N/A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCPSC
N/A 		APB2PSC
rw 		APB1PSC
rw 		AHBPSC
rw 		SCSS
r 		SCS
rw
Toggle Fields.

SCS

Bits 0-1: System clock switch.

Allowed values:
0: IRC8M: IRC8M used as system clock
1: HXTAL: HXTAL used as system clock
2: PLL: PLL used as system clock

SCSS

Bits 2-3: System clock switch status.

Allowed values:
0: IRC8M: IRC8M used as system clock
1: HXTAL: HXTAL used as system clock
2: PLL: PLL used as system clock

AHBPSC

Bits 4-7: AHB prescaler selection.

Allowed values:
0: Div1: CK_SYS
8: Div2: CK_SYS divided by 2
9: Div4: CK_SYS divided by 4
10: Div8: CK_SYS divided by 8
11: Div16: CK_SYS divided by 16
12: Div64: CK_SYS divided by 64
13: Div128: CK_SYS divided by 128
14: Div256: CK_SYS divided by 256
15: Div512: CK_SYS divided by 512

APB1PSC

Bits 8-10: APB1 prescaler selection.

Allowed values:
0: Div1: CK_AHB
4: Div2: CK_AHB divided by 2
5: Div4: CK_AHB divided by 4
6: Div8: CK_AHB divided by 8
7: Div16: CK_AHB divided by 16

APB2PSC

Bits 11-13: APB2 prescaler selection.

Allowed values:
0: Div1: CK_AHB
4: Div2: CK_AHB divided by 2
5: Div4: CK_AHB divided by 4
6: Div8: CK_AHB divided by 8
7: Div16: CK_AHB divided by 16

ADCPSC

Bits 14-16: ADC clock prescaler selection.

Allowed values:
4: Div12: CK_APB2 divided by 12
5: Div16: CK_APB2 divided by 16
0: Div2: CK_APB2 divided by 2
1: Div4: CK_APB2 divided by 4
2: Div6: CK_APB2 divided by 6
3: Div8: CK_APB2 divided by 8

PLLSEL

Bit 16: PLL Clock Source Selection.

Allowed values:
0: IRC8M_2: IRC8M / 2 selected as PLL source clock
1: HXTAL: HXTAL selected as PLL source clock

PLLPREDV

Bit 17: The LSB of PREDV0 division factor.

Allowed values:
0: Div1: HXTAL clock not divided
1: Div2: HXTAL clock divided by 2

PLLMF

Bits 18-21: The PLL clock multiplication factor.

Allowed values:
0: Mul2: PLL input clock x2
1: Mul3: PLL input clock x3
2: Mul4: PLL input clock x4
3: Mul5: PLL input clock x5
4: Mul6: PLL input clock x6
5: Mul7: PLL input clock x7
6: Mul8: PLL input clock x8
7: Mul9: PLL input clock x9
8: Mul10: PLL input clock x10
9: Mul11: PLL input clock x11
10: Mul12: PLL input clock x12
11: Mul13: PLL input clock x13
12: Mul14: PLL input clock x14
13: Mul15: PLL input clock x15
14: Mul16: PLL input clock x16
15: Mul16x: PLL input clock x16

USBFSPSC

Bits 22-23: USBFS clock prescaler selection.

CKOUTSEL

Bits 24-27: CKOUT0 Clock Source Selection.

Allowed values:
0: None: No clock selected
1: IRC14M: Internal 14 MHz RC oscillator clock selected
2: LSI40K: Internal 40 kHz RC oscillator clock selected
3: LXTAL: External low speed oscillator clock selected
4: SYSCLK: System clock selected
5: IRC8M: Internal RC 8 MHz (HSI) oscillator clock selected
6: HXTAL: External 4-32 MHz (HSE) oscillator clock selected
7: PLL: PLL clock selected (divided by 1 or 2, depending on PLLDV)

PLLMF_MSB

Bit 29: Bit 4 of PLLMF.

Allowed values:
0: None: Value of PLLMF is as set
1: Plus15: Add 15 to the value of PLLMF

INT

Clock interrupt register (RCU_INT)

Offset: 0x8, reset: 0x00000000, access: Unspecified

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKMIC
w 		PLL2STBIC
w 		PLL1STBIC
w 		PLLSTBIC
w 		HXTALSTBIC
w 		IRC8MSTBIC
w 		LXTALSTBIC
w 		IRC40KSTBIC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL2STBIE
rw 		PLL1STBIE
rw 		PLLSTBIE
rw 		HXTALSTBIE
rw 		IRC8MSTBIE
rw 		LXTALSTBIE
rw 		IRC40KSTBIE
rw 		CKMIF
r 		PLL2STBIF
r 		PLL1STBIF
r 		PLLSTBIF
r 		HXTALSTBIF
r 		IRC8MSTBIF
r 		LXTALSTBIF
r 		IRC40KSTBIF
r
Toggle Fields.

IRC40KSTBIF

Bit 0: IRC40K stabilization interrupt flag.

Allowed values:
0: NotInterrupted: No interrupt generated
1: Interrupted: IRC40K stabilisation interrupt generated

LXTALSTBIF

Bit 1: LXTAL stabilization interrupt flag.

Allowed values:
0: NotInterrupted: No interrupt generated
1: Interrupted: LXTAL stabilisation interrupt generated

IRC8MSTBIF

Bit 2: IRC8M stabilization interrupt flag.

Allowed values:
0: NotInterrupted: No interrupt generated
1: Interrupted: IRC8M stabilisation interrupt generated

HXTALSTBIF

Bit 3: HXTAL stabilization interrupt flag.

Allowed values:
0: NotInterrupted: No interrupt generated
1: Interrupted: HXTAL stabilisation interrupt generated

PLLSTBIF

Bit 4: PLL stabilization interrupt flag.

Allowed values:
0: NotInterrupted: No interrupt generated
1: Interrupted: PLL stabilisation interrupt generated

PLL1STBIF

Bit 5: PLL1 stabilization interrupt flag.

Allowed values:
0: NotInterrupted: No interrupt generated
1: Interrupted: PLL stabilisation interrupt generated

PLL2STBIF

Bit 6: PLL2 stabilization interrupt flag.

Allowed values:
0: NotInterrupted: No interrupt generated
1: Interrupted: PLL stabilisation interrupt generated

CKMIF

Bit 7: HXTAL Clock Stuck Interrupt Flag.

Allowed values:
0: NotInterrupted: Clock operating normally
1: Interrupted: HXTAL clock stuck

IRC40KSTBIE

Bit 8: IRC40K Stabilization interrupt enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

LXTALSTBIE

Bit 9: LXTAL Stabilization Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

IRC8MSTBIE

Bit 10: IRC8M Stabilization Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HXTALSTBIE

Bit 11: HXTAL Stabilization Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

PLLSTBIE

Bit 12: PLL Stabilization Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

PLL1STBIE

Bit 13: PLL1 Stabilization Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

PLL2STBIE

Bit 14: PLL2 Stabilization Interrupt Enable.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

IRC40KSTBIC

Bit 16: IRC40K Stabilization Interrupt Clear.

Allowed values:
1: Clear: Clear IRC40KSTBIF flag

LXTALSTBIC

Bit 17: LXTAL Stabilization Interrupt Clear.

Allowed values:
1: Clear: Clear LXTALSTBIF flag

IRC8MSTBIC

Bit 18: IRC8M Stabilization Interrupt Clear.

Allowed values:
1: Clear: Clear IRC8MSTBIF flag

HXTALSTBIC

Bit 19: HXTAL Stabilization Interrupt Clear.

Allowed values:
1: Clear: Clear HXTALSTBIF flag

PLLSTBIC

Bit 20: PLL stabilization Interrupt Clear.

Allowed values:
1: Clear: Clear PLLSTBIF flag

PLL1STBIC

Bit 21: PLL1 stabilization Interrupt Clear.

Allowed values:
1: Clear: Clear PLLSTBIF flag

PLL2STBIC

Bit 22: PLL2 stabilization Interrupt Clear.

Allowed values:
1: Clear: Clear PLLSTBIF flag

CKMIC

Bit 23: HXTAL Clock Stuck Interrupt Clear.

Allowed values:
1: Clear: Clear CKMIF flag

APB2RST

APB2 reset register (RCU_APB2RST)

Offset: 0xC, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIMER10RST
rw 		TIMER9RST
rw 		TIMER8RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC2RST
rw 		USART0RST
rw 		TIMER7RST
rw 		SPI0RST
rw 		TIMER0RST
rw 		ADC1RST
rw 		ADC0RST
rw 		PGRST
rw 		PFRST
rw 		PERST
rw 		PDRST
rw 		PCRST
rw 		PBRST
rw 		PARST
rw 		AFRST
rw
Toggle Fields.

AFRST

Bit 0: Alternate function I/O reset.

Allowed values:
1: Reset: Reset the selected module

PARST

Bit 2: GPIO port A reset.

Allowed values:
1: Reset: Reset the selected module

PBRST

Bit 3: GPIO port B reset.

Allowed values:
1: Reset: Reset the selected module

PCRST

Bit 4: GPIO port C reset.

Allowed values:
1: Reset: Reset the selected module

PDRST

Bit 5: GPIO port D reset.

Allowed values:
1: Reset: Reset the selected module

PERST

Bit 6: GPIO port E reset.

Allowed values:
1: Reset: Reset the selected module

PFRST

Bit 7: GPIO portF reset.

Allowed values:
1: Reset: Reset the selected module

PGRST

Bit 8: GPIO port G reset.

Allowed values:
1: Reset: Reset the selected module

ADC0RST

Bit 9: ADC0 reset.

Allowed values:
1: Reset: Reset the selected module

ADC1RST

Bit 10: ADC1 reset.

Allowed values:
1: Reset: Reset the selected module

TIMER0RST

Bit 11: Timer 0 reset.

Allowed values:
1: Reset: Reset the selected module

SPI0RST

Bit 12: SPI0 reset.

Allowed values:
1: Reset: Reset the selected module

TIMER7RST

Bit 13: Timer 7 reset.

Allowed values:
1: Reset: Reset the selected module

USART0RST

Bit 14: USART0 Reset.

Allowed values:
1: Reset: Reset the selected module

ADC2RST

Bit 15: ADC2 reset.

Allowed values:
1: Reset: Reset the selected module

TIMER8RST

Bit 19: Timer 8 reset.

Allowed values:
1: Reset: Reset the selected module

TIMER9RST

Bit 20: Timer 9 reset.

Allowed values:
1: Reset: Reset the selected module

TIMER10RST

Bit 21: Timer 10 reset.

Allowed values:
1: Reset: Reset the selected module

APB1RST

APB1 reset register (RCU_APB1RST)

Offset: 0x10, reset: 0x00000000, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACRST
rw 		PMURST
rw 		BKPIRST
rw 		CAN1RST
rw 		CAN0RST
rw 		I2C1RST
rw 		I2C0RST
rw 		UART4RST
rw 		UART3RST
rw 		USART2RST
rw 		USART1RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2RST
rw 		SPI1RST
rw 		WWDGTRST
rw 		TIMER13RST
rw 		TIMER12RST
rw 		TIMER11RST
rw 		TIMER6RST
rw 		TIMER5RST
rw 		TIMER4RST
rw 		TIMER3RST
rw 		TIMER2RST
rw 		TIMER1RST
rw
Toggle Fields.

TIMER1RST

Bit 0: TIMER1 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIMER2RST

Bit 1: TIMER2 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIMER3RST

Bit 2: TIMER3 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIMER4RST

Bit 3: TIMER4 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIMER5RST

Bit 4: TIMER5 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIMER6RST

Bit 5: TIMER6 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIMER11RST

Bit 6: TIMER11 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIMER12RST

Bit 7: TIMER12 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIMER13RST

Bit 8: TIMER13 timer reset.

Allowed values:
1: Reset: Reset the selected module

WWDGTRST

Bit 11: Window watchdog timer reset.

Allowed values:
1: Reset: Reset the selected module

SPI1RST

Bit 14: SPI1 reset.

Allowed values:
1: Reset: Reset the selected module

SPI2RST

Bit 15: SPI2 reset.

Allowed values:
1: Reset: Reset the selected module

USART1RST

Bit 17: USART1 reset.

Allowed values:
1: Reset: Reset the selected module

USART2RST

Bit 18: USART2 reset.

Allowed values:
1: Reset: Reset the selected module

UART3RST

Bit 19: UART3 reset.

Allowed values:
1: Reset: Reset the selected module

UART4RST

Bit 20: UART4 reset.

Allowed values:
1: Reset: Reset the selected module

I2C0RST

Bit 21: I2C0 reset.

Allowed values:
1: Reset: Reset the selected module

I2C1RST

Bit 22: I2C1 reset.

Allowed values:
1: Reset: Reset the selected module

CAN0RST

Bit 25: CAN0 reset.

Allowed values:
1: Reset: Reset the selected module

CAN1RST

Bit 26: CAN1 reset.

Allowed values:
1: Reset: Reset the selected module

BKPIRST

Bit 27: Backup interface reset.

Allowed values:
1: Reset: Reset the selected module

PMURST

Bit 28: Power control reset.

Allowed values:
1: Reset: Reset the selected module

DACRST

Bit 29: DAC reset.

Allowed values:
1: Reset: Reset the selected module

AHB1EN

AHB1 enable register

Offset: 0x14, reset: 0x00000014, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENETRXEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENETTXEN
rw 		ENETEN
rw 		USBFSEN
rw 		SDIOEN
rw 		EXMCEN
rw 		CRCEN
rw 		FMCSPEN
rw 		SRAMSPEN
rw 		DMA1EN
rw 		DMA0EN
rw
Toggle Fields.

DMA0EN

Bit 0: DMA0 clock enable.

DMA1EN

Bit 1: DMA1 clock enable.

SRAMSPEN

Bit 2: SRAM interface clock enable when sleep mode.

FMCSPEN

Bit 4: FMC clock enable when sleep mode.

CRCEN

Bit 6: CRC clock enable.

EXMCEN

Bit 8: EXMC clock enable.

SDIOEN

Bit 10: SDIO clock enable.

USBFSEN

Bit 12: USBFS clock enable.

ENETEN

Bit 14: Ethernet clock enable.

ENETTXEN

Bit 15: Ethernet TX clock enable.

ENETRXEN

Bit 16: Ethernet RX clock enable.

APB2EN

APB2 clock enable register (RCU_APB2EN)

Offset: 0x18, reset: 0x00000000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIMER10EN
rw 		TIMER9EN
rw 		TIMER8EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC2EN
rw 		USART0EN
rw 		TIMER7EN
rw 		SPI0EN
rw 		TIMER0EN
rw 		ADC1EN
rw 		ADC0EN
rw 		PGEN
rw 		PFEN
rw 		PEEN
rw 		PDEN
rw 		PCEN
rw 		PBEN
rw 		PAEN
rw 		AFEN
rw
Toggle Fields.

AFEN

Bit 0: Alternate function IO clock enable .

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PAEN

Bit 2: GPIO port A clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PBEN

Bit 3: GPIO port B clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PCEN

Bit 4: GPIO port C clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PDEN

Bit 5: GPIO port D clock enable .

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PEEN

Bit 6: GPIO port E clock enable .

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PFEN

Bit 7: GPIO port F clock enable .

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PGEN

Bit 8: GPIO port G clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ADC0EN

Bit 9: ADC0 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ADC1EN

Bit 10: ADC1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIMER0EN

Bit 11: TIMER0 clock enable .

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI0EN

Bit 12: SPI0 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIMER7EN

Bit 13: TIMER7 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART0EN

Bit 14: USART0 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ADC2EN

Bit 15: ADC2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIMER8EN

Bit 19: TIMER8 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIMER9EN

Bit 20: TIMER9 clock enable .

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIMER10EN

Bit 21: TIMER10 clock enable .

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB1EN

APB1 clock enable register (RCU_APB1EN)

Offset: 0x1C, reset: 0x00000000, access: read-write

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACEN
rw 		PMUEN
rw 		BKPIEN
rw 		CAN1EN
rw 		CAN0EN
rw 		I2C1EN
rw 		I2C0EN
rw 		UART4EN
rw 		UART3EN
rw 		USART2EN
rw 		USART1EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2EN
rw 		SPI1EN
rw 		WWDGTEN
rw 		TIMER13EN
rw 		TIMER12EN
rw 		TIMER11EN
rw 		TIMER6EN
rw 		TIMER5EN
rw 		TIMER4EN
rw 		TIMER3EN
rw 		TIMER2EN
rw 		TIMER1EN
rw
Toggle Fields.

TIMER1EN

Bit 0: TIMER1 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIMER2EN

Bit 1: TIMER2 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIMER3EN

Bit 2: TIMER3 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIMER4EN

Bit 3: TIMER4 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIMER5EN

Bit 4: TIMER5 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIMER6EN

Bit 5: TIMER6 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIMER11EN

Bit 6: TIMER11 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIMER12EN

Bit 7: TIMER12 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIMER13EN

Bit 8: TIMER13 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

WWDGTEN

Bit 11: Window watchdog timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI1EN

Bit 14: SPI1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI2EN

Bit 15: SPI2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART1EN

Bit 17: USART1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART2EN

Bit 18: USART2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART3EN

Bit 19: UART3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART4EN

Bit 20: UART4 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C0EN

Bit 21: I2C0 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C1EN

Bit 22: I2C1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CAN0EN

Bit 25: CAN0 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CAN1EN

Bit 26: CAN1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

BKPIEN

Bit 27: Backup interface clock enable .

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PMUEN

Bit 28: Power control clock enable .

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DACEN

Bit 29: DAC clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

BDCTL

Backup domain control register (RCU_BDCTL)

Offset: 0x20, reset: 0x00000018, access: Unspecified

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKPRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCEN
rw 		RTCSRC
rw 		LXTALDRI
rw 		LXTALBPS
rw 		LXTALSTB
r 		LXTALEN
rw
Toggle Fields.

LXTALEN

Bit 0: LXTAL enable.

Allowed values:
0: Off: LXTAL oscillator Off
1: On: LXTAL oscillator On

LXTALSTB

Bit 1: External low-speed oscillator stabilization.

Allowed values:
0: NotReady: LXTAL oscillator not ready
1: Ready: LXTAL oscillator ready

LXTALBPS

Bit 2: LXTAL bypass mode enable.

Allowed values:
0: NotBypassed: LXTAL crystal oscillator not bypassed
1: Bypassed: LXTAL crystal oscillator bypassed with external clock

LXTALDRI

Bits 3-4: LXTAL drive capability.

Allowed values:
0: Low: Low driving capability
1: MediumLow: Medium low driving capability
2: MediumHigh: Medium high driving capability
3: High: High driving capability (reset value)

RTCSRC

Bits 8-9: RTC clock entry selection.

Allowed values:
0: NoClock: No clock
1: LXTAL: LXTAL oscillator clock used as RTC clock
2: IRC40K: IRC40K oscillator clock used as RTC clock
3: HXTAL: HXTAL oscillator / 32 used as RTC clock

RTCEN

Bit 15: RTC clock enable.

Allowed values:
0: Disabled: RTC clock disabled
1: Enabled: RTC clock enabled

BKPRST

Bit 16: Backup domain reset.

Allowed values:
0: NoReset: Reset not activated
1: Reset: Reset the entire RTC domain

RSTSCK

Reset source /clock register (RCU_RSTSCK)

Offset: 0x24, reset: 0x0C000000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPRSTF
r 		WWDGTRSTF
r 		FWDGTRSTF
r 		SWRSTF
r 		PORRSTF
r 		EPRSTF
r 		RSTFC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRC40KSTB
r 		IRC40KEN
rw
Toggle Fields.

IRC40KEN

Bit 0: IRC40K enable.

Allowed values:
0: Off: IRC40K oscillator disabled
1: On: IRC40K oscillator enabled

IRC40KSTB

Bit 1: IRC40K stabilization.

Allowed values:
0: NotReady: IRC40K oscillator is not stable
1: Ready: IRC40K oscillator is stable

RSTFC

Bit 24: Reset flag clear.

Allowed values:
1: Clear: Clears reset flags

EPRSTF

Bit 26: External PIN reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

PORRSTF

Bit 27: Power reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

SWRSTF

Bit 28: Software reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

FWDGTRSTF

Bit 29: Free Watchdog timer reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

WWDGTRSTF

Bit 30: Window watchdog timer reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

LPRSTF

Bit 31: Low-power reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

AHB1RST

AHB1 reset register

Offset: 0x28, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENETRST
rw 		USBFSRST
rw
Toggle Fields.

USBFSRST

Bit 12: USBFS reset.

ENETRST

Bit 14: ENET reset.

CFG1

Clock Configuration register 1

Offset: 0x2C, reset: 0x00000000, access: read-write

2/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I2S2SEL
rw 		I2S1SEL
rw 		PREDV0SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL2MF
rw 		PLL1MF
rw 		PREDV1
rw 		PREDV0
rw
Toggle Fields.

PREDV0

Bits 0-3: PREDV0 division factor.

Allowed values:
0: Div1: Input to PLL not divided
1: Div2: Input to PLL divided by 2
2: Div3: Input to PLL divided by 3
3: Div4: Input to PLL divided by 4
4: Div5: Input to PLL divided by 5
5: Div6: Input to PLL divided by 6
6: Div7: Input to PLL divided by 7
7: Div8: Input to PLL divided by 8
8: Div9: Input to PLL divided by 9
9: Div10: Input to PLL divided by 10
10: Div11: Input to PLL divided by 11
11: Div12: Input to PLL divided by 12
12: Div13: Input to PLL divided by 13
13: Div14: Input to PLL divided by 14
14: Div15: Input to PLL divided by 15
15: Div16: Input to PLL divided by 16

PREDV1

Bits 4-7: PREDV1 division factor.

Allowed values:
0: Div1: Input to PLL not divided
1: Div2: Input to PLL divided by 2
2: Div3: Input to PLL divided by 3
3: Div4: Input to PLL divided by 4
4: Div5: Input to PLL divided by 5
5: Div6: Input to PLL divided by 6
6: Div7: Input to PLL divided by 7
7: Div8: Input to PLL divided by 8
8: Div9: Input to PLL divided by 9
9: Div10: Input to PLL divided by 10
10: Div11: Input to PLL divided by 11
11: Div12: Input to PLL divided by 12
12: Div13: Input to PLL divided by 13
13: Div14: Input to PLL divided by 14
14: Div15: Input to PLL divided by 15
15: Div16: Input to PLL divided by 16

PLL1MF

Bits 8-11: The PLL1 clock multiplication factor.

PLL2MF

Bits 12-15: The PLL2 clock multiplication factor.

PREDV0SEL

Bit 16: PREDV0 input Clock Source Selection.

I2S1SEL

Bit 17: I2S1 Clock Source Selection.

I2S2SEL

Bit 18: I2S2 Clock Source Selection.

DSV

Deep sleep mode Voltage register

Offset: 0x34, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSLPVS
rw
Toggle Fields.

DSLPVS

Bits 0-2: Deep-sleep mode voltage select.

AHB2EN

AHB2 enable register

Offset: 0x60, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRNGEN
rw 		HAUEN
rw 		CAUEN
rw 		DCIEN
rw
Toggle Fields.

DCIEN

Bit 0: DCI clock enable.

CAUEN

Bit 4: CAU clock enable.

HAUEN

Bit 5: HAU clock enable.

TRNGEN

Bit 6: TRNG clock enable.

ADDAPB2EN

APB2 additional enable register

Offset: 0x64, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIEN
rw 		PHEN
rw 		TLIEN
rw 		USART5EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

USART5EN

Bit 24: USART5 clock enable.

TLIEN

Bit 26: TLI clock enable.

PHEN

Bit 30: GPIO port H clock enable.

PIEN

Bit 31: GPIO port I clock enable.

ADDAPB1EN

APB1 additional enable register

Offset: 0x68, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UART7EN
rw 		UART6EN
rw 		I2C2EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

I2C2EN

Bit 23: I2C2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART6EN

Bit 30: UART6 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART7EN

Bit 31: UART7 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB2RST

AHB2 reset register

Offset: 0x70, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRNGRST
rw 		HAURST
rw 		CAURST
rw 		DCIRST
rw
Toggle Fields.

DCIRST

Bit 0: DCI reset.

CAURST

Bit 4: CAU reset.

HAURST

Bit 5: HAU reset.

TRNGRST

Bit 6: TRNG reset.

ADDAPB2RST

APB2 additional enable register

Offset: 0x74, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIRST
rw 		PHRST
rw 		TLIRST
rw 		USART5RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

USART5RST

Bit 24: USART5 reset.

TLIRST

Bit 26: TLI reset.

PHRST

Bit 30: GPIO port H reset.

PIRST

Bit 31: GPIO port I reset.

ADDAPB1RST

APB1 additional enable register

Offset: 0x78, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UART7RST
rw 		UART6RST
rw 		I2C2RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

I2C2RST

Bit 23: I2C2 reset.

Allowed values:
1: Reset: Reset the selected module

UART6RST

Bit 30: UART6 reset.

Allowed values:
1: Reset: Reset the selected module

UART7RST

Bit 31: UART7 reset.

Allowed values:
1: Reset: Reset the selected module

CFG2

configuration register 2

Offset: 0x80, reset: 0x00000000, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKOUT1SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKOUT1DIV
rw 		CKOUT0DIV
rw
Toggle Fields.

CKOUT0DIV

Bits 0-5: the CK_OUT0 divider.

CKOUT1DIV

Bits 8-13: the CK_OUT1 divider.

CKOUT1SEL

Bits 16-19: CK_OUT1 clock source selection.

Allowed values:
0: NOCLK: No clock selected
1: SYSCLK: System clock selected
2: IRC8M: High Speed 8M Internal Oscillator clock (IRC8M) selected
3: HXTAL: External High Speed oscillator clock (HXTAL) selected

PLLTCTL

PLLT control register

Offset: 0x90, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLTSTB
r 		PLLTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PLLTEN

Bit 28: PLLT enable.

PLLTSTB

Bit 29: PLLTclock stabilization flag.

PLLTINT

PLLT interrupt register

Offset: 0x94, reset: 0x00000000, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLTSTBIC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLTSTBIE
rw 		PLLTSTBIF
r
Toggle Fields.

PLLTSTBIF

Bit 6: PLLT stabilization interrupt flag.

PLLTSTBIE

Bit 14: PLLT stabilization Interrupt Enable.

PLLTSTBIC

Bit 22: PLLT stabilization Interrupt clear.

PLLTCFG

PLLT configuration register

Offset: 0x98, reset: 0x20003010, access: Unspecified

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLTSEL
rw 		PLLTRPSC
rw 		TLIPSC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLTMF
rw 		PLLTPSC
rw
Toggle Fields.

PLLTPSC

Bits 0-5: PLLT prescaler selection.

PLLTMF

Bits 6-14: PLLT multiply factor for VCO.

TLIPSC

Bits 16-17: TLI prescaler selection.

PLLTRPSC

Bits 28-30: PLLTR prescaler selection.

PLLTSEL

Bit 31: PLLT clock source select.

RTC

0x40002800: Real-time clock

3/17 fields covered. Toggle Registers.

INTEN

RTC interrupt enable register

Offset: 0x0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVIE
rw 		ALRMIE
rw 		SCIE
rw
Toggle Fields.

SCIE

Bit 0: Second interrupt.

ALRMIE

Bit 1: Alarm interrupt enable.

OVIE

Bit 2: Overflow interrupt enable.

CTL

control register

Offset: 0x4, reset: 0x00000020, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LWOFF
r 		CMF
rw 		RSYNF
rw 		OVIF
rw 		ALRMIF
rw 		SCIF
rw
Toggle Fields.

SCIF

Bit 0: Sencond interrupt flag.

ALRMIF

Bit 1: Alarm interrupt flag.

OVIF

Bit 2: Overflow interrupt flag.

RSYNF

Bit 3: Registers synchronized flag.

CMF

Bit 4: Configuration mode flag.

LWOFF

Bit 5: Last write operation finished flag.

PSCH

RTC prescaler high register

Offset: 0x8, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
w
Toggle Fields.

PSC

Bits 0-3: RTC prescaler value high.

PSCL

RTC prescaler low register

Offset: 0xC, reset: 0x00008000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
w
Toggle Fields.

PSC

Bits 0-15: RTC prescaler value low.

DIVH

RTC divider high register

Offset: 0x10, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
r
Toggle Fields.

DIV

Bits 0-3: RTC divider value high.

DIVL

RTC divider low register

Offset: 0x14, reset: 0x00008000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
r
Toggle Fields.

DIV

Bits 0-15: RTC divider value low.

CNTH

RTC counter high register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: RTC counter value high.

CNTL

RTC counter low register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: RTC conuter value low.

ALRMH

Alarm high register

Offset: 0x20, reset: 0x0000FFFF, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALRM
w
Toggle Fields.

ALRM

Bits 0-15: Alarm value high.

ALRML

RTC alarm low register

Offset: 0x24, reset: 0x0000FFFF, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALRM
w
Toggle Fields.

ALRM

Bits 0-15: alarm value low.

SDIO

0x40018000: Secure digital input/output interface

31/99 fields covered. Toggle Registers.

PWRCTL

Power control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWRCTL
rw
Toggle Fields.

PWRCTL

Bits 0-1: PWRCTL.

CLKCTL

SDI clock control register (SDIO_CLKCTL)

Offset: 0x4, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIV_8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HWCLKEN
rw 		CLKEDGE
rw 		BUSMODE
rw 		CLKBYP
rw 		CLKPWRSAV
rw 		CLKEN
rw 		DIV
rw
Toggle Fields.

DIV

Bits 0-7: Clock divide factor.

CLKEN

Bit 8: Clock enable bit.

CLKPWRSAV

Bit 9: SDIO_CLK clock dynamic switch on/off for power saving.

CLKBYP

Bit 10: Clock divider bypass enable bit.

BUSMODE

Bits 11-12: SDIO card bus mode control bit.

CLKEDGE

Bit 13: SDIO_CLK clock edge selection bit.

HWCLKEN

Bit 14: Hardware Clock Control enable bit.

DIV_8

Bit 31: MSB of Clock Division.

CMDAGMT

Command argument register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDAGMT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDAGMT
rw
Toggle Fields.

CMDAGMT

Bits 0-31: SDIO card command argument.

CMDCTL

Command control register

Offset: 0xC, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATAEN
rw 		NINTEN
rw 		ENCMDC
rw 		SUSPEND
rw 		CSMEN
rw 		WAITDEND
rw 		INTWAIT
rw 		CMDRESP
rw 		CMDIDX
rw
Toggle Fields.

CMDIDX

Bits 0-5: Command index.

CMDRESP

Bits 6-7: Command response type bits.

INTWAIT

Bit 8: Interrupt wait instead of timeout.

WAITDEND

Bit 9: Waits for ends of data transfer.

CSMEN

Bit 10: Command state machine (CSM) enable bit.

SUSPEND

Bit 11: SD I/O suspend command(SD I/O only).

ENCMDC

Bit 12: CMD completion signal enabled (CE-ATA only).

NINTEN

Bit 13: No CE-ATA Interrupt (CE-ATA only).

ATAEN

Bit 14: CE-ATA command enable(CE-ATA only).

RSPCMDIDX

Command index response register

Offset: 0x10, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSPCMDIDX
r
Toggle Fields.

RSPCMDIDX

Bits 0-5: Last response command index.

RESP0

Response register 0

Offset: 0x14, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESP0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESP0
r
Toggle Fields.

RESP0

Bits 0-31: Card state.

RESP1

Response register 1

Offset: 0x18, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESP1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESP1
r
Toggle Fields.

RESP1

Bits 0-31: Card state.

RESP2

Response register 2

Offset: 0x1C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESP2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESP2
r
Toggle Fields.

RESP2

Bits 0-31: Card state.

RESP3

Response register 3

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESP3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESP3
r
Toggle Fields.

RESP3

Bits 0-31: Card state.

DATATO

Data timeout register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATATO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATATO
rw
Toggle Fields.

DATATO

Bits 0-31: Data timeout period.

DATALEN

Data length register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATALEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATALEN
rw
Toggle Fields.

DATALEN

Bits 0-24: Data transfer length.

DATACTL

Data control register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOEN
rw 		RWTYPE
rw 		RWSTOP
rw 		RWEN
rw 		BLKSZ
rw 		DMAEN
rw 		TRANSMOD
rw 		DATADIR
rw 		DATAEN
rw
Toggle Fields.

DATAEN

Bit 0: Data transfer enable bit.

DATADIR

Bit 1: Data transfer direction.

TRANSMOD

Bit 2: Data transfer mode.

DMAEN

Bit 3: DMA enable bit.

BLKSZ

Bits 4-7: Data block size.

RWEN

Bit 8: Read wait mode enabled(SD I/O only).

RWSTOP

Bit 9: Read wait stop(SD I/O only).

RWTYPE

Bit 10: Read wait type(SD I/O only).

IOEN

Bit 11: SD I/O specific function enable(SD I/O only).

DATACNT

Data counter register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATACNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATACNT
r
Toggle Fields.

DATACNT

Bits 0-24: Data count value.

STAT

SDIO status register (SDIO_STR)

Offset: 0x34, reset: 0x00000000, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATAEND
r 		SDIOINT
r 		RXDTVAL
r 		TXDTVAL
r 		RFE
r 		TFE
r 		RFF
r 		TFF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFH
r 		TFH
r 		RXRUN
r 		TXRUN
r 		CMDRUN
r 		DTBLKEND
r 		STBITE
r 		DTEND
r 		CMDSEND
r 		CMDRECV
r 		RXORE
r 		TXURE
r 		DTTMOUT
r 		CMDTMOUT
r 		DTCRCERR
r 		CCRCERR
r
Toggle Fields.

CCRCERR

Bit 0: Command response received (CRC check failed).

DTCRCERR

Bit 1: Data block sent/received (CRC check failed).

CMDTMOUT

Bit 2: Command response timeout.

DTTMOUT

Bit 3: Data timeout.

TXURE

Bit 4: Transmit FIFO underrun error occurs.

RXORE

Bit 5: Received FIFO overrun error occurs.

CMDRECV

Bit 6: Command response received (CRC check passed).

CMDSEND

Bit 7: Command sent (no response required).

DTEND

Bit 8: Data end (data counter, SDIO_DATACNT, is zero).

STBITE

Bit 9: Start bit error in the bus.

DTBLKEND

Bit 10: Data block sent/received (CRC check passed).

CMDRUN

Bit 11: Command transmission in progress.

TXRUN

Bit 12: Data transmission in progress.

RXRUN

Bit 13: Data reception in progress.

TFH

Bit 14: Transmit FIFO is half empty: at least 8 words can be written into the FIFO.

RFH

Bit 15: Receive FIFO is half full: at least 8 words can be read in the FIFO.

TFF

Bit 16: Transmit FIFO is full.

RFF

Bit 17: Receive FIFO is full.

TFE

Bit 18: Transmit FIFO is empty.

RFE

Bit 19: Receive FIFO is empty.

TXDTVAL

Bit 20: Data is valid in transmit FIFO.

RXDTVAL

Bit 21: Data is valid in receive FIFO.

SDIOINT

Bit 22: SD I/O interrupt received.

ATAEND

Bit 23: CE-ATA command completion signal received (only for CMD61).

INTC

Interrupt clear register (SDIO_INTC)

Offset: 0x38, reset: 0x00000000, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATAENDC
w 		SDIOINTC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTBLKENDC
w 		STBITEC
w 		DTENDC
w 		CMDSENDC
w 		CMDRECVC
w 		RXOREC
w 		TXUREC
w 		DTTMOUTC
w 		CMDTMOUTC
w 		DTCRCERRC
w 		CCRCERRC
w
Toggle Fields.

CCRCERRC

Bit 0: CCRCERR flag clear bit.

DTCRCERRC

Bit 1: DTCRCERR flag clear bit.

CMDTMOUTC

Bit 2: CMDTMOUT flag clear bit.

DTTMOUTC

Bit 3: DTTMOUT flag clear bit.

TXUREC

Bit 4: TXURE flag clear bit.

RXOREC

Bit 5: RXORE flag clear bit.

CMDRECVC

Bit 6: CMDRECV flag clear bit.

CMDSENDC

Bit 7: CMDSEND flag clear bit.

DTENDC

Bit 8: DTEND flag clear bit.

STBITEC

Bit 9: STBITE flag clear bit.

DTBLKENDC

Bit 10: DTBLKEND flag clear bit.

SDIOINTC

Bit 22: SDIOINT flag clear bit.

ATAENDC

Bit 23: ATAEND flag clear bit.

INTEN

Interrupt Enable register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATAENDIE
rw 		SDIOINTIE
rw 		RXDTVALIE
rw 		TXDTVALIE
rw 		RFEIE
rw 		TFEIE
rw 		RFFIE
rw 		TFFIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFHIE
rw 		TFHIE
rw 		RXRUNIE
rw 		TXRUNIE
rw 		CMDRUNIE
rw 		DTBLKENDIE
rw 		STBITEIE
rw 		DTENDIE
rw 		CMDSENDIE
rw 		CMDRECVIE
rw 		RXOREIE
rw 		TXUREIE
rw 		DTTMOUTIE
rw 		CMDTMOUTIE
rw 		DTCRCERRIE
rw 		CCRCERRIE
rw
Toggle Fields.

CCRCERRIE

Bit 0: Command response CRC fail interrupt enable.

DTCRCERRIE

Bit 1: Data CRC fail interrupt enable.

CMDTMOUTIE

Bit 2: Command response timeout interrupt enable.

DTTMOUTIE

Bit 3: Data timeout interrupt enable.

TXUREIE

Bit 4: Transmit FIFO underrun error interrupt enable.

RXOREIE

Bit 5: Received FIFO overrun error interrupt enable.

CMDRECVIE

Bit 6: Command response received interrupt enable.

CMDSENDIE

Bit 7: Command sent interrupt enable.

DTENDIE

Bit 8: Data end interrupt enable.

STBITEIE

Bit 9: Start bit error interrupt enable.

DTBLKENDIE

Bit 10: Data block end interrupt enable.

CMDRUNIE

Bit 11: Command transmission interrupt enable.

TXRUNIE

Bit 12: Data transmission interrupt enable.

RXRUNIE

Bit 13: Data reception interrupt enable.

TFHIE

Bit 14: Transmit FIFO half empty interrupt enable.

RFHIE

Bit 15: Receive FIFO half full interrupt enable.

TFFIE

Bit 16: Transmit FIFO full interrupt enable.

RFFIE

Bit 17: Receive FIFO full interrupt enable.

TFEIE

Bit 18: Transmit FIFO empty interrupt enable.

RFEIE

Bit 19: Receive FIFO empty interrupt enable.

TXDTVALIE

Bit 20: Data valid in transmit FIFO interrupt enable.

RXDTVALIE

Bit 21: Data valid in receive FIFO interrupt enable.

SDIOINTIE

Bit 22: SD I/O interrupt received interrupt enable.

ATAENDIE

Bit 23: CE-ATA command completion signal received interrupt enable.

FIFOCNT

FIFO counter register

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCNT
r
Toggle Fields.

FIFOCNT

Bits 0-23: FIFO counter.

FIFO

FIFO data register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODT
rw
Toggle Fields.

FIFODT

Bits 0-31: Receive FIFO data or transmit FIFO data.

SPI0

0x40013000: Serial peripheral interface

46/46 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDEN
rw 		BDOEN
rw 		CRCEN
rw 		CRCNT
rw 		FF16
rw 		RO
rw 		SWNSSEN
rw 		SWNSS
rw 		LF
rw 		SPIEN
rw 		PSC
rw 		MSTMOD
rw 		CKPL
rw 		CKPH
rw
Toggle Fields.

CKPH

Bit 0: Clock Phase Selection.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CKPL

Bit 1: Clock polarity Selection.

Allowed values:
0: IdleLow: CLK pulled low when idle
1: IdleHigh: CLK pulled high when idle

MSTMOD

Bit 2: Master Mode Enable.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

PSC

Bits 3-5: Master Clock Prescaler Selection.

Allowed values:
0: Div2: PCLK / 2
1: Div4: PCLK / 4
2: Div8: PCLK / 8
3: Div16: PCLK / 16
4: Div32: PCLK / 32
5: Div64: PCLK / 64
6: Div128: PCLK / 128
7: Div256: PCLK / 256

SPIEN

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LF

Bit 7: LSB First Mode.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SWNSS

Bit 8: NSS Pin Selection In NSS Software Mode.

Allowed values:
0: SlaveSelected: NSS is pulled low
1: SlaveNotSelected: NSS is pulled high

SWNSSEN

Bit 9: NSS Software Mode Selection.

Allowed values:
0: Hardware: Software slave management disabled
1: Software: Software slave management enabled

RO

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: ReceiveOnly: Output disabled (Receive-only mode)

FF16

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNT

Bit 12: CRC Next Transfer.

Allowed values:
0: Data: Next transmit value is data from Tx buffer
1: CRC: Next transmit value is CRC value from TCRC

CRCEN

Bit 13: CRC Calculation Enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BDOEN

Bit 14: Bidirectional Transmit output enable .

Allowed values:
0: ReceiveOnly: Receive-only mode
1: TransmitOnly: Transmit-only mode

BDEN

Bit 15: Bidirectional enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBEIE
rw 		RBNEIE
rw 		ERRIE
rw 		NSSDRV
rw 		DMATEN
rw 		DMAREN
rw
Toggle Fields.

DMAREN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

DMATEN

Bit 1: Transmit Buffer DMA Enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

NSSDRV

Bit 2: Drive NSS Output.

Allowed values:
0: Disabled: NSS output is disabled in master mode
1: Enabled: NSS output is enabled in master mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

RBNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Disabled: RBNE interrupt disabled
1: Enabled: RBNE interrupt enabled

TBEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Disabled: TBE interrupt disabled
1: Enabled: TBE interrupt enabled

STAT

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRANS
r 		RXORERR
r 		CONFERR
r 		CRCERR
rw 		TXURERR
r 		I2SCH
r 		TBE
r 		RBNE
r
Toggle Fields.

RBNE

Bit 0: Receive Buffer Not Empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TBE

Bit 1: Transmit Buffer Empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

I2SCH

Bit 2: I2S channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

TXURERR

Bit 3: Transmission underrun error bit.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: SPI CRC Error Bit.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

CONFERR

Bit 5: SPI Configuration error.

Allowed values:
0: NoFault: No configuration fault occurred
1: Fault: Configuration fault occurred

RXORERR

Bit 6: Reception Overrun Error Bit.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

TRANS

Bit 7: Transmitting On-going Bit.

Allowed values:
0: Idle: SPI or I2S is idle
1: Busy: SPI or I2S is currently transmitting or receiving

DATA

data register

Offset: 0xC, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Data transfer register.

Allowed values: 0-65535

CRCPOLY

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0-65535

RCRC

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCRC
r
Toggle Fields.

RCRC

Bits 0-15: RX CRC register.

Allowed values: 0-65535

TCRC

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRC
r
Toggle Fields.

TCRC

Bits 0-15: Tx CRC register.

Allowed values: 0-65535

I2SCTL

I2S control register

Offset: 0x1C, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SSEL
rw 		I2SEN
rw 		I2SOPMOD
rw 		PCMSMOD
rw 		I2SSTD
rw 		CKPL
rw 		DTLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DTLEN

Bits 1-2: Data length.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPL

Bit 3: Idle state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSMOD

Bit 7: PCM frame synchronization mode.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SOPMOD

Bits 8-9: I2S operation mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SEN

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SSEL

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPSC

I2S prescaler register

Offset: 0x20, reset: 0x0002, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOEN
rw 		OF
rw 		DIV
rw
Toggle Fields.

DIV

Bits 0-7: Dividing factor for the prescaler.

Allowed values: 1-255

OF

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is DIV * 2
1: Odd: Real divider value is (DIV * 2) + 1

MCKOEN

Bit 9: I2S_MCK output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

QCTL

Quad-SPI mode control register

Offset: 0x80, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IO23_DRV
rw 		QRD
rw 		QMOD
rw
Toggle Fields.

QMOD

Bit 0: Quad-SPI mode enable.

Allowed values:
0: Single: Single wire mode
1: Quad: Quad-SPI mode

QRD

Bit 1: Quad-SPI mode read select.

Allowed values:
0: Write: Quad wire write mode
1: Read: Quad wire read mode

IO23_DRV

Bit 2: Drive IO2 and IO3 enable.

Allowed values:
0: Disabled: IO2 and IO3 are not driven in single wire mode
1: High: IO2 and IO3 are driven high in single wire mode

SPI1

0x40003800: Serial peripheral interface

46/46 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDEN
rw 		BDOEN
rw 		CRCEN
rw 		CRCNT
rw 		FF16
rw 		RO
rw 		SWNSSEN
rw 		SWNSS
rw 		LF
rw 		SPIEN
rw 		PSC
rw 		MSTMOD
rw 		CKPL
rw 		CKPH
rw
Toggle Fields.

CKPH

Bit 0: Clock Phase Selection.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CKPL

Bit 1: Clock polarity Selection.

Allowed values:
0: IdleLow: CLK pulled low when idle
1: IdleHigh: CLK pulled high when idle

MSTMOD

Bit 2: Master Mode Enable.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

PSC

Bits 3-5: Master Clock Prescaler Selection.

Allowed values:
0: Div2: PCLK / 2
1: Div4: PCLK / 4
2: Div8: PCLK / 8
3: Div16: PCLK / 16
4: Div32: PCLK / 32
5: Div64: PCLK / 64
6: Div128: PCLK / 128
7: Div256: PCLK / 256

SPIEN

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LF

Bit 7: LSB First Mode.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SWNSS

Bit 8: NSS Pin Selection In NSS Software Mode.

Allowed values:
0: SlaveSelected: NSS is pulled low
1: SlaveNotSelected: NSS is pulled high

SWNSSEN

Bit 9: NSS Software Mode Selection.

Allowed values:
0: Hardware: Software slave management disabled
1: Software: Software slave management enabled

RO

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: ReceiveOnly: Output disabled (Receive-only mode)

FF16

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNT

Bit 12: CRC Next Transfer.

Allowed values:
0: Data: Next transmit value is data from Tx buffer
1: CRC: Next transmit value is CRC value from TCRC

CRCEN

Bit 13: CRC Calculation Enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BDOEN

Bit 14: Bidirectional Transmit output enable .

Allowed values:
0: ReceiveOnly: Receive-only mode
1: TransmitOnly: Transmit-only mode

BDEN

Bit 15: Bidirectional enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBEIE
rw 		RBNEIE
rw 		ERRIE
rw 		NSSDRV
rw 		DMATEN
rw 		DMAREN
rw
Toggle Fields.

DMAREN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

DMATEN

Bit 1: Transmit Buffer DMA Enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

NSSDRV

Bit 2: Drive NSS Output.

Allowed values:
0: Disabled: NSS output is disabled in master mode
1: Enabled: NSS output is enabled in master mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

RBNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Disabled: RBNE interrupt disabled
1: Enabled: RBNE interrupt enabled

TBEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Disabled: TBE interrupt disabled
1: Enabled: TBE interrupt enabled

STAT

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRANS
r 		RXORERR
r 		CONFERR
r 		CRCERR
rw 		TXURERR
r 		I2SCH
r 		TBE
r 		RBNE
r
Toggle Fields.

RBNE

Bit 0: Receive Buffer Not Empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TBE

Bit 1: Transmit Buffer Empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

I2SCH

Bit 2: I2S channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

TXURERR

Bit 3: Transmission underrun error bit.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: SPI CRC Error Bit.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

CONFERR

Bit 5: SPI Configuration error.

Allowed values:
0: NoFault: No configuration fault occurred
1: Fault: Configuration fault occurred

RXORERR

Bit 6: Reception Overrun Error Bit.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

TRANS

Bit 7: Transmitting On-going Bit.

Allowed values:
0: Idle: SPI or I2S is idle
1: Busy: SPI or I2S is currently transmitting or receiving

DATA

data register

Offset: 0xC, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Data transfer register.

Allowed values: 0-65535

CRCPOLY

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0-65535

RCRC

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCRC
r
Toggle Fields.

RCRC

Bits 0-15: RX CRC register.

Allowed values: 0-65535

TCRC

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRC
r
Toggle Fields.

TCRC

Bits 0-15: Tx CRC register.

Allowed values: 0-65535

I2SCTL

I2S control register

Offset: 0x1C, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SSEL
rw 		I2SEN
rw 		I2SOPMOD
rw 		PCMSMOD
rw 		I2SSTD
rw 		CKPL
rw 		DTLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DTLEN

Bits 1-2: Data length.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPL

Bit 3: Idle state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSMOD

Bit 7: PCM frame synchronization mode.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SOPMOD

Bits 8-9: I2S operation mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SEN

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SSEL

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPSC

I2S prescaler register

Offset: 0x20, reset: 0x0002, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOEN
rw 		OF
rw 		DIV
rw
Toggle Fields.

DIV

Bits 0-7: Dividing factor for the prescaler.

Allowed values: 1-255

OF

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is DIV * 2
1: Odd: Real divider value is (DIV * 2) + 1

MCKOEN

Bit 9: I2S_MCK output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

QCTL

Quad-SPI mode control register

Offset: 0x80, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IO23_DRV
rw 		QRD
rw 		QMOD
rw
Toggle Fields.

QMOD

Bit 0: Quad-SPI mode enable.

Allowed values:
0: Single: Single wire mode
1: Quad: Quad-SPI mode

QRD

Bit 1: Quad-SPI mode read select.

Allowed values:
0: Write: Quad wire write mode
1: Read: Quad wire read mode

IO23_DRV

Bit 2: Drive IO2 and IO3 enable.

Allowed values:
0: Disabled: IO2 and IO3 are not driven in single wire mode
1: High: IO2 and IO3 are driven high in single wire mode

SPI2

0x40003C00: Serial peripheral interface

46/46 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDEN
rw 		BDOEN
rw 		CRCEN
rw 		CRCNT
rw 		FF16
rw 		RO
rw 		SWNSSEN
rw 		SWNSS
rw 		LF
rw 		SPIEN
rw 		PSC
rw 		MSTMOD
rw 		CKPL
rw 		CKPH
rw
Toggle Fields.

CKPH

Bit 0: Clock Phase Selection.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CKPL

Bit 1: Clock polarity Selection.

Allowed values:
0: IdleLow: CLK pulled low when idle
1: IdleHigh: CLK pulled high when idle

MSTMOD

Bit 2: Master Mode Enable.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

PSC

Bits 3-5: Master Clock Prescaler Selection.

Allowed values:
0: Div2: PCLK / 2
1: Div4: PCLK / 4
2: Div8: PCLK / 8
3: Div16: PCLK / 16
4: Div32: PCLK / 32
5: Div64: PCLK / 64
6: Div128: PCLK / 128
7: Div256: PCLK / 256

SPIEN

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LF

Bit 7: LSB First Mode.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SWNSS

Bit 8: NSS Pin Selection In NSS Software Mode.

Allowed values:
0: SlaveSelected: NSS is pulled low
1: SlaveNotSelected: NSS is pulled high

SWNSSEN

Bit 9: NSS Software Mode Selection.

Allowed values:
0: Hardware: Software slave management disabled
1: Software: Software slave management enabled

RO

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: ReceiveOnly: Output disabled (Receive-only mode)

FF16

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNT

Bit 12: CRC Next Transfer.

Allowed values:
0: Data: Next transmit value is data from Tx buffer
1: CRC: Next transmit value is CRC value from TCRC

CRCEN

Bit 13: CRC Calculation Enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BDOEN

Bit 14: Bidirectional Transmit output enable .

Allowed values:
0: ReceiveOnly: Receive-only mode
1: TransmitOnly: Transmit-only mode

BDEN

Bit 15: Bidirectional enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBEIE
rw 		RBNEIE
rw 		ERRIE
rw 		NSSDRV
rw 		DMATEN
rw 		DMAREN
rw
Toggle Fields.

DMAREN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

DMATEN

Bit 1: Transmit Buffer DMA Enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

NSSDRV

Bit 2: Drive NSS Output.

Allowed values:
0: Disabled: NSS output is disabled in master mode
1: Enabled: NSS output is enabled in master mode

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

RBNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Disabled: RBNE interrupt disabled
1: Enabled: RBNE interrupt enabled

TBEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Disabled: TBE interrupt disabled
1: Enabled: TBE interrupt enabled

STAT

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRANS
r 		RXORERR
r 		CONFERR
r 		CRCERR
rw 		TXURERR
r 		I2SCH
r 		TBE
r 		RBNE
r
Toggle Fields.

RBNE

Bit 0: Receive Buffer Not Empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TBE

Bit 1: Transmit Buffer Empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

I2SCH

Bit 2: I2S channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

TXURERR

Bit 3: Transmission underrun error bit.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: SPI CRC Error Bit.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

CONFERR

Bit 5: SPI Configuration error.

Allowed values:
0: NoFault: No configuration fault occurred
1: Fault: Configuration fault occurred

RXORERR

Bit 6: Reception Overrun Error Bit.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

TRANS

Bit 7: Transmitting On-going Bit.

Allowed values:
0: Idle: SPI or I2S is idle
1: Busy: SPI or I2S is currently transmitting or receiving

DATA

data register

Offset: 0xC, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Data transfer register.

Allowed values: 0-65535

CRCPOLY

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0-65535

RCRC

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCRC
r
Toggle Fields.

RCRC

Bits 0-15: RX CRC register.

Allowed values: 0-65535

TCRC

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRC
r
Toggle Fields.

TCRC

Bits 0-15: Tx CRC register.

Allowed values: 0-65535

I2SCTL

I2S control register

Offset: 0x1C, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SSEL
rw 		I2SEN
rw 		I2SOPMOD
rw 		PCMSMOD
rw 		I2SSTD
rw 		CKPL
rw 		DTLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DTLEN

Bits 1-2: Data length.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPL

Bit 3: Idle state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSMOD

Bit 7: PCM frame synchronization mode.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SOPMOD

Bits 8-9: I2S operation mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SEN

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SSEL

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPSC

I2S prescaler register

Offset: 0x20, reset: 0x0002, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOEN
rw 		OF
rw 		DIV
rw
Toggle Fields.

DIV

Bits 0-7: Dividing factor for the prescaler.

Allowed values: 1-255

OF

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is DIV * 2
1: Odd: Real divider value is (DIV * 2) + 1

MCKOEN

Bit 9: I2S_MCK output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

QCTL

Quad-SPI mode control register

Offset: 0x80, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IO23_DRV
rw 		QRD
rw 		QMOD
rw
Toggle Fields.

QMOD

Bit 0: Quad-SPI mode enable.

Allowed values:
0: Single: Single wire mode
1: Quad: Quad-SPI mode

QRD

Bit 1: Quad-SPI mode read select.

Allowed values:
0: Write: Quad wire write mode
1: Read: Quad wire read mode

IO23_DRV

Bit 2: Drive IO2 and IO3 enable.

Allowed values:
0: Disabled: IO2 and IO3 are not driven in single wire mode
1: High: IO2 and IO3 are driven high in single wire mode

TIMER0

0x40012C00: Advanced timer

127/127 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UPDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

UPS

Bit 2: Update source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UPG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

SPM

Bit 3: Single pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CAM

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAlignedCountingDown: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAlignedCountingUp: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAlignedCountingUpDown: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:
0: Disabled: The shadow register for CAR is disabled
1: Enabled: The shadow register for CAR is enabled

CKDIV

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISO3
rw 		ISO2N
rw 		ISO2
rw 		ISO1N
rw 		ISO1
rw 		ISO0N
rw 		ISO0
rw 		TI0S
rw 		MMC
rw 		DMAS
rw 		CCUC
rw 		CCSE
rw
Toggle Fields.

CCSE

Bit 0: Commutation control shadow enable.

Allowed values:
0: NotPreloaded: The shadow registers for CHxEN, CHxNEN and CHxCOMCTL bits are disabled
1: Preloaded: The shadow registers for CHxEN, CHxNEN and CHxCOMCTL bits are enabled

CCUC

Bit 2: Commutation control shadow register update control.

Allowed values:
0: Default: Capture/compare are updated only by setting the CMTG bit
1: WithRisingEdge: Capture/compare are updated by setting the CMTG bit or when an rising edge occurs on TRGI

DMAS

Bit 3: DMA request source selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMC

Bits 4-6: Master mode control.

Allowed values:
0: Reset: Use UPG bit from SWEVG register
1: Enable: Use CEN bit from CTL0 register
2: Update: Use the update event
3: CaptureComparePulse: The trigger output send a positive pulse when a capture or a compare match occurred in channel 0
4: CompareO0C: O0CPRE signal is used as trigger output
5: CompareO1C: O1CPRE signal is used as trigger output
6: CompareO2C: O2CPRE signal is used as trigger output
7: CompareO3C: O3CPRE signal is used as trigger output

TI0S

Bit 7: Channel 0 trigger input selection.

Allowed values:
0: Normal: The CH0 pin input is selected as channel 0 trigger input
1: XOR: The XOR of CH0, CH1 and CH2 pins are selected as channel 0 trigger input

ISO0

Bit 8: Idle state of channel 0 output.

Allowed values:
0: Low: CHn_O=0 (after a dead-time if CHn_ON is implemented) when POEN=0
1: High: CHn_O=1 (after a dead-time if CHn_ON is implemented) when POEN=0

ISO0N

Bit 9: Idle state of channel 0 complementary output.

Allowed values:
0: Low: CHn_ON=0 when POEN=0
1: High: CHn_ON=1 when POEN=0

ISO1

Bit 10: Idle state of channel 1 output.

Allowed values:

ISO1N

Bit 11: Idle state of channel 1 complementary output.

Allowed values:
0: Low: CHn_ON=0 when POEN=0
1: High: CHn_ON=1 when POEN=0

ISO2

Bit 12: Idle state of channel 2 output.

Allowed values:
0: Low: CHn_O=0 (after a dead-time if CHn_ON is implemented) when POEN=0
1: High: CHn_O=1 (after a dead-time if CHn_ON is implemented) when POEN=0

ISO2N

Bit 13: Idle state of channel 2 complementary output.

Allowed values:
0: Low: CHn_ON=0 when POEN=0
1: High: CHn_ON=1 when POEN=0

ISO3

Bit 14: Idle state of channel 3 output.

Allowed values:
0: Low: CHn_O=0 (after a dead-time if CHn_ON is implemented) when POEN=0
1: High: CHn_O=1 (after a dead-time if CHn_ON is implemented) when POEN=0

SMCFG

slave mode configuration register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

Allowed values:
0: Disabled: Slave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.
1: QuadratureDecoderMode0: Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.
2: QuadratureDecoderMode1: Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.
3: QuadratureDecoderMode2: Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.
4: RestartMode: Restart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: PauseMode: Pause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: EventMode: Event Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: ExternalClockMode: External Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.

TRGS

Bits 4-6: Trigger selection.

Allowed values:
0: ITI0: Internal Trigger 0 (ITI0)
1: ITI1: Internal Trigger 1 (ITI1)
2: ITI2: Internal Trigger 2 (ITI2)
4: CI0F_ED: CI0 Edge Detector (CI0F_ED)
5: CI0FE0: Filtered Timer Input 0 (CI0FE0)
6: CI1FE1: Filtered Timer Input 1 (CI1FE1)
7: ETIFP: External Trigger input (ETIFP)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETFC

Bits 8-11: External trigger filter control.

Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8

ETPSC

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: External trigger prescaler disabled
1: Div2: ETI frequency divided by 2
2: Div4: ETI frequency divided by 4
3: Div8: ETI frequency divided by 8

SMC1

Bit 14: Part of SMC for enable External clock mode1.

Allowed values:
0: Disabled: External clock mode 1 disabled
1: Enabled: External clock mode 1 enabled. The counter is clocked by any active edge on the ETIF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETI is noninverted, active at high level or rising edge
1: Inverted: ETI is inverted, active at low level or falling edge

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CMTDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		BRKIE
rw 		TRGIE
rw 		CMTIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

Allowed values:
0: Disabled: Capture/compare interrupt disabled
1: Enabled: Capture/compare interrupt enabled

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

Allowed values:
0: Disabled: Capture/compare interrupt disabled
1: Enabled: Capture/compare interrupt enabled

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

Allowed values:
0: Disabled: Capture/compare interrupt disabled
1: Enabled: Capture/compare interrupt enabled

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

Allowed values:
0: Disabled: Capture/compare interrupt disabled
1: Enabled: Capture/compare interrupt enabled

CMTIE

Bit 5: commutation interrupt enable.

Allowed values:
0: Disabled: Commutation interrupt disabled
1: Enabled: Commutation interrupt enabled

TRGIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BRKIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CMTDEN

Bit 13: Commutation DMA request enable.

Allowed values:
0: Disabled: Commutation DMA request disabled
1: Enabled: Commutation DMA request enabled

TRGDEN

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

INTF

Interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		BRKIF
rw 		TRGIF
rw 		CMTIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update interrupt occurred
1: UpdatePending: Update interrupt pending.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

Allowed values:
0: Clear: No capture or compare interrupt occurred
1: CaptureCompare: A capture or compare event occurred

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

Allowed values:
0: Clear: No capture or compare interrupt occurred
1: CaptureCompare: A capture or compare event occurred

CH2IF

Bit 3: Channel 2 capture/compare interrupt flag.

Allowed values:
0: Clear: No capture or compare interrupt occurred
1: CaptureCompare: A capture or compare event occurred

CH3IF

Bit 4: Channel 3 capture/compare interrupt flag.

Allowed values:
0: Clear: No capture or compare interrupt occurred
1: CaptureCompare: A capture or compare event occurred

CMTIF

Bit 5: Channel commutation interrupt flag.

Allowed values:
0: Clear: No channel commutation event occured
1: Commutation: Channel commutation event occurred

TRGIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: Clear: No trigger event occured
1: Triggered: Trigger event occurred

BRKIF

Bit 7: Break interrupt flag.

Allowed values:
0: Clear: No active level break detected
1: Break: Active level detected

CH0OF

Bit 9: Channel 0 over capture flag.

Allowed values:
0: Clear: No over capture occurred
1: OverCapture: A capture event occured while CHnIF was already set

CH1OF

Bit 10: Channel 1 over capture flag.

Allowed values:
0: Clear: No over capture occurred
1: OverCapture: A capture event occured while CHnIF was already set

CH2OF

Bit 11: Channel 2 over capture flag.

Allowed values:
0: Clear: No over capture occurred
1: OverCapture: A capture event occured while CHnIF was already set

CH3OF

Bit 12: Channel 3 over capture flag.

Allowed values:
0: Clear: No over capture occurred
1: OverCapture: A capture event occured while CHnIF was already set

SWEVG

Software event generation register

Offset: 0x14, reset: 0x0000, access: write-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRKG
w 		TRGG
w 		CMTG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update event generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CH0G

Bit 1: Channel 0 capture or compare event generation.

Allowed values:
1: CaptureCompare: Generate a capture or compare event

CH1G

Bit 2: Channel 1 capture or compare event generation.

Allowed values:
1: CaptureCompare: Generate a capture or compare event

CH2G

Bit 3: Channel 2 capture or compare event generation.

Allowed values:
1: CaptureCompare: Generate a capture or compare event

CH3G

Bit 4: Channel 3 capture or compare event generation.

Allowed values:
1: CaptureCompare: Generate a capture or compare event

CMTG

Bit 5: Channel commutation event generation.

Allowed values:
1: Update: Generate a channel commutation event, updating capture/compare control registers based on the value of CCSE

TRGG

Bit 6: Trigger event generation.

Allowed values:
1: Trigger: Generate a trigger event

BRKG

Bit 7: Break event generation.

Allowed values:
1: Break: Generate a break event

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

Allowed values:
0: Output: Channel is configured as output
1: CI0: Channel is configured as input, ISx is connected to CI0FEx
2: CI1: Channel is configured as input, ISx is connected to CI1FEx
3: ITS: Channel is configured as input, ISx is connected to ITS

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

Allowed values:
0: Div1: Prescaler disabled, capture on every edge
1: Div2: Capture every 2 edges
2: Div4: Capture every 4 edges
3: Div8: Capture every 8 edges

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8

CH1MS

Bits 8-9: Channel 1 mode selection.

Allowed values:

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

Allowed values:

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

Allowed values:

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

Allowed values:

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

Allowed values:

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

Allowed values:

CH3MS

Bits 8-9: Channel 3 mode selection.

Allowed values:

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

Allowed values:

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

Allowed values:

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2NEN
rw 		CH2P
rw 		CH2EN
rw 		CH1NP
rw 		CH1NEN
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0NEN
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

Allowed values:
0: Disabled: Channel output is disabled
1: Enabled: Channel output is enabled

CH0P

Bit 1: Channel 0 capture/compare function polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH0NEN

Bit 2: Channel 0 complementary output enable.

Allowed values:

CH0NP

Bit 3: Channel 0 complementary output polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH1EN

Bit 4: Channel 1 capture/compare function enable.

Allowed values:
0: Disabled: Channel output is disabled
1: Enabled: Channel output is enabled

CH1P

Bit 5: Channel 1 capture/compare function polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH1NEN

Bit 6: Channel 1 complementary output enable.

Allowed values:

CH1NP

Bit 7: Channel 1 complementary output polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH2EN

Bit 8: Channel 2 capture/compare function enable.

Allowed values:
0: Disabled: Channel output is disabled
1: Enabled: Channel output is enabled

CH2P

Bit 9: Channel 2 capture/compare function polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH2NEN

Bit 10: Channel 2 complementary output enable.

Allowed values:

CH2NP

Bit 11: Channel 2 complementary output polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH3EN

Bit 12: Channel 3 capture/compare function enable.

Allowed values:
0: Disabled: Channel output is disabled
1: Enabled: Channel output is enabled

CH3P

Bit 13: Channel 3 capture/compare function polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

CAR

Counter auto-reload register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto-reload.

Allowed values: 0-65535

CREP

Counter repetition register

Offset: 0x30, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CREP
rw
Toggle Fields.

CREP

Bits 0-7: Counter repetition value.

Allowed values: 0-255

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

Allowed values: 0-65535

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel 1.

Allowed values: 0-65535

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: Capture or compare value of channel 2.

Allowed values: 0-65535

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: Capture or compare value of channel 3.

Allowed values: 0-65535

CCHP

channel complementary protection register

Offset: 0x44, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POEN
rw 		OAEN
rw 		BRKP
rw 		BRKEN
rw 		ROS
rw 		IOS
rw 		PROT
rw 		DTCFG
rw
Toggle Fields.

DTCFG

Bits 0-7: Dead time configure.

Allowed values: 0-255

PROT

Bits 8-9: Complementary register protect control.

Allowed values:
0: Disabled: Write protection disabled
1: Mode0: Protection mode 0
2: Mode1: Protection mode 1
3: Mode2: Protection mode 2

IOS

Bit 10: Idle mode off-state configure.

Allowed values:
0: Disabled: When POEN is reset, the channel output signals are disabled
1: Enabled: When POEN is reset, the channel output signals are enabled

ROS

Bit 11: Run mode off-state configure.

Allowed values:
0: Disabled: When POEN is set, the channel output signals are disabled
1: Enabled: When POEN is set, the channel output signals are enabled

BRKEN

Bit 12: Break enable.

Allowed values:
0: Disabled: Break inputs disabled
1: Enabled: Break inputs enabled

BRKP

Bit 13: Break polarity.

Allowed values:
0: Inverted: BRKIN is active low
1: NotInverted: BRKIN is active high

OAEN

Bit 14: Output automatic enable.

Allowed values:
0: Manual: POEN cannot be set by hardware
1: Automatic: POEN can be set by hardware automatically at the next update event

POEN

Bit 15: Primary output enable.

Allowed values:
0: Disabled: Channel outputs are disabled
1: Enabled: Channel outputs are enabled

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

Allowed values: 0-31

DMATC

Bits 8-12: DMA transfer count.

Allowed values: 0-31

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

Allowed values: 0-65535

TIMER1

0x40000000: General-purpose-timers

96/96 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

SPM

Bit 3: Single pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:

CAM

Bits 5-6: Counter aligns mode selection.

Allowed values:

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

Allowed values:

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI0S
rw 		MMC
rw 		DMAS
rw
Toggle Fields.

DMAS

Bit 3: DMA request source selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMC

Bits 4-6: Master mode control.

Allowed values:
0: Reset: Use UPG bit from SWEVG register
1: Enable: Use CEN bit from CTL0 register
2: Update: Use the update event

TI0S

Bit 7: Channel 0 trigger input selection.

Allowed values:
0: Normal: The CH0 pin input is selected as channel 0 trigger input
1: XOR: The XOR of CH0, CH1 and CH2 pins are selected as channel 0 trigger input

SMCFG

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

Allowed values:
0: Disabled: Slave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.
1: QuadratureDecoderMode0: Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.
2: QuadratureDecoderMode1: Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.
3: QuadratureDecoderMode2: Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.
4: RestartMode: Restart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: PauseMode: Pause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: EventMode: Event Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: ExternalClockMode: External Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.

TRGS

Bits 4-6: Trigger selection.

Allowed values:
0: ITI0: Internal Trigger 0 (ITI0)
1: ITI1: Internal Trigger 1 (ITI1)
2: ITI2: Internal Trigger 2 (ITI2)
4: CI0F_ED: CI0 Edge Detector (CI0F_ED)
5: CI0FE0: Filtered Timer Input 0 (CI0FE0)
6: CI1FE1: Filtered Timer Input 1 (CI1FE1)
7: ETIFP: External Trigger input (ETIFP)

MSM

Bit 7: Master-slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETFC

Bits 8-11: External trigger filter control.

Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8

ETPSC

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: External trigger prescaler disabled
1: Div2: ETI frequency divided by 2
2: Div4: ETI frequency divided by 4
3: Div8: ETI frequency divided by 8

SMC1

Bit 14: Part of SMC for enable External clock mode1.

Allowed values:
0: Disabled: External clock mode 1 disabled
1: Enabled: External clock mode 1 enabled. The counter is clocked by any active edge on the ETIF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETI is noninverted, active at high level or rising edge
1: Inverted: ETI is inverted, active at low level or falling edge

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		TRGIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

Allowed values:

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

Allowed values:

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

Allowed values:

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

Allowed values:

TRGIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

TRGDEN

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

Allowed values:

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

Allowed values:

CH2IF

Bit 3: Channel 2 capture/compare interrupt enable.

Allowed values:

CH3IF

Bit 4: Channel 3 capture/compare interrupt enable.

Allowed values:

TRGIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: Clear: No trigger event occured
1: Triggered: Trigger event occurred

CH0OF

Bit 9: Channel 0 over capture flag.

Allowed values:

CH1OF

Bit 10: Channel 1 over capture flag.

Allowed values:

CH2OF

Bit 11: Channel 2 over capture flag.

Allowed values:

CH3OF

Bit 12: Channel 3 over capture flag.

Allowed values:

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

Allowed values:

CH1G

Bit 2: Channel 1 capture or compare event generation.

Allowed values:

CH2G

Bit 3: Channel 2 capture or compare event generation.

Allowed values:

CH3G

Bit 4: Channel 3 capture or compare event generation.

Allowed values:

TRGG

Bit 6: Trigger event generation.

Allowed values:
1: Trigger: Generate a trigger event

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

Allowed values:

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

Allowed values:

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

Allowed values:

CH1MS

Bits 8-9: Channel 1 mode selection.

Allowed values:

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

Allowed values:

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

Allowed values:

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

Allowed values:

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

Allowed values:

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

Allowed values:

CH3MS

Bits 8-9: Channel 3 mode selection.

Allowed values:

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

Allowed values:

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

Allowed values:

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2P
rw 		CH2EN
rw 		CH1P
rw 		CH1EN
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

Allowed values:

CH0P

Bit 1: Channel 0 capture/compare function polarity.

Allowed values:

CH1EN

Bit 4: Channel 1 capture/compare function enable.

Allowed values:

CH1P

Bit 5: Channel 1 capture/compare function polarity.

Allowed values:

CH2EN

Bit 8: Channel 2 capture/compare function enable.

Allowed values:

CH2P

Bit 9: Channel 2 capture/compare function polarity.

Allowed values:

CH3EN

Bit 12: Channel 3 capture/compare function enable.

Allowed values:

CH3P

Bit 13: Channel 3 capture/compare function polarity.

Allowed values:

CNT

Counter register

Offset: 0x24, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

Allowed values: 0-65535

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

Allowed values: 0-65535

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: Capture or compare value of channel 2.

Allowed values: 0-65535

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: Capture or compare value of channel 3.

Allowed values: 0-65535

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

Allowed values: 0-31

DMATC

Bits 8-12: DMA transfer count.

Allowed values: 0-31

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

Allowed values: 0-65535

TIMER10

0x40015400: General-purpose-timers

11/29 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMC
rw
Toggle Fields.

MMC

Bits 4-6: Master mode control.

DMAINTEN

DMA Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0OF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

CHCTL0_Input

Channel control register 0 ( (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CNT

Counter register

Offset: 0x24, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

Allowed values: 0-65535

TIMER11

0x40001800: General-purpose-timers

12/51 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

4/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

SPM

Bit 3: Single pulse mode.

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

SMCFG

slave mode configuration register

Offset: 0x8, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master-slave mode.

DMAINTEN

DMA and interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGIE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

TRGIF

Bit 6: Trigger interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

TRGG

Bit 6: Trigger event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CNT

Counter register

Offset: 0x24, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel0.

Allowed values: 0-65535

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

Allowed values: 0-65535

TIMER12

0x40001C00: General-purpose-timers

11/29 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMC
rw
Toggle Fields.

MMC

Bits 4-6: Master mode control.

DMAINTEN

DMA Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0OF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

CHCTL0_Input

Channel control register 0 ( (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CNT

Counter register

Offset: 0x24, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

Allowed values: 0-65535

TIMER13

0x40002000: General-purpose-timers

11/29 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMC
rw
Toggle Fields.

MMC

Bits 4-6: Master mode control.

DMAINTEN

DMA Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0OF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

CHCTL0_Input

Channel control register 0 ( (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CNT

Counter register

Offset: 0x24, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

Allowed values: 0-65535

TIMER2

0x40000400: General-purpose-timers

96/96 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

SPM

Bit 3: Single pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:

CAM

Bits 5-6: Counter aligns mode selection.

Allowed values:

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

Allowed values:

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI0S
rw 		MMC
rw 		DMAS
rw
Toggle Fields.

DMAS

Bit 3: DMA request source selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMC

Bits 4-6: Master mode control.

Allowed values:
0: Reset: Use UPG bit from SWEVG register
1: Enable: Use CEN bit from CTL0 register
2: Update: Use the update event

TI0S

Bit 7: Channel 0 trigger input selection.

Allowed values:
0: Normal: The CH0 pin input is selected as channel 0 trigger input
1: XOR: The XOR of CH0, CH1 and CH2 pins are selected as channel 0 trigger input

SMCFG

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

Allowed values:
0: Disabled: Slave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.
1: QuadratureDecoderMode0: Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.
2: QuadratureDecoderMode1: Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.
3: QuadratureDecoderMode2: Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.
4: RestartMode: Restart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: PauseMode: Pause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: EventMode: Event Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: ExternalClockMode: External Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.

TRGS

Bits 4-6: Trigger selection.

Allowed values:
0: ITI0: Internal Trigger 0 (ITI0)
1: ITI1: Internal Trigger 1 (ITI1)
2: ITI2: Internal Trigger 2 (ITI2)
4: CI0F_ED: CI0 Edge Detector (CI0F_ED)
5: CI0FE0: Filtered Timer Input 0 (CI0FE0)
6: CI1FE1: Filtered Timer Input 1 (CI1FE1)
7: ETIFP: External Trigger input (ETIFP)

MSM

Bit 7: Master-slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETFC

Bits 8-11: External trigger filter control.

Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8

ETPSC

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: External trigger prescaler disabled
1: Div2: ETI frequency divided by 2
2: Div4: ETI frequency divided by 4
3: Div8: ETI frequency divided by 8

SMC1

Bit 14: Part of SMC for enable External clock mode1.

Allowed values:
0: Disabled: External clock mode 1 disabled
1: Enabled: External clock mode 1 enabled. The counter is clocked by any active edge on the ETIF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETI is noninverted, active at high level or rising edge
1: Inverted: ETI is inverted, active at low level or falling edge

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		TRGIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

Allowed values:

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

Allowed values:

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

Allowed values:

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

Allowed values:

TRGIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

TRGDEN

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

Allowed values:

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

Allowed values:

CH2IF

Bit 3: Channel 2 capture/compare interrupt enable.

Allowed values:

CH3IF

Bit 4: Channel 3 capture/compare interrupt enable.

Allowed values:

TRGIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: Clear: No trigger event occured
1: Triggered: Trigger event occurred

CH0OF

Bit 9: Channel 0 over capture flag.

Allowed values:

CH1OF

Bit 10: Channel 1 over capture flag.

Allowed values:

CH2OF

Bit 11: Channel 2 over capture flag.

Allowed values:

CH3OF

Bit 12: Channel 3 over capture flag.

Allowed values:

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

Allowed values:

CH1G

Bit 2: Channel 1 capture or compare event generation.

Allowed values:

CH2G

Bit 3: Channel 2 capture or compare event generation.

Allowed values:

CH3G

Bit 4: Channel 3 capture or compare event generation.

Allowed values:

TRGG

Bit 6: Trigger event generation.

Allowed values:
1: Trigger: Generate a trigger event

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

Allowed values:

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

Allowed values:

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

Allowed values:

CH1MS

Bits 8-9: Channel 1 mode selection.

Allowed values:

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

Allowed values:

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

Allowed values:

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

Allowed values:

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

Allowed values:

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

Allowed values:

CH3MS

Bits 8-9: Channel 3 mode selection.

Allowed values:

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

Allowed values:

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

Allowed values:

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2P
rw 		CH2EN
rw 		CH1P
rw 		CH1EN
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

Allowed values:

CH0P

Bit 1: Channel 0 capture/compare function polarity.

Allowed values:

CH1EN

Bit 4: Channel 1 capture/compare function enable.

Allowed values:

CH1P

Bit 5: Channel 1 capture/compare function polarity.

Allowed values:

CH2EN

Bit 8: Channel 2 capture/compare function enable.

Allowed values:

CH2P

Bit 9: Channel 2 capture/compare function polarity.

Allowed values:

CH3EN

Bit 12: Channel 3 capture/compare function enable.

Allowed values:

CH3P

Bit 13: Channel 3 capture/compare function polarity.

Allowed values:

CNT

Counter register

Offset: 0x24, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

Allowed values: 0-65535

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

Allowed values: 0-65535

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: Capture or compare value of channel 2.

Allowed values: 0-65535

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: Capture or compare value of channel 3.

Allowed values: 0-65535

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

Allowed values: 0-31

DMATC

Bits 8-12: DMA transfer count.

Allowed values: 0-31

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

Allowed values: 0-65535

TIMER3

0x40000800: General-purpose-timers

96/96 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

SPM

Bit 3: Single pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:

CAM

Bits 5-6: Counter aligns mode selection.

Allowed values:

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

Allowed values:

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI0S
rw 		MMC
rw 		DMAS
rw
Toggle Fields.

DMAS

Bit 3: DMA request source selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMC

Bits 4-6: Master mode control.

Allowed values:
0: Reset: Use UPG bit from SWEVG register
1: Enable: Use CEN bit from CTL0 register
2: Update: Use the update event

TI0S

Bit 7: Channel 0 trigger input selection.

Allowed values:
0: Normal: The CH0 pin input is selected as channel 0 trigger input
1: XOR: The XOR of CH0, CH1 and CH2 pins are selected as channel 0 trigger input

SMCFG

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

Allowed values:
0: Disabled: Slave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.
1: QuadratureDecoderMode0: Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.
2: QuadratureDecoderMode1: Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.
3: QuadratureDecoderMode2: Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.
4: RestartMode: Restart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: PauseMode: Pause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: EventMode: Event Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: ExternalClockMode: External Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.

TRGS

Bits 4-6: Trigger selection.

Allowed values:
0: ITI0: Internal Trigger 0 (ITI0)
1: ITI1: Internal Trigger 1 (ITI1)
2: ITI2: Internal Trigger 2 (ITI2)
4: CI0F_ED: CI0 Edge Detector (CI0F_ED)
5: CI0FE0: Filtered Timer Input 0 (CI0FE0)
6: CI1FE1: Filtered Timer Input 1 (CI1FE1)
7: ETIFP: External Trigger input (ETIFP)

MSM

Bit 7: Master-slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETFC

Bits 8-11: External trigger filter control.

Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8

ETPSC

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: External trigger prescaler disabled
1: Div2: ETI frequency divided by 2
2: Div4: ETI frequency divided by 4
3: Div8: ETI frequency divided by 8

SMC1

Bit 14: Part of SMC for enable External clock mode1.

Allowed values:
0: Disabled: External clock mode 1 disabled
1: Enabled: External clock mode 1 enabled. The counter is clocked by any active edge on the ETIF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETI is noninverted, active at high level or rising edge
1: Inverted: ETI is inverted, active at low level or falling edge

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		TRGIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

Allowed values:

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

Allowed values:

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

Allowed values:

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

Allowed values:

TRGIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

TRGDEN

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

Allowed values:

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

Allowed values:

CH2IF

Bit 3: Channel 2 capture/compare interrupt enable.

Allowed values:

CH3IF

Bit 4: Channel 3 capture/compare interrupt enable.

Allowed values:

TRGIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: Clear: No trigger event occured
1: Triggered: Trigger event occurred

CH0OF

Bit 9: Channel 0 over capture flag.

Allowed values:

CH1OF

Bit 10: Channel 1 over capture flag.

Allowed values:

CH2OF

Bit 11: Channel 2 over capture flag.

Allowed values:

CH3OF

Bit 12: Channel 3 over capture flag.

Allowed values:

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

Allowed values:

CH1G

Bit 2: Channel 1 capture or compare event generation.

Allowed values:

CH2G

Bit 3: Channel 2 capture or compare event generation.

Allowed values:

CH3G

Bit 4: Channel 3 capture or compare event generation.

Allowed values:

TRGG

Bit 6: Trigger event generation.

Allowed values:
1: Trigger: Generate a trigger event

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

Allowed values:

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

Allowed values:

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

Allowed values:

CH1MS

Bits 8-9: Channel 1 mode selection.

Allowed values:

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

Allowed values:

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

Allowed values:

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

Allowed values:

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

Allowed values:

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

Allowed values:

CH3MS

Bits 8-9: Channel 3 mode selection.

Allowed values:

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

Allowed values:

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

Allowed values:

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2P
rw 		CH2EN
rw 		CH1P
rw 		CH1EN
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

Allowed values:

CH0P

Bit 1: Channel 0 capture/compare function polarity.

Allowed values:

CH1EN

Bit 4: Channel 1 capture/compare function enable.

Allowed values:

CH1P

Bit 5: Channel 1 capture/compare function polarity.

Allowed values:

CH2EN

Bit 8: Channel 2 capture/compare function enable.

Allowed values:

CH2P

Bit 9: Channel 2 capture/compare function polarity.

Allowed values:

CH3EN

Bit 12: Channel 3 capture/compare function enable.

Allowed values:

CH3P

Bit 13: Channel 3 capture/compare function polarity.

Allowed values:

CNT

Counter register

Offset: 0x24, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

Allowed values: 0-65535

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

Allowed values: 0-65535

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: Capture or compare value of channel 2.

Allowed values: 0-65535

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: Capture or compare value of channel 3.

Allowed values: 0-65535

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

Allowed values: 0-31

DMATC

Bits 8-12: DMA transfer count.

Allowed values: 0-31

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

Allowed values: 0-65535

TIMER4

0x40000C00: General-purpose-timers

96/96 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

SPM

Bit 3: Single pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:

CAM

Bits 5-6: Counter aligns mode selection.

Allowed values:

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

Allowed values:

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI0S
rw 		MMC
rw 		DMAS
rw
Toggle Fields.

DMAS

Bit 3: DMA request source selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMC

Bits 4-6: Master mode control.

Allowed values:
0: Reset: Use UPG bit from SWEVG register
1: Enable: Use CEN bit from CTL0 register
2: Update: Use the update event

TI0S

Bit 7: Channel 0 trigger input selection.

Allowed values:
0: Normal: The CH0 pin input is selected as channel 0 trigger input
1: XOR: The XOR of CH0, CH1 and CH2 pins are selected as channel 0 trigger input

SMCFG

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

Allowed values:
0: Disabled: Slave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.
1: QuadratureDecoderMode0: Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.
2: QuadratureDecoderMode1: Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.
3: QuadratureDecoderMode2: Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.
4: RestartMode: Restart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: PauseMode: Pause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: EventMode: Event Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: ExternalClockMode: External Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.

TRGS

Bits 4-6: Trigger selection.

Allowed values:
0: ITI0: Internal Trigger 0 (ITI0)
1: ITI1: Internal Trigger 1 (ITI1)
2: ITI2: Internal Trigger 2 (ITI2)
4: CI0F_ED: CI0 Edge Detector (CI0F_ED)
5: CI0FE0: Filtered Timer Input 0 (CI0FE0)
6: CI1FE1: Filtered Timer Input 1 (CI1FE1)
7: ETIFP: External Trigger input (ETIFP)

MSM

Bit 7: Master-slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETFC

Bits 8-11: External trigger filter control.

Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8

ETPSC

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: External trigger prescaler disabled
1: Div2: ETI frequency divided by 2
2: Div4: ETI frequency divided by 4
3: Div8: ETI frequency divided by 8

SMC1

Bit 14: Part of SMC for enable External clock mode1.

Allowed values:
0: Disabled: External clock mode 1 disabled
1: Enabled: External clock mode 1 enabled. The counter is clocked by any active edge on the ETIF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETI is noninverted, active at high level or rising edge
1: Inverted: ETI is inverted, active at low level or falling edge

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		TRGIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

Allowed values:

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

Allowed values:

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

Allowed values:

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

Allowed values:

TRGIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

TRGDEN

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

Allowed values:

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

Allowed values:

CH2IF

Bit 3: Channel 2 capture/compare interrupt enable.

Allowed values:

CH3IF

Bit 4: Channel 3 capture/compare interrupt enable.

Allowed values:

TRGIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: Clear: No trigger event occured
1: Triggered: Trigger event occurred

CH0OF

Bit 9: Channel 0 over capture flag.

Allowed values:

CH1OF

Bit 10: Channel 1 over capture flag.

Allowed values:

CH2OF

Bit 11: Channel 2 over capture flag.

Allowed values:

CH3OF

Bit 12: Channel 3 over capture flag.

Allowed values:

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

Allowed values:

CH1G

Bit 2: Channel 1 capture or compare event generation.

Allowed values:

CH2G

Bit 3: Channel 2 capture or compare event generation.

Allowed values:

CH3G

Bit 4: Channel 3 capture or compare event generation.

Allowed values:

TRGG

Bit 6: Trigger event generation.

Allowed values:
1: Trigger: Generate a trigger event

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

Allowed values:

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

Allowed values:

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

Allowed values:

CH1MS

Bits 8-9: Channel 1 mode selection.

Allowed values:

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

Allowed values:

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

Allowed values:

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

Allowed values:

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

Allowed values:

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

Allowed values:

CH3MS

Bits 8-9: Channel 3 mode selection.

Allowed values:

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

Allowed values:

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

Allowed values:

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2P
rw 		CH2EN
rw 		CH1P
rw 		CH1EN
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

Allowed values:

CH0P

Bit 1: Channel 0 capture/compare function polarity.

Allowed values:

CH1EN

Bit 4: Channel 1 capture/compare function enable.

Allowed values:

CH1P

Bit 5: Channel 1 capture/compare function polarity.

Allowed values:

CH2EN

Bit 8: Channel 2 capture/compare function enable.

Allowed values:

CH2P

Bit 9: Channel 2 capture/compare function polarity.

Allowed values:

CH3EN

Bit 12: Channel 3 capture/compare function enable.

Allowed values:

CH3P

Bit 13: Channel 3 capture/compare function polarity.

Allowed values:

CNT

Counter register

Offset: 0x24, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

Allowed values: 0-65535

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

Allowed values: 0-65535

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: Capture or compare value of channel 2.

Allowed values: 0-65535

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: Capture or compare value of channel 3.

Allowed values: 0-65535

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

Allowed values: 0-31

DMATC

Bits 8-12: DMA transfer count.

Allowed values: 0-31

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

Allowed values: 0-65535

TIMER5

0x40001000: Basic-timers

13/13 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARSE
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

SPM

Bit 3: Single pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMC
rw
Toggle Fields.

MMC

Bits 4-6: Master mode control.

Allowed values:
0: Reset: Use UPG bit from SWEVG register
1: Enable: Use CEN bit from CTL0 register
2: Update: Use the update event

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPDEN
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

INTF

Interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CNT

Counter register

Offset: 0x24, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

TIMER6

0x40001400: Basic-timers

13/13 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARSE
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

SPM

Bit 3: Single pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMC
rw
Toggle Fields.

MMC

Bits 4-6: Master mode control.

Allowed values:
0: Reset: Use UPG bit from SWEVG register
1: Enable: Use CEN bit from CTL0 register
2: Update: Use the update event

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPDEN
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

INTF

Interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CNT

Counter register

Offset: 0x24, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

TIMER7

0x40013400: Advanced timer

127/127 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UPDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

UPS

Bit 2: Update source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UPG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

SPM

Bit 3: Single pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CAM

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAlignedCountingDown: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAlignedCountingUp: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAlignedCountingUpDown: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:
0: Disabled: The shadow register for CAR is disabled
1: Enabled: The shadow register for CAR is enabled

CKDIV

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISO3
rw 		ISO2N
rw 		ISO2
rw 		ISO1N
rw 		ISO1
rw 		ISO0N
rw 		ISO0
rw 		TI0S
rw 		MMC
rw 		DMAS
rw 		CCUC
rw 		CCSE
rw
Toggle Fields.

CCSE

Bit 0: Commutation control shadow enable.

Allowed values:
0: NotPreloaded: The shadow registers for CHxEN, CHxNEN and CHxCOMCTL bits are disabled
1: Preloaded: The shadow registers for CHxEN, CHxNEN and CHxCOMCTL bits are enabled

CCUC

Bit 2: Commutation control shadow register update control.

Allowed values:
0: Default: Capture/compare are updated only by setting the CMTG bit
1: WithRisingEdge: Capture/compare are updated by setting the CMTG bit or when an rising edge occurs on TRGI

DMAS

Bit 3: DMA request source selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMC

Bits 4-6: Master mode control.

Allowed values:
0: Reset: Use UPG bit from SWEVG register
1: Enable: Use CEN bit from CTL0 register
2: Update: Use the update event
3: CaptureComparePulse: The trigger output send a positive pulse when a capture or a compare match occurred in channel 0
4: CompareO0C: O0CPRE signal is used as trigger output
5: CompareO1C: O1CPRE signal is used as trigger output
6: CompareO2C: O2CPRE signal is used as trigger output
7: CompareO3C: O3CPRE signal is used as trigger output

TI0S

Bit 7: Channel 0 trigger input selection.

Allowed values:
0: Normal: The CH0 pin input is selected as channel 0 trigger input
1: XOR: The XOR of CH0, CH1 and CH2 pins are selected as channel 0 trigger input

ISO0

Bit 8: Idle state of channel 0 output.

Allowed values:
0: Low: CHn_O=0 (after a dead-time if CHn_ON is implemented) when POEN=0
1: High: CHn_O=1 (after a dead-time if CHn_ON is implemented) when POEN=0

ISO0N

Bit 9: Idle state of channel 0 complementary output.

Allowed values:
0: Low: CHn_ON=0 when POEN=0
1: High: CHn_ON=1 when POEN=0

ISO1

Bit 10: Idle state of channel 1 output.

Allowed values:

ISO1N

Bit 11: Idle state of channel 1 complementary output.

Allowed values:
0: Low: CHn_ON=0 when POEN=0
1: High: CHn_ON=1 when POEN=0

ISO2

Bit 12: Idle state of channel 2 output.

Allowed values:
0: Low: CHn_O=0 (after a dead-time if CHn_ON is implemented) when POEN=0
1: High: CHn_O=1 (after a dead-time if CHn_ON is implemented) when POEN=0

ISO2N

Bit 13: Idle state of channel 2 complementary output.

Allowed values:
0: Low: CHn_ON=0 when POEN=0
1: High: CHn_ON=1 when POEN=0

ISO3

Bit 14: Idle state of channel 3 output.

Allowed values:
0: Low: CHn_O=0 (after a dead-time if CHn_ON is implemented) when POEN=0
1: High: CHn_O=1 (after a dead-time if CHn_ON is implemented) when POEN=0

SMCFG

slave mode configuration register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

Allowed values:
0: Disabled: Slave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.
1: QuadratureDecoderMode0: Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.
2: QuadratureDecoderMode1: Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.
3: QuadratureDecoderMode2: Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.
4: RestartMode: Restart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: PauseMode: Pause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: EventMode: Event Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: ExternalClockMode: External Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.

TRGS

Bits 4-6: Trigger selection.

Allowed values:
0: ITI0: Internal Trigger 0 (ITI0)
1: ITI1: Internal Trigger 1 (ITI1)
2: ITI2: Internal Trigger 2 (ITI2)
4: CI0F_ED: CI0 Edge Detector (CI0F_ED)
5: CI0FE0: Filtered Timer Input 0 (CI0FE0)
6: CI1FE1: Filtered Timer Input 1 (CI1FE1)
7: ETIFP: External Trigger input (ETIFP)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETFC

Bits 8-11: External trigger filter control.

Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8

ETPSC

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: External trigger prescaler disabled
1: Div2: ETI frequency divided by 2
2: Div4: ETI frequency divided by 4
3: Div8: ETI frequency divided by 8

SMC1

Bit 14: Part of SMC for enable External clock mode1.

Allowed values:
0: Disabled: External clock mode 1 disabled
1: Enabled: External clock mode 1 enabled. The counter is clocked by any active edge on the ETIF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETI is noninverted, active at high level or rising edge
1: Inverted: ETI is inverted, active at low level or falling edge

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CMTDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		BRKIE
rw 		TRGIE
rw 		CMTIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

Allowed values:
0: Disabled: Capture/compare interrupt disabled
1: Enabled: Capture/compare interrupt enabled

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

Allowed values:
0: Disabled: Capture/compare interrupt disabled
1: Enabled: Capture/compare interrupt enabled

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

Allowed values:
0: Disabled: Capture/compare interrupt disabled
1: Enabled: Capture/compare interrupt enabled

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

Allowed values:
0: Disabled: Capture/compare interrupt disabled
1: Enabled: Capture/compare interrupt enabled

CMTIE

Bit 5: commutation interrupt enable.

Allowed values:
0: Disabled: Commutation interrupt disabled
1: Enabled: Commutation interrupt enabled

TRGIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BRKIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UPDEN

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

Allowed values:
0: Disabled: Capture/compare DMA request disabled
1: Enabled: Capture/compare DMA request enabled

CMTDEN

Bit 13: Commutation DMA request enable.

Allowed values:
0: Disabled: Commutation DMA request disabled
1: Enabled: Commutation DMA request enabled

TRGDEN

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

INTF

Interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		BRKIF
rw 		TRGIF
rw 		CMTIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update interrupt occurred
1: UpdatePending: Update interrupt pending.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

Allowed values:
0: Clear: No capture or compare interrupt occurred
1: CaptureCompare: A capture or compare event occurred

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

Allowed values:
0: Clear: No capture or compare interrupt occurred
1: CaptureCompare: A capture or compare event occurred

CH2IF

Bit 3: Channel 2 capture/compare interrupt flag.

Allowed values:
0: Clear: No capture or compare interrupt occurred
1: CaptureCompare: A capture or compare event occurred

CH3IF

Bit 4: Channel 3 capture/compare interrupt flag.

Allowed values:
0: Clear: No capture or compare interrupt occurred
1: CaptureCompare: A capture or compare event occurred

CMTIF

Bit 5: Channel commutation interrupt flag.

Allowed values:
0: Clear: No channel commutation event occured
1: Commutation: Channel commutation event occurred

TRGIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: Clear: No trigger event occured
1: Triggered: Trigger event occurred

BRKIF

Bit 7: Break interrupt flag.

Allowed values:
0: Clear: No active level break detected
1: Break: Active level detected

CH0OF

Bit 9: Channel 0 over capture flag.

Allowed values:
0: Clear: No over capture occurred
1: OverCapture: A capture event occured while CHnIF was already set

CH1OF

Bit 10: Channel 1 over capture flag.

Allowed values:
0: Clear: No over capture occurred
1: OverCapture: A capture event occured while CHnIF was already set

CH2OF

Bit 11: Channel 2 over capture flag.

Allowed values:
0: Clear: No over capture occurred
1: OverCapture: A capture event occured while CHnIF was already set

CH3OF

Bit 12: Channel 3 over capture flag.

Allowed values:
0: Clear: No over capture occurred
1: OverCapture: A capture event occured while CHnIF was already set

SWEVG

Software event generation register

Offset: 0x14, reset: 0x0000, access: write-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRKG
w 		TRGG
w 		CMTG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update event generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CH0G

Bit 1: Channel 0 capture or compare event generation.

Allowed values:
1: CaptureCompare: Generate a capture or compare event

CH1G

Bit 2: Channel 1 capture or compare event generation.

Allowed values:
1: CaptureCompare: Generate a capture or compare event

CH2G

Bit 3: Channel 2 capture or compare event generation.

Allowed values:
1: CaptureCompare: Generate a capture or compare event

CH3G

Bit 4: Channel 3 capture or compare event generation.

Allowed values:
1: CaptureCompare: Generate a capture or compare event

CMTG

Bit 5: Channel commutation event generation.

Allowed values:
1: Update: Generate a channel commutation event, updating capture/compare control registers based on the value of CCSE

TRGG

Bit 6: Trigger event generation.

Allowed values:
1: Trigger: Generate a trigger event

BRKG

Bit 7: Break event generation.

Allowed values:
1: Break: Generate a break event

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

Allowed values:
0: Output: Channel is configured as output
1: CI0: Channel is configured as input, ISx is connected to CI0FEx
2: CI1: Channel is configured as input, ISx is connected to CI1FEx
3: ITS: Channel is configured as input, ISx is connected to ITS

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

Allowed values:
0: Div1: Prescaler disabled, capture on every edge
1: Div2: Capture every 2 edges
2: Div4: Capture every 4 edges
3: Div8: Capture every 8 edges

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8

CH1MS

Bits 8-9: Channel 1 mode selection.

Allowed values:

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

Allowed values:

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

Allowed values:

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

Allowed values:

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

Allowed values:

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

Allowed values:

CH3MS

Bits 8-9: Channel 3 mode selection.

Allowed values:

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

Allowed values:

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

Allowed values:

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2NEN
rw 		CH2P
rw 		CH2EN
rw 		CH1NP
rw 		CH1NEN
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0NEN
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

Allowed values:
0: Disabled: Channel output is disabled
1: Enabled: Channel output is enabled

CH0P

Bit 1: Channel 0 capture/compare function polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH0NEN

Bit 2: Channel 0 complementary output enable.

Allowed values:

CH0NP

Bit 3: Channel 0 complementary output polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH1EN

Bit 4: Channel 1 capture/compare function enable.

Allowed values:
0: Disabled: Channel output is disabled
1: Enabled: Channel output is enabled

CH1P

Bit 5: Channel 1 capture/compare function polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH1NEN

Bit 6: Channel 1 complementary output enable.

Allowed values:

CH1NP

Bit 7: Channel 1 complementary output polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH2EN

Bit 8: Channel 2 capture/compare function enable.

Allowed values:
0: Disabled: Channel output is disabled
1: Enabled: Channel output is enabled

CH2P

Bit 9: Channel 2 capture/compare function polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH2NEN

Bit 10: Channel 2 complementary output enable.

Allowed values:

CH2NP

Bit 11: Channel 2 complementary output polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CH3EN

Bit 12: Channel 3 capture/compare function enable.

Allowed values:
0: Disabled: Channel output is disabled
1: Enabled: Channel output is enabled

CH3P

Bit 13: Channel 3 capture/compare function polarity.

Allowed values:
0: NotInverted: Active high
1: Inverted: Active low

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

CAR

Counter auto-reload register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto-reload.

Allowed values: 0-65535

CREP

Counter repetition register

Offset: 0x30, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CREP
rw
Toggle Fields.

CREP

Bits 0-7: Counter repetition value.

Allowed values: 0-255

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

Allowed values: 0-65535

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel 1.

Allowed values: 0-65535

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: Capture or compare value of channel 2.

Allowed values: 0-65535

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: Capture or compare value of channel 3.

Allowed values: 0-65535

CCHP

channel complementary protection register

Offset: 0x44, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POEN
rw 		OAEN
rw 		BRKP
rw 		BRKEN
rw 		ROS
rw 		IOS
rw 		PROT
rw 		DTCFG
rw
Toggle Fields.

DTCFG

Bits 0-7: Dead time configure.

Allowed values: 0-255

PROT

Bits 8-9: Complementary register protect control.

Allowed values:
0: Disabled: Write protection disabled
1: Mode0: Protection mode 0
2: Mode1: Protection mode 1
3: Mode2: Protection mode 2

IOS

Bit 10: Idle mode off-state configure.

Allowed values:
0: Disabled: When POEN is reset, the channel output signals are disabled
1: Enabled: When POEN is reset, the channel output signals are enabled

ROS

Bit 11: Run mode off-state configure.

Allowed values:
0: Disabled: When POEN is set, the channel output signals are disabled
1: Enabled: When POEN is set, the channel output signals are enabled

BRKEN

Bit 12: Break enable.

Allowed values:
0: Disabled: Break inputs disabled
1: Enabled: Break inputs enabled

BRKP

Bit 13: Break polarity.

Allowed values:
0: Inverted: BRKIN is active low
1: NotInverted: BRKIN is active high

OAEN

Bit 14: Output automatic enable.

Allowed values:
0: Manual: POEN cannot be set by hardware
1: Automatic: POEN can be set by hardware automatically at the next update event

POEN

Bit 15: Primary output enable.

Allowed values:
0: Disabled: Channel outputs are disabled
1: Enabled: Channel outputs are enabled

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

Allowed values: 0-31

DMATC

Bits 8-12: DMA transfer count.

Allowed values: 0-31

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

Allowed values: 0-65535

TIMER8

0x40014c00: General-purpose-timers

12/51 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

4/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

SPM

Bit 3: Single pulse mode.

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

SMCFG

slave mode configuration register

Offset: 0x8, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master-slave mode.

DMAINTEN

DMA and interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGIE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

TRGIF

Bit 6: Trigger interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

TRGG

Bit 6: Trigger event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CNT

Counter register

Offset: 0x24, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel0.

Allowed values: 0-65535

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

Allowed values: 0-65535

TIMER9

0x40015000: General-purpose-timers

11/29 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

4/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:

UPDIS

Bit 1: Update disable.

Allowed values:

UPS

Bit 2: Update source.

Allowed values:

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

Allowed values:

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMC
rw
Toggle Fields.

MMC

Bits 4-6: Master mode control.

DMAINTEN

DMA Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

Allowed values:

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0OF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

Allowed values:

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

Allowed values:

CH0G

Bit 1: Channel 0 capture or compare event generation.

CHCTL0_Input

Channel control register 0 ( (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CNT

Counter register

Offset: 0x24, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

Allowed values: 0-65535

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

Allowed values: 0-65535

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

Allowed values: 0-65535

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

Allowed values: 0-65535

TLI

0x40016800: TFT-LCD interface

13/93 fields covered. Toggle Registers.

SPSZ

Synchronous pulse size register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HPSZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPSZ
rw
Toggle Fields.

VPSZ

Bits 0-11: size of vertical synchronous pluse.

HPSZ

Bits 16-27: size of horizontal synchronous pluse.

BPSZ

Back-porch size register

Offset: 0xC, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HBPSZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBPSZ
rw
Toggle Fields.

VBPSZ

Bits 0-11: Size of the vertical back porch plus synchronous pulse.

HBPSZ

Bits 16-27: Size of the horizontal back porch plus synchronous pulse.

ASZ

Active size register

Offset: 0x10, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HASZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VASZ
rw
Toggle Fields.

VASZ

Bits 0-11: Size of the vertical active area width plus back porch and synchronous pulse.

HASZ

Bits 16-27: Size of the horizontal active area width plus back porch and synchronous pulse.

TSZ

Total size register

Offset: 0x14, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTSZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VTSZ
rw
Toggle Fields.

VTSZ

Bits 0-11: Vertical total size of the display.

HTSZ

Bits 16-27: Horizontal total size of the display.

CTL

Control register

Offset: 0x18, reset: 0x00002220, access: Unspecified

3/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HPPS
rw 		VPPS
rw 		DEPS
rw 		CLKPS
rw 		DFEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDB
r 		GDB
r 		BDB
r 		TLIEN
rw
Toggle Fields.

TLIEN

Bit 0: TLI enable bit.

BDB

Bits 4-6: Blue channel Dither Bits Number.

GDB

Bits 8-10: Green channel Dither Bits Number.

RDB

Bits 12-14: Red channel Dither Bits Number.

DFEN

Bit 16: Dither Function Enable .

CLKPS

Bit 28: Pixel Clock Polarity Selection .

DEPS

Bit 29: Data Enable Polarity Selection.

VPPS

Bit 30: Vertical Pulse Polarity Selection.

HPPS

Bit 31: Horizontal Pulse Polarity Selection .

RL

Reload layer register

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FBR
rw 		RQR
rw
Toggle Fields.

RQR

Bit 0: Request Reload.

FBR

Bit 1: Frame Blank Reload.

BGC

Background color register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BVR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BVG
rw 		BVB
rw
Toggle Fields.

BVB

Bits 0-7: Background value blue .

BVG

Bits 8-15: Background value green .

BVR

Bits 16-23: Background value red .

INTEN

Interrupt enable register

Offset: 0x34, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCRIE
rw 		TEIE
rw 		FEIE
rw 		LMIE
rw
Toggle Fields.

LMIE

Bit 0: Line Mark Interrupt Enable.

FEIE

Bit 1: FIFO Error Interrupt Enable.

TEIE

Bit 2: Transaction Error Interrupt Enable.

LCRIE

Bit 3: Layer Configuration Reloaded Interrupt Enable.

INTF

Interrupt flag register

Offset: 0x38, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCRF
r 		TEF
r 		FEF
r 		LMF
r
Toggle Fields.

LMF

Bit 0: Line Mark Flag.

FEF

Bit 1: FIFO Error Flag.

TEF

Bit 2: Transaction Error Flag.

LCRF

Bit 3: Layer Configuration Reloaded Flag.

INTC

Interrupt flag clear register

Offset: 0x3C, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCRC
w 		TEC
w 		FEC
w 		LMC
w
Toggle Fields.

LMC

Bit 0: Line Mark Flag Clear.

FEC

Bit 1: FIFO Error Flag Clear.

TEC

Bit 2: Transaction Error Flag Clear.

LCRC

Bit 3: Layer Configuration Reloaded Flag Clear.

LM

Line mark register

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LM
rw
Toggle Fields.

LM

Bits 0-10: Line Mark value.

CPPOS

Current pixel position register

Offset: 0x44, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HPOS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPOS
r
Toggle Fields.

VPOS

Bits 0-15: Vertical position.

HPOS

Bits 16-31: Horizontal position.

STAT

Status register

Offset: 0x48, reset: 0x0000000F, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HS
r 		VS
r 		HDE
r 		VDE
r
Toggle Fields.

VDE

Bit 0: Current VDE status.

HDE

Bit 1: Current HDE status.

VS

Bit 2: Current VS staus of the TLI .

HS

Bit 3: Current HS staus of the TLI .

L0CTL

Layer 0 control register

Offset: 0x84, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LUTEN
rw 		CKEYEN
rw 		LEN
rw
Toggle Fields.

LEN

Bit 0: Layer enable.

CKEYEN

Bit 1: Color keying enable.

LUTEN

Bit 4: LUT enable .

L0HPOS

Layer 0 horizontal position parameters register

Offset: 0x88, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WLP
rw
Toggle Fields.

WLP

Bits 0-11: Window left position.

WRP

Bits 16-27: Window right position.

L0VPOS

Layer 0 vertical position parameters register

Offset: 0x8C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WBP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WTP
rw
Toggle Fields.

WTP

Bits 0-11: Window top position.

WBP

Bits 16-27: Window bottom position.

L0CKEY

Layer 0 color key register

Offset: 0x90, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKEYR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKEYG
rw 		CKEYB
rw
Toggle Fields.

CKEYB

Bits 0-7: Color Key Blue.

CKEYG

Bits 8-15: Color Key Green.

CKEYR

Bits 16-23: Color Key Red.

L0PPF

Layer 0 packeted pixel format register

Offset: 0x94, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PPF
rw
Toggle Fields.

PPF

Bits 0-2: Packeted Pixel Format.

L0SA

Layer 0 specified alpha register

Offset: 0x98, reset: 0x000000FF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SA
rw
Toggle Fields.

SA

Bits 0-7: Specified alpha.

L0DC

Layer 0 default color register

Offset: 0x9C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DCA
rw 		DCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCG
rw 		DCB
rw
Toggle Fields.

DCB

Bits 0-7: The default color blue.

DCG

Bits 8-15: The default color green.

DCR

Bits 16-23: The default color red.

DCA

Bits 24-31: The default color ALPHA.

L0BLEND

Layer 0 blending register

Offset: 0xA0, reset: 0x00000607, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACF1
rw 		ACF2
rw
Toggle Fields.

ACF2

Bits 0-2: Alpha Calculation Factor 2 of Blending Method.

ACF1

Bits 8-10: Alpha Calculation Factor 1 of Blending Method.

L0FBADDR

Layer 0 frame base address register

Offset: 0xAC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FBADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FBADD
rw
Toggle Fields.

FBADD

Bits 0-31: Frame Buffer base Address.

L0FLLEN

Layer 0 frame line length register

Offset: 0xB0, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STDOFF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLL
rw
Toggle Fields.

FLL

Bits 0-13: Frame Line Length.

STDOFF

Bits 16-29: Frame Buffer Stride Offset.

L0FTLN

Layer 0 frame total line number register

Offset: 0xB4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLN
rw
Toggle Fields.

FTLN

Bits 0-10: Frame Total Line Number.

L0LUT

Layer 0 look up table register

Offset: 0xC4, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TADD
w 		TR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		TB
w
Toggle Fields.

TB

Bits 0-7: Blue channel of a LUT entry.

TG

Bits 8-15: Green channel of a LUT entry.

TR

Bits 16-23: Red Channel of a LUT entry.

TADD

Bits 24-31: Look Up Table Write Address.

L1CTL

Layer 1 control register

Offset: 0x104, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LUTEN
rw 		CKEYEN
rw 		LEN
rw
Toggle Fields.

LEN

Bit 0: Layer enable.

CKEYEN

Bit 1: Color keying enable.

LUTEN

Bit 4: LUT enable .

L1HPOS

Layer 1 horizontal position parameters register

Offset: 0x108, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WLP
rw
Toggle Fields.

WLP

Bits 0-11: Window left position.

WRP

Bits 16-27: Window right position.

L1VPOS

Layer 1 vertical position parameters register

Offset: 0x10C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WBP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WTP
rw
Toggle Fields.

WTP

Bits 0-11: Window top position.

WBP

Bits 16-27: Window bottom position.

L1CKEY

Layer 1 color key register

Offset: 0x110, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKEYR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKEYG
rw 		CKEYB
rw
Toggle Fields.

CKEYB

Bits 0-7: Color Key Blue.

CKEYG

Bits 8-15: Color Key Green.

CKEYR

Bits 16-23: Color Key Red.

L1PPF

Layer 1 packeted pixel format register

Offset: 0x114, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PPF
rw
Toggle Fields.

PPF

Bits 0-2: Packeted Pixel Format.

L1SA

Layer 1 specified alpha register

Offset: 0x118, reset: 0x000000FF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SA
rw
Toggle Fields.

SA

Bits 0-7: Specified alpha.

L1DC

Layer 1 default color register

Offset: 0x11C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DCA
rw 		DCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCG
rw 		DCB
rw
Toggle Fields.

DCB

Bits 0-7: The default color blue.

DCG

Bits 8-15: The default color green.

DCR

Bits 16-23: The default color red.

DCA

Bits 24-31: The default color ALPHA.

L1BLEND

Layer 1 blending register

Offset: 0x120, reset: 0x00000607, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACF1
rw 		ACF2
rw
Toggle Fields.

ACF2

Bits 0-2: Alpha Calculation Factor 2 of Blending Method.

ACF1

Bits 8-10: Alpha Calculation Factor 1 of Blending Method.

L1FBADDR

Layer 1 frame base address register

Offset: 0x12C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FBADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FBADD
rw
Toggle Fields.

FBADD

Bits 0-31: Frame Buffer base Address.

L1FLLEN

Layer 1 frame line length register

Offset: 0x130, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STDOFF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLL
rw
Toggle Fields.

FLL

Bits 0-13: Frame Line Length.

STDOFF

Bits 16-29: Frame Buffer Stride Offset.

L1FTLN

Layer 1 frame total line number register

Offset: 0x134, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLN
rw
Toggle Fields.

FTLN

Bits 0-10: Frame Total Line Number.

L1LUT

Layer 1 look up table register

Offset: 0x144, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TADD
w 		TR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		TB
w
Toggle Fields.

TB

Bits 0-7: Blue channel of a LUT entry.

TG

Bits 8-15: Green channel of a LUT entry.

TR

Bits 16-23: Red channel of a LUT entry.

TADD

Bits 24-31: Look Up Table Write Address.

UART3

0x40004C00: Universal asynchronous receiver transmitter

6/38 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: Unspecified

6/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LBDF
rw 		TBE
r 		TC
rw 		RBNE
rw 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

INTDIV

Bits 4-15: Integer part of baud-rate divider.

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

RWU

Bit 1: Receiver wakeup from mute mode.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE line detected interrupt enable.

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

PERRIE

Bit 8: Parity error interrupt enable.

PM

Bit 9: Parity mode.

PCEN

Bit 10: Parity check function enable.

WM

Bit 11: Wakeup method in mute mode.

WL

Bit 12: Word length.

UEN

Bit 13: USART enable.

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

LBLEN

Bit 5: LIN break frame length.

LBDIE

Bit 6: LIN break detection interrupt enable.

STB

Bits 12-13: STOP bits length.

LMEN

Bit 14: LIN mode enable.

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DENT
rw 		DENR
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDEN

Bit 3: Half-duplex selection.

DENR

Bit 6: DMA request enable for reception.

DENT

Bit 7: DMA request enable for transmission.

GP

Guard time and prescaler register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-7: specify the division factor that is used to divide the peripheral clock (PCLK1/PCLK2) to generate the low-power frequency.

UART4

0x40005000: Universal asynchronous receiver transmitter

6/38 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: Unspecified

6/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LBDF
rw 		TBE
r 		TC
rw 		RBNE
rw 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

INTDIV

Bits 4-15: Integer part of baud-rate divider.

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

RWU

Bit 1: Receiver wakeup from mute mode.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE line detected interrupt enable.

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

PERRIE

Bit 8: Parity error interrupt enable.

PM

Bit 9: Parity mode.

PCEN

Bit 10: Parity check function enable.

WM

Bit 11: Wakeup method in mute mode.

WL

Bit 12: Word length.

UEN

Bit 13: USART enable.

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

LBLEN

Bit 5: LIN break frame length.

LBDIE

Bit 6: LIN break detection interrupt enable.

STB

Bits 12-13: STOP bits length.

LMEN

Bit 14: LIN mode enable.

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DENT
rw 		DENR
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDEN

Bit 3: Half-duplex selection.

DENR

Bit 6: DMA request enable for reception.

DENT

Bit 7: DMA request enable for transmission.

GP

Guard time and prescaler register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-7: specify the division factor that is used to divide the peripheral clock (PCLK1/PCLK2) to generate the low-power frequency.

UART6

0x40007800: Universal asynchronous receiver transmitter

6/38 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: Unspecified

6/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LBDF
rw 		TBE
r 		TC
rw 		RBNE
rw 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

INTDIV

Bits 4-15: Integer part of baud-rate divider.

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

RWU

Bit 1: Receiver wakeup from mute mode.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE line detected interrupt enable.

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

PERRIE

Bit 8: Parity error interrupt enable.

PM

Bit 9: Parity mode.

PCEN

Bit 10: Parity check function enable.

WM

Bit 11: Wakeup method in mute mode.

WL

Bit 12: Word length.

UEN

Bit 13: USART enable.

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

LBLEN

Bit 5: LIN break frame length.

LBDIE

Bit 6: LIN break detection interrupt enable.

STB

Bits 12-13: STOP bits length.

LMEN

Bit 14: LIN mode enable.

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DENT
rw 		DENR
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDEN

Bit 3: Half-duplex selection.

DENR

Bit 6: DMA request enable for reception.

DENT

Bit 7: DMA request enable for transmission.

GP

Guard time and prescaler register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-7: specify the division factor that is used to divide the peripheral clock (PCLK1/PCLK2) to generate the low-power frequency.

UART7

0x40007C00: Universal asynchronous receiver transmitter

6/38 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: Unspecified

6/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LBDF
rw 		TBE
r 		TC
rw 		RBNE
rw 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

INTDIV

Bits 4-15: Integer part of baud-rate divider.

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

RWU

Bit 1: Receiver wakeup from mute mode.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE line detected interrupt enable.

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

PERRIE

Bit 8: Parity error interrupt enable.

PM

Bit 9: Parity mode.

PCEN

Bit 10: Parity check function enable.

WM

Bit 11: Wakeup method in mute mode.

WL

Bit 12: Word length.

UEN

Bit 13: USART enable.

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

LBLEN

Bit 5: LIN break frame length.

LBDIE

Bit 6: LIN break detection interrupt enable.

STB

Bits 12-13: STOP bits length.

LMEN

Bit 14: LIN mode enable.

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DENT
rw 		DENR
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDEN

Bit 3: Half-duplex selection.

DENR

Bit 6: DMA request enable for reception.

DENT

Bit 7: DMA request enable for transmission.

GP

Guard time and prescaler register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-7: specify the division factor that is used to divide the peripheral clock (PCLK1/PCLK2) to generate the low-power frequency.

USART0

0x40013800: Universal synchronous asynchronous receiver transmitter

48/62 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSF
rw 		LBDF
rw 		TBE
r 		TC
rw 		RBNE
rw 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS change flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

Allowed values: 0-255

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

Allowed values: 0-15

INTDIV

Bits 4-15: Integer part of baud-rate divider.

Allowed values: 0-4095

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

Allowed values:
0: Disabled: Do not transmit a break frame
1: Enabled: Do not transmit a break frame

RWU

Bit 1: Receiver wakeup from mute mode.

Allowed values:
0: Disabled: Receiver wakeup from mute mode
1: Enabled: Receiver in mute mode

REN

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TEN

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE line detected interrupt enable.

Allowed values:
0: Disabled: Idle line detected interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLEF=1 in the STAT register

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

Allowed values:
0: Disabled: Read data buffer not empty and overrrun error interrupts are disabled
1: Enabled: Interrupt is generated whenever ORERR=1 or RBNE=1 in the STAT register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Transmission complete interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the STAT register

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

Allowed values:
0: Disabled: Transmission register empty interrupt is disabled
1: Enabled: Interrupt is generated whenever TBE=1 in the STAT register

PERRIE

Bit 8: Parity error interrupt enable.

Allowed values:
0: Disabled: Parity error interrupt is disabled
1: Enabled: Interrupt is generated whenever PERR=1 in the STAT register

PM

Bit 9: Parity mode.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCEN

Bit 10: Parity check function enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WM

Bit 11: Wakeup method in mute mode.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

WL

Bit 12: Word length.

Allowed values:
0: Bit8: 8 data bits
1: Bit9: 9 data bits

UEN

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART prescaler and outputs enabled

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

Allowed values:
0: Bit4: 4-bit address detection
1: Full: Full-bit address detection

LBLEN

Bit 5: LIN break frame length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: An interrupt is generated whenever LBDF=1 in the STAT register

CLEN

Bit 8: CK Length.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPH

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPL

Bit 10: Clock polarity.

Allowed values:
0: NotInverted: Steady low value on CK pin outside tranmission window
1: Inverted: Steady high value on CK pin outside tranmission window

CKEN

Bit 11: CK pin enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STB

Bits 12-13: STOP bits length.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LMEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt is disabled
1: Enabled: An interrupt is generated when FERR=1 or ORERR=1 or NERR=1 in the STAT register

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDEN

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NKEN

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DENR

Bit 6: DMA request enable for reception.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DENT

Bit 7: DMA request enable for transmission.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSEN

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSEN

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: An interrupt is generated whenever CTS=1 in the STAT register

GP

Guard time and prescaler register

Offset: 0x18, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

Allowed values: 0-255

GUAT

Bits 8-15: Guard time value in Smartcard mode.

Allowed values: 0-255

CTL3

Control register 3

Offset: 0x80, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSBF
rw 		DINV
rw 		TINV
rw 		RINV
rw 		EBIE
rw 		RTIE
rw 		SCRTNUM
rw 		RTEN
rw
Toggle Fields.

RTEN

Bit 0: Receiver timeout enable.

SCRTNUM

Bits 1-3: Smartcard auto-retry number.

RTIE

Bit 4: Interrupt enable bit of receive timeout event.

EBIE

Bit 5: Interrupt enable bit of end of block event.

RINV

Bit 8: RX pin level inversion.

TINV

Bit 9: TX pin level inversion.

DINV

Bit 10: Data bit level inversion.

MSBF

Bit 11: Most significant bit first.

RT

Receiver timeout register

Offset: 0x84, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BL
rw 		RT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT
rw
Toggle Fields.

RT

Bits 0-23: Receiver timeout threshold.

Allowed values: 0-16777215

BL

Bits 24-31: Block Length.

Allowed values: 0-255

STAT1

Status register 1

Offset: 0x88, reset: 0x00000000, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBF
w 		RTF
w
Toggle Fields.

RTF

Bit 11: Receiver timeout flag.

EBF

Bit 12: End of block flag.

BSY

Bit 16: Busy flag.

USART1

0x40004400: Universal synchronous asynchronous receiver transmitter

48/62 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSF
rw 		LBDF
rw 		TBE
r 		TC
rw 		RBNE
rw 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS change flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

Allowed values: 0-255

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

Allowed values: 0-15

INTDIV

Bits 4-15: Integer part of baud-rate divider.

Allowed values: 0-4095

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

Allowed values:
0: Disabled: Do not transmit a break frame
1: Enabled: Do not transmit a break frame

RWU

Bit 1: Receiver wakeup from mute mode.

Allowed values:
0: Disabled: Receiver wakeup from mute mode
1: Enabled: Receiver in mute mode

REN

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TEN

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE line detected interrupt enable.

Allowed values:
0: Disabled: Idle line detected interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLEF=1 in the STAT register

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

Allowed values:
0: Disabled: Read data buffer not empty and overrrun error interrupts are disabled
1: Enabled: Interrupt is generated whenever ORERR=1 or RBNE=1 in the STAT register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Transmission complete interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the STAT register

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

Allowed values:
0: Disabled: Transmission register empty interrupt is disabled
1: Enabled: Interrupt is generated whenever TBE=1 in the STAT register

PERRIE

Bit 8: Parity error interrupt enable.

Allowed values:
0: Disabled: Parity error interrupt is disabled
1: Enabled: Interrupt is generated whenever PERR=1 in the STAT register

PM

Bit 9: Parity mode.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCEN

Bit 10: Parity check function enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WM

Bit 11: Wakeup method in mute mode.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

WL

Bit 12: Word length.

Allowed values:
0: Bit8: 8 data bits
1: Bit9: 9 data bits

UEN

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART prescaler and outputs enabled

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

Allowed values:
0: Bit4: 4-bit address detection
1: Full: Full-bit address detection

LBLEN

Bit 5: LIN break frame length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: An interrupt is generated whenever LBDF=1 in the STAT register

CLEN

Bit 8: CK Length.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPH

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPL

Bit 10: Clock polarity.

Allowed values:
0: NotInverted: Steady low value on CK pin outside tranmission window
1: Inverted: Steady high value on CK pin outside tranmission window

CKEN

Bit 11: CK pin enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STB

Bits 12-13: STOP bits length.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LMEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt is disabled
1: Enabled: An interrupt is generated when FERR=1 or ORERR=1 or NERR=1 in the STAT register

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDEN

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NKEN

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DENR

Bit 6: DMA request enable for reception.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DENT

Bit 7: DMA request enable for transmission.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSEN

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSEN

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: An interrupt is generated whenever CTS=1 in the STAT register

GP

Guard time and prescaler register

Offset: 0x18, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

Allowed values: 0-255

GUAT

Bits 8-15: Guard time value in Smartcard mode.

Allowed values: 0-255

CTL3

Control register 3

Offset: 0x80, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSBF
rw 		DINV
rw 		TINV
rw 		RINV
rw 		EBIE
rw 		RTIE
rw 		SCRTNUM
rw 		RTEN
rw
Toggle Fields.

RTEN

Bit 0: Receiver timeout enable.

SCRTNUM

Bits 1-3: Smartcard auto-retry number.

RTIE

Bit 4: Interrupt enable bit of receive timeout event.

EBIE

Bit 5: Interrupt enable bit of end of block event.

RINV

Bit 8: RX pin level inversion.

TINV

Bit 9: TX pin level inversion.

DINV

Bit 10: Data bit level inversion.

MSBF

Bit 11: Most significant bit first.

RT

Receiver timeout register

Offset: 0x84, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BL
rw 		RT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT
rw
Toggle Fields.

RT

Bits 0-23: Receiver timeout threshold.

Allowed values: 0-16777215

BL

Bits 24-31: Block Length.

Allowed values: 0-255

STAT1

Status register 1

Offset: 0x88, reset: 0x00000000, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBF
w 		RTF
w
Toggle Fields.

RTF

Bit 11: Receiver timeout flag.

EBF

Bit 12: End of block flag.

BSY

Bit 16: Busy flag.

USART2

0x40004800: Universal synchronous asynchronous receiver transmitter

48/62 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSF
rw 		LBDF
rw 		TBE
r 		TC
rw 		RBNE
rw 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS change flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

Allowed values: 0-255

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

Allowed values: 0-15

INTDIV

Bits 4-15: Integer part of baud-rate divider.

Allowed values: 0-4095

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

Allowed values:
0: Disabled: Do not transmit a break frame
1: Enabled: Do not transmit a break frame

RWU

Bit 1: Receiver wakeup from mute mode.

Allowed values:
0: Disabled: Receiver wakeup from mute mode
1: Enabled: Receiver in mute mode

REN

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TEN

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE line detected interrupt enable.

Allowed values:
0: Disabled: Idle line detected interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLEF=1 in the STAT register

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

Allowed values:
0: Disabled: Read data buffer not empty and overrrun error interrupts are disabled
1: Enabled: Interrupt is generated whenever ORERR=1 or RBNE=1 in the STAT register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Transmission complete interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the STAT register

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

Allowed values:
0: Disabled: Transmission register empty interrupt is disabled
1: Enabled: Interrupt is generated whenever TBE=1 in the STAT register

PERRIE

Bit 8: Parity error interrupt enable.

Allowed values:
0: Disabled: Parity error interrupt is disabled
1: Enabled: Interrupt is generated whenever PERR=1 in the STAT register

PM

Bit 9: Parity mode.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCEN

Bit 10: Parity check function enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WM

Bit 11: Wakeup method in mute mode.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

WL

Bit 12: Word length.

Allowed values:
0: Bit8: 8 data bits
1: Bit9: 9 data bits

UEN

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART prescaler and outputs enabled

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

Allowed values:
0: Bit4: 4-bit address detection
1: Full: Full-bit address detection

LBLEN

Bit 5: LIN break frame length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: An interrupt is generated whenever LBDF=1 in the STAT register

CLEN

Bit 8: CK Length.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPH

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPL

Bit 10: Clock polarity.

Allowed values:
0: NotInverted: Steady low value on CK pin outside tranmission window
1: Inverted: Steady high value on CK pin outside tranmission window

CKEN

Bit 11: CK pin enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STB

Bits 12-13: STOP bits length.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LMEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt is disabled
1: Enabled: An interrupt is generated when FERR=1 or ORERR=1 or NERR=1 in the STAT register

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDEN

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NKEN

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DENR

Bit 6: DMA request enable for reception.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DENT

Bit 7: DMA request enable for transmission.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSEN

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSEN

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: An interrupt is generated whenever CTS=1 in the STAT register

GP

Guard time and prescaler register

Offset: 0x18, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

Allowed values: 0-255

GUAT

Bits 8-15: Guard time value in Smartcard mode.

Allowed values: 0-255

CTL3

Control register 3

Offset: 0x80, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSBF
rw 		DINV
rw 		TINV
rw 		RINV
rw 		EBIE
rw 		RTIE
rw 		SCRTNUM
rw 		RTEN
rw
Toggle Fields.

RTEN

Bit 0: Receiver timeout enable.

SCRTNUM

Bits 1-3: Smartcard auto-retry number.

RTIE

Bit 4: Interrupt enable bit of receive timeout event.

EBIE

Bit 5: Interrupt enable bit of end of block event.

RINV

Bit 8: RX pin level inversion.

TINV

Bit 9: TX pin level inversion.

DINV

Bit 10: Data bit level inversion.

MSBF

Bit 11: Most significant bit first.

RT

Receiver timeout register

Offset: 0x84, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BL
rw 		RT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT
rw
Toggle Fields.

RT

Bits 0-23: Receiver timeout threshold.

Allowed values: 0-16777215

BL

Bits 24-31: Block Length.

Allowed values: 0-255

STAT1

Status register 1

Offset: 0x88, reset: 0x00000000, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBF
w 		RTF
w
Toggle Fields.

RTF

Bit 11: Receiver timeout flag.

EBF

Bit 12: End of block flag.

BSY

Bit 16: Busy flag.

USART5

0x40017000: Universal synchronous asynchronous receiver transmitter

48/62 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSF
rw 		LBDF
rw 		TBE
r 		TC
rw 		RBNE
rw 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS change flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

Allowed values: 0-255

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

Allowed values: 0-15

INTDIV

Bits 4-15: Integer part of baud-rate divider.

Allowed values: 0-4095

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

Allowed values:
0: Disabled: Do not transmit a break frame
1: Enabled: Do not transmit a break frame

RWU

Bit 1: Receiver wakeup from mute mode.

Allowed values:
0: Disabled: Receiver wakeup from mute mode
1: Enabled: Receiver in mute mode

REN

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TEN

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE line detected interrupt enable.

Allowed values:
0: Disabled: Idle line detected interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLEF=1 in the STAT register

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

Allowed values:
0: Disabled: Read data buffer not empty and overrrun error interrupts are disabled
1: Enabled: Interrupt is generated whenever ORERR=1 or RBNE=1 in the STAT register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Transmission complete interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the STAT register

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

Allowed values:
0: Disabled: Transmission register empty interrupt is disabled
1: Enabled: Interrupt is generated whenever TBE=1 in the STAT register

PERRIE

Bit 8: Parity error interrupt enable.

Allowed values:
0: Disabled: Parity error interrupt is disabled
1: Enabled: Interrupt is generated whenever PERR=1 in the STAT register

PM

Bit 9: Parity mode.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCEN

Bit 10: Parity check function enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WM

Bit 11: Wakeup method in mute mode.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

WL

Bit 12: Word length.

Allowed values:
0: Bit8: 8 data bits
1: Bit9: 9 data bits

UEN

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART prescaler and outputs enabled

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

Allowed values:
0: Bit4: 4-bit address detection
1: Full: Full-bit address detection

LBLEN

Bit 5: LIN break frame length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: An interrupt is generated whenever LBDF=1 in the STAT register

CLEN

Bit 8: CK Length.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPH

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPL

Bit 10: Clock polarity.

Allowed values:
0: NotInverted: Steady low value on CK pin outside tranmission window
1: Inverted: Steady high value on CK pin outside tranmission window

CKEN

Bit 11: CK pin enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STB

Bits 12-13: STOP bits length.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LMEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt is disabled
1: Enabled: An interrupt is generated when FERR=1 or ORERR=1 or NERR=1 in the STAT register

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDEN

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NKEN

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DENR

Bit 6: DMA request enable for reception.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DENT

Bit 7: DMA request enable for transmission.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSEN

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSEN

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: An interrupt is generated whenever CTS=1 in the STAT register

GP

Guard time and prescaler register

Offset: 0x18, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

Allowed values: 0-255

GUAT

Bits 8-15: Guard time value in Smartcard mode.

Allowed values: 0-255

CTL3

Control register 3

Offset: 0x80, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSBF
rw 		DINV
rw 		TINV
rw 		RINV
rw 		EBIE
rw 		RTIE
rw 		SCRTNUM
rw 		RTEN
rw
Toggle Fields.

RTEN

Bit 0: Receiver timeout enable.

SCRTNUM

Bits 1-3: Smartcard auto-retry number.

RTIE

Bit 4: Interrupt enable bit of receive timeout event.

EBIE

Bit 5: Interrupt enable bit of end of block event.

RINV

Bit 8: RX pin level inversion.

TINV

Bit 9: TX pin level inversion.

DINV

Bit 10: Data bit level inversion.

MSBF

Bit 11: Most significant bit first.

RT

Receiver timeout register

Offset: 0x84, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BL
rw 		RT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT
rw
Toggle Fields.

RT

Bits 0-23: Receiver timeout threshold.

Allowed values: 0-16777215

BL

Bits 24-31: Block Length.

Allowed values: 0-255

STAT1

Status register 1

Offset: 0x88, reset: 0x00000000, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBF
w 		RTF
w
Toggle Fields.

RTF

Bit 11: Receiver timeout flag.

EBF

Bit 12: End of block flag.

BSY

Bit 16: Busy flag.

USBFS_DEVICE

0x50000800: USB on the go full speed device

36/200 fields covered. Toggle Registers.

DCFG

device configuration register (DCFG)

Offset: 0x0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPFT
rw 		DAR
rw 		NZLSOH
rw 		DS
rw
Toggle Fields.

DS

Bits 0-1: Device speed.

NZLSOH

Bit 2: Non-zero-length status OUT handshake.

DAR

Bits 4-10: Device address.

EOPFT

Bits 11-12: end of periodic frame time.

DCTL

device control register (DCTL)

Offset: 0x4, reset: 0x00000000, access: Unspecified

2/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POIF
rw 		CGONAK
w 		SGONAK
w 		CGINAK
w 		SGINAK
w 		GONS
r 		GINS
r 		SD
rw 		RWKUP
rw
Toggle Fields.

RWKUP

Bit 0: Remote wakeup.

SD

Bit 1: Soft disconnect.

GINS

Bit 2: Global IN NAK status.

GONS

Bit 3: Global OUT NAK status.

SGINAK

Bit 7: Set global IN NAK.

CGINAK

Bit 8: Clear global IN NAK.

SGONAK

Bit 9: Set global OUT NAK.

CGONAK

Bit 10: Clear global OUT NAK.

POIF

Bit 11: Power-on initialization flag.

DSTAT

device status register (DSTAT)

Offset: 0x8, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FNRSOF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNRSOF
r 		ERER
r 		ES
r 		SPST
r
Toggle Fields.

SPST

Bit 0: Suspend status.

ES

Bits 1-2: Enumerated speed.

ERER

Bit 3: Erratic error.

FNRSOF

Bits 8-21: Frame number of the received SOF.

DIEPINTEN

device IN endpoint common interrupt mask register (DIEPINTEN)

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPNEEN
rw 		EPTXFUDEN
rw 		CITOEN
rw 		EPDISEN
rw 		TFEN
rw
Toggle Fields.

TFEN

Bit 0: Transfer finished interrupt enable.

EPDISEN

Bit 1: Endpoint disabled interrupt enable.

CITOEN

Bit 3: Control IN timeout condition interrupt enable (Non-isochronous endpoints).

EPTXFUDEN

Bit 4: Endpoint Tx FIFO underrun interrupt enable bit.

IEPNEEN

Bit 6: IN endpoint NAK effective interrupt enable.

DOEPINTEN

device OUT endpoint common interrupt enable register (DOEPINTEN)

Offset: 0x14, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTBSTPEN
rw 		EPRXFOVREN
rw 		STPFEN
rw 		EPDISEN
rw 		TFEN
rw
Toggle Fields.

TFEN

Bit 0: Transfer finished interrupt enable.

EPDISEN

Bit 1: Endpoint disabled interrupt enable.

STPFEN

Bit 3: SETUP phase finished interrupt enable.

EPRXFOVREN

Bit 4: Endpoint Rx FIFO overrun interrupt enable.

BTBSTPEN

Bit 6: Back-to-back SETUP packets interrupt enable.

DAEPINT

device all endpoints interrupt register (DAEPINT)

Offset: 0x18, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPITB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPITB
r
Toggle Fields.

IEPITB

Bits 0-3: Device all IN endpoint interrupt bits.

OEPITB

Bits 16-19: Device all OUT endpoint interrupt bits.

DAEPINTEN

Device all endpoints interrupt enable register (DAEPINTEN)

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPIE
rw
Toggle Fields.

IEPIE

Bits 0-3: IN EP interrupt interrupt enable bits.

OEPIE

Bits 16-19: OUT endpoint interrupt enable bits.

DVBUSDT

device VBUS discharge time register

Offset: 0x28, reset: 0x000017D7, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DVBUSDT
rw
Toggle Fields.

DVBUSDT

Bits 0-15: Device VBUS discharge time.

DVBUSPT

device VBUS pulsing time register

Offset: 0x2C, reset: 0x000005B8, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DVBUSPT
rw
Toggle Fields.

DVBUSPT

Bits 0-11: Device VBUS pulsing time.

DIEPFEINTEN

device IN endpoint FIFO empty interrupt enable register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTXFEIE
rw
Toggle Fields.

IEPTXFEIE

Bits 0-3: IN EP Tx FIFO empty interrupt enable bits.

DIEP0CTL

device IN endpoint 0 control register (DIEP0CTL)

Offset: 0x100, reset: 0x00008000, access: Unspecified

3/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYPE
r 		NAKS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
r 		MPL
rw
Toggle Fields.

MPL

Bits 0-1: Maximum packet length.

EPACT

Bit 15: endpoint active.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DIEP0INTF

device endpoint-0 interrupt register

Offset: 0x108, reset: 0x00000080, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r 		IEPNE
rw 		EPTXFUD
rw 		CITO
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint finished.

CITO

Bit 3: Control in timeout interrupt.

EPTXFUD

Bit 4: Endpoint Tx FIFO underrun.

IEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

DIEP0LEN

device IN endpoint-0 transfer length register

Offset: 0x110, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-6: Transfer length.

PCNT

Bits 19-20: Packet count.

DIEP0TFSTAT

device IN endpoint 0 transmit FIFO status register

Offset: 0x118, reset: 0x00000200, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTFS
r
Toggle Fields.

IEPTFS

Bits 0-15: IN endpoint TxFIFO space remaining.

DIEP1CTL

device in endpoint-1 control register

Offset: 0x120, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: Tx FIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVNFRM.

SD1PID_SODDFRM

Bit 29: Set DATA1 PID/Set odd frame.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DIEP1INTF

device endpoint-1 interrupt register

Offset: 0x128, reset: 0x00000080, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r 		IEPNE
rw 		EPTXFUD
rw 		CITO
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint finished.

CITO

Bit 3: Control in timeout interrupt.

EPTXFUD

Bit 4: Endpoint Tx FIFO underrun.

IEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

DIEP1LEN

device IN endpoint-1 transfer length register

Offset: 0x130, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DIEP1TFSTAT

device IN endpoint 1 transmit FIFO status register

Offset: 0x138, reset: 0x00000200, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTFS
r
Toggle Fields.

IEPTFS

Bits 0-15: IN endpoint TxFIFO space remaining.

DIEP2CTL

device endpoint-2 control register

Offset: 0x140, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: Tx FIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVNFRM.

SD1PID_SODDFRM

Bit 29: Set DATA1 PID/Set odd frame.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DIEP2INTF

device endpoint-2 interrupt register

Offset: 0x148, reset: 0x00000080, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r 		IEPNE
rw 		EPTXFUD
rw 		CITO
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint finished.

CITO

Bit 3: Control in timeout interrupt.

EPTXFUD

Bit 4: Endpoint Tx FIFO underrun.

IEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

DIEP2LEN

device IN endpoint-2 transfer length register

Offset: 0x150, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DIEP2TFSTAT

device IN endpoint 2 transmit FIFO status register

Offset: 0x158, reset: 0x00000200, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTFS
r
Toggle Fields.

IEPTFS

Bits 0-15: IN endpoint TxFIFO space remaining.

DIEP3CTL

device endpoint-3 control register

Offset: 0x160, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: Tx FIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVNFRM.

SD1PID_SODDFRM

Bit 29: Set DATA1 PID/Set odd frame.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DIEP3INTF

device endpoint-3 interrupt register

Offset: 0x168, reset: 0x00000080, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r 		IEPNE
rw 		EPTXFUD
rw 		CITO
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint finished.

CITO

Bit 3: Control in timeout interrupt.

EPTXFUD

Bit 4: Endpoint Tx FIFO underrun.

IEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

DIEP3LEN

device IN endpoint-3 transfer length register

Offset: 0x170, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DIEP3TFSTAT

device IN endpoint 3 transmit FIFO status register

Offset: 0x178, reset: 0x00000200, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTFS
r
Toggle Fields.

IEPTFS

Bits 0-15: IN endpoint TxFIFO space remaining.

DOEP0CTL

device endpoint-0 control register

Offset: 0x300, reset: 0x00008000, access: Unspecified

5/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
w 		EPD
r 		SNAK
w 		CNAK
w 		STALL
rw 		SNOOP
rw 		EPTYPE
r 		NAKS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
r 		MPL
r
Toggle Fields.

MPL

Bits 0-1: Maximum packet length.

EPACT

Bit 15: Endpoint active.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

SNOOP

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DOEP0INTF

device out endpoint-0 interrupt flag register

Offset: 0x308, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTBSTP
rw 		EPRXFOVR
rw 		STPF
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint disabled.

STPF

Bit 3: Setup phase finished.

EPRXFOVR

Bit 4: Endpoint Rx FIFO overrun.

BTBSTP

Bit 6: Back-to-back SETUP packets.

DOEP0LEN

device OUT endpoint-0 transfer length register

Offset: 0x310, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STPCNT
rw 		PCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-6: Transfer length.

PCNT

Bit 19: Packet count.

STPCNT

Bits 29-30: SETUP packet count.

DOEP1CTL

device endpoint-1 control register

Offset: 0x320, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNOOP
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

SNOOP

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVENFRM.

SD1PID_SODDFRM

Bit 29: SD1PID/SODDFRM.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DOEP1INTF

device out endpoint-1 interrupt flag register

Offset: 0x328, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTBSTP
rw 		EPRXFOVR
rw 		STPF
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint disabled.

STPF

Bit 3: Setup phase finished.

EPRXFOVR

Bit 4: Endpoint Rx FIFO overrun.

BTBSTP

Bit 6: Back-to-back SETUP packets.

DOEP1LEN

device OUT endpoint-1 transfer length register

Offset: 0x330, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STPCNT_RXDPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

STPCNT_RXDPID

Bits 29-30: SETUP packet count/Received data PID.

DOEP2CTL

device endpoint-2 control register

Offset: 0x340, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNOOP
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

SNOOP

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVENFRM.

SD1PID_SODDFRM

Bit 29: SD1PID/SODDFRM.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DOEP2INTF

device out endpoint-2 interrupt flag register

Offset: 0x348, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTBSTP
rw 		EPRXFOVR
rw 		STPF
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint disabled.

STPF

Bit 3: Setup phase finished.

EPRXFOVR

Bit 4: Endpoint Rx FIFO overrun.

BTBSTP

Bit 6: Back-to-back SETUP packets.

DOEP2LEN

device OUT endpoint-2 transfer length register

Offset: 0x350, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STPCNT_RXDPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

STPCNT_RXDPID

Bits 29-30: SETUP packet count/Received data PID.

DOEP3CTL

device endpoint-3 control register

Offset: 0x360, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNOOP
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

SNOOP

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVENFRM.

SD1PID_SODDFRM

Bit 29: SD1PID/SODDFRM.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DOEP3INTF

device out endpoint-3 interrupt flag register

Offset: 0x368, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTBSTP
rw 		EPRXFOVR
rw 		STPF
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint disabled.

STPF

Bit 3: Setup phase finished.

EPRXFOVR

Bit 4: Endpoint Rx FIFO overrun.

BTBSTP

Bit 6: Back-to-back SETUP packets.

DOEP3LEN

device OUT endpoint-3 transfer length register

Offset: 0x370, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STPCNT_RXDPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

STPCNT_RXDPID

Bits 29-30: SETUP packet count/Received data PID.

USBFS_GLOBAL

0x50000000: USB full speed global registers

39/120 fields covered. Toggle Registers.

GOTGCS

Global OTG control and status register (USBFS_GOTGCS)

Offset: 0x0, reset: 0x00000800, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSV
r 		ASV
r 		DI
r 		IDPS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DHNPEN
rw 		HHNPEN
rw 		HNPREQ
rw 		HNPS
r 		SRPREQ
rw 		SRPS
r
Toggle Fields.

SRPS

Bit 0: SRP success.

SRPREQ

Bit 1: SRP request.

HNPS

Bit 8: Host success.

HNPREQ

Bit 9: HNP request.

HHNPEN

Bit 10: Host HNP enable.

DHNPEN

Bit 11: Device HNP enabled.

IDPS

Bit 16: ID pin status.

DI

Bit 17: Debounce interval.

ASV

Bit 18: A-session valid.

BSV

Bit 19: B-session valid.

GOTGINTF

Global OTG interrupt flag register (USBFS_GOTGINTF)

Offset: 0x4, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DF
rw 		ADTO
rw 		HNPDET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HNPEND
rw 		SRPEND
rw 		SESEND
rw
Toggle Fields.

SESEND

Bit 2: Session end .

SRPEND

Bit 8: Session request success status change.

HNPEND

Bit 9: HNP end.

HNPDET

Bit 17: Host negotiation request detected.

ADTO

Bit 18: A-device timeout.

DF

Bit 19: Debounce finish.

GAHBCS

Global AHB control and status register (USBFS_GAHBCS)

Offset: 0x8, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFTH
rw 		TXFTH
rw 		GINTEN
rw
Toggle Fields.

GINTEN

Bit 0: Global interrupt enable.

TXFTH

Bit 7: Tx FIFO threshold.

PTXFTH

Bit 8: Periodic Tx FIFO threshold.

GUSBCS

Global USB control and status register (OTG_FS_GUSBCSR)

Offset: 0xC, reset: 0x00000A80, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDM
rw 		FHM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UTT
rw 		HNPCEN
rw 		SRPCEN
rw 		FSSTS
r 		TOC
rw
Toggle Fields.

TOC

Bits 0-2: Timeout calibration.

FSSTS

Bit 7: Full speed serial transceiver select.

SRPCEN

Bit 8: SRP capability enable.

HNPCEN

Bit 9: HNP capability enable.

UTT

Bits 10-13: USB turnaround time.

FHM

Bit 29: Force host mode.

FDM

Bit 30: Force device mode.

GRSTCTL

Global reset control register (USBFS_GRSTCTL)

Offset: 0x10, reset: 0x80000000, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AHBMIDL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFNUM
rw 		TXFF
rw 		RXFF
rw 		HFCRST
rw 		HCSRST
rw 		CSRST
rw
Toggle Fields.

CSRST

Bit 0: Core soft reset.

HCSRST

Bit 1: HCLK soft reset.

HFCRST

Bit 2: Host frame counter reset.

RXFF

Bit 4: RxFIFO flush.

TXFF

Bit 5: TxFIFO flush.

TXFNUM

Bits 6-10: TxFIFO number.

AHBMIDL

Bit 31: AHB master idle.

GINTF

Global interrupt flag register (USBFS_GINTF)

Offset: 0x14, reset: 0x04000021, access: Unspecified

11/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPIF
rw 		SESIF
rw 		DISCIF
rw 		IDPSC
rw 		PTXFEIF
r 		HCIF
r 		HPIF
r 		PXNCIF_ISOONCIF
rw 		ISOINCIF
rw 		OEPIF
r 		IEPIF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPFIF
rw 		ISOOPDIF
rw 		ENUMF
rw 		RST
rw 		SP
rw 		ESP
rw 		GONAK
r 		GNPINAK
r 		NPTXFEIF
r 		RXFNEIF
r 		SOF
rw 		OTGIF
r 		MFIF
rw 		COPM
r
Toggle Fields.

COPM

Bit 0: Current operation mode.

MFIF

Bit 1: Mode fault interrupt flag.

OTGIF

Bit 2: OTG interrupt flag.

SOF

Bit 3: Start of frame.

RXFNEIF

Bit 4: RxFIFO non-empty interrupt flag.

NPTXFEIF

Bit 5: Non-periodic TxFIFO empty interrupt flag.

GNPINAK

Bit 6: Global Non-Periodic IN NAK effective.

GONAK

Bit 7: Global OUT NAK effective.

ESP

Bit 10: Early suspend.

SP

Bit 11: USB suspend.

RST

Bit 12: USB reset.

ENUMF

Bit 13: Enumeration finished.

ISOOPDIF

Bit 14: Isochronous OUT packet dropped interrupt.

EOPFIF

Bit 15: End of periodic frame interrupt flag.

IEPIF

Bit 18: IN endpoint interrupt flag.

OEPIF

Bit 19: OUT endpoint interrupt flag.

ISOINCIF

Bit 20: Isochronous IN transfer Not Complete Interrupt Flag.

PXNCIF_ISOONCIF

Bit 21: periodic transfer not complete interrupt flag(Host mode)/isochronous OUT transfer not complete interrupt flag(Device mode).

HPIF

Bit 24: Host port interrupt flag.

HCIF

Bit 25: Host channels interrupt flag.

PTXFEIF

Bit 26: Periodic TxFIFO empty interrupt flag.

IDPSC

Bit 28: ID pin status change.

DISCIF

Bit 29: Disconnect interrupt flag.

SESIF

Bit 30: Session interrupt flag.

WKUPIF

Bit 31: Wakeup interrupt flag.

GINTEN

Global interrupt enable register (USBFS_GINTEN)

Offset: 0x18, reset: 0x00000000, access: Unspecified

1/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPIE
rw 		SESIE
rw 		DISCIE
rw 		IDPSCIE
rw 		PTXFEIE
rw 		HCIE
rw 		HPIE
r 		PXNCIE_ISOONCIE
rw 		ISOINCIE
rw 		OEPIE
rw 		IEPIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPFIE
rw 		ISOOPDIE
rw 		ENUMFIE
rw 		RSTIE
rw 		SPIE
rw 		ESPIE
rw 		GONAKIE
rw 		GNPINAKIE
rw 		NPTXFEIE
rw 		RXFNEIE
rw 		SOFIE
rw 		OTGIE
rw 		MFIE
rw
Toggle Fields.

MFIE

Bit 1: Mode fault interrupt enable.

OTGIE

Bit 2: OTG interrupt enable .

SOFIE

Bit 3: Start of frame interrupt enable.

RXFNEIE

Bit 4: Receive FIFO non-empty interrupt enable.

NPTXFEIE

Bit 5: Non-periodic TxFIFO empty interrupt enable.

GNPINAKIE

Bit 6: Global non-periodic IN NAK effective interrupt enable.

GONAKIE

Bit 7: Global OUT NAK effective interrupt enable.

ESPIE

Bit 10: Early suspend interrupt enable.

SPIE

Bit 11: USB suspend interrupt enable.

RSTIE

Bit 12: USB reset interrupt enable.

ENUMFIE

Bit 13: Enumeration finish interrupt enable.

ISOOPDIE

Bit 14: Isochronous OUT packet dropped interrupt enable.

EOPFIE

Bit 15: End of periodic frame interrupt enable.

IEPIE

Bit 18: IN endpoints interrupt enable.

OEPIE

Bit 19: OUT endpoints interrupt enable.

ISOINCIE

Bit 20: isochronous IN transfer not complete interrupt enable.

PXNCIE_ISOONCIE

Bit 21: periodic transfer not compelete Interrupt enable(Host mode)/isochronous OUT transfer not complete interrupt enable(Device mode).

HPIE

Bit 24: Host port interrupt enable.

HCIE

Bit 25: Host channels interrupt enable.

PTXFEIE

Bit 26: Periodic TxFIFO empty interrupt enable.

IDPSCIE

Bit 28: ID pin status change interrupt enable.

DISCIE

Bit 29: Disconnect interrupt enable.

SESIE

Bit 30: Session interrupt enable.

WKUPIE

Bit 31: Wakeup interrupt enable.

GRSTATR_Host

Global Receive status read(Host mode)

Offset: 0x1C, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPCKST
r 		DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r 		BCOUNT
r 		CNUM
r
Toggle Fields.

CNUM

Bits 0-3: Channel number.

BCOUNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

RPCKST

Bits 17-20: Reivece packet status.

GRSTATP_Host

Global Receive status pop(Host mode)

Offset: 0x20, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPCKST
r 		DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r 		BCOUNT
r 		CNUM
r
Toggle Fields.

CNUM

Bits 0-3: Channel number.

BCOUNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

RPCKST

Bits 17-20: Reivece packet status.

GRFLEN

Global Receive FIFO size register (USBFS_GRFLEN)

Offset: 0x24, reset: 0x00000200, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFD
rw
Toggle Fields.

RXFD

Bits 0-15: Rx FIFO depth.

DIEP0TFLEN

Device IN endpoint 0 transmit FIFO length (Device mode)

Offset: 0x28, reset: 0x02000200, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEP0TXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEP0TXRSAR
rw
Toggle Fields.

IEP0TXRSAR

Bits 0-15: in endpoint 0 Tx RAM start address.

IEP0TXFD

Bits 16-31: in endpoint 0 Tx FIFO depth.

HNPTFQSTAT

Host non-periodic transmit FIFO/queue status register (HNPTFQSTAT)

Offset: 0x2C, reset: 0x00080200, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPTXRQTOP
r 		NPTXRQS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPTXFS
r
Toggle Fields.

NPTXFS

Bits 0-15: Non-periodic TxFIFO space.

NPTXRQS

Bits 16-23: Non-periodic transmit request queue space .

NPTXRQTOP

Bits 24-30: Top of the non-periodic transmit request queue.

GCCFG

Global core configuration register (USBFS_GCCFG)

Offset: 0x38, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VBUSIG
rw 		SOFOEN
rw 		VBUSBCEN
rw 		VBUSACEN
rw 		PWRON
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PWRON

Bit 16: Power on.

VBUSACEN

Bit 18: The VBUS A-device Comparer enable.

VBUSBCEN

Bit 19: The VBUS B-device Comparer enable.

SOFOEN

Bit 20: SOF output enable.

VBUSIG

Bit 21: VBUS ignored.

CID

core ID register

Offset: 0x3C, reset: 0x00001000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CID
rw
Toggle Fields.

CID

Bits 0-31: Core ID.

HPTFLEN

Host periodic transmit FIFO length register (HPTFLEN)

Offset: 0x100, reset: 0x02000600, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HPTXFSAR
rw
Toggle Fields.

HPTXFSAR

Bits 0-15: Host periodic TxFIFO start address.

HPTXFD

Bits 16-31: Host periodic TxFIFO depth.

DIEP1TFLEN

device IN endpoint transmit FIFO size register (DIEP1TFLEN)

Offset: 0x104, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTXRSAR
rw
Toggle Fields.

IEPTXRSAR

Bits 0-15: IN endpoint FIFO transmit RAM start address.

IEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEP2TFLEN

device IN endpoint transmit FIFO size register (DIEP2TFLEN)

Offset: 0x108, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTXRSAR
rw
Toggle Fields.

IEPTXRSAR

Bits 0-15: IN endpoint FIFO transmit RAM start address.

IEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEP3TFLEN

device IN endpoint transmit FIFO size register (FS_DIEP3TXFLEN)

Offset: 0x10C, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTXRSAR
rw
Toggle Fields.

IEPTXRSAR

Bits 0-15: IN endpoint FIFO4 transmit RAM start address.

IEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

USBFS_HOST

0x50000400: USB on the go full speed host

10/261 fields covered. Toggle Registers.

HCTL

host configuration register (HCTL)

Offset: 0x0, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKSEL
rw
Toggle Fields.

CLKSEL

Bits 0-1: clock select for USB clock.

HFT

Host frame interval register

Offset: 0x4, reset: 0x0000BB80, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRI
rw
Toggle Fields.

FRI

Bits 0-15: Frame interval.

HFINFR

OTG_FS host frame number/frame time remaining register (HFINFR)

Offset: 0x8, reset: 0xBB800000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRNUM
r
Toggle Fields.

FRNUM

Bits 0-15: Frame number.

FRT

Bits 16-31: Frame remaining time.

HPTFQSTAT

Host periodic transmit FIFO/queue status register (HPTFQSTAT)

Offset: 0x10, reset: 0x00080200, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTXREQT
r 		PTXREQS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFS
r
Toggle Fields.

PTXFS

Bits 0-15: Periodic transmit data FIFO space available.

PTXREQS

Bits 16-23: Periodic transmit request queue space available.

PTXREQT

Bits 24-31: Top of the periodic transmit request queue.

HACHINT

Host all channels interrupt register

Offset: 0x14, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HACHINT
r
Toggle Fields.

HACHINT

Bits 0-7: Host all channel interrupts.

HACHINTEN

host all channels interrupt mask register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CINTEN
rw
Toggle Fields.

CINTEN

Bits 0-7: Channel interrupt enable.

HPCS

Host port control and status register (USBFS_HPCS)

Offset: 0x40, reset: 0x00000000, access: Unspecified

4/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PP
rw 		PLST
r 		PRST
rw 		PSP
rw 		PREM
rw 		POCC
rw 		PCA
r 		PEDC
rw 		PE
rw 		PCD
rw 		PCST
r
Toggle Fields.

PCST

Bit 0: Port connect status.

PCD

Bit 1: Port connect detected.

PE

Bit 2: Port enable.

PEDC

Bit 3: Port enable/disable change.

PCA

Bit 4: Port over-current active.

POCC

Bit 5: Port over-current change.

PREM

Bit 6: Port resume.

PSP

Bit 7: Port suspend.

PRST

Bit 8: Port reset.

PLST

Bits 10-11: Port line status.

PP

Bit 12: Port power.

PS

Bits 17-18: Port speed.

HCH0CTL

host channel-0 characteristics register (HCH0CTL)

Offset: 0x100, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH0INTF

host channel-0 interrupt register (USBFS_HCHxINTF)

Offset: 0x108, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

CH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH0INTEN

host channel-0 interrupt enable register (HCH0INTEN)

Offset: 0x10C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer completed interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH0LEN

host channel-0 transfer length register

Offset: 0x110, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

HCH1CTL

host channel-1 characteristics register (HCH1CTL)

Offset: 0x120, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH1INTF

host channel-1 interrupt register (HCH1INTF)

Offset: 0x128, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

CH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH1INTEN

host channel-1 interrupt enable register (HCH1INTEN)

Offset: 0x12C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer completed interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH1LEN

host channel-1 transfer length register

Offset: 0x130, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

HCH2CTL

host channel-2 characteristics register (HCH2CTL)

Offset: 0x140, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH2INTF

host channel-2 interrupt register (HCH2INTF)

Offset: 0x148, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

CH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH2INTEN

host channel-2 interrupt enable register (HCH2INTEN)

Offset: 0x14C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer completed interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH2LEN

host channel-2 transfer length register

Offset: 0x150, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

HCH3CTL

host channel-3 characteristics register (HCH3CTL)

Offset: 0x160, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH3INTF

host channel-3 interrupt register (HCH3INTF)

Offset: 0x168, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

CH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH3INTEN

host channel-3 interrupt enable register (HCH3INTEN)

Offset: 0x16C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer completed interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH3LEN

host channel-3 transfer length register

Offset: 0x170, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

HCH4CTL

host channel-4 characteristics register (HCH4CTL)

Offset: 0x180, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH4INTF

host channel-4 interrupt register (HCH4INTF)

Offset: 0x188, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

CH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH4INTEN

host channel-4 interrupt enable register (HCH4INTEN)

Offset: 0x18C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer completed interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH4LEN

host channel-4 transfer length register

Offset: 0x190, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

HCH5CTL

host channel-5 characteristics register (HCH5CTL)

Offset: 0x1A0, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH5INTF

host channel-5 interrupt register (HCH5INTF)

Offset: 0x1A8, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

CH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH5INTEN

host channel-5 interrupt enable register (HCH5INTEN)

Offset: 0x1AC, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer completed interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH5LEN

host channel-5 transfer length register

Offset: 0x1B0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

HCH6CTL

host channel-6 characteristics register (HCH6CTL)

Offset: 0x1C0, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH6INTF

host channel-6 interrupt register (HCH6INTF)

Offset: 0x1C8, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

CH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH6INTEN

host channel-6 interrupt enable register (HCH6INTEN)

Offset: 0x1CC, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer completed interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH6LEN

host channel-6 transfer length register

Offset: 0x1D0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

HCH7CTL

host channel-7 characteristics register (HCH7CTL)

Offset: 0x1E0, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH7INTF

host channel-7 interrupt register (HCH7INTF)

Offset: 0x1E8, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

CH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH7INTEN

host channel-7 interrupt enable register (HCH7INTEN)

Offset: 0x1EC, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer completed interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH7LEN

host channel-7 transfer length register

Offset: 0x1F0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

USBFS_PWRCLK

0x50000E00: USB on the go full speed

0/2 fields covered. Toggle Registers.

PWRCLKCTL

power and clock gating control register (PWRCLKCTL)

Offset: 0x0, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHCLK
rw 		SUCLK
rw
Toggle Fields.

SUCLK

Bit 0: Stop the USB clock.

SHCLK

Bit 1: Stop HCLK.

WWDGT

0x40002C00: Window watchdog timer

6/6 fields covered. Toggle Registers.

CTL

Control register

Offset: 0x0, reset: 0x0000007F, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGTEN
rw 		CNT
rw
Toggle Fields.

CNT

Bits 0-6: 7-bit counter.

Allowed values: 0-127

WDGTEN

Bit 7: Activation bit.

Allowed values:
0: Disabled: Watchdog disabled
1: Enabled: Watchdog enabled

CFG

Configuration register

Offset: 0x4, reset: 0x0000007F, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIE
rw 		PSC
rw 		WIN
rw
Toggle Fields.

WIN

Bits 0-6: 7-bit window value.

Allowed values: 0-127

PSC

Bits 7-8: Prescaler.

Allowed values:
0: Div1: Counter clock (PCLK1 div 4096) div 1
1: Div2: Counter clock (PCLK1 div 4096) div 2
2: Div4: Counter clock (PCLK1 div 4096) div 4
3: Div8: Counter clock (PCLK1 div 4096) div 8

EWIE

Bit 9: Early wakeup interrupt.

Allowed values:
1: Enable: interrupt occurs whenever the counter reaches the value 0x40

STAT

Status register

Offset: 0x8, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
rw
Toggle Fields.

EWIF

Bit 0: Early wakeup interrupt flag.

Allowed values:
1: Pending: The EWI Interrupt Service Routine has been triggered
0: Finished: The EWI Interrupt Service Routine has been serviced