0x40012400: Analog to digital converter
87/88 fields covered. Toggle Registers.
control register 1
Offset: 0x8, reset: 0x00000000, access: read-write
13/13 fields covered.
Bits 12-14: External trigger select for inserted channel.
Allowed values:
0: Timer0Trgo: Timer 0 TRGO event
1: Timer0Ch3: Timer 0 channel 3 event
2: Timer1Trgo: Timer 1 TRGO event
3: Timer1Ch0: Timer 1 channel 0 event
4: Timer2Ch2: Timer 2 channel 3 event
5: Timer14Trgo: Timer 14 TRGO event
6: Exti15: EXTI line 15
7: Swicst: SWICST
Bits 17-19: External trigger select for regular channel.
Allowed values:
0: Timer0Ch0: Timer 0 channel 0 event
1: Timer0Ch1: Timer 0 channel 1 event
2: Timer0Ch2: Timer 0 channel 2 event
3: Timer1Ch1: Timer 1 channel 1 event
4: Timer2Trgo: Timer 2 TRGO event
5: Timer14Ch0: Timer 14 channel 0 event
6: Exti11: EXTI line 11
7: Swrcst: SWRCST
Sample time register 0
Offset: 0xC, reset: 0x00000000, access: read-write
8/8 fields covered.
Bits 0-2: Channel 10 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 3-5: Channel 11 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 6-8: Channel 12 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 9-11: Channel 13 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 12-14: Channel 14 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 15-17: Channel 15 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 18-20: Channel 16 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 21-23: Channel 17 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Sample time register 1
Offset: 0x10, reset: 0x00000000, access: read-write
10/10 fields covered.
Bits 0-2: Channel 0 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 3-5: Channel 1 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 6-8: Channel 2 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 9-11: Channel 3 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 12-14: Channel 4 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 15-17: Channel 5 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 18-20: Channel 6 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 21-23: Channel 7 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 24-26: Channel 8 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 27-29: Channel 9 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Inserted channel data offset register 0
Offset: 0x14, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOFF
rw |
Inserted channel data offset register 1
Offset: 0x18, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOFF
rw |
Inserted channel data offset register 2
Offset: 0x1C, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOFF
rw |
Inserted channel data offset register 3
Offset: 0x20, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOFF
rw |
watchdog higher threshold register
Offset: 0x24, reset: 0x00000FFF, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WDHT
rw |
watchdog lower threshold register
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WDLT
rw |
Inserted data register 0
Offset: 0x3C, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDATAn
r |
Inserted data register 1
Offset: 0x40, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDATAn
r |
Inserted data register 2
Offset: 0x44, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDATAn
r |
Inserted data register 3
Offset: 0x48, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDATAn
r |
regular data register
Offset: 0x4C, reset: 0x00000000, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADC1RDTR
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RDATA
r |
0x40012800: Analog to digital converter
87/88 fields covered. Toggle Registers.
control register 1
Offset: 0x8, reset: 0x00000000, access: read-write
13/13 fields covered.
Bits 12-14: External trigger select for inserted channel.
Allowed values:
0: Timer0Trgo: Timer 0 TRGO event
1: Timer0Ch3: Timer 0 channel 3 event
2: Timer1Trgo: Timer 1 TRGO event
3: Timer1Ch0: Timer 1 channel 0 event
4: Timer2Ch2: Timer 2 channel 3 event
5: Timer14Trgo: Timer 14 TRGO event
6: Exti15: EXTI line 15
7: Swicst: SWICST
Bits 17-19: External trigger select for regular channel.
Allowed values:
0: Timer0Ch0: Timer 0 channel 0 event
1: Timer0Ch1: Timer 0 channel 1 event
2: Timer0Ch2: Timer 0 channel 2 event
3: Timer1Ch1: Timer 1 channel 1 event
4: Timer2Trgo: Timer 2 TRGO event
5: Timer14Ch0: Timer 14 channel 0 event
6: Exti11: EXTI line 11
7: Swrcst: SWRCST
Sample time register 0
Offset: 0xC, reset: 0x00000000, access: read-write
8/8 fields covered.
Bits 0-2: Channel 10 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 3-5: Channel 11 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 6-8: Channel 12 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 9-11: Channel 13 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 12-14: Channel 14 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 15-17: Channel 15 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 18-20: Channel 16 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 21-23: Channel 17 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Sample time register 1
Offset: 0x10, reset: 0x00000000, access: read-write
10/10 fields covered.
Bits 0-2: Channel 0 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 3-5: Channel 1 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 6-8: Channel 2 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 9-11: Channel 3 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 12-14: Channel 4 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 15-17: Channel 5 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 18-20: Channel 6 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 21-23: Channel 7 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 24-26: Channel 8 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 27-29: Channel 9 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Inserted channel data offset register 0
Offset: 0x14, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOFF
rw |
Inserted channel data offset register 1
Offset: 0x18, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOFF
rw |
Inserted channel data offset register 2
Offset: 0x1C, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOFF
rw |
Inserted channel data offset register 3
Offset: 0x20, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOFF
rw |
watchdog higher threshold register
Offset: 0x24, reset: 0x00000FFF, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WDHT
rw |
watchdog lower threshold register
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WDLT
rw |
Inserted data register 0
Offset: 0x3C, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDATAn
r |
Inserted data register 1
Offset: 0x40, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDATAn
r |
Inserted data register 2
Offset: 0x44, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDATAn
r |
Inserted data register 3
Offset: 0x48, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDATAn
r |
regular data register
Offset: 0x4C, reset: 0x00000000, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADC1RDTR
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RDATA
r |
0x40013C00: Analog to digital converter
87/88 fields covered. Toggle Registers.
control register 1
Offset: 0x8, reset: 0x00000000, access: read-write
13/13 fields covered.
Bits 12-14: External trigger select for inserted channel.
Allowed values:
0: Timer0Trgo: Timer 0 TRGO event
1: Timer0Ch3: Timer 0 channel 3 event
2: Timer1Trgo: Timer 1 TRGO event
3: Timer1Ch0: Timer 1 channel 0 event
4: Timer2Ch2: Timer 2 channel 3 event
5: Timer14Trgo: Timer 14 TRGO event
6: Exti15: EXTI line 15
7: Swicst: SWICST
Bits 17-19: External trigger select for regular channel.
Allowed values:
0: Timer0Ch0: Timer 0 channel 0 event
1: Timer0Ch1: Timer 0 channel 1 event
2: Timer0Ch2: Timer 0 channel 2 event
3: Timer1Ch1: Timer 1 channel 1 event
4: Timer2Trgo: Timer 2 TRGO event
5: Timer14Ch0: Timer 14 channel 0 event
6: Exti11: EXTI line 11
7: Swrcst: SWRCST
Sample time register 0
Offset: 0xC, reset: 0x00000000, access: read-write
8/8 fields covered.
Bits 0-2: Channel 10 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 3-5: Channel 11 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 6-8: Channel 12 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 9-11: Channel 13 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 12-14: Channel 14 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 15-17: Channel 15 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 18-20: Channel 16 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 21-23: Channel 17 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Sample time register 1
Offset: 0x10, reset: 0x00000000, access: read-write
10/10 fields covered.
Bits 0-2: Channel 0 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 3-5: Channel 1 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 6-8: Channel 2 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 9-11: Channel 3 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 12-14: Channel 4 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 15-17: Channel 5 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 18-20: Channel 6 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 21-23: Channel 7 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 24-26: Channel 8 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Bits 27-29: Channel 9 sample time selection.
Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles
Inserted channel data offset register 0
Offset: 0x14, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOFF
rw |
Inserted channel data offset register 1
Offset: 0x18, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOFF
rw |
Inserted channel data offset register 2
Offset: 0x1C, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOFF
rw |
Inserted channel data offset register 3
Offset: 0x20, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOFF
rw |
watchdog higher threshold register
Offset: 0x24, reset: 0x00000FFF, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WDHT
rw |
watchdog lower threshold register
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WDLT
rw |
Inserted data register 0
Offset: 0x3C, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDATAn
r |
Inserted data register 1
Offset: 0x40, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDATAn
r |
Inserted data register 2
Offset: 0x44, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDATAn
r |
Inserted data register 3
Offset: 0x48, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDATAn
r |
regular data register
Offset: 0x4C, reset: 0x00000000, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADC1RDTR
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RDATA
r |
0x40010000: Alternate-function I/Os
0/150 fields covered. Toggle Registers.
Event control register
Offset: 0x0, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EOE
rw |
PORT
rw |
PIN
rw |
AFIO port configuration register 0
Offset: 0x4, reset: 0x00000000, access: read-write
0/23 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PTP_PPS_REMAP
rw |
TIMER1ITR0_REMAP
rw |
SPI2_REMAP
rw |
SWJ_CFG
rw |
ENET_PHY_SEL
rw |
CAN1_REMAP
rw |
ENET_REMAP
rw |
ADC1_ETRGREG_REMAP
rw |
ADC1_ETRGINS_REMAP
rw |
ADC0_ETRGREG_REMAP
rw |
ADC0_ETRGINS_REMAP
rw |
TIMER4CH3_IREMAP
rw |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PD01_REMAP
rw |
CAN0_REMAP
rw |
TIMER3_REMAP
rw |
TIMER2_REMAP
rw |
TIMER1_REMAP
rw |
TIMER0_REMAP
rw |
USART2_REMAP
rw |
USART1_REMAP
rw |
USART0_REMAP
rw |
I2C0_REMAP
rw |
SPI0_REMAP
rw |
EXTI sources selection register 0
Offset: 0x8, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EXTI3_SS
rw |
EXTI2_SS
rw |
EXTI1_SS
rw |
EXTI0_SS
rw |
EXTI sources selection register 1
Offset: 0xC, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EXTI7_SS
rw |
EXTI6_SS
rw |
EXTI5_SS
rw |
EXTI4_SS
rw |
EXTI sources selection register 2
Offset: 0x10, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EXTI11_SS
rw |
EXTI10_SS
rw |
EXTI9_SS
rw |
EXTI8_SS
rw |
EXTI sources selection register 3
Offset: 0x14, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EXTI15_SS
rw |
EXTI14_SS
rw |
EXTI13_SS
rw |
EXTI12_SS
rw |
AFIO port configuration register 1
Offset: 0x1C, reset: 0x00000000, access: read-write
0/6 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EXMC_NADV
rw |
TIMER13_REMAP
rw |
TIMER12_REMAP
rw |
TIMER10_REMAP
rw |
TIMER9_REMAP
rw |
TIMER8_REMAP
rw |
AFIO port configuration register 2
Offset: 0x3C, reset: 0x00000000, access: read-write
0/17 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PH01_REMAP
rw |
DCI_HSYNC_REMAP
rw |
DCI_D13_REMAP
rw |
DCI_D12_REMAP
rw |
DCI_D11_REMAP
rw |
DCI_D10_REMAP
rw |
DCI_D9_REMAP
rw |
DCI_D8_REMAP
rw |
DCI_D7_REMAP
rw |
|||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DCI_D6_REMAP
rw |
DCI_D5_REMAP
rw |
DCI_D4_REMAP
rw |
DCI_D3_REMAP
rw |
DCI_D2_REMAP
rw |
DCI_D1_REMAP
rw |
DCI_D0_REMAP
rw |
DCI_VSYNC_REMAP
rw |
AFIO port configuration register 3
Offset: 0x40, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TLI_B3_PG11_REMAP
rw |
TLI_B2_PG10_REMAP
rw |
TLI_G3_PG10_REMAP
rw |
TLI_CLK_PG7_REMAP
rw |
TLI_R7_PG6_REMAP
rw |
TLI_DE_PF10_REMAP
rw |
TLI_R7_PE15_REMAP
rw |
TLI_CLK_PE14_REMAP
rw |
TLI_DE_PE13_REMAP
rw |
TLI_B4_PE12_REMAP
rw |
TLI_G3_PE11_REMAP
rw |
TLI_G1_PE6_REMAP
rw |
TLI_G0_PE5_REMAP
rw |
TLI_B0_PE4_REMAP
rw |
TLI_B3_PD10_REMAP
rw |
TLI_B2_PD6_REMAP
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TLI_G7_PD3_REMAP
rw |
TLI_R2_PC10_REMAP
rw |
TLI_G6_PC7_REMAP
rw |
TLI_HSYNC_PC6_REMAP
rw |
TLI_G5_PB11_REMAP
rw |
TLI_G4_PB10_REMAP
rw |
TLI_B7_PB9_REMAP
rw |
TLI_B6_PB8_REMAP
rw |
TLI_R6_PB1_REMAP
rw |
TLI_R3_PB0_REMAP
rw |
TLI_R5_PA12_REMAP
rw |
TLI_R4_PA11_REMAP
rw |
TLI_R6_PA8_REMAP
rw |
TLI_G2_PA6_REMAP
rw |
TLI_VSYNC_PA4_REMAP
rw |
TLI_B5_PA3_REMAP
rw |
AFIO port configuration register 4
Offset: 0x44, reset: 0x00000000, access: read-write
0/25 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SPI2_MOSI_REMAP
rw |
SPI1_SCK_REMAP
rw |
TLI_R1_PI3_REMAP
rw |
TLI_R0_PH4_REMAP
rw |
TLI_HSYNC_PI10_REMAP
rw |
TLI_VSYNC_PI9_REMAP
rw |
TLI_B7_PI7_REMAP
rw |
TLI_B6_PI6_REMAP
rw |
TLI_B5_PI5_REMAP
rw |
|||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TLI_B4_PI4_REMAP
rw |
TLI_G7_PI2_REMAP
rw |
TLI_G6_PI1_REMAP
rw |
TLI_G5_PI0_REMAP
rw |
TLI_G4_PH15_REMAP
rw |
TLI_G3_PH14_REMAP
rw |
TLI_G2_PH13_REMAP
rw |
TLI_R6_PH12_REMAP
rw |
TLI_R5_PH11_REMAP
rw |
TLI_R4_PH10_REMAP
rw |
TLI_R3_PH9_REMAP
rw |
TLI_R2_PH8_REMAP
rw |
TLI_R1_PH3_REMAP
rw |
TLI_R0_PH2_REMAP
rw |
TLI_B1_PG12_REMAP
rw |
TLI_B4_PG12_REMAP
rw |
AFIO port configuration register 5
Offset: 0x48, reset: 0x00000000, access: read-write
0/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EXMC_SDNE1_REMAP
rw |
EXMC_SDNE0_REMAP
rw |
EXMC_SDCKE1_REMAP
rw |
EXMC_SDCKE0_REMAP
rw |
EXMC_SDNWE_REMAP
rw |
USART5_RX_REMAP
rw |
USART5_TX_REMAP
rw |
USART5_CTS_REMAP
rw |
USART5_RTS_REMAP
rw |
USART5_CK_REMAP
rw |
UART6_REMAP
rw |
ENET_RX_HI_REMAP
rw |
ENET_CRSCOL_REMAP
rw |
ENET_TXD01_REMAP
rw |
PPS_HI_REMAP
rw |
ENET_TXD3_REMAP
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAN0_ADD_REMAP
rw |
TIMER11_REMAP
rw |
UART3_REMAP
rw |
SPI1_IO_REMAP
rw |
SPI1_NSCK_REMAP
rw |
I2C1_REMAP
rw |
TIMER7_CH_REMAP
rw |
TIMER7_CHON_REMAP
rw |
TIMER4_REMAP
rw |
TIMER1_CH0_REMAP
rw |
I2C2_REMAP1
rw |
I2C2_REMAP0
rw |
0x40006C00: Backup registers
0/64 fields covered. Toggle Registers.
Backup data register 0
Offset: 0x4, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 1
Offset: 0x8, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 2
Offset: 0xC, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 3
Offset: 0x10, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 4
Offset: 0x14, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 5
Offset: 0x18, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 6
Offset: 0x1C, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 7
Offset: 0x20, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 8
Offset: 0x24, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 9
Offset: 0x28, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Tamper pin control register 0
Offset: 0x30, reset: 0x0000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TPAL0
rw |
TPEN0
rw |
Tamper pin control register 1
Offset: 0x38, reset: 0x0000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TPM1
rw |
TPM2
rw |
TPAL1
rw |
TPEN1
rw |
Backup data register 10
Offset: 0x40, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 11
Offset: 0x44, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 12
Offset: 0x48, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 13
Offset: 0x4C, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 14
Offset: 0x50, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 15
Offset: 0x54, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 16
Offset: 0x58, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 17
Offset: 0x5C, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 18
Offset: 0x60, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 19
Offset: 0x64, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 20
Offset: 0x68, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 21
Offset: 0x6C, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 22
Offset: 0x70, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 23
Offset: 0x74, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 24
Offset: 0x78, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 25
Offset: 0x7C, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 26
Offset: 0x80, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 27
Offset: 0x84, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 28
Offset: 0x88, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 29
Offset: 0x8C, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 30
Offset: 0x90, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 31
Offset: 0x94, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 32
Offset: 0x98, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 33
Offset: 0x9C, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 34
Offset: 0xA0, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 35
Offset: 0xA4, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 36
Offset: 0xA8, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 37
Offset: 0xAC, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 38
Offset: 0xB0, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 39
Offset: 0xB4, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 40
Offset: 0xB8, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Backup data register 41
Offset: 0xBC, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
0x40006400: Controller area network
261/2059 fields covered. Toggle Registers.
Receive message FIFO0 register
Offset: 0xC, reset: 0x00000000, access: Unspecified
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RFD0
rw |
RFO0
rw |
RFF0
rw |
RFL0
r |
Receive message FIFO1 register
Offset: 0x10, reset: 0x00000000, access: Unspecified
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RFD1
rw |
RFO1
rw |
RFF1
rw |
RFL1
r |
Transmit mailbox property register 0
Offset: 0x184, reset: 0x00000000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSEN
rw |
DLENC
rw |
Transmit mailbox data0 register
Offset: 0x188, reset: 0x00000000, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DB3
rw |
DB2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DB1
rw |
DB0
rw |
Transmit mailbox data1 register
Offset: 0x18C, reset: 0x00000000, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DB7
rw |
DB6
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DB5
rw |
DB4
rw |
Transmit mailbox property register 1
Offset: 0x194, reset: 0x00000000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSEN
rw |
DLENC
rw |
Transmit mailbox data0 register
Offset: 0x198, reset: 0x00000000, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DB3
rw |
DB2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DB1
rw |
DB0
rw |
Transmit mailbox data1 register
Offset: 0x19C, reset: 0x00000000, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DB7
rw |
DB6
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DB5
rw |
DB4
rw |
Transmit mailbox property register 2
Offset: 0x1A4, reset: 0x00000000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSEN
rw |
DLENC
rw |
Transmit mailbox data0 register
Offset: 0x1A8, reset: 0x00000000, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DB3
rw |
DB2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DB1
rw |
DB0
rw |
Transmit mailbox data1 register
Offset: 0x1AC, reset: 0x00000000, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DB7
rw |
DB6
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DB5
rw |
DB4
rw |
Receive FIFO0 mailbox property register
Offset: 0x1B4, reset: 0x00000000, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TS
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FI
r |
DLENC
r |
Receive FIFO0 mailbox data0 register
Offset: 0x1B8, reset: 0x00000000, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DB3
r |
DB2
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DB1
r |
DB0
r |
Receive FIFO0 mailbox data1 register
Offset: 0x1BC, reset: 0x00000000, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DB7
r |
DB6
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DB5
r |
DB4
r |
Receive FIFO1 mailbox property register
Offset: 0x1C4, reset: 0x00000000, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TS
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FI
r |
DLENC
r |
Receive FIFO1 mailbox data0 register
Offset: 0x1C8, reset: 0x00000000, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DB3
r |
DB2
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DB1
r |
DB0
r |
Receive FIFO1 mailbox data1 register
Offset: 0x1CC, reset: 0x00000000, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DB7
r |
DB6
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DB5
r |
DB4
r |
Filter control register
Offset: 0x200, reset: 0x2A1C0E01, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HBC1F
rw |
FLD
rw |
Filter mode configuration register
Offset: 0x204, reset: 0x00000000, access: read-write
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FMOD27
rw |
FMOD26
rw |
FMOD25
rw |
FMOD24
rw |
FMOD23
rw |
FMOD22
rw |
FMOD21
rw |
FMOD20
rw |
FMOD19
rw |
FMOD18
rw |
FMOD17
rw |
FMOD16
rw |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FMOD15
rw |
FMOD14
rw |
FMOD13
rw |
FMOD12
rw |
FMOD11
rw |
FMOD10
rw |
FMOD9
rw |
FMOD8
rw |
FMOD7
rw |
FMOD6
rw |
FMOD5
rw |
FMOD4
rw |
FMOD3
rw |
FMOD2
rw |
FMOD1
rw |
FMOD0
rw |
Filter scale configuration register
Offset: 0x20C, reset: 0x00000000, access: read-write
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FS27
rw |
FS26
rw |
FS25
rw |
FS24
rw |
FS23
rw |
FS22
rw |
FS21
rw |
FS20
rw |
FS19
rw |
FS18
rw |
FS17
rw |
FS16
rw |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FS15
rw |
FS14
rw |
FS13
rw |
FS12
rw |
FS11
rw |
FS10
rw |
FS9
rw |
FS8
rw |
FS7
rw |
FS6
rw |
FS5
rw |
FS4
rw |
FS3
rw |
FS2
rw |
FS1
rw |
FS0
rw |
Filter associated FIFO register
Offset: 0x214, reset: 0x00000000, access: read-write
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FAF27
rw |
FAF26
rw |
FAF25
rw |
FAF24
rw |
FAF23
rw |
FAF22
rw |
FAF21
rw |
FAF20
rw |
FAF19
rw |
FAF18
rw |
FAF17
rw |
FAF16
rw |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FAF15
rw |
FAF14
rw |
FAF13
rw |
FAF12
rw |
FAF11
rw |
FAF10
rw |
FAF9
rw |
FAF8
rw |
FAF7
rw |
FAF6
rw |
FAF5
rw |
FAF4
rw |
FAF3
rw |
FAF2
rw |
FAF1
rw |
FAF0
rw |
Filter working register
Offset: 0x21C, reset: 0x00000000, access: read-write
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FW27
rw |
FW26
rw |
FW25
rw |
FW24
rw |
FW23
rw |
FW22
rw |
FW21
rw |
FW20
rw |
FW19
rw |
FW18
rw |
FW17
rw |
FW16
rw |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FW15
rw |
FW14
rw |
FW13
rw |
FW12
rw |
FW11
rw |
FW10
rw |
FW9
rw |
FW8
rw |
FW7
rw |
FW6
rw |
FW5
rw |
FW4
rw |
FW3
rw |
FW2
rw |
FW1
rw |
FW0
rw |
Filter 0 data 0 register
Offset: 0x240, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 0 data 1 register
Offset: 0x244, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 1 data 0 register
Offset: 0x248, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 1 data 1 register
Offset: 0x24C, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 2 data 0 register
Offset: 0x250, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 2 data 1 register
Offset: 0x254, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 3 data 0 register
Offset: 0x258, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 3 data 1 register
Offset: 0x25C, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 4 data 0 register
Offset: 0x260, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 4 data 1 register
Offset: 0x264, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 5 data 0 register
Offset: 0x268, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 5 data 1 register
Offset: 0x26C, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 6 data 0 register
Offset: 0x270, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 6 data 1 register
Offset: 0x274, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 7 data 0 register
Offset: 0x278, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 7 data 1 register
Offset: 0x27C, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 8 data 0 register
Offset: 0x280, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 8 data 1 register
Offset: 0x284, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 9 data 0 register
Offset: 0x288, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 9 data 1 register
Offset: 0x28C, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 10 data 0 register
Offset: 0x290, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 10 data 1 register
Offset: 0x294, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 11 data 0 register
Offset: 0x298, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 11 data 1 register
Offset: 0x29C, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 12 data 0 register
Offset: 0x2A0, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 12 data 1 register
Offset: 0x2A4, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 13 data 0 register
Offset: 0x2A8, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 13 data 1 register
Offset: 0x2AC, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 14 data 0 register
Offset: 0x2B0, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 14 data 1 register
Offset: 0x2B4, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 15 data 0 register
Offset: 0x2B8, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 15 data 1 register
Offset: 0x2BC, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 16 data 0 register
Offset: 0x2C0, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 16 data 1 register
Offset: 0x2C4, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 17 data 0 register
Offset: 0x2C8, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 17 data 1 register
Offset: 0x2CC, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 18 data 0 register
Offset: 0x2D0, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 18 data 1 register
Offset: 0x2D4, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 19 data 0 register
Offset: 0x2D8, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 19 data 1 register
Offset: 0x2DC, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 20 data 0 register
Offset: 0x2E0, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 20 data 1 register
Offset: 0x2E4, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 21 data 0 register
Offset: 0x2E8, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 21 data 1 register
Offset: 0x2EC, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 22 data 0 register
Offset: 0x2F0, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 22 data 1 register
Offset: 0x2F4, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 23 data 0 register
Offset: 0x2F8, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 23 data 1 register
Offset: 0x2FC, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 24 data 0 register
Offset: 0x300, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 24 data 1 register
Offset: 0x304, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 25 data 0 register
Offset: 0x308, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 25 data 1 register
Offset: 0x30C, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 26 data 0 register
Offset: 0x310, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 26 data 1 register
Offset: 0x314, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 27 data 0 register
Offset: 0x318, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 27 data 1 register
Offset: 0x31C, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
0x40006800: Controller area network
261/2059 fields covered. Toggle Registers.
Receive message FIFO0 register
Offset: 0xC, reset: 0x00000000, access: Unspecified
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RFD0
rw |
RFO0
rw |
RFF0
rw |
RFL0
r |
Receive message FIFO1 register
Offset: 0x10, reset: 0x00000000, access: Unspecified
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RFD1
rw |
RFO1
rw |
RFF1
rw |
RFL1
r |
Transmit mailbox property register 0
Offset: 0x184, reset: 0x00000000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSEN
rw |
DLENC
rw |
Transmit mailbox data0 register
Offset: 0x188, reset: 0x00000000, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DB3
rw |
DB2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DB1
rw |
DB0
rw |
Transmit mailbox data1 register
Offset: 0x18C, reset: 0x00000000, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DB7
rw |
DB6
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DB5
rw |
DB4
rw |
Transmit mailbox property register 1
Offset: 0x194, reset: 0x00000000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSEN
rw |
DLENC
rw |
Transmit mailbox data0 register
Offset: 0x198, reset: 0x00000000, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DB3
rw |
DB2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DB1
rw |
DB0
rw |
Transmit mailbox data1 register
Offset: 0x19C, reset: 0x00000000, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DB7
rw |
DB6
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DB5
rw |
DB4
rw |
Transmit mailbox property register 2
Offset: 0x1A4, reset: 0x00000000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TSEN
rw |
DLENC
rw |
Transmit mailbox data0 register
Offset: 0x1A8, reset: 0x00000000, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DB3
rw |
DB2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DB1
rw |
DB0
rw |
Transmit mailbox data1 register
Offset: 0x1AC, reset: 0x00000000, access: read-write
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DB7
rw |
DB6
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DB5
rw |
DB4
rw |
Receive FIFO0 mailbox property register
Offset: 0x1B4, reset: 0x00000000, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TS
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FI
r |
DLENC
r |
Receive FIFO0 mailbox data0 register
Offset: 0x1B8, reset: 0x00000000, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DB3
r |
DB2
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DB1
r |
DB0
r |
Receive FIFO0 mailbox data1 register
Offset: 0x1BC, reset: 0x00000000, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DB7
r |
DB6
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DB5
r |
DB4
r |
Receive FIFO1 mailbox property register
Offset: 0x1C4, reset: 0x00000000, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TS
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FI
r |
DLENC
r |
Receive FIFO1 mailbox data0 register
Offset: 0x1C8, reset: 0x00000000, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DB3
r |
DB2
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DB1
r |
DB0
r |
Receive FIFO1 mailbox data1 register
Offset: 0x1CC, reset: 0x00000000, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DB7
r |
DB6
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DB5
r |
DB4
r |
Filter control register
Offset: 0x200, reset: 0x2A1C0E01, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HBC1F
rw |
FLD
rw |
Filter mode configuration register
Offset: 0x204, reset: 0x00000000, access: read-write
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FMOD27
rw |
FMOD26
rw |
FMOD25
rw |
FMOD24
rw |
FMOD23
rw |
FMOD22
rw |
FMOD21
rw |
FMOD20
rw |
FMOD19
rw |
FMOD18
rw |
FMOD17
rw |
FMOD16
rw |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FMOD15
rw |
FMOD14
rw |
FMOD13
rw |
FMOD12
rw |
FMOD11
rw |
FMOD10
rw |
FMOD9
rw |
FMOD8
rw |
FMOD7
rw |
FMOD6
rw |
FMOD5
rw |
FMOD4
rw |
FMOD3
rw |
FMOD2
rw |
FMOD1
rw |
FMOD0
rw |
Filter scale configuration register
Offset: 0x20C, reset: 0x00000000, access: read-write
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FS27
rw |
FS26
rw |
FS25
rw |
FS24
rw |
FS23
rw |
FS22
rw |
FS21
rw |
FS20
rw |
FS19
rw |
FS18
rw |
FS17
rw |
FS16
rw |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FS15
rw |
FS14
rw |
FS13
rw |
FS12
rw |
FS11
rw |
FS10
rw |
FS9
rw |
FS8
rw |
FS7
rw |
FS6
rw |
FS5
rw |
FS4
rw |
FS3
rw |
FS2
rw |
FS1
rw |
FS0
rw |
Filter associated FIFO register
Offset: 0x214, reset: 0x00000000, access: read-write
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FAF27
rw |
FAF26
rw |
FAF25
rw |
FAF24
rw |
FAF23
rw |
FAF22
rw |
FAF21
rw |
FAF20
rw |
FAF19
rw |
FAF18
rw |
FAF17
rw |
FAF16
rw |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FAF15
rw |
FAF14
rw |
FAF13
rw |
FAF12
rw |
FAF11
rw |
FAF10
rw |
FAF9
rw |
FAF8
rw |
FAF7
rw |
FAF6
rw |
FAF5
rw |
FAF4
rw |
FAF3
rw |
FAF2
rw |
FAF1
rw |
FAF0
rw |
Filter working register
Offset: 0x21C, reset: 0x00000000, access: read-write
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FW27
rw |
FW26
rw |
FW25
rw |
FW24
rw |
FW23
rw |
FW22
rw |
FW21
rw |
FW20
rw |
FW19
rw |
FW18
rw |
FW17
rw |
FW16
rw |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FW15
rw |
FW14
rw |
FW13
rw |
FW12
rw |
FW11
rw |
FW10
rw |
FW9
rw |
FW8
rw |
FW7
rw |
FW6
rw |
FW5
rw |
FW4
rw |
FW3
rw |
FW2
rw |
FW1
rw |
FW0
rw |
Filter 0 data 0 register
Offset: 0x240, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 0 data 1 register
Offset: 0x244, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 1 data 0 register
Offset: 0x248, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 1 data 1 register
Offset: 0x24C, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 2 data 0 register
Offset: 0x250, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 2 data 1 register
Offset: 0x254, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 3 data 0 register
Offset: 0x258, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 3 data 1 register
Offset: 0x25C, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 4 data 0 register
Offset: 0x260, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 4 data 1 register
Offset: 0x264, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 5 data 0 register
Offset: 0x268, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 5 data 1 register
Offset: 0x26C, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 6 data 0 register
Offset: 0x270, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 6 data 1 register
Offset: 0x274, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 7 data 0 register
Offset: 0x278, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 7 data 1 register
Offset: 0x27C, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 8 data 0 register
Offset: 0x280, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 8 data 1 register
Offset: 0x284, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 9 data 0 register
Offset: 0x288, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 9 data 1 register
Offset: 0x28C, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 10 data 0 register
Offset: 0x290, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 10 data 1 register
Offset: 0x294, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 11 data 0 register
Offset: 0x298, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 11 data 1 register
Offset: 0x29C, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 12 data 0 register
Offset: 0x2A0, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 12 data 1 register
Offset: 0x2A4, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 13 data 0 register
Offset: 0x2A8, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 13 data 1 register
Offset: 0x2AC, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 14 data 0 register
Offset: 0x2B0, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 14 data 1 register
Offset: 0x2B4, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 15 data 0 register
Offset: 0x2B8, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 15 data 1 register
Offset: 0x2BC, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 16 data 0 register
Offset: 0x2C0, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 16 data 1 register
Offset: 0x2C4, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 17 data 0 register
Offset: 0x2C8, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 17 data 1 register
Offset: 0x2CC, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 18 data 0 register
Offset: 0x2D0, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 18 data 1 register
Offset: 0x2D4, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 19 data 0 register
Offset: 0x2D8, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 19 data 1 register
Offset: 0x2DC, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 20 data 0 register
Offset: 0x2E0, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 20 data 1 register
Offset: 0x2E4, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 21 data 0 register
Offset: 0x2E8, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 21 data 1 register
Offset: 0x2EC, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 22 data 0 register
Offset: 0x2F0, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 22 data 1 register
Offset: 0x2F4, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 23 data 0 register
Offset: 0x2F8, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 23 data 1 register
Offset: 0x2FC, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 24 data 0 register
Offset: 0x300, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 24 data 1 register
Offset: 0x304, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 25 data 0 register
Offset: 0x308, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 25 data 1 register
Offset: 0x30C, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 26 data 0 register
Offset: 0x310, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 26 data 1 register
Offset: 0x314, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 27 data 0 register
Offset: 0x318, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
Filter 27 data 1 register
Offset: 0x31C, reset: 0x00000000, access: read-write
0/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FD31
rw |
FD30
rw |
FD29
rw |
FD28
rw |
FD27
rw |
FD26
rw |
FD25
rw |
FD24
rw |
FD23
rw |
FD22
rw |
FD21
rw |
FD20
rw |
FD19
rw |
FD18
rw |
FD17
rw |
FD16
rw |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD15
rw |
FD14
rw |
FD13
rw |
FD12
rw |
FD11
rw |
FD10
rw |
FD9
rw |
FD8
rw |
FD7
rw |
FD6
rw |
FD5
rw |
FD4
rw |
FD3
rw |
FD2
rw |
FD1
rw |
FD0
rw |
0x40023000: CRC calculation unit
3/3 fields covered. Toggle Registers.
Data register
Offset: 0x0, reset: 0xFFFFFFFF, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Independent Data register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FDATA
rw |
Control register
Offset: 0x8, reset: 0x00000000, access: write-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RST
w |
0x40007400: Digital to analog converter
26/30 fields covered. Toggle Registers.
software trigger register
Offset: 0x4, reset: 0x00000000, access: write-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SWTR1
w |
SWTR0
w |
DAC0 12-bit right-aligned data holding register
Offset: 0x8, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DAC0_DH
rw |
DAC0 12-bit left-aligned data holding register
Offset: 0xC, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DAC0_DH
rw |
DAC0 8-bit right aligned data holding register
Offset: 0x10, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DAC0_DH
rw |
DAC1 12-bit right-aligned data holding register
Offset: 0x14, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DAC1_DH
rw |
DAC1 12-bit left aligned data holding register
Offset: 0x18, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DAC1_DH
rw |
DAC1 8-bit right aligned data holding register
Offset: 0x1C, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DAC1_DH
rw |
DAC concurrent mode 12-bit right-aligned data holding register
Offset: 0x20, reset: 0x00000000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DAC1_DH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DAC0_DH
rw |
DAC concurrent mode 12-bit left aligned data holding register
Offset: 0x24, reset: 0x00000000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DAC1_DH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DAC0_DH
rw |
DAC concurrent mode 8-bit right aligned data holding register
Offset: 0x28, reset: 0x00000000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DAC1_DH
rw |
DAC0_DH
rw |
DAC0 data output register
Offset: 0x2C, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DAC0_DO
r |
DAC1 data output register
Offset: 0x30, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DAC1_DO
r |
0xE0042000: Debug support
24/26 fields covered. Toggle Registers.
ID code register
Offset: 0x0, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID_CODE
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ID_CODE
r |
Control register
Offset: 0x4, reset: 0x00000000, access: read-write
23/25 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TIMER10_HOLD
rw |
TIMER9_HOLD
rw |
TIMER8_HOLD
rw |
TIMER13_HOLD
rw |
TIMER12_HOLD
rw |
TIMER11_HOLD
rw |
CAN1_HOLD
rw |
TIMER7_HOLD
rw |
TIMER6_HOLD
rw |
TIMER5_HOLD
rw |
TIMER4_HOLD
rw |
I2C1_HOLD
rw |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
I2C0_HOLD
rw |
CAN0_HOLD
rw |
TIMER3_HOLD
rw |
TIMER2_HOLD
rw |
TIMER1_HOLD
rw |
TIMER0_HOLD
rw |
WWDGT_HOLD
rw |
FWDGT_HOLD
rw |
TRACE_MODE
rw |
TRACE_IOEN
rw |
STB_HOLD
rw |
DSLP_HOLD
rw |
SLP_HOLD
rw |
0x50050000: Digital Camera Interface
17/50 fields covered. Toggle Registers.
DCI Status register 0
Offset: 0x4, reset: 0x00000000, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FV
r |
VS
r |
HS
r |
DCI Synchronization codes register
Offset: 0x18, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FE
rw |
LE
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LS
rw |
FS
rw |
DCI Synchronization codes unmask register
Offset: 0x1C, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FEM
rw |
LEM
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LSM
rw |
FSM
rw |
DCI Cropping window start position register
Offset: 0x20, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WVSP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WHSP
rw |
DCI Cropping window size register
Offset: 0x24, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WVSZ
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WHSZ
rw |
DCI DATA register
Offset: 0x28, reset: 0x00000000, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DT3
r |
DT2
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DT1
r |
DT0
r |
0x40020000: DMA controller
147/161 fields covered. Toggle Registers.
Interrupt flag register
Offset: 0x0, reset: 0x00000000, access: read-only
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ERRIF6
r |
HTFIF6
r |
FTFIF6
r |
GIF6
r |
ERRIF5
r |
HTFIF5
r |
FTFIF5
r |
GIF5
r |
ERRIF4
r |
HTFIF4
r |
FTFIF4
r |
GIF4
r |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ERRIF3
r |
HTFIF3
r |
FTFIF3
r |
GIF3
r |
ERRIF2
r |
HTFIF2
r |
FTFIF2
r |
GIF2
r |
ERRIF1
r |
HTFIF1
r |
FTFIF1
r |
GIF1
r |
ERRIF0
r |
HTFIF0
r |
FTFIF0
r |
GIF0
r |
Interrupt flag clear register
Offset: 0x4, reset: 0x00000000, access: write-only
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ERRIFC6
w |
HTFIFC6
w |
FTFIFC6
w |
GIFC6
w |
ERRIFC5
w |
HTFIFC5
w |
FTFIFC5
w |
GIFC5
w |
ERRIFC4
w |
HTFIFC4
w |
FTFIFC4
w |
GIFC4
w |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ERRIFC3
w |
HTFIFC3
w |
FTFIFC3
w |
GIFC3
w |
ERRIFC2
w |
HTFIFC2
w |
FTFIFC2
w |
GIFC2
w |
ERRIFC1
w |
HTFIFC1
w |
FTFIFC1
w |
GIFC1
w |
ERRIFC0
w |
HTFIFC0
w |
FTFIFC0
w |
GIFC0
w |
Channel 0 counter register
Offset: 0xC, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Channel 0 peripheral base address register
Offset: 0x10, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PADDR
rw |
Channel 0 memory base address register
Offset: 0x14, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MADDR
rw |
Channel 1 counter register
Offset: 0x20, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Channel 1 peripheral base address register
Offset: 0x24, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PADDR
rw |
Channel 1 memory base address register
Offset: 0x28, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MADDR
rw |
Channel 2 counter register
Offset: 0x34, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Channel 2 peripheral base address register
Offset: 0x38, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PADDR
rw |
Channel 2 memory base address register
Offset: 0x3C, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MADDR
rw |
Channel 3 counter register
Offset: 0x48, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Channel 3 peripheral base address register
Offset: 0x4C, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PADDR
rw |
Channel 3 memory base address register
Offset: 0x50, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MADDR
rw |
Channel 4 counter register
Offset: 0x5C, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Channel 4 peripheral base address register
Offset: 0x60, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PADDR
rw |
Channel 4 memory base address register
Offset: 0x64, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MADDR
rw |
Channel 5 counter register
Offset: 0x70, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Channel 5 peripheral base address register
Offset: 0x74, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PADDR
rw |
Channel 5 memory base address register
Offset: 0x78, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MADDR
rw |
Channel 6 counter register
Offset: 0x84, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Channel 6 peripheral base address register
Offset: 0x88, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PADDR
rw |
Channel 6 memory base address register
Offset: 0x8C, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MADDR
rw |
0x40020400: DMA controller
147/162 fields covered. Toggle Registers.
Interrupt flag register
Offset: 0x0, reset: 0x00000000, access: read-only
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ERRIF6
r |
HTFIF6
r |
FTFIF6
r |
GIF6
r |
ERRIF5
r |
HTFIF5
r |
FTFIF5
r |
GIF5
r |
ERRIF4
r |
HTFIF4
r |
FTFIF4
r |
GIF4
r |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ERRIF3
r |
HTFIF3
r |
FTFIF3
r |
GIF3
r |
ERRIF2
r |
HTFIF2
r |
FTFIF2
r |
GIF2
r |
ERRIF1
r |
HTFIF1
r |
FTFIF1
r |
GIF1
r |
ERRIF0
r |
HTFIF0
r |
FTFIF0
r |
GIF0
r |
Interrupt flag clear register
Offset: 0x4, reset: 0x00000000, access: write-only
28/28 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ERRIFC6
w |
HTFIFC6
w |
FTFIFC6
w |
GIFC6
w |
ERRIFC5
w |
HTFIFC5
w |
FTFIFC5
w |
GIFC5
w |
ERRIFC4
w |
HTFIFC4
w |
FTFIFC4
w |
GIFC4
w |
||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ERRIFC3
w |
HTFIFC3
w |
FTFIFC3
w |
GIFC3
w |
ERRIFC2
w |
HTFIFC2
w |
FTFIFC2
w |
GIFC2
w |
ERRIFC1
w |
HTFIFC1
w |
FTFIFC1
w |
GIFC1
w |
ERRIFC0
w |
HTFIFC0
w |
FTFIFC0
w |
GIFC0
w |
Channel 0 counter register
Offset: 0xC, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Channel 0 peripheral base address register
Offset: 0x10, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PADDR
rw |
Channel 0 memory base address register
Offset: 0x14, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MADDR
rw |
Channel 1 counter register
Offset: 0x20, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Channel 1 peripheral base address register
Offset: 0x24, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PADDR
rw |
Channel 1 memory base address register
Offset: 0x28, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MADDR
rw |
Channel 2 counter register
Offset: 0x34, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Channel 2 peripheral base address register
Offset: 0x38, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PADDR
rw |
Channel 2 memory base address register
Offset: 0x3C, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MADDR
rw |
Channel 3 counter register
Offset: 0x48, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Channel 3 peripheral base address register
Offset: 0x4C, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PADDR
rw |
Channel 3 memory base address register
Offset: 0x50, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MADDR
rw |
Channel 4 counter register
Offset: 0x5C, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Channel 4 peripheral base address register
Offset: 0x60, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PADDR
rw |
Channel 4 memory base address register
Offset: 0x64, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MADDR
rw |
Channel 5 counter register
Offset: 0x70, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Channel 5 peripheral base address register
Offset: 0x74, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PADDR
rw |
Channel 5 memory base address register
Offset: 0x78, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MADDR
rw |
Channel 6 counter register
Offset: 0x84, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Channel 6 peripheral base address register
Offset: 0x88, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PADDR
rw |
Channel 6 memory base address register
Offset: 0x8C, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MADDR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MADDR
rw |
DMA additional configuration register
Offset: 0x300, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FD_CH5EN
rw |
0x40029000: Ethernet: DMA controller operation
13/69 fields covered. Toggle Registers.
Ethernet DMA transmit poll enable register
Offset: 0x4, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TPE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TPE
rw |
Ethernet DMA receive poll enable register
Offset: 0x8, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RPE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RPE
rw |
Ethernet DMA receive descriptor table address register
Offset: 0xC, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SRT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SRT
rw |
Ethernet DMA transmit descriptor table address register
Offset: 0x10, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STT
rw |
Ethernet DMA missed frame and buffer overflow counter register
Offset: 0x20, reset: 0x00000000, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OBFOC
r |
MSFA
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSFC
r |
DMA current transmit descriptor address register
Offset: 0x48, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TDAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TDAP
r |
Ethernet DMA current receive descriptor address register
Offset: 0x4C, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RDAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RDAP
r |
Ethernet DMA current transmit buffer address register
Offset: 0x50, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TBAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TBAP
r |
Ethernet DMA current receive buffer address register
Offset: 0x54, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RBAP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RBAP
r |
0x40028000: Ethernet: media access control
5/78 fields covered. Toggle Registers.
Ethernet MAC hash list high register
Offset: 0x8, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HLH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HLH
rw |
Ethernet MAC hash list low register
Offset: 0xC, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HLL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HLL
rw |
Ethernet MAC MII data register (MAC_PHY_DATA)
Offset: 0x14, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PD
rw |
Ethernet MAC VLAN tag register (MAC_VLT)
Offset: 0x1C, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VLTC
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VLTI
rw |
Ethernet MAC remote wakeup frame filter register (MAC_RWFF)
Offset: 0x28, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Ethernet MAC interrupt mask register (MAC_INTMSK)
Offset: 0x3C, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TMSTIM
rw |
WUMIM
rw |
Ethernet MAC address 0 high register (MAC_ADDR0H)
Offset: 0x40, reset: 0x8000FFFF, access: Unspecified
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MO
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR0H
rw |
Ethernet MAC address 0 low register
Offset: 0x44, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADDR0L
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR0L
rw |
Ethernet MAC address 1 high register (MAC_ADDR1H)
Offset: 0x48, reset: 0x0000FFFF, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFE
rw |
SAF
rw |
MB
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR1H
rw |
Ethernet MAC address1 low register
Offset: 0x4C, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADDR1L
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR1L
rw |
Ethernet MAC address 2 high register (MAC_ADDR2H)
Offset: 0x50, reset: 0x0000FFFF, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFE
rw |
SAF
rw |
MB
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR2H
rw |
Ethernet MAC address 2 low register
Offset: 0x54, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADDR2L
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR2L
rw |
Ethernet MAC address 3 high register (MAC_ADDR3H)
Offset: 0x58, reset: 0x0000FFFF, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
AFE
rw |
SAF
rw |
MB
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR3H
rw |
Ethernet MAC address 3 low register
Offset: 0x5C, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADDR3L
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR3L
rw |
Ethernet MAC flow control threshold register
Offset: 0x1080, reset: 0x00000015, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RFD
rw |
RFA
rw |
0x40028100: Ethernet: MAC statistics counters
12/22 fields covered. Toggle Registers.
Ethernet MSC control register (MSC_CTL)
Offset: 0x0, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MCFZ
rw |
RTOR
rw |
CTSR
rw |
CTR
rw |
Ethernet MSC receive interrupt flag register (MSC_RINTF)
Offset: 0x4, reset: 0x00000000, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RGUF
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RFAE
r |
RFCE
r |
Ethernet MSC transmit interrupt flag register (MSC_TINTF)
Offset: 0x8, reset: 0x00000000, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TGF
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TGFMSC
r |
TGFSC
r |
Ethernet MSC receive interrupt mask register (MSC_RINTMSK)
Offset: 0xC, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RGUFIM
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RFAEIM
rw |
RFCEIM
rw |
Ethernet MSC transmit interrupt mask register (MSC_TINTMSK)
Offset: 0x10, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TGFIM
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TGFMSCIM
rw |
TGFSCIM
rw |
Ethernet MSC transmitted good frames after a single collision counter
Offset: 0x4C, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SCC
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SCC
r |
Ethernet MSC transmitted good frames after more than a single collision
Offset: 0x50, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MSCC
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSCC
r |
Ethernet MSC transmitted good frames counter register
Offset: 0x68, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TGF
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TGF
r |
Ethernet MSC received frames with CRC error counter register
Offset: 0x94, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RFCER
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RFCER
r |
Ethernet MSC received frames with alignment error counter register
Offset: 0x98, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RFAER
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RFAER
r |
MSC received good unicast frames counter register
Offset: 0xC4, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RGUF
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RGUF
r |
0x40028700: Ethernet: Precision time protocol
3/16 fields covered. Toggle Registers.
Ethernet PTP subsecond increment register
Offset: 0x4, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STMSSI
rw |
Ethernet PTP time stamp high register
Offset: 0x8, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STMS
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STMS
r |
Ethernet PTP time stamp low register (PTP_TSL)
Offset: 0xC, reset: 0x00000000, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STS
r |
STMSS
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STMSS
r |
Ethernet PTP time stamp high update register
Offset: 0x10, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TMSUS
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TMSUS
rw |
Ethernet PTP time stamp low update register (PTP_TSUL)
Offset: 0x14, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TMSUPNS
rw |
TMSUSS
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TMSUSS
rw |
Ethernet PTP time stamp addend register
Offset: 0x18, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TMSA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TMSA
rw |
Ethernet PTP expected time high register
Offset: 0x1C, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ETSH
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ETSH
rw |
Ethernet PTP expected time low register
Offset: 0x20, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ETSL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ETSL
rw |
0xA0000000: External memory controller
5/183 fields covered. Toggle Registers.
NAND flash/PC card common space timing configuration register 1
Offset: 0x68, reset: 0xFCFCFCFC, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
COMHIZ
rw |
COMHLD
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMWAIT
rw |
COMSET
rw |
NAND flash/PC card attribute space timing configuration register 1
Offset: 0x6C, reset: 0xFCFCFCFC, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ATTHIZ
rw |
ATTHLD
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ATTWAIT
rw |
ATTSET
rw |
NAND flash ECC register 1
Offset: 0x74, reset: 0x00000000, access: Unspecified
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ECC
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC
r |
NAND flash/PC card common space timing configuration register 2
Offset: 0x88, reset: 0xFCFCFCFC, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
COMHIZ
rw |
COMHLD
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMWAIT
rw |
COMSET
rw |
NAND flash/PC card attribute space timing configuration register 2
Offset: 0x8C, reset: 0xFCFCFCFC, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ATTHIZ
rw |
ATTHLD
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ATTWAIT
rw |
ATTSET
rw |
NAND flash ECC register 2
Offset: 0x94, reset: 0x00000000, access: Unspecified
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ECC
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC
r |
NAND flash/PC card common space timing configuration register 3
Offset: 0xA8, reset: 0xFCFCFCFC, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
COMHIZ
rw |
COMHLD
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMWAIT
rw |
COMSET
rw |
NAND flash/PC card attribute space timing configuration register 3
Offset: 0xAC, reset: 0xFCFCFCFC, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ATTHIZ
rw |
ATTHLD
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ATTWAIT
rw |
ATTSET
rw |
PC card I/O space timing configuration register
Offset: 0xB0, reset: 0xFCFCFCFC, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IOHIZ
rw |
IOHLD
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IOWAIT
rw |
IOSET
rw |
0x40010400: External interrupt/event controller
120/120 fields covered. Toggle Registers.
Interrupt enable register (EXTI_INTEN)
Offset: 0x0, reset: 0x00000000, access: read-write
20/20 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
INTEN19
rw |
INTEN18
rw |
INTEN17
rw |
INTEN16
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTEN15
rw |
INTEN14
rw |
INTEN13
rw |
INTEN12
rw |
INTEN11
rw |
INTEN10
rw |
INTEN9
rw |
INTEN8
rw |
INTEN7
rw |
INTEN6
rw |
INTEN5
rw |
INTEN4
rw |
INTEN3
rw |
INTEN2
rw |
INTEN1
rw |
INTEN0
rw |
Software interrupt event register (EXTI_SWIEV)
Offset: 0x10, reset: 0x00000000, access: read-write
20/20 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SWIEV19
rw |
SWIEV18
rw |
SWIEV17
rw |
SWIEV16
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SWIEV15
rw |
SWIEV14
rw |
SWIEV13
rw |
SWIEV12
rw |
SWIEV11
rw |
SWIEV10
rw |
SWIEV9
rw |
SWIEV8
rw |
SWIEV7
rw |
SWIEV6
rw |
SWIEV5
rw |
SWIEV4
rw |
SWIEV3
rw |
SWIEV2
rw |
SWIEV1
rw |
SWIEV0
rw |
0x40022000: FMC
38/38 fields covered. Toggle Registers.
wait state counter register
Offset: 0x0, reset: 0x00000000, access: Unspecified
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WSCNT
rw |
Flash unlock key register
Offset: 0x4, reset: 0x00000000, access: write-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KEY
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY
w |
Option byte unlock key register
Offset: 0x8, reset: 0x00000000, access: write-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OBKEY
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OBKEY
w |
Status register 0
Offset: 0xC, reset: 0x00000000, access: Unspecified
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENDF
rw |
WPERR
rw |
PGERR
rw |
BUSY
r |
Address register 0
Offset: 0x14, reset: 0x00000000, access: write-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADDR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR
w |
Erase/Program Protection register
Offset: 0x20, reset: 0x000000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WP
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WP
r |
Unlock key register 1
Offset: 0x44, reset: 0x00000000, access: write-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KEY
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY
w |
Status register 1
Offset: 0x4C, reset: 0x00000000, access: Unspecified
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENDF
rw |
WPERR
rw |
PGERR
rw |
BUSY
r |
Address register 1
Offset: 0x54, reset: 0x00000000, access: write-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADDR
w |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR
w |
Wait state enable register
Offset: 0xFC, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WSEN
rw |
Product ID register
Offset: 0x100, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PID
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PID
r |
0x40003000: free watchdog timer
5/5 fields covered. Toggle Registers.
Control register
Offset: 0x0, reset: 0x00000000, access: write-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMD
w |
Prescaler register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
rw |
Reload register
Offset: 0x8, reset: 0x00000FFF, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RLD
rw |
Status register
Offset: 0xC, reset: 0x00000000, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RUD
r |
PUD
r |
0x40010800: General-purpose I/Os
129/129 fields covered. Toggle Registers.
port control register 0
Offset: 0x0, reset: 0x44444444, access: read-write
16/16 fields covered.
Bits 2-3: Port x configuration bits (x = 0).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 6-7: Port x configuration bits (x = 1).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 10-11: Port x configuration bits (x = 2).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 14-15: Port x configuration bits (x = 3).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 18-19: Port x configuration bits (x = 4).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 22-23: Port x configuration bits (x = 5).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 26-27: Port x configuration bits (x = 6).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 30-31: Port x configuration bits (x = 7).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
port control register 1
Offset: 0x4, reset: 0x44444444, access: read-write
16/16 fields covered.
Bits 2-3: Port x configuration bits (x = 8).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 6-7: Port x configuration bits (x = 9).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 10-11: Port x configuration bits (x = 10).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 14-15: Port x configuration bits (x = 11).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 18-19: Port x configuration bits (x = 12).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 22-23: Port x configuration bits (x = 13).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 26-27: Port x configuration bits (x = 14).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 30-31: Port x configuration bits (x = 15).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Port bit operate register
Offset: 0x10, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CR15
w |
CR14
w |
CR13
w |
CR12
w |
CR11
w |
CR10
w |
CR9
w |
CR8
w |
CR7
w |
CR6
w |
CR5
w |
CR4
w |
CR3
w |
CR2
w |
CR1
w |
CR0
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BOP15
w |
BOP14
w |
BOP13
w |
BOP12
w |
BOP11
w |
BOP10
w |
BOP9
w |
BOP8
w |
BOP7
w |
BOP6
w |
BOP5
w |
BOP4
w |
BOP3
w |
BOP2
w |
BOP1
w |
BOP0
w |
0x40010C00: General-purpose I/Os
129/129 fields covered. Toggle Registers.
port control register 0
Offset: 0x0, reset: 0x44444444, access: read-write
16/16 fields covered.
Bits 2-3: Port x configuration bits (x = 0).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 6-7: Port x configuration bits (x = 1).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 10-11: Port x configuration bits (x = 2).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 14-15: Port x configuration bits (x = 3).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 18-19: Port x configuration bits (x = 4).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 22-23: Port x configuration bits (x = 5).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 26-27: Port x configuration bits (x = 6).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 30-31: Port x configuration bits (x = 7).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
port control register 1
Offset: 0x4, reset: 0x44444444, access: read-write
16/16 fields covered.
Bits 2-3: Port x configuration bits (x = 8).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 6-7: Port x configuration bits (x = 9).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 10-11: Port x configuration bits (x = 10).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 14-15: Port x configuration bits (x = 11).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 18-19: Port x configuration bits (x = 12).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 22-23: Port x configuration bits (x = 13).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 26-27: Port x configuration bits (x = 14).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 30-31: Port x configuration bits (x = 15).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Port bit operate register
Offset: 0x10, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CR15
w |
CR14
w |
CR13
w |
CR12
w |
CR11
w |
CR10
w |
CR9
w |
CR8
w |
CR7
w |
CR6
w |
CR5
w |
CR4
w |
CR3
w |
CR2
w |
CR1
w |
CR0
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BOP15
w |
BOP14
w |
BOP13
w |
BOP12
w |
BOP11
w |
BOP10
w |
BOP9
w |
BOP8
w |
BOP7
w |
BOP6
w |
BOP5
w |
BOP4
w |
BOP3
w |
BOP2
w |
BOP1
w |
BOP0
w |
0x40011000: General-purpose I/Os
129/129 fields covered. Toggle Registers.
port control register 0
Offset: 0x0, reset: 0x44444444, access: read-write
16/16 fields covered.
Bits 2-3: Port x configuration bits (x = 0).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 6-7: Port x configuration bits (x = 1).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 10-11: Port x configuration bits (x = 2).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 14-15: Port x configuration bits (x = 3).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 18-19: Port x configuration bits (x = 4).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 22-23: Port x configuration bits (x = 5).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 26-27: Port x configuration bits (x = 6).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 30-31: Port x configuration bits (x = 7).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
port control register 1
Offset: 0x4, reset: 0x44444444, access: read-write
16/16 fields covered.
Bits 2-3: Port x configuration bits (x = 8).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 6-7: Port x configuration bits (x = 9).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 10-11: Port x configuration bits (x = 10).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 14-15: Port x configuration bits (x = 11).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 18-19: Port x configuration bits (x = 12).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 22-23: Port x configuration bits (x = 13).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 26-27: Port x configuration bits (x = 14).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 30-31: Port x configuration bits (x = 15).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Port bit operate register
Offset: 0x10, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CR15
w |
CR14
w |
CR13
w |
CR12
w |
CR11
w |
CR10
w |
CR9
w |
CR8
w |
CR7
w |
CR6
w |
CR5
w |
CR4
w |
CR3
w |
CR2
w |
CR1
w |
CR0
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BOP15
w |
BOP14
w |
BOP13
w |
BOP12
w |
BOP11
w |
BOP10
w |
BOP9
w |
BOP8
w |
BOP7
w |
BOP6
w |
BOP5
w |
BOP4
w |
BOP3
w |
BOP2
w |
BOP1
w |
BOP0
w |
0x40011400: General-purpose I/Os
129/129 fields covered. Toggle Registers.
port control register 0
Offset: 0x0, reset: 0x44444444, access: read-write
16/16 fields covered.
Bits 2-3: Port x configuration bits (x = 0).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 6-7: Port x configuration bits (x = 1).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 10-11: Port x configuration bits (x = 2).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 14-15: Port x configuration bits (x = 3).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 18-19: Port x configuration bits (x = 4).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 22-23: Port x configuration bits (x = 5).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 26-27: Port x configuration bits (x = 6).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 30-31: Port x configuration bits (x = 7).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
port control register 1
Offset: 0x4, reset: 0x44444444, access: read-write
16/16 fields covered.
Bits 2-3: Port x configuration bits (x = 8).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 6-7: Port x configuration bits (x = 9).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 10-11: Port x configuration bits (x = 10).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 14-15: Port x configuration bits (x = 11).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 18-19: Port x configuration bits (x = 12).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 22-23: Port x configuration bits (x = 13).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 26-27: Port x configuration bits (x = 14).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 30-31: Port x configuration bits (x = 15).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Port bit operate register
Offset: 0x10, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CR15
w |
CR14
w |
CR13
w |
CR12
w |
CR11
w |
CR10
w |
CR9
w |
CR8
w |
CR7
w |
CR6
w |
CR5
w |
CR4
w |
CR3
w |
CR2
w |
CR1
w |
CR0
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BOP15
w |
BOP14
w |
BOP13
w |
BOP12
w |
BOP11
w |
BOP10
w |
BOP9
w |
BOP8
w |
BOP7
w |
BOP6
w |
BOP5
w |
BOP4
w |
BOP3
w |
BOP2
w |
BOP1
w |
BOP0
w |
0x40011800: General-purpose I/Os
129/129 fields covered. Toggle Registers.
port control register 0
Offset: 0x0, reset: 0x44444444, access: read-write
16/16 fields covered.
Bits 2-3: Port x configuration bits (x = 0).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 6-7: Port x configuration bits (x = 1).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 10-11: Port x configuration bits (x = 2).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 14-15: Port x configuration bits (x = 3).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 18-19: Port x configuration bits (x = 4).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 22-23: Port x configuration bits (x = 5).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 26-27: Port x configuration bits (x = 6).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 30-31: Port x configuration bits (x = 7).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
port control register 1
Offset: 0x4, reset: 0x44444444, access: read-write
16/16 fields covered.
Bits 2-3: Port x configuration bits (x = 8).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 6-7: Port x configuration bits (x = 9).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 10-11: Port x configuration bits (x = 10).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 14-15: Port x configuration bits (x = 11).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 18-19: Port x configuration bits (x = 12).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 22-23: Port x configuration bits (x = 13).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 26-27: Port x configuration bits (x = 14).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 30-31: Port x configuration bits (x = 15).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Port bit operate register
Offset: 0x10, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CR15
w |
CR14
w |
CR13
w |
CR12
w |
CR11
w |
CR10
w |
CR9
w |
CR8
w |
CR7
w |
CR6
w |
CR5
w |
CR4
w |
CR3
w |
CR2
w |
CR1
w |
CR0
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BOP15
w |
BOP14
w |
BOP13
w |
BOP12
w |
BOP11
w |
BOP10
w |
BOP9
w |
BOP8
w |
BOP7
w |
BOP6
w |
BOP5
w |
BOP4
w |
BOP3
w |
BOP2
w |
BOP1
w |
BOP0
w |
0x40011C00: General-purpose I/Os
129/129 fields covered. Toggle Registers.
port control register 0
Offset: 0x0, reset: 0x44444444, access: read-write
16/16 fields covered.
Bits 2-3: Port x configuration bits (x = 0).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 6-7: Port x configuration bits (x = 1).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 10-11: Port x configuration bits (x = 2).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 14-15: Port x configuration bits (x = 3).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 18-19: Port x configuration bits (x = 4).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 22-23: Port x configuration bits (x = 5).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 26-27: Port x configuration bits (x = 6).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 30-31: Port x configuration bits (x = 7).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
port control register 1
Offset: 0x4, reset: 0x44444444, access: read-write
16/16 fields covered.
Bits 2-3: Port x configuration bits (x = 8).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 6-7: Port x configuration bits (x = 9).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 10-11: Port x configuration bits (x = 10).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 14-15: Port x configuration bits (x = 11).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 18-19: Port x configuration bits (x = 12).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 22-23: Port x configuration bits (x = 13).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 26-27: Port x configuration bits (x = 14).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 30-31: Port x configuration bits (x = 15).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Port bit operate register
Offset: 0x10, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CR15
w |
CR14
w |
CR13
w |
CR12
w |
CR11
w |
CR10
w |
CR9
w |
CR8
w |
CR7
w |
CR6
w |
CR5
w |
CR4
w |
CR3
w |
CR2
w |
CR1
w |
CR0
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BOP15
w |
BOP14
w |
BOP13
w |
BOP12
w |
BOP11
w |
BOP10
w |
BOP9
w |
BOP8
w |
BOP7
w |
BOP6
w |
BOP5
w |
BOP4
w |
BOP3
w |
BOP2
w |
BOP1
w |
BOP0
w |
0x40012000: General-purpose I/Os
129/129 fields covered. Toggle Registers.
port control register 0
Offset: 0x0, reset: 0x44444444, access: read-write
16/16 fields covered.
Bits 2-3: Port x configuration bits (x = 0).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 6-7: Port x configuration bits (x = 1).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 10-11: Port x configuration bits (x = 2).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 14-15: Port x configuration bits (x = 3).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 18-19: Port x configuration bits (x = 4).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 22-23: Port x configuration bits (x = 5).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 26-27: Port x configuration bits (x = 6).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 30-31: Port x configuration bits (x = 7).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
port control register 1
Offset: 0x4, reset: 0x44444444, access: read-write
16/16 fields covered.
Bits 2-3: Port x configuration bits (x = 8).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 6-7: Port x configuration bits (x = 9).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 10-11: Port x configuration bits (x = 10).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 14-15: Port x configuration bits (x = 11).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 18-19: Port x configuration bits (x = 12).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 22-23: Port x configuration bits (x = 13).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 26-27: Port x configuration bits (x = 14).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 30-31: Port x configuration bits (x = 15).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Port bit operate register
Offset: 0x10, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CR15
w |
CR14
w |
CR13
w |
CR12
w |
CR11
w |
CR10
w |
CR9
w |
CR8
w |
CR7
w |
CR6
w |
CR5
w |
CR4
w |
CR3
w |
CR2
w |
CR1
w |
CR0
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BOP15
w |
BOP14
w |
BOP13
w |
BOP12
w |
BOP11
w |
BOP10
w |
BOP9
w |
BOP8
w |
BOP7
w |
BOP6
w |
BOP5
w |
BOP4
w |
BOP3
w |
BOP2
w |
BOP1
w |
BOP0
w |
0x40017400: General-purpose I/Os
129/129 fields covered. Toggle Registers.
port control register 0
Offset: 0x0, reset: 0x44444444, access: read-write
16/16 fields covered.
Bits 2-3: Port x configuration bits (x = 0).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 6-7: Port x configuration bits (x = 1).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 10-11: Port x configuration bits (x = 2).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 14-15: Port x configuration bits (x = 3).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 18-19: Port x configuration bits (x = 4).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 22-23: Port x configuration bits (x = 5).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 26-27: Port x configuration bits (x = 6).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 30-31: Port x configuration bits (x = 7).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
port control register 1
Offset: 0x4, reset: 0x44444444, access: read-write
16/16 fields covered.
Bits 2-3: Port x configuration bits (x = 8).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 6-7: Port x configuration bits (x = 9).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 10-11: Port x configuration bits (x = 10).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 14-15: Port x configuration bits (x = 11).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 18-19: Port x configuration bits (x = 12).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 22-23: Port x configuration bits (x = 13).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 26-27: Port x configuration bits (x = 14).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 30-31: Port x configuration bits (x = 15).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Port bit operate register
Offset: 0x10, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CR15
w |
CR14
w |
CR13
w |
CR12
w |
CR11
w |
CR10
w |
CR9
w |
CR8
w |
CR7
w |
CR6
w |
CR5
w |
CR4
w |
CR3
w |
CR2
w |
CR1
w |
CR0
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BOP15
w |
BOP14
w |
BOP13
w |
BOP12
w |
BOP11
w |
BOP10
w |
BOP9
w |
BOP8
w |
BOP7
w |
BOP6
w |
BOP5
w |
BOP4
w |
BOP3
w |
BOP2
w |
BOP1
w |
BOP0
w |
0x40017800: General-purpose I/Os
129/129 fields covered. Toggle Registers.
port control register 0
Offset: 0x0, reset: 0x44444444, access: read-write
16/16 fields covered.
Bits 2-3: Port x configuration bits (x = 0).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 6-7: Port x configuration bits (x = 1).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 10-11: Port x configuration bits (x = 2).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 14-15: Port x configuration bits (x = 3).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 18-19: Port x configuration bits (x = 4).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 22-23: Port x configuration bits (x = 5).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 26-27: Port x configuration bits (x = 6).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 30-31: Port x configuration bits (x = 7).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
port control register 1
Offset: 0x4, reset: 0x44444444, access: read-write
16/16 fields covered.
Bits 2-3: Port x configuration bits (x = 8).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 6-7: Port x configuration bits (x = 9).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 10-11: Port x configuration bits (x = 10).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 14-15: Port x configuration bits (x = 11).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 18-19: Port x configuration bits (x = 12).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 22-23: Port x configuration bits (x = 13).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 26-27: Port x configuration bits (x = 14).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Bits 30-31: Port x configuration bits (x = 15).
Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain
Port bit operate register
Offset: 0x10, reset: 0x00000000, access: write-only
32/32 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CR15
w |
CR14
w |
CR13
w |
CR12
w |
CR11
w |
CR10
w |
CR9
w |
CR8
w |
CR7
w |
CR6
w |
CR5
w |
CR4
w |
CR3
w |
CR2
w |
CR1
w |
CR0
w |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BOP15
w |
BOP14
w |
BOP13
w |
BOP12
w |
BOP11
w |
BOP10
w |
BOP9
w |
BOP8
w |
BOP7
w |
BOP6
w |
BOP5
w |
BOP4
w |
BOP3
w |
BOP2
w |
BOP1
w |
BOP0
w |
0x40005400: Inter integrated circuit
49/51 fields covered. Toggle Registers.
Slave address register 0
Offset: 0x8, reset: 0x0000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDFORMAT
rw |
ADDRESS
rw |
Slave address register 1
Offset: 0xC, reset: 0x0000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDRESS2
rw |
DUADEN
rw |
Transfer buffer register
Offset: 0x10, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRB
rw |
Clock configure register
Offset: 0x1C, reset: 0x0000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FAST
rw |
DTCY
rw |
CLKC
rw |
Rise time register
Offset: 0x20, reset: 0x0002, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RISETIME
rw |
0x40005800: Inter integrated circuit
49/51 fields covered. Toggle Registers.
Slave address register 0
Offset: 0x8, reset: 0x0000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDFORMAT
rw |
ADDRESS
rw |
Slave address register 1
Offset: 0xC, reset: 0x0000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDRESS2
rw |
DUADEN
rw |
Transfer buffer register
Offset: 0x10, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRB
rw |
Clock configure register
Offset: 0x1C, reset: 0x0000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FAST
rw |
DTCY
rw |
CLKC
rw |
Rise time register
Offset: 0x20, reset: 0x0002, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RISETIME
rw |
0x4000C000: Inter integrated circuit
49/51 fields covered. Toggle Registers.
Slave address register 0
Offset: 0x8, reset: 0x0000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDFORMAT
rw |
ADDRESS
rw |
Slave address register 1
Offset: 0xC, reset: 0x0000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDRESS2
rw |
DUADEN
rw |
Transfer buffer register
Offset: 0x10, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRB
rw |
Clock configure register
Offset: 0x1C, reset: 0x0000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FAST
rw |
DTCY
rw |
CLKC
rw |
Rise time register
Offset: 0x20, reset: 0x0002, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RISETIME
rw |
0xE000E000: Nested Vectored Interrupt Controller
4/113 fields covered. Toggle Registers.
Interrupt Controller Type Register
Offset: 0x4, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTLINESNUM
r |
Interrupt Set-Enable Register
Offset: 0x100, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SETENA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETENA
rw |
Interrupt Set-Enable Register
Offset: 0x104, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SETENA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETENA
rw |
Interrupt Set-Enable Register
Offset: 0x108, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SETENA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETENA
rw |
Interrupt Clear-Enable Register
Offset: 0x180, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLRENA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRENA
rw |
Interrupt Clear-Enable Register
Offset: 0x184, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLRENA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRENA
rw |
Interrupt Clear-Enable Register
Offset: 0x188, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLRENA
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRENA
rw |
Interrupt Set-Pending Register
Offset: 0x200, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SETPEND
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETPEND
rw |
Interrupt Set-Pending Register
Offset: 0x204, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SETPEND
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETPEND
rw |
Interrupt Set-Pending Register
Offset: 0x208, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SETPEND
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETPEND
rw |
Interrupt Clear-Pending Register
Offset: 0x280, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLRPEND
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRPEND
rw |
Interrupt Clear-Pending Register
Offset: 0x284, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLRPEND
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRPEND
rw |
Interrupt Clear-Pending Register
Offset: 0x288, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CLRPEND
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRPEND
rw |
Interrupt Active Bit Register
Offset: 0x300, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ACTIVE
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ACTIVE
r |
Interrupt Active Bit Register
Offset: 0x304, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ACTIVE
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ACTIVE
r |
Interrupt Active Bit Register
Offset: 0x308, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ACTIVE
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ACTIVE
r |
Interrupt Priority Register
Offset: 0x400, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x404, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x408, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x40C, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x410, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x414, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x418, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x41C, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x420, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x424, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x428, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x42C, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x430, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x434, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x438, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x43C, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x440, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x444, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x448, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x44C, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x450, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x454, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x458, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Interrupt Priority Register
Offset: 0x45C, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IPR_N3
rw |
IPR_N2
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IPR_N1
rw |
IPR_N0
rw |
Software Triggered Interrupt Register
Offset: 0xF00, reset: 0x00000000, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTID
w |
0x40007000: Power management unit
11/11 fields covered. Toggle Registers.
power control/status register
Offset: 0x4, reset: 0x00000000, access: Unspecified
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WUPEN0
rw |
LVDF
r |
STBF
r |
WUF
r |
Bit 8: Enable WKUP pin.
Allowed values:
0: Disabled: WKUP pin 0 is used for general purpose I/Os. An event on the WKUP pin 0 does not wakeup the device from Standby mode
1: Enabled: WKUP pin 0 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 0 wakes-up the system from Standby mode)
0x40021000: Reset and clock unit
157/203 fields covered. Toggle Registers.
Clock configuration register 0 (RCU_CFG0)
Offset: 0x4, reset: 0x00000000, access: Unspecified
11/12 fields covered.
Bits 4-7: AHB prescaler selection.
Allowed values:
0: Div1: CK_SYS
8: Div2: CK_SYS divided by 2
9: Div4: CK_SYS divided by 4
10: Div8: CK_SYS divided by 8
11: Div16: CK_SYS divided by 16
12: Div64: CK_SYS divided by 64
13: Div128: CK_SYS divided by 128
14: Div256: CK_SYS divided by 256
15: Div512: CK_SYS divided by 512
Bits 18-21: The PLL clock multiplication factor.
Allowed values:
0: Mul2: PLL input clock x2
1: Mul3: PLL input clock x3
2: Mul4: PLL input clock x4
3: Mul5: PLL input clock x5
4: Mul6: PLL input clock x6
5: Mul7: PLL input clock x7
6: Mul8: PLL input clock x8
7: Mul9: PLL input clock x9
8: Mul10: PLL input clock x10
9: Mul11: PLL input clock x11
10: Mul12: PLL input clock x12
11: Mul13: PLL input clock x13
12: Mul14: PLL input clock x14
13: Mul15: PLL input clock x15
14: Mul16: PLL input clock x16
15: Mul16x: PLL input clock x16
Bits 24-27: CKOUT0 Clock Source Selection.
Allowed values:
0: None: No clock selected
1: IRC14M: Internal 14 MHz RC oscillator clock selected
2: LSI40K: Internal 40 kHz RC oscillator clock selected
3: LXTAL: External low speed oscillator clock selected
4: SYSCLK: System clock selected
5: IRC8M: Internal RC 8 MHz (HSI) oscillator clock selected
6: HXTAL: External 4-32 MHz (HSE) oscillator clock selected
7: PLL: PLL clock selected (divided by 1 or 2, depending on PLLDV)
Clock interrupt register (RCU_INT)
Offset: 0x8, reset: 0x00000000, access: Unspecified
23/23 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CKMIC
w |
PLL2STBIC
w |
PLL1STBIC
w |
PLLSTBIC
w |
HXTALSTBIC
w |
IRC8MSTBIC
w |
LXTALSTBIC
w |
IRC40KSTBIC
w |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PLL2STBIE
rw |
PLL1STBIE
rw |
PLLSTBIE
rw |
HXTALSTBIE
rw |
IRC8MSTBIE
rw |
LXTALSTBIE
rw |
IRC40KSTBIE
rw |
CKMIF
r |
PLL2STBIF
r |
PLL1STBIF
r |
PLLSTBIF
r |
HXTALSTBIF
r |
IRC8MSTBIF
r |
LXTALSTBIF
r |
IRC40KSTBIF
r |
APB1 reset register (RCU_APB1RST)
Offset: 0x10, reset: 0x00000000, access: read-write
23/23 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DACRST
rw |
PMURST
rw |
BKPIRST
rw |
CAN1RST
rw |
CAN0RST
rw |
I2C1RST
rw |
I2C0RST
rw |
UART4RST
rw |
UART3RST
rw |
USART2RST
rw |
USART1RST
rw |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPI2RST
rw |
SPI1RST
rw |
WWDGTRST
rw |
TIMER13RST
rw |
TIMER12RST
rw |
TIMER11RST
rw |
TIMER6RST
rw |
TIMER5RST
rw |
TIMER4RST
rw |
TIMER3RST
rw |
TIMER2RST
rw |
TIMER1RST
rw |
APB1 clock enable register (RCU_APB1EN)
Offset: 0x1C, reset: 0x00000000, access: read-write
23/23 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DACEN
rw |
PMUEN
rw |
BKPIEN
rw |
CAN1EN
rw |
CAN0EN
rw |
I2C1EN
rw |
I2C0EN
rw |
UART4EN
rw |
UART3EN
rw |
USART2EN
rw |
USART1EN
rw |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPI2EN
rw |
SPI1EN
rw |
WWDGTEN
rw |
TIMER13EN
rw |
TIMER12EN
rw |
TIMER11EN
rw |
TIMER6EN
rw |
TIMER5EN
rw |
TIMER4EN
rw |
TIMER3EN
rw |
TIMER2EN
rw |
TIMER1EN
rw |
AHB1 reset register
Offset: 0x28, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENETRST
rw |
USBFSRST
rw |
Clock Configuration register 1
Offset: 0x2C, reset: 0x00000000, access: read-write
2/7 fields covered.
Bits 0-3: PREDV0 division factor.
Allowed values:
0: Div1: Input to PLL not divided
1: Div2: Input to PLL divided by 2
2: Div3: Input to PLL divided by 3
3: Div4: Input to PLL divided by 4
4: Div5: Input to PLL divided by 5
5: Div6: Input to PLL divided by 6
6: Div7: Input to PLL divided by 7
7: Div8: Input to PLL divided by 8
8: Div9: Input to PLL divided by 9
9: Div10: Input to PLL divided by 10
10: Div11: Input to PLL divided by 11
11: Div12: Input to PLL divided by 12
12: Div13: Input to PLL divided by 13
13: Div14: Input to PLL divided by 14
14: Div15: Input to PLL divided by 15
15: Div16: Input to PLL divided by 16
Bits 4-7: PREDV1 division factor.
Allowed values:
0: Div1: Input to PLL not divided
1: Div2: Input to PLL divided by 2
2: Div3: Input to PLL divided by 3
3: Div4: Input to PLL divided by 4
4: Div5: Input to PLL divided by 5
5: Div6: Input to PLL divided by 6
6: Div7: Input to PLL divided by 7
7: Div8: Input to PLL divided by 8
8: Div9: Input to PLL divided by 9
9: Div10: Input to PLL divided by 10
10: Div11: Input to PLL divided by 11
11: Div12: Input to PLL divided by 12
12: Div13: Input to PLL divided by 13
13: Div14: Input to PLL divided by 14
14: Div15: Input to PLL divided by 15
15: Div16: Input to PLL divided by 16
Deep sleep mode Voltage register
Offset: 0x34, reset: 0x00000000, access: Unspecified
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DSLPVS
rw |
AHB2 enable register
Offset: 0x60, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRNGEN
rw |
HAUEN
rw |
CAUEN
rw |
DCIEN
rw |
APB2 additional enable register
Offset: 0x64, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PIEN
rw |
PHEN
rw |
TLIEN
rw |
USART5EN
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
APB1 additional enable register
Offset: 0x68, reset: 0x00000000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UART7EN
rw |
UART6EN
rw |
I2C2EN
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AHB2 reset register
Offset: 0x70, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRNGRST
rw |
HAURST
rw |
CAURST
rw |
DCIRST
rw |
APB2 additional enable register
Offset: 0x74, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PIRST
rw |
PHRST
rw |
TLIRST
rw |
USART5RST
rw |
||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
APB1 additional enable register
Offset: 0x78, reset: 0x00000000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
UART7RST
rw |
UART6RST
rw |
I2C2RST
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
configuration register 2
Offset: 0x80, reset: 0x00000000, access: Unspecified
1/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CKOUT1SEL
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CKOUT1DIV
rw |
CKOUT0DIV
rw |
PLLT control register
Offset: 0x90, reset: 0x00000000, access: Unspecified
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PLLTSTB
r |
PLLTEN
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PLLT interrupt register
Offset: 0x94, reset: 0x00000000, access: Unspecified
1/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PLLTSTBIC
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PLLTSTBIE
rw |
PLLTSTBIF
r |
0x40002800: Real-time clock
3/17 fields covered. Toggle Registers.
RTC interrupt enable register
Offset: 0x0, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OVIE
rw |
ALRMIE
rw |
SCIE
rw |
RTC prescaler high register
Offset: 0x8, reset: 0x00000000, access: Unspecified
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
w |
RTC prescaler low register
Offset: 0xC, reset: 0x00008000, access: Unspecified
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
w |
RTC divider high register
Offset: 0x10, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
r |
RTC divider low register
Offset: 0x14, reset: 0x00008000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV
r |
RTC counter high register
Offset: 0x18, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
RTC counter low register
Offset: 0x1C, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Alarm high register
Offset: 0x20, reset: 0x0000FFFF, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ALRM
w |
RTC alarm low register
Offset: 0x24, reset: 0x0000FFFF, access: write-only
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ALRM
w |
0x40018000: Secure digital input/output interface
31/99 fields covered. Toggle Registers.
Power control register
Offset: 0x0, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PWRCTL
rw |
Command argument register
Offset: 0x8, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMDAGMT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMDAGMT
rw |
Command index response register
Offset: 0x10, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSPCMDIDX
r |
Response register 0
Offset: 0x14, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RESP0
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESP0
r |
Response register 1
Offset: 0x18, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RESP1
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESP1
r |
Response register 2
Offset: 0x1C, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RESP2
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESP2
r |
Response register 3
Offset: 0x20, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RESP3
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESP3
r |
Data timeout register
Offset: 0x24, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATATO
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATATO
rw |
Data length register
Offset: 0x28, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATALEN
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATALEN
rw |
Data counter register
Offset: 0x30, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DATACNT
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATACNT
r |
SDIO status register (SDIO_STR)
Offset: 0x34, reset: 0x00000000, access: read-only
24/24 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ATAEND
r |
SDIOINT
r |
RXDTVAL
r |
TXDTVAL
r |
RFE
r |
TFE
r |
RFF
r |
TFF
r |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RFH
r |
TFH
r |
RXRUN
r |
TXRUN
r |
CMDRUN
r |
DTBLKEND
r |
STBITE
r |
DTEND
r |
CMDSEND
r |
CMDRECV
r |
RXORE
r |
TXURE
r |
DTTMOUT
r |
CMDTMOUT
r |
DTCRCERR
r |
CCRCERR
r |
Interrupt Enable register
Offset: 0x3C, reset: 0x00000000, access: read-write
0/24 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ATAENDIE
rw |
SDIOINTIE
rw |
RXDTVALIE
rw |
TXDTVALIE
rw |
RFEIE
rw |
TFEIE
rw |
RFFIE
rw |
TFFIE
rw |
||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RFHIE
rw |
TFHIE
rw |
RXRUNIE
rw |
TXRUNIE
rw |
CMDRUNIE
rw |
DTBLKENDIE
rw |
STBITEIE
rw |
DTENDIE
rw |
CMDSENDIE
rw |
CMDRECVIE
rw |
RXOREIE
rw |
TXUREIE
rw |
DTTMOUTIE
rw |
CMDTMOUTIE
rw |
DTCRCERRIE
rw |
CCRCERRIE
rw |
FIFO counter register
Offset: 0x48, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FIFOCNT
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFOCNT
r |
FIFO data register
Offset: 0x80, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FIFODT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FIFODT
rw |
0x40013000: Serial peripheral interface
46/46 fields covered. Toggle Registers.
data register
Offset: 0xC, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
CRC polynomial register
Offset: 0x10, reset: 0x0007, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRCPOLY
rw |
RX CRC register
Offset: 0x14, reset: 0x0000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RCRC
r |
TX CRC register
Offset: 0x18, reset: 0x0000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TCRC
r |
I2S prescaler register
Offset: 0x20, reset: 0x0002, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MCKOEN
rw |
OF
rw |
DIV
rw |
Quad-SPI mode control register
Offset: 0x80, reset: 0x0000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IO23_DRV
rw |
QRD
rw |
QMOD
rw |
0x40003800: Serial peripheral interface
46/46 fields covered. Toggle Registers.
data register
Offset: 0xC, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
CRC polynomial register
Offset: 0x10, reset: 0x0007, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRCPOLY
rw |
RX CRC register
Offset: 0x14, reset: 0x0000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RCRC
r |
TX CRC register
Offset: 0x18, reset: 0x0000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TCRC
r |
I2S prescaler register
Offset: 0x20, reset: 0x0002, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MCKOEN
rw |
OF
rw |
DIV
rw |
Quad-SPI mode control register
Offset: 0x80, reset: 0x0000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IO23_DRV
rw |
QRD
rw |
QMOD
rw |
0x40003C00: Serial peripheral interface
46/46 fields covered. Toggle Registers.
data register
Offset: 0xC, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
CRC polynomial register
Offset: 0x10, reset: 0x0007, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRCPOLY
rw |
RX CRC register
Offset: 0x14, reset: 0x0000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RCRC
r |
TX CRC register
Offset: 0x18, reset: 0x0000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TCRC
r |
I2S prescaler register
Offset: 0x20, reset: 0x0002, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MCKOEN
rw |
OF
rw |
DIV
rw |
Quad-SPI mode control register
Offset: 0x80, reset: 0x0000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IO23_DRV
rw |
QRD
rw |
QMOD
rw |
0x40012C00: Advanced timer
127/127 fields covered. Toggle Registers.
control register 0
Offset: 0x0, reset: 0x0000, access: read-write
8/8 fields covered.
Bits 5-6: Center-aligned mode selection.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAlignedCountingDown: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAlignedCountingUp: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAlignedCountingUpDown: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
control register 1
Offset: 0x4, reset: 0x0000, access: read-write
12/12 fields covered.
Bits 4-6: Master mode control.
Allowed values:
0: Reset: Use UPG bit from SWEVG register
1: Enable: Use CEN bit from CTL0 register
2: Update: Use the update event
3: CaptureComparePulse: The trigger output send a positive pulse when a capture or a compare match occurred in channel 0
4: CompareO0C: O0CPRE signal is used as trigger output
5: CompareO1C: O1CPRE signal is used as trigger output
6: CompareO2C: O2CPRE signal is used as trigger output
7: CompareO3C: O3CPRE signal is used as trigger output
slave mode configuration register
Offset: 0x8, reset: 0x0000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode control.
Allowed values:
0: Disabled: Slave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.
1: QuadratureDecoderMode0: Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.
2: QuadratureDecoderMode1: Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.
3: QuadratureDecoderMode2: Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.
4: RestartMode: Restart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: PauseMode: Pause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: EventMode: Event Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: ExternalClockMode: External Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITI0: Internal Trigger 0 (ITI0)
1: ITI1: Internal Trigger 1 (ITI1)
2: ITI2: Internal Trigger 2 (ITI2)
4: CI0F_ED: CI0 Edge Detector (CI0F_ED)
5: CI0FE0: Filtered Timer Input 0 (CI0FE0)
6: CI1FE1: Filtered Timer Input 1 (CI1FE1)
7: ETIFP: External Trigger input (ETIFP)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter control.
Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8
Channel control register 0 (input mode)
Offset: 0x18, reset: 0x0000, access: read-write
6/6 fields covered.
Bits 4-7: Channel 0 input capture filter control.
Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8
counter
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
rw |
Counter auto-reload register
Offset: 0x2C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAR
rw |
Counter repetition register
Offset: 0x30, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CREP
rw |
Channel 0 capture/compare value register
Offset: 0x34, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0VAL
rw |
Channel 1 capture/compare value register
Offset: 0x38, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH1VAL
rw |
Channel 2 capture/compare value register
Offset: 0x3C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH2VAL
rw |
Channel 3 capture/compare value register
Offset: 0x40, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH3VAL
rw |
DMA configuration register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMATC
rw |
DMATA
rw |
DMA transfer buffer register
Offset: 0x4C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMATB
rw |
0x40000000: General-purpose-timers
96/96 fields covered. Toggle Registers.
control register 1
Offset: 0x4, reset: 0x0000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TI0S
rw |
MMC
rw |
DMAS
rw |
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode control.
Allowed values:
0: Disabled: Slave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.
1: QuadratureDecoderMode0: Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.
2: QuadratureDecoderMode1: Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.
3: QuadratureDecoderMode2: Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.
4: RestartMode: Restart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: PauseMode: Pause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: EventMode: Event Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: ExternalClockMode: External Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITI0: Internal Trigger 0 (ITI0)
1: ITI1: Internal Trigger 1 (ITI1)
2: ITI2: Internal Trigger 2 (ITI2)
4: CI0F_ED: CI0 Edge Detector (CI0F_ED)
5: CI0FE0: Filtered Timer Input 0 (CI0FE0)
6: CI1FE1: Filtered Timer Input 1 (CI1FE1)
7: ETIFP: External Trigger input (ETIFP)
Bit 7: Master-slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter control.
Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8
Counter register
Offset: 0x24, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Prescaler register
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
rw |
Counter auto reload register
Offset: 0x2C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAR
rw |
Channel 0 capture/compare value register
Offset: 0x34, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0VAL
rw |
Channel 1 capture/compare value register
Offset: 0x38, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH1VAL
rw |
Channel 2 capture/compare value register
Offset: 0x3C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH2VAL
rw |
Channel 3 capture/compare value register
Offset: 0x40, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH3VAL
rw |
DMA configuration register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMATC
rw |
DMATA
rw |
DMA transfer buffer register
Offset: 0x4C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMATB
rw |
0x40015400: General-purpose-timers
11/29 fields covered. Toggle Registers.
control register 1
Offset: 0x4, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MMC
rw |
DMA Interrupt enable register
Offset: 0xC, reset: 0x0000, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0IE
rw |
UPIE
rw |
interrupt flag register
Offset: 0x10, reset: 0x0000, access: read-write
1/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0OF
rw |
CH0IF
rw |
UPIF
rw |
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0G
w |
UPG
w |
Channel control register 0 ( (input mode)
Offset: 0x18, reset: 0x0000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0CAPFLT
rw |
CH0CAPPSC
rw |
CH0MS
rw |
Channel control register 2
Offset: 0x20, reset: 0x0000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0NP
rw |
CH0P
rw |
CH0EN
rw |
Counter register
Offset: 0x24, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Prescaler register
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
rw |
Counter auto reload register
Offset: 0x2C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAR
rw |
Channel 0 capture/compare value register
Offset: 0x34, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0VAL
rw |
0x40001800: General-purpose-timers
12/51 fields covered. Toggle Registers.
slave mode configuration register
Offset: 0x8, reset: 0x0000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSM
rw |
TRGS
rw |
SMC
rw |
DMA and interrupt enable register
Offset: 0xC, reset: 0x0000, access: read-write
1/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRGIE
rw |
CH1IE
rw |
CH0IE
rw |
UPIE
rw |
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRGG
w |
CH1G
w |
CH0G
w |
UPG
w |
Counter register
Offset: 0x24, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Prescaler register
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
rw |
Counter auto reload register
Offset: 0x2C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAR
rw |
Channel 0 capture/compare value register
Offset: 0x34, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0VAL
rw |
Channel 1 capture/compare value register
Offset: 0x38, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH1VAL
rw |
0x40001C00: General-purpose-timers
11/29 fields covered. Toggle Registers.
control register 1
Offset: 0x4, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MMC
rw |
DMA Interrupt enable register
Offset: 0xC, reset: 0x0000, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0IE
rw |
UPIE
rw |
interrupt flag register
Offset: 0x10, reset: 0x0000, access: read-write
1/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0OF
rw |
CH0IF
rw |
UPIF
rw |
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0G
w |
UPG
w |
Channel control register 0 ( (input mode)
Offset: 0x18, reset: 0x0000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0CAPFLT
rw |
CH0CAPPSC
rw |
CH0MS
rw |
Channel control register 2
Offset: 0x20, reset: 0x0000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0NP
rw |
CH0P
rw |
CH0EN
rw |
Counter register
Offset: 0x24, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Prescaler register
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
rw |
Counter auto reload register
Offset: 0x2C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAR
rw |
Channel 0 capture/compare value register
Offset: 0x34, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0VAL
rw |
0x40002000: General-purpose-timers
11/29 fields covered. Toggle Registers.
control register 1
Offset: 0x4, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MMC
rw |
DMA Interrupt enable register
Offset: 0xC, reset: 0x0000, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0IE
rw |
UPIE
rw |
interrupt flag register
Offset: 0x10, reset: 0x0000, access: read-write
1/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0OF
rw |
CH0IF
rw |
UPIF
rw |
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0G
w |
UPG
w |
Channel control register 0 ( (input mode)
Offset: 0x18, reset: 0x0000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0CAPFLT
rw |
CH0CAPPSC
rw |
CH0MS
rw |
Channel control register 2
Offset: 0x20, reset: 0x0000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0NP
rw |
CH0P
rw |
CH0EN
rw |
Counter register
Offset: 0x24, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Prescaler register
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
rw |
Counter auto reload register
Offset: 0x2C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAR
rw |
Channel 0 capture/compare value register
Offset: 0x34, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0VAL
rw |
0x40000400: General-purpose-timers
96/96 fields covered. Toggle Registers.
control register 1
Offset: 0x4, reset: 0x0000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TI0S
rw |
MMC
rw |
DMAS
rw |
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode control.
Allowed values:
0: Disabled: Slave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.
1: QuadratureDecoderMode0: Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.
2: QuadratureDecoderMode1: Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.
3: QuadratureDecoderMode2: Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.
4: RestartMode: Restart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: PauseMode: Pause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: EventMode: Event Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: ExternalClockMode: External Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITI0: Internal Trigger 0 (ITI0)
1: ITI1: Internal Trigger 1 (ITI1)
2: ITI2: Internal Trigger 2 (ITI2)
4: CI0F_ED: CI0 Edge Detector (CI0F_ED)
5: CI0FE0: Filtered Timer Input 0 (CI0FE0)
6: CI1FE1: Filtered Timer Input 1 (CI1FE1)
7: ETIFP: External Trigger input (ETIFP)
Bit 7: Master-slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter control.
Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8
Counter register
Offset: 0x24, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Prescaler register
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
rw |
Counter auto reload register
Offset: 0x2C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAR
rw |
Channel 0 capture/compare value register
Offset: 0x34, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0VAL
rw |
Channel 1 capture/compare value register
Offset: 0x38, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH1VAL
rw |
Channel 2 capture/compare value register
Offset: 0x3C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH2VAL
rw |
Channel 3 capture/compare value register
Offset: 0x40, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH3VAL
rw |
DMA configuration register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMATC
rw |
DMATA
rw |
DMA transfer buffer register
Offset: 0x4C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMATB
rw |
0x40000800: General-purpose-timers
96/96 fields covered. Toggle Registers.
control register 1
Offset: 0x4, reset: 0x0000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TI0S
rw |
MMC
rw |
DMAS
rw |
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode control.
Allowed values:
0: Disabled: Slave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.
1: QuadratureDecoderMode0: Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.
2: QuadratureDecoderMode1: Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.
3: QuadratureDecoderMode2: Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.
4: RestartMode: Restart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: PauseMode: Pause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: EventMode: Event Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: ExternalClockMode: External Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITI0: Internal Trigger 0 (ITI0)
1: ITI1: Internal Trigger 1 (ITI1)
2: ITI2: Internal Trigger 2 (ITI2)
4: CI0F_ED: CI0 Edge Detector (CI0F_ED)
5: CI0FE0: Filtered Timer Input 0 (CI0FE0)
6: CI1FE1: Filtered Timer Input 1 (CI1FE1)
7: ETIFP: External Trigger input (ETIFP)
Bit 7: Master-slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter control.
Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8
Counter register
Offset: 0x24, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Prescaler register
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
rw |
Counter auto reload register
Offset: 0x2C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAR
rw |
Channel 0 capture/compare value register
Offset: 0x34, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0VAL
rw |
Channel 1 capture/compare value register
Offset: 0x38, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH1VAL
rw |
Channel 2 capture/compare value register
Offset: 0x3C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH2VAL
rw |
Channel 3 capture/compare value register
Offset: 0x40, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH3VAL
rw |
DMA configuration register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMATC
rw |
DMATA
rw |
DMA transfer buffer register
Offset: 0x4C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMATB
rw |
0x40000C00: General-purpose-timers
96/96 fields covered. Toggle Registers.
control register 1
Offset: 0x4, reset: 0x0000, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TI0S
rw |
MMC
rw |
DMAS
rw |
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode control.
Allowed values:
0: Disabled: Slave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.
1: QuadratureDecoderMode0: Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.
2: QuadratureDecoderMode1: Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.
3: QuadratureDecoderMode2: Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.
4: RestartMode: Restart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: PauseMode: Pause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: EventMode: Event Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: ExternalClockMode: External Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITI0: Internal Trigger 0 (ITI0)
1: ITI1: Internal Trigger 1 (ITI1)
2: ITI2: Internal Trigger 2 (ITI2)
4: CI0F_ED: CI0 Edge Detector (CI0F_ED)
5: CI0FE0: Filtered Timer Input 0 (CI0FE0)
6: CI1FE1: Filtered Timer Input 1 (CI1FE1)
7: ETIFP: External Trigger input (ETIFP)
Bit 7: Master-slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter control.
Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8
Counter register
Offset: 0x24, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Prescaler register
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
rw |
Counter auto reload register
Offset: 0x2C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAR
rw |
Channel 0 capture/compare value register
Offset: 0x34, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0VAL
rw |
Channel 1 capture/compare value register
Offset: 0x38, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH1VAL
rw |
Channel 2 capture/compare value register
Offset: 0x3C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH2VAL
rw |
Channel 3 capture/compare value register
Offset: 0x40, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH3VAL
rw |
DMA configuration register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMATC
rw |
DMATA
rw |
DMA transfer buffer register
Offset: 0x4C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMATB
rw |
0x40001000: Basic-timers
13/13 fields covered. Toggle Registers.
control register 1
Offset: 0x4, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MMC
rw |
DMA/Interrupt enable register
Offset: 0xC, reset: 0x0000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UPDEN
rw |
UPIE
rw |
Interrupt flag register
Offset: 0x10, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UPIF
rw |
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UPG
w |
Counter register
Offset: 0x24, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Prescaler register
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
rw |
Counter auto reload register
Offset: 0x2C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAR
rw |
0x40001400: Basic-timers
13/13 fields covered. Toggle Registers.
control register 1
Offset: 0x4, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MMC
rw |
DMA/Interrupt enable register
Offset: 0xC, reset: 0x0000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UPDEN
rw |
UPIE
rw |
Interrupt flag register
Offset: 0x10, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UPIF
rw |
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UPG
w |
Counter register
Offset: 0x24, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Prescaler register
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
rw |
Counter auto reload register
Offset: 0x2C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAR
rw |
0x40013400: Advanced timer
127/127 fields covered. Toggle Registers.
control register 0
Offset: 0x0, reset: 0x0000, access: read-write
8/8 fields covered.
Bits 5-6: Center-aligned mode selection.
Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAlignedCountingDown: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAlignedCountingUp: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAlignedCountingUpDown: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.
control register 1
Offset: 0x4, reset: 0x0000, access: read-write
12/12 fields covered.
Bits 4-6: Master mode control.
Allowed values:
0: Reset: Use UPG bit from SWEVG register
1: Enable: Use CEN bit from CTL0 register
2: Update: Use the update event
3: CaptureComparePulse: The trigger output send a positive pulse when a capture or a compare match occurred in channel 0
4: CompareO0C: O0CPRE signal is used as trigger output
5: CompareO1C: O1CPRE signal is used as trigger output
6: CompareO2C: O2CPRE signal is used as trigger output
7: CompareO3C: O3CPRE signal is used as trigger output
slave mode configuration register
Offset: 0x8, reset: 0x0000, access: read-write
7/7 fields covered.
Bits 0-2: Slave mode control.
Allowed values:
0: Disabled: Slave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.
1: QuadratureDecoderMode0: Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.
2: QuadratureDecoderMode1: Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.
3: QuadratureDecoderMode2: Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.
4: RestartMode: Restart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: PauseMode: Pause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: EventMode: Event Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: ExternalClockMode: External Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.
Bits 4-6: Trigger selection.
Allowed values:
0: ITI0: Internal Trigger 0 (ITI0)
1: ITI1: Internal Trigger 1 (ITI1)
2: ITI2: Internal Trigger 2 (ITI2)
4: CI0F_ED: CI0 Edge Detector (CI0F_ED)
5: CI0FE0: Filtered Timer Input 0 (CI0FE0)
6: CI1FE1: Filtered Timer Input 1 (CI1FE1)
7: ETIFP: External Trigger input (ETIFP)
Bit 7: Master/Slave mode.
Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter control.
Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8
Channel control register 0 (input mode)
Offset: 0x18, reset: 0x0000, access: read-write
6/6 fields covered.
Bits 4-7: Channel 0 input capture filter control.
Allowed values:
0: NoFilter: Filter disabled. fSAMP=fDTS, N=1
1: TimerCk_N2: fSAMP=fTIMER_CK, N=2
2: TimerCk_N4: fSAMP=fTIMER_CK, N=4
3: TimerCk_N8: fSAMP=fTIMER_CK, N=8
4: FDTS_Div2_N6: fSAMP=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMP=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMP=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMP=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMP=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMP=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMP=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMP=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMP=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMP=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMP=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMP=fDTS/32, N=8
counter
Offset: 0x24, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
rw |
Counter auto-reload register
Offset: 0x2C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAR
rw |
Counter repetition register
Offset: 0x30, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CREP
rw |
Channel 0 capture/compare value register
Offset: 0x34, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0VAL
rw |
Channel 1 capture/compare value register
Offset: 0x38, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH1VAL
rw |
Channel 2 capture/compare value register
Offset: 0x3C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH2VAL
rw |
Channel 3 capture/compare value register
Offset: 0x40, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH3VAL
rw |
DMA configuration register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMATC
rw |
DMATA
rw |
DMA transfer buffer register
Offset: 0x4C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DMATB
rw |
0x40014c00: General-purpose-timers
12/51 fields covered. Toggle Registers.
slave mode configuration register
Offset: 0x8, reset: 0x0000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSM
rw |
TRGS
rw |
SMC
rw |
DMA and interrupt enable register
Offset: 0xC, reset: 0x0000, access: read-write
1/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRGIE
rw |
CH1IE
rw |
CH0IE
rw |
UPIE
rw |
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRGG
w |
CH1G
w |
CH0G
w |
UPG
w |
Counter register
Offset: 0x24, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Prescaler register
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
rw |
Counter auto reload register
Offset: 0x2C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAR
rw |
Channel 0 capture/compare value register
Offset: 0x34, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0VAL
rw |
Channel 1 capture/compare value register
Offset: 0x38, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH1VAL
rw |
0x40015000: General-purpose-timers
11/29 fields covered. Toggle Registers.
control register 1
Offset: 0x4, reset: 0x0000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MMC
rw |
DMA Interrupt enable register
Offset: 0xC, reset: 0x0000, access: read-write
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0IE
rw |
UPIE
rw |
interrupt flag register
Offset: 0x10, reset: 0x0000, access: read-write
1/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0OF
rw |
CH0IF
rw |
UPIF
rw |
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0G
w |
UPG
w |
Channel control register 0 ( (input mode)
Offset: 0x18, reset: 0x0000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0CAPFLT
rw |
CH0CAPPSC
rw |
CH0MS
rw |
Channel control register 2
Offset: 0x20, reset: 0x0000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0NP
rw |
CH0P
rw |
CH0EN
rw |
Counter register
Offset: 0x24, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CNT
rw |
Prescaler register
Offset: 0x28, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
rw |
Counter auto reload register
Offset: 0x2C, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAR
rw |
Channel 0 capture/compare value register
Offset: 0x34, reset: 0x0000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH0VAL
rw |
0x40016800: TFT-LCD interface
13/93 fields covered. Toggle Registers.
Synchronous pulse size register
Offset: 0x8, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HPSZ
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VPSZ
rw |
Back-porch size register
Offset: 0xC, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HBPSZ
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VBPSZ
rw |
Active size register
Offset: 0x10, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HASZ
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VASZ
rw |
Total size register
Offset: 0x14, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HTSZ
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VTSZ
rw |
Reload layer register
Offset: 0x24, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FBR
rw |
RQR
rw |
Background color register
Offset: 0x2C, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BVR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BVG
rw |
BVB
rw |
Interrupt enable register
Offset: 0x34, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LCRIE
rw |
TEIE
rw |
FEIE
rw |
LMIE
rw |
Interrupt flag register
Offset: 0x38, reset: 0x00000000, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LCRF
r |
TEF
r |
FEF
r |
LMF
r |
Interrupt flag clear register
Offset: 0x3C, reset: 0x00000000, access: write-only
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LCRC
w |
TEC
w |
FEC
w |
LMC
w |
Line mark register
Offset: 0x40, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LM
rw |
Current pixel position register
Offset: 0x44, reset: 0x00000000, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HPOS
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VPOS
r |
Status register
Offset: 0x48, reset: 0x0000000F, access: read-only
4/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HS
r |
VS
r |
HDE
r |
VDE
r |
Layer 0 control register
Offset: 0x84, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LUTEN
rw |
CKEYEN
rw |
LEN
rw |
Layer 0 horizontal position parameters register
Offset: 0x88, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WRP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WLP
rw |
Layer 0 vertical position parameters register
Offset: 0x8C, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WBP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WTP
rw |
Layer 0 color key register
Offset: 0x90, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CKEYR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CKEYG
rw |
CKEYB
rw |
Layer 0 packeted pixel format register
Offset: 0x94, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PPF
rw |
Layer 0 specified alpha register
Offset: 0x98, reset: 0x000000FF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SA
rw |
Layer 0 default color register
Offset: 0x9C, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DCA
rw |
DCR
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DCG
rw |
DCB
rw |
Layer 0 blending register
Offset: 0xA0, reset: 0x00000607, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ACF1
rw |
ACF2
rw |
Layer 0 frame base address register
Offset: 0xAC, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FBADD
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FBADD
rw |
Layer 0 frame line length register
Offset: 0xB0, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STDOFF
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FLL
rw |
Layer 0 frame total line number register
Offset: 0xB4, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FTLN
rw |
Layer 0 look up table register
Offset: 0xC4, reset: 0x00000000, access: write-only
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TADD
w |
TR
w |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TG
w |
TB
w |
Layer 1 control register
Offset: 0x104, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LUTEN
rw |
CKEYEN
rw |
LEN
rw |
Layer 1 horizontal position parameters register
Offset: 0x108, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WRP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WLP
rw |
Layer 1 vertical position parameters register
Offset: 0x10C, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WBP
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WTP
rw |
Layer 1 color key register
Offset: 0x110, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CKEYR
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CKEYG
rw |
CKEYB
rw |
Layer 1 packeted pixel format register
Offset: 0x114, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PPF
rw |
Layer 1 specified alpha register
Offset: 0x118, reset: 0x000000FF, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SA
rw |
Layer 1 default color register
Offset: 0x11C, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DCA
rw |
DCR
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DCG
rw |
DCB
rw |
Layer 1 blending register
Offset: 0x120, reset: 0x00000607, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ACF1
rw |
ACF2
rw |
Layer 1 frame base address register
Offset: 0x12C, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FBADD
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FBADD
rw |
Layer 1 frame line length register
Offset: 0x130, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STDOFF
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FLL
rw |
Layer 1 frame total line number register
Offset: 0x134, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FTLN
rw |
Layer 1 look up table register
Offset: 0x144, reset: 0x00000000, access: write-only
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TADD
w |
TR
w |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TG
w |
TB
w |
0x40004C00: Universal asynchronous receiver transmitter
6/38 fields covered. Toggle Registers.
Data register
Offset: 0x4, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Baud rate register
Offset: 0x8, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTDIV
rw |
FRADIV
rw |
Guard time and prescaler register
Offset: 0x18, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
rw |
0x40005000: Universal asynchronous receiver transmitter
6/38 fields covered. Toggle Registers.
Data register
Offset: 0x4, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Baud rate register
Offset: 0x8, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTDIV
rw |
FRADIV
rw |
Guard time and prescaler register
Offset: 0x18, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
rw |
0x40007800: Universal asynchronous receiver transmitter
6/38 fields covered. Toggle Registers.
Data register
Offset: 0x4, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Baud rate register
Offset: 0x8, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTDIV
rw |
FRADIV
rw |
Guard time and prescaler register
Offset: 0x18, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
rw |
0x40007C00: Universal asynchronous receiver transmitter
6/38 fields covered. Toggle Registers.
Data register
Offset: 0x4, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Baud rate register
Offset: 0x8, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTDIV
rw |
FRADIV
rw |
Guard time and prescaler register
Offset: 0x18, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSC
rw |
0x40013800: Universal synchronous asynchronous receiver transmitter
48/62 fields covered. Toggle Registers.
Data register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Baud rate register
Offset: 0x8, reset: 0x00000000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTDIV
rw |
FRADIV
rw |
Guard time and prescaler register
Offset: 0x18, reset: 0x00000000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GUAT
rw |
PSC
rw |
Receiver timeout register
Offset: 0x84, reset: 0x00000000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BL
rw |
RT
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RT
rw |
Status register 1
Offset: 0x88, reset: 0x00000000, access: Unspecified
1/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BSY
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EBF
w |
RTF
w |
0x40004400: Universal synchronous asynchronous receiver transmitter
48/62 fields covered. Toggle Registers.
Data register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Baud rate register
Offset: 0x8, reset: 0x00000000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTDIV
rw |
FRADIV
rw |
Guard time and prescaler register
Offset: 0x18, reset: 0x00000000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GUAT
rw |
PSC
rw |
Receiver timeout register
Offset: 0x84, reset: 0x00000000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BL
rw |
RT
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RT
rw |
Status register 1
Offset: 0x88, reset: 0x00000000, access: Unspecified
1/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BSY
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EBF
w |
RTF
w |
0x40004800: Universal synchronous asynchronous receiver transmitter
48/62 fields covered. Toggle Registers.
Data register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Baud rate register
Offset: 0x8, reset: 0x00000000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTDIV
rw |
FRADIV
rw |
Guard time and prescaler register
Offset: 0x18, reset: 0x00000000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GUAT
rw |
PSC
rw |
Receiver timeout register
Offset: 0x84, reset: 0x00000000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BL
rw |
RT
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RT
rw |
Status register 1
Offset: 0x88, reset: 0x00000000, access: Unspecified
1/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BSY
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EBF
w |
RTF
w |
0x40017000: Universal synchronous asynchronous receiver transmitter
48/62 fields covered. Toggle Registers.
Data register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA
rw |
Baud rate register
Offset: 0x8, reset: 0x00000000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTDIV
rw |
FRADIV
rw |
Guard time and prescaler register
Offset: 0x18, reset: 0x00000000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GUAT
rw |
PSC
rw |
Receiver timeout register
Offset: 0x84, reset: 0x00000000, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BL
rw |
RT
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RT
rw |
Status register 1
Offset: 0x88, reset: 0x00000000, access: Unspecified
1/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BSY
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EBF
w |
RTF
w |
0x50000800: USB on the go full speed device
36/200 fields covered. Toggle Registers.
device configuration register (DCFG)
Offset: 0x0, reset: 0x00000000, access: read-write
0/4 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EOPFT
rw |
DAR
rw |
NZLSOH
rw |
DS
rw |
device OUT endpoint common interrupt enable register (DOEPINTEN)
Offset: 0x14, reset: 0x00000000, access: read-write
0/5 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BTBSTPEN
rw |
EPRXFOVREN
rw |
STPFEN
rw |
EPDISEN
rw |
TFEN
rw |
device all endpoints interrupt register (DAEPINT)
Offset: 0x18, reset: 0x00000000, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OEPITB
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IEPITB
r |
Device all endpoints interrupt enable register (DAEPINTEN)
Offset: 0x1C, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
OEPIE
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IEPIE
rw |
device VBUS discharge time register
Offset: 0x28, reset: 0x000017D7, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DVBUSDT
rw |
device VBUS pulsing time register
Offset: 0x2C, reset: 0x000005B8, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DVBUSPT
rw |
device IN endpoint FIFO empty interrupt enable register
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IEPTXFEIE
rw |
device IN endpoint-0 transfer length register
Offset: 0x110, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PCNT
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TLEN
rw |
device IN endpoint 0 transmit FIFO status register
Offset: 0x118, reset: 0x00000200, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IEPTFS
r |
device in endpoint-1 control register
Offset: 0x120, reset: 0x00000000, access: Unspecified
2/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EPEN
rw |
EPD
rw |
SD1PID_SODDFRM
w |
SD0PID_SEVENFRM
w |
SNAK
w |
CNAK
w |
TXFNUM
rw |
STALL
rw |
EPTYPE
rw |
NAKS
r |
EOFRM_DPID
r |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPACT
rw |
MPL
rw |
device IN endpoint-1 transfer length register
Offset: 0x130, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PCNT
rw |
TLEN
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TLEN
rw |
device IN endpoint 1 transmit FIFO status register
Offset: 0x138, reset: 0x00000200, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IEPTFS
r |
device endpoint-2 control register
Offset: 0x140, reset: 0x00000000, access: Unspecified
2/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EPEN
rw |
EPD
rw |
SD1PID_SODDFRM
w |
SD0PID_SEVENFRM
w |
SNAK
w |
CNAK
w |
TXFNUM
rw |
STALL
rw |
EPTYPE
rw |
NAKS
r |
EOFRM_DPID
r |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPACT
rw |
MPL
rw |
device IN endpoint-2 transfer length register
Offset: 0x150, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PCNT
rw |
TLEN
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TLEN
rw |
device IN endpoint 2 transmit FIFO status register
Offset: 0x158, reset: 0x00000200, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IEPTFS
r |
device endpoint-3 control register
Offset: 0x160, reset: 0x00000000, access: Unspecified
2/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EPEN
rw |
EPD
rw |
SD1PID_SODDFRM
w |
SD0PID_SEVENFRM
w |
SNAK
w |
CNAK
w |
TXFNUM
rw |
STALL
rw |
EPTYPE
rw |
NAKS
r |
EOFRM_DPID
r |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPACT
rw |
MPL
rw |
device IN endpoint-3 transfer length register
Offset: 0x170, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PCNT
rw |
TLEN
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TLEN
rw |
device IN endpoint 3 transmit FIFO status register
Offset: 0x178, reset: 0x00000200, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IEPTFS
r |
device OUT endpoint-0 transfer length register
Offset: 0x310, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STPCNT
rw |
PCNT
rw |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TLEN
rw |
device endpoint-1 control register
Offset: 0x320, reset: 0x00000000, access: Unspecified
2/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EPEN
rw |
EPD
rw |
SD1PID_SODDFRM
w |
SD0PID_SEVENFRM
w |
SNAK
w |
CNAK
w |
STALL
rw |
SNOOP
rw |
EPTYPE
rw |
NAKS
r |
EOFRM_DPID
r |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPACT
rw |
MPL
rw |
device OUT endpoint-1 transfer length register
Offset: 0x330, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STPCNT_RXDPID
rw |
PCNT
rw |
TLEN
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TLEN
rw |
device endpoint-2 control register
Offset: 0x340, reset: 0x00000000, access: Unspecified
2/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EPEN
rw |
EPD
rw |
SD1PID_SODDFRM
w |
SD0PID_SEVENFRM
w |
SNAK
w |
CNAK
w |
STALL
rw |
SNOOP
rw |
EPTYPE
rw |
NAKS
r |
EOFRM_DPID
r |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPACT
rw |
MPL
rw |
device OUT endpoint-2 transfer length register
Offset: 0x350, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STPCNT_RXDPID
rw |
PCNT
rw |
TLEN
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TLEN
rw |
device endpoint-3 control register
Offset: 0x360, reset: 0x00000000, access: Unspecified
2/13 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
EPEN
rw |
EPD
rw |
SD1PID_SODDFRM
w |
SD0PID_SEVENFRM
w |
SNAK
w |
CNAK
w |
STALL
rw |
SNOOP
rw |
EPTYPE
rw |
NAKS
r |
EOFRM_DPID
r |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPACT
rw |
MPL
rw |
device OUT endpoint-3 transfer length register
Offset: 0x370, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STPCNT_RXDPID
rw |
PCNT
rw |
TLEN
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TLEN
rw |
0x50000000: USB full speed global registers
39/120 fields covered. Toggle Registers.
Global AHB control and status register (USBFS_GAHBCS)
Offset: 0x8, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PTXFTH
rw |
TXFTH
rw |
GINTEN
rw |
Global interrupt flag register (USBFS_GINTF)
Offset: 0x14, reset: 0x04000021, access: Unspecified
11/25 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WKUPIF
rw |
SESIF
rw |
DISCIF
rw |
IDPSC
rw |
PTXFEIF
r |
HCIF
r |
HPIF
r |
PXNCIF_ISOONCIF
rw |
ISOINCIF
rw |
OEPIF
r |
IEPIF
r |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EOPFIF
rw |
ISOOPDIF
rw |
ENUMF
rw |
RST
rw |
SP
rw |
ESP
rw |
GONAK
r |
GNPINAK
r |
NPTXFEIF
r |
RXFNEIF
r |
SOF
rw |
OTGIF
r |
MFIF
rw |
COPM
r |
Global interrupt enable register (USBFS_GINTEN)
Offset: 0x18, reset: 0x00000000, access: Unspecified
1/24 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
WKUPIE
rw |
SESIE
rw |
DISCIE
rw |
IDPSCIE
rw |
PTXFEIE
rw |
HCIE
rw |
HPIE
r |
PXNCIE_ISOONCIE
rw |
ISOINCIE
rw |
OEPIE
rw |
IEPIE
rw |
|||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EOPFIE
rw |
ISOOPDIE
rw |
ENUMFIE
rw |
RSTIE
rw |
SPIE
rw |
ESPIE
rw |
GONAKIE
rw |
GNPINAKIE
rw |
NPTXFEIE
rw |
RXFNEIE
rw |
SOFIE
rw |
OTGIE
rw |
MFIE
rw |
Global Receive FIFO size register (USBFS_GRFLEN)
Offset: 0x24, reset: 0x00000200, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RXFD
rw |
Device IN endpoint 0 transmit FIFO length (Device mode)
Offset: 0x28, reset: 0x02000200, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IEP0TXFD
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IEP0TXRSAR
rw |
Host non-periodic transmit FIFO/queue status register (HNPTFQSTAT)
Offset: 0x2C, reset: 0x00080200, access: read-only
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NPTXRQTOP
r |
NPTXRQS
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NPTXFS
r |
core ID register
Offset: 0x3C, reset: 0x00001000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CID
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CID
rw |
Host periodic transmit FIFO length register (HPTFLEN)
Offset: 0x100, reset: 0x02000600, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
HPTXFD
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HPTXFSAR
rw |
device IN endpoint transmit FIFO size register (DIEP1TFLEN)
Offset: 0x104, reset: 0x02000400, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IEPTXFD
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IEPTXRSAR
rw |
device IN endpoint transmit FIFO size register (DIEP2TFLEN)
Offset: 0x108, reset: 0x02000400, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IEPTXFD
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IEPTXRSAR
rw |
device IN endpoint transmit FIFO size register (FS_DIEP3TXFLEN)
Offset: 0x10C, reset: 0x02000400, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
IEPTXFD
rw |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IEPTXRSAR
rw |
0x50000400: USB on the go full speed host
10/261 fields covered. Toggle Registers.
host configuration register (HCTL)
Offset: 0x0, reset: 0x00000000, access: Unspecified
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLKSEL
rw |
Host frame interval register
Offset: 0x4, reset: 0x0000BB80, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FRI
rw |
OTG_FS host frame number/frame time remaining register (HFINFR)
Offset: 0x8, reset: 0xBB800000, access: read-only
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
FRT
r |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FRNUM
r |
Host periodic transmit FIFO/queue status register (HPTFQSTAT)
Offset: 0x10, reset: 0x00080200, access: Unspecified
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PTXREQT
r |
PTXREQS
r |
||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PTXFS
r |
Host all channels interrupt register
Offset: 0x14, reset: 0x00000000, access: read-only
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HACHINT
r |
host all channels interrupt mask register
Offset: 0x18, reset: 0x00000000, access: read-write
0/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CINTEN
rw |
host channel-0 transfer length register
Offset: 0x110, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DPID
rw |
PCNT
rw |
TLEN
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TLEN
rw |
host channel-1 transfer length register
Offset: 0x130, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DPID
rw |
PCNT
rw |
TLEN
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TLEN
rw |
host channel-2 transfer length register
Offset: 0x150, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DPID
rw |
PCNT
rw |
TLEN
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TLEN
rw |
host channel-3 transfer length register
Offset: 0x170, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DPID
rw |
PCNT
rw |
TLEN
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TLEN
rw |
host channel-4 transfer length register
Offset: 0x190, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DPID
rw |
PCNT
rw |
TLEN
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TLEN
rw |
host channel-5 transfer length register
Offset: 0x1B0, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DPID
rw |
PCNT
rw |
TLEN
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TLEN
rw |
host channel-6 transfer length register
Offset: 0x1D0, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DPID
rw |
PCNT
rw |
TLEN
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TLEN
rw |
host channel-7 transfer length register
Offset: 0x1F0, reset: 0x00000000, access: read-write
0/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DPID
rw |
PCNT
rw |
TLEN
rw |
|||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TLEN
rw |
0x50000E00: USB on the go full speed
0/2 fields covered. Toggle Registers.
power and clock gating control register (PWRCLKCTL)
Offset: 0x0, reset: 0x00000000, access: read-write
0/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SHCLK
rw |
SUCLK
rw |
0x40002C00: Window watchdog timer
6/6 fields covered. Toggle Registers.
Control register
Offset: 0x0, reset: 0x0000007F, access: read-write
2/2 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WDGTEN
rw |
CNT
rw |
Configuration register
Offset: 0x4, reset: 0x0000007F, access: read-write
3/3 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EWIE
rw |
PSC
rw |
WIN
rw |
Status register
Offset: 0x8, reset: 0x00000000, access: read-write
1/1 fields covered.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EWIF
rw |