Overall: 2428/5893 fields covered

ADC0

0x40012400: Analog to digital converter

86/87 fields covered. Toggle Registers.

STAT

status register

Offset: 0x0, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRC
rw 		STIC
rw 		EOIC
rw 		EOC
rw 		WDE
rw
Toggle Fields.

WDE

Bit 0: Analog watchdog event flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC

Bit 1: End of group conversion flag.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

EOIC

Bit 2: End of inserted group conversion flag.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

STIC

Bit 3: Start flag of inserted channel group.

Allowed values:
0: NotStarted: No inserted channel group conversion started
1: Started: Inserted channel group conversion has started

STRC

Bit 4: Start flag of regular channel group.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

CTL0

control register 0

Offset: 0x4, reset: 0x00000000, access: read-write

12/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RWDEN
rw 		IWDEN
rw 		SYNCM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISNUM
rw 		DISIC
rw 		DISRC
rw 		ICA
rw 		WDSC
rw 		SM
rw 		EOICIE
rw 		WDEIE
rw 		EOCIE
rw 		WDCHSEL
rw
Toggle Fields.

WDCHSEL

Bits 0-4: Analog watchdog channel select.

Allowed values: 0-18

EOCIE

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set

WDEIE

Bit 6: Interrupt enable for WDE.

Allowed values:
0: Disabled: WDE interrupt disabled
1: Enabled: WDE interrupt enabled. An interrupt is generated when the WDE bit is set

EOICIE

Bit 7: Interrupt enable for EOIC.

Allowed values:
0: Disabled: EOIC interrupt disabled
1: Enabled: EOIC interrupt enabled. An interrupt is generated when the EOIC bit is set

SM

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

WDSC

Bit 9: When in scan mode, analog watchdog is effective on a single channel.

Allowed values:
0: All: Analog watchdog enabled on all channels
1: Single: Analog watchdog enabled on a single channel

ICA

Bit 10: Inserted channel group convert automatically.

Allowed values:
0: Disabled: Automatic inserted group conversion disabled
1: Enabled: Automatic inserted group conversion enabled

DISRC

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

DISIC

Bit 12: Discontinuous mode on inserted channels.

Allowed values:
0: Disabled: Discontinuous mode on inserted channels disabled
1: Enabled: Discontinuous mode on inserted channels enabled

DISNUM

Bits 13-15: Number of conversions in discontinuous mode.

Allowed values: 0-7

SYNCM

Bits 16-18: sync mode selection.

IWDEN

Bit 22: Inserted channel analog watchdog enable.

Allowed values:
0: Disabled: Analog watchdog disabled on inserted channels
1: Enabled: Analog watchdog enabled on inserted channels

RWDEN

Bit 23: Regular channel analog watchdog enable.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

CTL1

control register 1

Offset: 0x8, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSVREN
rw 		SWRCST
rw 		SWICST
rw 		ETERC
rw 		ETSRC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETSIC
rw 		DAL
rw 		DMA
rw 		RSTCLB
rw 		CLB
rw 		CTN
rw 		ADCON
rw
Toggle Fields.

ADCON

Bit 0: ADC on.

Allowed values:
0: Disabled: Disable ADC conversion/calibration and go to power down mode
1: Enabled: Enable ADC and to start conversion

CTN

Bit 1: Continuous mode.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

CLB

Bit 2: ADC calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

RSTCLB

Bit 3: Reset calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

DMA

Bit 8: DMA request enable.

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

DAL

Bit 11: Data alignment.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

ETSIC

Bits 12-14: External trigger select for inserted channel.

Allowed values:
0: Timer0Trgo: Timer 0 TRGO event
1: Timer0Ch3: Timer 0 channel 3 event
2: Timer1Trgo: Timer 1 TRGO event
3: Timer1Ch0: Timer 1 channel 0 event
4: Timer2Ch2: Timer 2 channel 3 event
5: Timer14Trgo: Timer 14 TRGO event
6: Exti15: EXTI line 15
7: Swicst: SWICST

ETSRC

Bits 17-19: External trigger select for regular channel.

Allowed values:
0: Timer0Ch0: Timer 0 channel 0 event
1: Timer0Ch1: Timer 0 channel 1 event
2: Timer0Ch2: Timer 0 channel 2 event
3: Timer1Ch1: Timer 1 channel 1 event
4: Timer2Trgo: Timer 2 TRGO event
5: Timer14Ch0: Timer 14 channel 0 event
6: Exti11: EXTI line 11
7: Swrcst: SWRCST

ETERC

Bit 20: External trigger enable for regular channel.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

SWICST

Bit 21: Start on inserted channel.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of inserted channels

SWRCST

Bit 22: Start on regular channel.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of regular channels

TSVREN

Bit 23: Channel 16 and 17 enable of ADC0.

Allowed values:
0: Disabled: Channel 16 and 17 disabled
1: Enabled: Channel 16 and 17 enabled

SAMPT0

Sample time register 0

Offset: 0xC, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT17
rw 		SPT16
rw 		SPT15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT15
rw 		SPT14
rw 		SPT13
rw 		SPT12
rw 		SPT11
rw 		SPT10
rw
Toggle Fields.

SPT10

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT11

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT12

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT13

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT14

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT15

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT16

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT17

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SAMPT1

Sample time register 1

Offset: 0x10, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT9
rw 		SPT8
rw 		SPT7
rw 		SPT6
rw 		SPT5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT5
rw 		SPT4
rw 		SPT3
rw 		SPT2
rw 		SPT1
rw 		SPT0
rw
Toggle Fields.

SPT0

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT1

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT2

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT3

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT4

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT5

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT6

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT7

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT8

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT9

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

IOFF0

Inserted channel data offset register 0

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 0.

Allowed values: 0-4095

IOFF1

Inserted channel data offset register 1

Offset: 0x18, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 1.

Allowed values: 0-4095

IOFF2

Inserted channel data offset register 2

Offset: 0x1C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 2.

Allowed values: 0-4095

IOFF3

Inserted channel data offset register 3

Offset: 0x20, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 3.

Allowed values: 0-4095

WDHT

watchdog higher threshold register

Offset: 0x24, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDHT
rw
Toggle Fields.

WDHT

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0-4095

WDLT

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDLT
rw
Toggle Fields.

WDLT

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0-4095

RSQ0

regular sequence register 0

Offset: 0x2C, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RL
rw 		RSQ15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ15
rw 		RSQ14
rw 		RSQ13
rw 		RSQ12
rw
Toggle Fields.

RSQ12

Bits 0-4: 13th conversion in regular sequence.

Allowed values: 0-18

RSQ13

Bits 5-9: 14th conversion in regular sequence.

Allowed values: 0-18

RSQ14

Bits 10-14: 15th conversion in regular sequence.

Allowed values: 0-18

RSQ15

Bits 15-19: 16th conversion in regular sequence.

Allowed values: 0-18

RL

Bits 20-23: Regular channel group length.

Allowed values: 0-15

RSQ1

regular sequence register 1

Offset: 0x30, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ11
rw 		RSQ10
rw 		RSQ9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ9
rw 		RSQ8
rw 		RSQ7
rw 		RSQ6
rw
Toggle Fields.

RSQ6

Bits 0-4: 7th conversion in regular sequence.

Allowed values: 0-18

RSQ7

Bits 5-9: 8th conversion in regular sequence.

Allowed values: 0-18

RSQ8

Bits 10-14: 9th conversion in regular sequence.

Allowed values: 0-18

RSQ9

Bits 15-19: 10th conversion in regular sequence.

Allowed values: 0-18

RSQ10

Bits 20-24: 11th conversion in regular sequence.

Allowed values: 0-18

RSQ11

Bits 25-29: 12th conversion in regular sequence.

Allowed values: 0-18

RSQ2

regular sequence register 2

Offset: 0x34, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ5
rw 		RSQ4
rw 		RSQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ3
rw 		RSQ2
rw 		RSQ1
rw 		RSQ0
rw
Toggle Fields.

RSQ0

Bits 0-4: 1st conversion in regular sequence.

Allowed values: 0-18

RSQ1

Bits 5-9: 2nd conversion in regular sequence.

Allowed values: 0-18

RSQ2

Bits 10-14: 3rd conversion in regular sequence.

Allowed values: 0-18

RSQ3

Bits 15-19: 4th conversion in regular sequence.

Allowed values: 0-18

RSQ4

Bits 20-24: 5th conversion in regular sequence.

Allowed values: 0-18

RSQ5

Bits 25-29: 6th conversion in regular sequence.

Allowed values: 0-18

ISQ

Inserted sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IL
rw 		ISQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISQ3
rw 		ISQ2
rw 		ISQ1
rw 		ISQ0
rw
Toggle Fields.

ISQ0

Bits 0-4: 1st conversion in inserted sequence.

Allowed values: 0-18

ISQ1

Bits 5-9: 2nd conversion in inserted sequence.

Allowed values: 0-18

ISQ2

Bits 10-14: 3rd conversion in inserted sequence.

Allowed values: 0-18

ISQ3

Bits 15-19: 4th conversion in inserted sequence.

Allowed values: 0-18

IL

Bits 20-21: Inserted channel group length.

Allowed values: 0-3

IDATA0

Inserted data register 0

Offset: 0x3C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

IDATA1

Inserted data register 1

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

IDATA2

Inserted data register 2

Offset: 0x44, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

IDATA3

Inserted data register 3

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

RDATA

regular data register

Offset: 0x4C, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADC1RDTR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle Fields.

RDATA

Bits 0-15: Regular channel data.

Allowed values: 0-65535

ADC1RDTR

Bits 16-31: ADCegular channel data.

OVSAMPCTL

Oversample control register

Offset: 0x80, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRES
rw 		TOVS
rw 		OVSS
rw 		OVSR
rw 		OVSEN
rw
Toggle Fields.

OVSEN

Bit 0: Oversampling Enable.

Allowed values:
0: Disabled: Oversampling disabled
1: Enabled: Oversampling enabled

OVSR

Bits 2-4: Oversampling ratio.

Allowed values:
0: Times2: 2x
1: Times4: 4x
2: Times8: 8x
3: Times16: 16x
4: Times32: 32x
5: Times64: 64x
6: Times128: 128x
7: Times256: 256x

OVSS

Bits 5-8: Oversampling shift.

Allowed values: 0-8

TOVS

Bit 9: Triggered Oversampling.

Allowed values:
0: Consecutive: All oversampled conversions are done consecutively
1: Individual: Each oversampled conversion needs a trigger

DRES

Bits 12-13: ADC resolution.

Allowed values:
0: Bits12: 12 bit resolution
1: Bits10: 10 bit resolution
2: Bits8: 8 bit resolution
3: Bits6: 6 bit resolution

ADC1

0x40012800: Analog to digital converter

85/86 fields covered. Toggle Registers.

STAT

status register

Offset: 0x0, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRC
rw 		STIC
rw 		EOIC
rw 		EOC
rw 		WDE
rw
Toggle Fields.

WDE

Bit 0: Analog watchdog event flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC

Bit 1: End of group conversion flag.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

EOIC

Bit 2: End of inserted group conversion flag.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

STIC

Bit 3: Start flag of inserted channel group.

Allowed values:
0: NotStarted: No inserted channel group conversion started
1: Started: Inserted channel group conversion has started

STRC

Bit 4: Start flag of regular channel group.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

CTL0

control register 0

Offset: 0x4, reset: 0x00000000, access: read-write

12/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RWDEN
rw 		IWDEN
rw 		SYNCM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISNUM
rw 		DISIC
rw 		DISRC
rw 		ICA
rw 		WDSC
rw 		SM
rw 		EOICIE
rw 		WDEIE
rw 		EOCIE
rw 		WDCHSEL
rw
Toggle Fields.

WDCHSEL

Bits 0-4: Analog watchdog channel select.

Allowed values: 0-18

EOCIE

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set

WDEIE

Bit 6: Interrupt enable for WDE.

Allowed values:
0: Disabled: WDE interrupt disabled
1: Enabled: WDE interrupt enabled. An interrupt is generated when the WDE bit is set

EOICIE

Bit 7: Interrupt enable for EOIC.

Allowed values:
0: Disabled: EOIC interrupt disabled
1: Enabled: EOIC interrupt enabled. An interrupt is generated when the EOIC bit is set

SM

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

WDSC

Bit 9: When in scan mode, analog watchdog is effective on a single channel.

Allowed values:
0: All: Analog watchdog enabled on all channels
1: Single: Analog watchdog enabled on a single channel

ICA

Bit 10: Inserted channel group convert automatically.

Allowed values:
0: Disabled: Automatic inserted group conversion disabled
1: Enabled: Automatic inserted group conversion enabled

DISRC

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

DISIC

Bit 12: Discontinuous mode on inserted channels.

Allowed values:
0: Disabled: Discontinuous mode on inserted channels disabled
1: Enabled: Discontinuous mode on inserted channels enabled

DISNUM

Bits 13-15: Number of conversions in discontinuous mode.

Allowed values: 0-7

SYNCM

Bits 16-18: sync mode selection.

IWDEN

Bit 22: Inserted channel analog watchdog enable.

Allowed values:
0: Disabled: Analog watchdog disabled on inserted channels
1: Enabled: Analog watchdog enabled on inserted channels

RWDEN

Bit 23: Regular channel analog watchdog enable.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

CTL1

control register 1

Offset: 0x8, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSVREN
rw 		SWRCST
rw 		SWICST
rw 		ETERC
rw 		ETSRC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETSIC
rw 		DAL
rw 		DMA
rw 		RSTCLB
rw 		CLB
rw 		CTN
rw 		ADCON
rw
Toggle Fields.

ADCON

Bit 0: ADC on.

Allowed values:
0: Disabled: Disable ADC conversion/calibration and go to power down mode
1: Enabled: Enable ADC and to start conversion

CTN

Bit 1: Continuous mode.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

CLB

Bit 2: ADC calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

RSTCLB

Bit 3: Reset calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

DMA

Bit 8: DMA request enable.

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

DAL

Bit 11: Data alignment.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

ETSIC

Bits 12-14: External trigger select for inserted channel.

Allowed values:
0: Timer0Trgo: Timer 0 TRGO event
1: Timer0Ch3: Timer 0 channel 3 event
2: Timer1Trgo: Timer 1 TRGO event
3: Timer1Ch0: Timer 1 channel 0 event
4: Timer2Ch2: Timer 2 channel 3 event
5: Timer14Trgo: Timer 14 TRGO event
6: Exti15: EXTI line 15
7: Swicst: SWICST

ETSRC

Bits 17-19: External trigger select for regular channel.

Allowed values:
0: Timer0Ch0: Timer 0 channel 0 event
1: Timer0Ch1: Timer 0 channel 1 event
2: Timer0Ch2: Timer 0 channel 2 event
3: Timer1Ch1: Timer 1 channel 1 event
4: Timer2Trgo: Timer 2 TRGO event
5: Timer14Ch0: Timer 14 channel 0 event
6: Exti11: EXTI line 11
7: Swrcst: SWRCST

ETERC

Bit 20: External trigger enable for regular channel.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

SWICST

Bit 21: Start on inserted channel.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of inserted channels

SWRCST

Bit 22: Start on regular channel.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of regular channels

TSVREN

Bit 23: Channel 16 and 17 enable of ADC0.

Allowed values:
0: Disabled: Channel 16 and 17 disabled
1: Enabled: Channel 16 and 17 enabled

SAMPT0

Sample time register 0

Offset: 0xC, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT17
rw 		SPT16
rw 		SPT15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT15
rw 		SPT14
rw 		SPT13
rw 		SPT12
rw 		SPT11
rw 		SPT10
rw
Toggle Fields.

SPT10

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT11

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT12

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT13

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT14

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT15

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT16

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT17

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SAMPT1

Sample time register 1

Offset: 0x10, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT9
rw 		SPT8
rw 		SPT7
rw 		SPT6
rw 		SPT5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT5
rw 		SPT4
rw 		SPT3
rw 		SPT2
rw 		SPT1
rw 		SPT0
rw
Toggle Fields.

SPT0

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT1

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT2

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT3

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT4

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT5

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT6

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT7

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT8

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT9

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

IOFF0

Inserted channel data offset register 0

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 0.

Allowed values: 0-4095

IOFF1

Inserted channel data offset register 1

Offset: 0x18, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 1.

Allowed values: 0-4095

IOFF2

Inserted channel data offset register 2

Offset: 0x1C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 2.

Allowed values: 0-4095

IOFF3

Inserted channel data offset register 3

Offset: 0x20, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 3.

Allowed values: 0-4095

WDHT

watchdog higher threshold register

Offset: 0x24, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDHT
rw
Toggle Fields.

WDHT

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0-4095

WDLT

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDLT
rw
Toggle Fields.

WDLT

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0-4095

RSQ0

regular sequence register 0

Offset: 0x2C, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RL
rw 		RSQ15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ15
rw 		RSQ14
rw 		RSQ13
rw 		RSQ12
rw
Toggle Fields.

RSQ12

Bits 0-4: 13th conversion in regular sequence.

Allowed values: 0-18

RSQ13

Bits 5-9: 14th conversion in regular sequence.

Allowed values: 0-18

RSQ14

Bits 10-14: 15th conversion in regular sequence.

Allowed values: 0-18

RSQ15

Bits 15-19: 16th conversion in regular sequence.

Allowed values: 0-18

RL

Bits 20-23: Regular channel group length.

Allowed values: 0-15

RSQ1

regular sequence register 1

Offset: 0x30, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ11
rw 		RSQ10
rw 		RSQ9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ9
rw 		RSQ8
rw 		RSQ7
rw 		RSQ6
rw
Toggle Fields.

RSQ6

Bits 0-4: 7th conversion in regular sequence.

Allowed values: 0-18

RSQ7

Bits 5-9: 8th conversion in regular sequence.

Allowed values: 0-18

RSQ8

Bits 10-14: 9th conversion in regular sequence.

Allowed values: 0-18

RSQ9

Bits 15-19: 10th conversion in regular sequence.

Allowed values: 0-18

RSQ10

Bits 20-24: 11th conversion in regular sequence.

Allowed values: 0-18

RSQ11

Bits 25-29: 12th conversion in regular sequence.

Allowed values: 0-18

RSQ2

regular sequence register 2

Offset: 0x34, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ5
rw 		RSQ4
rw 		RSQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ3
rw 		RSQ2
rw 		RSQ1
rw 		RSQ0
rw
Toggle Fields.

RSQ0

Bits 0-4: 1st conversion in regular sequence.

Allowed values: 0-18

RSQ1

Bits 5-9: 2nd conversion in regular sequence.

Allowed values: 0-18

RSQ2

Bits 10-14: 3rd conversion in regular sequence.

Allowed values: 0-18

RSQ3

Bits 15-19: 4th conversion in regular sequence.

Allowed values: 0-18

RSQ4

Bits 20-24: 5th conversion in regular sequence.

Allowed values: 0-18

RSQ5

Bits 25-29: 6th conversion in regular sequence.

Allowed values: 0-18

ISQ

Inserted sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IL
rw 		ISQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISQ3
rw 		ISQ2
rw 		ISQ1
rw 		ISQ0
rw
Toggle Fields.

ISQ0

Bits 0-4: 1st conversion in inserted sequence.

Allowed values: 0-18

ISQ1

Bits 5-9: 2nd conversion in inserted sequence.

Allowed values: 0-18

ISQ2

Bits 10-14: 3rd conversion in inserted sequence.

Allowed values: 0-18

ISQ3

Bits 15-19: 4th conversion in inserted sequence.

Allowed values: 0-18

IL

Bits 20-21: Inserted channel group length.

Allowed values: 0-3

IDATA0

Inserted data register 0

Offset: 0x3C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

IDATA1

Inserted data register 1

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

IDATA2

Inserted data register 2

Offset: 0x44, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

IDATA3

Inserted data register 3

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

RDATA

regular data register

Offset: 0x4C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle Fields.

RDATA

Bits 0-15: Regular channel data.

Allowed values: 0-65535

OVSAMPCTL

Oversample control register

Offset: 0x80, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRES
rw 		TOVS
rw 		OVSS
rw 		OVSR
rw 		OVSEN
rw
Toggle Fields.

OVSEN

Bit 0: Oversampling Enable.

Allowed values:
0: Disabled: Oversampling disabled
1: Enabled: Oversampling enabled

OVSR

Bits 2-4: Oversampling ratio.

Allowed values:
0: Times2: 2x
1: Times4: 4x
2: Times8: 8x
3: Times16: 16x
4: Times32: 32x
5: Times64: 64x
6: Times128: 128x
7: Times256: 256x

OVSS

Bits 5-8: Oversampling shift.

Allowed values: 0-8

TOVS

Bit 9: Triggered Oversampling.

Allowed values:
0: Consecutive: All oversampled conversions are done consecutively
1: Individual: Each oversampled conversion needs a trigger

DRES

Bits 12-13: ADC resolution.

Allowed values:
0: Bits12: 12 bit resolution
1: Bits10: 10 bit resolution
2: Bits8: 8 bit resolution
3: Bits6: 6 bit resolution

ADC2

0x40013C00: Analog to digital converter

85/86 fields covered. Toggle Registers.

STAT

status register

Offset: 0x0, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STRC
rw 		STIC
rw 		EOIC
rw 		EOC
rw 		WDE
rw
Toggle Fields.

WDE

Bit 0: Analog watchdog event flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

EOC

Bit 1: End of group conversion flag.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

EOIC

Bit 2: End of inserted group conversion flag.

Allowed values:
0: NotComplete: Conversion is not complete
1: Complete: Conversion complete

STIC

Bit 3: Start flag of inserted channel group.

Allowed values:
0: NotStarted: No inserted channel group conversion started
1: Started: Inserted channel group conversion has started

STRC

Bit 4: Start flag of regular channel group.

Allowed values:
0: NotStarted: No regular channel conversion started
1: Started: Regular channel conversion has started

CTL0

control register 0

Offset: 0x4, reset: 0x00000000, access: read-write

12/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RWDEN
rw 		IWDEN
rw 		SYNCM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISNUM
rw 		DISIC
rw 		DISRC
rw 		ICA
rw 		WDSC
rw 		SM
rw 		EOICIE
rw 		WDEIE
rw 		EOCIE
rw 		WDCHSEL
rw
Toggle Fields.

WDCHSEL

Bits 0-4: Analog watchdog channel select.

Allowed values: 0-18

EOCIE

Bit 5: Interrupt enable for EOC.

Allowed values:
0: Disabled: EOC interrupt disabled
1: Enabled: EOC interrupt enabled. An interrupt is generated when the EOC bit is set

WDEIE

Bit 6: Interrupt enable for WDE.

Allowed values:
0: Disabled: WDE interrupt disabled
1: Enabled: WDE interrupt enabled. An interrupt is generated when the WDE bit is set

EOICIE

Bit 7: Interrupt enable for EOIC.

Allowed values:
0: Disabled: EOIC interrupt disabled
1: Enabled: EOIC interrupt enabled. An interrupt is generated when the EOIC bit is set

SM

Bit 8: Scan mode.

Allowed values:
0: Disabled: Scan mode disabled
1: Enabled: Scan mode enabled

WDSC

Bit 9: When in scan mode, analog watchdog is effective on a single channel.

Allowed values:
0: All: Analog watchdog enabled on all channels
1: Single: Analog watchdog enabled on a single channel

ICA

Bit 10: Inserted channel group convert automatically.

Allowed values:
0: Disabled: Automatic inserted group conversion disabled
1: Enabled: Automatic inserted group conversion enabled

DISRC

Bit 11: Discontinuous mode on regular channels.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

DISIC

Bit 12: Discontinuous mode on inserted channels.

Allowed values:
0: Disabled: Discontinuous mode on inserted channels disabled
1: Enabled: Discontinuous mode on inserted channels enabled

DISNUM

Bits 13-15: Number of conversions in discontinuous mode.

Allowed values: 0-7

SYNCM

Bits 16-18: sync mode selection.

IWDEN

Bit 22: Inserted channel analog watchdog enable.

Allowed values:
0: Disabled: Analog watchdog disabled on inserted channels
1: Enabled: Analog watchdog enabled on inserted channels

RWDEN

Bit 23: Regular channel analog watchdog enable.

Allowed values:
0: Disabled: Analog watchdog disabled on regular channels
1: Enabled: Analog watchdog enabled on regular channels

CTL1

control register 1

Offset: 0x8, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSVREN
rw 		SWRCST
rw 		SWICST
rw 		ETERC
rw 		ETSRC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETSIC
rw 		DAL
rw 		DMA
rw 		RSTCLB
rw 		CLB
rw 		CTN
rw 		ADCON
rw
Toggle Fields.

ADCON

Bit 0: ADC on.

Allowed values:
0: Disabled: Disable ADC conversion/calibration and go to power down mode
1: Enabled: Enable ADC and to start conversion

CTN

Bit 1: Continuous mode.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

CLB

Bit 2: ADC calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

RSTCLB

Bit 3: Reset calibration.

Allowed values:
0: Complete: Calibration completed
1: NotComplete: Calibrating

DMA

Bit 8: DMA request enable.

Allowed values:
0: Disabled: DMA mode disabled
1: Enabled: DMA mode enabled

DAL

Bit 11: Data alignment.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

ETSIC

Bits 12-14: External trigger select for inserted channel.

Allowed values:
0: Timer0Trgo: Timer 0 TRGO event
1: Timer0Ch3: Timer 0 channel 3 event
2: Timer1Trgo: Timer 1 TRGO event
3: Timer1Ch0: Timer 1 channel 0 event
4: Timer2Ch2: Timer 2 channel 3 event
5: Timer14Trgo: Timer 14 TRGO event
6: Exti15: EXTI line 15
7: Swicst: SWICST

ETSRC

Bits 17-19: External trigger select for regular channel.

Allowed values:
0: Timer0Ch0: Timer 0 channel 0 event
1: Timer0Ch1: Timer 0 channel 1 event
2: Timer0Ch2: Timer 0 channel 2 event
3: Timer1Ch1: Timer 1 channel 1 event
4: Timer2Trgo: Timer 2 TRGO event
5: Timer14Ch0: Timer 14 channel 0 event
6: Exti11: EXTI line 11
7: Swrcst: SWRCST

ETERC

Bit 20: External trigger enable for regular channel.

Allowed values:
0: Disabled: Conversion on external event disabled
1: Enabled: Conversion on external event enabled

SWICST

Bit 21: Start on inserted channel.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of inserted channels

SWRCST

Bit 22: Start on regular channel.

Allowed values:
0: Started: Reset state
1: NotStarted: Starting conversion of regular channels

TSVREN

Bit 23: Channel 16 and 17 enable of ADC0.

Allowed values:
0: Disabled: Channel 16 and 17 disabled
1: Enabled: Channel 16 and 17 enabled

SAMPT0

Sample time register 0

Offset: 0xC, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT17
rw 		SPT16
rw 		SPT15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT15
rw 		SPT14
rw 		SPT13
rw 		SPT12
rw 		SPT11
rw 		SPT10
rw
Toggle Fields.

SPT10

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT11

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT12

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT13

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT14

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT15

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT16

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT17

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SAMPT1

Sample time register 1

Offset: 0x10, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT9
rw 		SPT8
rw 		SPT7
rw 		SPT6
rw 		SPT5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT5
rw 		SPT4
rw 		SPT3
rw 		SPT2
rw 		SPT1
rw 		SPT0
rw
Toggle Fields.

SPT0

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT1

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT2

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT3

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT4

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT5

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT6

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT7

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT8

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

SPT9

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles1_5: 1.5 ADC clock cycles
1: Cycles7_5: 7.5 ADC clock cycles
2: Cycles13_5: 13.5 ADC clock cycles
3: Cycles28_5: 28.5 ADC clock cycles
4: Cycles41_5: 41.5 ADC clock cycles
5: Cycles55_5: 55.5 ADC clock cycles
6: Cycles71_5: 71.5 ADC clock cycles
7: Cycles239_5: 239.5 ADC clock cycles

IOFF0

Inserted channel data offset register 0

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 0.

Allowed values: 0-4095

IOFF1

Inserted channel data offset register 1

Offset: 0x18, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 1.

Allowed values: 0-4095

IOFF2

Inserted channel data offset register 2

Offset: 0x1C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 2.

Allowed values: 0-4095

IOFF3

Inserted channel data offset register 3

Offset: 0x20, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 3.

Allowed values: 0-4095

WDHT

watchdog higher threshold register

Offset: 0x24, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDHT
rw
Toggle Fields.

WDHT

Bits 0-11: Analog watchdog higher threshold.

Allowed values: 0-4095

WDLT

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDLT
rw
Toggle Fields.

WDLT

Bits 0-11: Analog watchdog lower threshold.

Allowed values: 0-4095

RSQ0

regular sequence register 0

Offset: 0x2C, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RL
rw 		RSQ15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ15
rw 		RSQ14
rw 		RSQ13
rw 		RSQ12
rw
Toggle Fields.

RSQ12

Bits 0-4: 13th conversion in regular sequence.

Allowed values: 0-18

RSQ13

Bits 5-9: 14th conversion in regular sequence.

Allowed values: 0-18

RSQ14

Bits 10-14: 15th conversion in regular sequence.

Allowed values: 0-18

RSQ15

Bits 15-19: 16th conversion in regular sequence.

Allowed values: 0-18

RL

Bits 20-23: Regular channel group length.

Allowed values: 0-15

RSQ1

regular sequence register 1

Offset: 0x30, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ11
rw 		RSQ10
rw 		RSQ9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ9
rw 		RSQ8
rw 		RSQ7
rw 		RSQ6
rw
Toggle Fields.

RSQ6

Bits 0-4: 7th conversion in regular sequence.

Allowed values: 0-18

RSQ7

Bits 5-9: 8th conversion in regular sequence.

Allowed values: 0-18

RSQ8

Bits 10-14: 9th conversion in regular sequence.

Allowed values: 0-18

RSQ9

Bits 15-19: 10th conversion in regular sequence.

Allowed values: 0-18

RSQ10

Bits 20-24: 11th conversion in regular sequence.

Allowed values: 0-18

RSQ11

Bits 25-29: 12th conversion in regular sequence.

Allowed values: 0-18

RSQ2

regular sequence register 2

Offset: 0x34, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ5
rw 		RSQ4
rw 		RSQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ3
rw 		RSQ2
rw 		RSQ1
rw 		RSQ0
rw
Toggle Fields.

RSQ0

Bits 0-4: 1st conversion in regular sequence.

Allowed values: 0-18

RSQ1

Bits 5-9: 2nd conversion in regular sequence.

Allowed values: 0-18

RSQ2

Bits 10-14: 3rd conversion in regular sequence.

Allowed values: 0-18

RSQ3

Bits 15-19: 4th conversion in regular sequence.

Allowed values: 0-18

RSQ4

Bits 20-24: 5th conversion in regular sequence.

Allowed values: 0-18

RSQ5

Bits 25-29: 6th conversion in regular sequence.

Allowed values: 0-18

ISQ

Inserted sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IL
rw 		ISQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISQ3
rw 		ISQ2
rw 		ISQ1
rw 		ISQ0
rw
Toggle Fields.

ISQ0

Bits 0-4: 1st conversion in inserted sequence.

Allowed values: 0-18

ISQ1

Bits 5-9: 2nd conversion in inserted sequence.

Allowed values: 0-18

ISQ2

Bits 10-14: 3rd conversion in inserted sequence.

Allowed values: 0-18

ISQ3

Bits 15-19: 4th conversion in inserted sequence.

Allowed values: 0-18

IL

Bits 20-21: Inserted channel group length.

Allowed values: 0-3

IDATA0

Inserted data register 0

Offset: 0x3C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

IDATA1

Inserted data register 1

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

IDATA2

Inserted data register 2

Offset: 0x44, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

IDATA3

Inserted data register 3

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

Allowed values: 0-65535

RDATA

regular data register

Offset: 0x4C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle Fields.

RDATA

Bits 0-15: Regular channel data.

Allowed values: 0-65535

OVSAMPCTL

Oversample control register

Offset: 0x80, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRES
rw 		TOVS
rw 		OVSS
rw 		OVSR
rw 		OVSEN
rw
Toggle Fields.

OVSEN

Bit 0: Oversampling Enable.

Allowed values:
0: Disabled: Oversampling disabled
1: Enabled: Oversampling enabled

OVSR

Bits 2-4: Oversampling ratio.

Allowed values:
0: Times2: 2x
1: Times4: 4x
2: Times8: 8x
3: Times16: 16x
4: Times32: 32x
5: Times64: 64x
6: Times128: 128x
7: Times256: 256x

OVSS

Bits 5-8: Oversampling shift.

Allowed values: 0-8

TOVS

Bit 9: Triggered Oversampling.

Allowed values:
0: Consecutive: All oversampled conversions are done consecutively
1: Individual: Each oversampled conversion needs a trigger

DRES

Bits 12-13: ADC resolution.

Allowed values:
0: Bits12: 12 bit resolution
1: Bits10: 10 bit resolution
2: Bits8: 8 bit resolution
3: Bits6: 6 bit resolution

AFIO

0x40010000: Alternate-function I/Os

0/45 fields covered. Toggle Registers.

EC

Event control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOE
rw 		PORT
rw 		PIN
rw
Toggle Fields.

PIN

Bits 0-3: Event output pin selection.

PORT

Bits 4-6: Event output port selection.

EOE

Bit 7: Event output enable.

PCF0

AFIO port configuration register 0

Offset: 0x4, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWJ_CFG
rw 		ADC1_ETRGREG_REMAP
rw 		ADC1_ETRGINJ_REMAP
rw 		ADC0_ETRGREG_REMAP
rw 		ADC0_ETRGINJ_REMAP
rw 		TIMER4CH3_IREMAP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD01_REMAP
rw 		CAN_REMAP
rw 		TIMER3_REMAP
rw 		TIMER2_REMAP
rw 		TIMER1_REMAP
rw 		TIMER0_REMAP
rw 		USART2_REMAP
rw 		USART1_REMAP
rw 		USART0_REMAP
rw 		I2C0_REMAP
rw 		SPI0_REMAP
rw
Toggle Fields.

SPI0_REMAP

Bit 0: SPI0 remapping.

I2C0_REMAP

Bit 1: I2C0 remapping.

USART0_REMAP

Bit 2: USART0 remapping.

USART1_REMAP

Bit 3: USART1 remapping.

USART2_REMAP

Bits 4-5: USART2 remapping.

TIMER0_REMAP

Bits 6-7: TIMER0 remapping.

TIMER1_REMAP

Bits 8-9: TIMER1 remapping.

TIMER2_REMAP

Bits 10-11: TIMER2 remapping.

TIMER3_REMAP

Bit 12: TIMER3 remapping.

CAN_REMAP

Bits 13-14: CAN interface remapping.

PD01_REMAP

Bit 15: Port D0/Port D1 mapping on OSC_IN/OSC_OUT.

TIMER4CH3_IREMAP

Bit 16: TIMER4 channel3 internal remapping.

ADC0_ETRGINJ_REMAP

Bit 17: ADC 0 external trigger injected conversion remapping.

ADC0_ETRGREG_REMAP

Bit 18: ADC 0 external trigger regular conversion remapping.

ADC1_ETRGINJ_REMAP

Bit 19: ADC 1 external trigger injected conversion remapping.

ADC1_ETRGREG_REMAP

Bit 20: ADC 1 external trigger regular conversion remapping.

SWJ_CFG

Bits 24-26: Serial wire JTAG configuration.

EXTISS0

EXTI sources selection register 0

Offset: 0x8, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3_SS
rw 		EXTI2_SS
rw 		EXTI1_SS
rw 		EXTI0_SS
rw
Toggle Fields.

EXTI0_SS

Bits 0-3: EXTI 0 sources selection.

EXTI1_SS

Bits 4-7: EXTI 1 sources selection.

EXTI2_SS

Bits 8-11: EXTI 2 sources selection.

EXTI3_SS

Bits 12-15: EXTI 3 sources selection.

EXTISS1

EXTI sources selection register 1

Offset: 0xC, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7_SS
rw 		EXTI6_SS
rw 		EXTI5_SS
rw 		EXTI4_SS
rw
Toggle Fields.

EXTI4_SS

Bits 0-3: EXTI 4 sources selection.

EXTI5_SS

Bits 4-7: EXTI 5 sources selection.

EXTI6_SS

Bits 8-11: EXTI 6 sources selection.

EXTI7_SS

Bits 12-15: EXTI 7 sources selection.

EXTISS2

EXTI sources selection register 2

Offset: 0x10, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11_SS
rw 		EXTI10_SS
rw 		EXTI9_SS
rw 		EXTI8_SS
rw
Toggle Fields.

EXTI8_SS

Bits 0-3: EXTI 8 sources selection.

EXTI9_SS

Bits 4-7: EXTI 9 sources selection.

EXTI10_SS

Bits 8-11: EXTI 10 sources selection.

EXTI11_SS

Bits 12-15: EXTI 11 sources selection.

EXTISS3

EXTI sources selection register 3

Offset: 0x14, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15_SS
rw 		EXTI14_SS
rw 		EXTI13_SS
rw 		EXTI12_SS
rw
Toggle Fields.

EXTI12_SS

Bits 0-3: EXTI 12 sources selection.

EXTI13_SS

Bits 4-7: EXTI 13 sources selection.

EXTI14_SS

Bits 8-11: EXTI 14 sources selection.

EXTI15_SS

Bits 12-15: EXTI 15 sources selection.

PCF1

AFIO port configuration register 1

Offset: 0x1C, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTC_REMAP
rw 		FSMC_NADV
rw 		TIMER13_REMAP
rw 		TIMER12_REMAP
rw 		TIMER10_REMAP
rw 		TIMER9_REMAP
rw 		TIMER8_REMAP
rw
Toggle Fields.

TIMER8_REMAP

Bit 5: TIMER8 remapping.

TIMER9_REMAP

Bit 6: TIMER9 remapping.

TIMER10_REMAP

Bit 7: TIMER10 remapping.

TIMER12_REMAP

Bit 8: TIMER12 remapping.

TIMER13_REMAP

Bit 9: TIMER13 remapping.

FSMC_NADV

Bit 10: FSMC_NADV connect/disconnect.

CTC_REMAP

Bits 11-12: CTC remapping.

CPSCTL

IO compensation control register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPS_RDY
rw 		CPS_EN
rw
Toggle Fields.

CPS_EN

Bit 0: I/O compensation cell enable.

CPS_RDY

Bit 8: I/O compensation cell is really or not.

BKP

0x40006C00: Backup registers

0/55 fields covered. Toggle Registers.

DATA0

Backup data register 0

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA1

Backup data register 1

Offset: 0x8, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA2

Backup data register 2

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA3

Backup data register 3

Offset: 0x10, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA4

Backup data register 4

Offset: 0x14, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA5

Backup data register 5

Offset: 0x18, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA6

Backup data register 6

Offset: 0x1C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA7

Backup data register 7

Offset: 0x20, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA8

Backup data register 8

Offset: 0x24, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA9

Backup data register 9

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

OCTL

RTC signal output control register

Offset: 0x2C, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALDIR
rw 		CCOSEL
rw 		ROSEL
rw 		ASOEN
rw 		COEN
rw 		RCCV
rw
Toggle Fields.

RCCV

Bits 0-6: RTC clock calibration value.

COEN

Bit 7: RTC clock calibration output enable.

ASOEN

Bit 8: RTC alarm or second signal output enable.

ROSEL

Bit 9: RTC output selection.

CCOSEL

Bit 14: RTC clock output selection.

CALDIR

Bit 15: RTC clock calibration direction.

TPCTL

Tamper pin control register

Offset: 0x30, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPAL
rw 		TPEN
rw
Toggle Fields.

TPEN

Bit 0: TAMPER detection enable.

TPAL

Bit 1: TAMPER pin active level.

TPCS

Tamper control and status register

Offset: 0x34, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIF
rw 		TEF
rw 		TPIE
rw 		TIR
rw 		TER
rw
Toggle Fields.

TER

Bit 0: Tamper event reset.

TIR

Bit 1: Tamper interrupt reset.

TPIE

Bit 2: Tamper interrupt enable.

TEF

Bit 8: Tamper event flag.

TIF

Bit 9: Tamper interrupt flag.

DATA10

Backup data register 10

Offset: 0x40, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA11

Backup data register 11

Offset: 0x44, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA12

Backup data register 12

Offset: 0x48, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA13

Backup data register 13

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA14

Backup data register 14

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA15

Backup data register 15

Offset: 0x54, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA16

Backup data register 16

Offset: 0x58, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA17

Backup data register 17

Offset: 0x5C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA18

Backup data register 18

Offset: 0x60, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA19

Backup data register 19

Offset: 0x64, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA20

Backup data register 20

Offset: 0x68, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA21

Backup data register 21

Offset: 0x6C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA22

Backup data register 22

Offset: 0x70, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA23

Backup data register 23

Offset: 0x74, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA24

Backup data register 24

Offset: 0x78, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA25

Backup data register 25

Offset: 0x7C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA26

Backup data register 26

Offset: 0x80, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA27

Backup data register 27

Offset: 0x84, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA28

Backup data register 28

Offset: 0x88, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA29

Backup data register 29

Offset: 0x8C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA30

Backup data register 30

Offset: 0x90, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA31

Backup data register 31

Offset: 0x94, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA32

Backup data register 32

Offset: 0x98, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA33

Backup data register 33

Offset: 0x9C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA34

Backup data register 34

Offset: 0xA0, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA35

Backup data register 35

Offset: 0xA4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA36

Backup data register 36

Offset: 0xA8, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA37

Backup data register 37

Offset: 0xAC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA38

Backup data register 38

Offset: 0xB0, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA39

Backup data register 39

Offset: 0xB4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA40

Backup data register 40

Offset: 0xB8, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

DATA41

Backup data register 41

Offset: 0xBC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Backup data.

CAN0

0x40006400: Controller area network

261/2059 fields covered. Toggle Registers.

CTL

Control register

Offset: 0x0, reset: 0x00010002, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
rw 		TTC
rw 		ABOR
rw 		AWU
rw 		ARD
rw 		RFOD
rw 		TFO
rw 		SLPWMOD
rw 		IWMOD
rw
Toggle Fields.

IWMOD

Bit 0: Initial working mode.

Allowed values:
0: Disabled: Disable initial working mode
1: Enabled: Enable initial working mode

SLPWMOD

Bit 1: Sleep working mode.

Allowed values:
0: Active: Disable sleep mode, bus activity detected
1: Sleep: Enable sleep mode

TFO

Bit 2: Transmit FIFO order.

Allowed values:
0: Identifier: Order by identifier of the frame
1: FIFO: First in first out order

RFOD

Bit 3: Receive FIFO overwrite disable.

Allowed values:
0: Overwrite: Overwrite full receive FIFO with incoming frame
1: Discard: Discard incoming frame when receive FIFO is full

ARD

Bit 4: Automatic retransmission disable.

Allowed values:
0: Enabled: Enable automatic retransmission
1: Disabled: Disable automatic retransmission

AWU

Bit 5: Automatic wakeup.

Allowed values:
0: Manual: Sleep state is set by software
1: Automatic: Sleep state is set automatically by hardware

ABOR

Bit 6: Automatic bus-off recovery.

Allowed values:
0: Manual: Bus off state is set by software
1: Automatic: Bus off state is set automatically by hardware

TTC

Bit 7: Time-triggered communication.

Allowed values:
0: Disabled: Disable time-triggered communication
1: Enabled: Enable time-triggered communication

SWRST

Bit 15: Software reset.

Allowed values:
0: NotResetting: Finished resetting
1: Resetting: Reset in progress

DFZ

Bit 16: Debug freeze.

Allowed values:
0: Continue: Continue running CAN during debug
1: Stop: Stop CAN reception and transmission during debug hold

STAT

Status register

Offset: 0x4, reset: 0x00000C02, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXL
r 		LASTRX
r 		RS
r 		TS
r 		SLPIF
rw 		WUIF
rw 		ERRIF
rw 		SLPWS
r 		IWS
r
Toggle Fields.

IWS

Bit 0: Initial working state.

Allowed values:
0: Normal: CAN is not in initial working mode
1: Initial: CAN is in initial working mode

SLPWS

Bit 1: Sleep working state.

Allowed values:
0: Normal: CAN is not in sleep working mode
1: Sleeping: CAN is in sleep working mode

ERRIF

Bit 2: Error interrupt flag.

Allowed values:
0: NoError: There was no error
1: Error: An error was detected

WUIF

Bit 3: Status change interrupt flag of wakeup from sleep working mode.

Allowed values:
0: NoWakeup: No wakeup event
1: Wakeup: Wakeup event

SLPIF

Bit 4: Status change interrupt flag of sleep working mode entering.

Allowed values:
0: Awake: CAN is not entering sleep working mode
1: Sleeping: CAN is entering sleep working mode

TS

Bit 8: Transmitting state.

Allowed values:
0: NotWorking: CAN is not working in transmitting state
1: Working: CAN is working in transmitting state

RS

Bit 9: Receiving state.

Allowed values:
0: NotWorking: CAN is not working in receiving state
1: Working: CAN is working in receiving state

LASTRX

Bit 10: Last sample value of RX pin.

RXL

Bit 11: RX level.

TSTAT

Transmit status register

Offset: 0x8, reset: 0x1C000000, access: Unspecified

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TMLS2
r 		TMLS1
r 		TMLS0
r 		TME2
r 		TME1
r 		TME0
r 		NUM
r 		MST2
rw 		MTE2
rw 		MAL2
rw 		MTFNERR2
rw 		MTF2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MST1
rw 		MTE1
rw 		MAL1
rw 		MTFNERR1
rw 		MTF1
rw 		MST0
rw 		MTE0
rw 		MAL0
rw 		MTFNERR0
rw 		MTF0
rw
Toggle Fields.

MTF0

Bit 0: Mailbox 0 transmit finished.

Allowed values:
0: InProgress: Mailbox transmission still in progress
1: Finished: Mailbox transmission finished

MTFNERR0

Bit 1: Mailbox 0 transmit finished and no error.

Allowed values:
0: FinishedWithError: Mailbox transmission finished with an error
1: FinishedNoError: Mailbox transmission finished with no error

MAL0

Bit 2: Mailbox 0 arbitration lost.

Allowed values:
0: NoArbitrationLost: Arbitration was not lost
1: ArbitrationLost: Arbitration lost

MTE0

Bit 3: Mailbox 0 transmit error.

Allowed values:
0: NoError: There was no error
1: Error: An error was detected

MST0

Bit 7: Mailbox 0 stop transmitting.

Allowed values:
0: NotStop: Mailbox is not stopped, or is empty
1: Stop: Stop mailbox transmitting

MTF1

Bit 8: Mailbox 1 transmit finished.

Allowed values:
0: InProgress: Mailbox transmission still in progress
1: Finished: Mailbox transmission finished

MTFNERR1

Bit 9: Mailbox 1 transmit finished and no error.

Allowed values:
0: FinishedWithError: Mailbox transmission finished with an error
1: FinishedNoError: Mailbox transmission finished with no error

MAL1

Bit 10: Mailbox 1 arbitration lost.

Allowed values:
0: NoArbitrationLost: Arbitration was not lost
1: ArbitrationLost: Arbitration lost

MTE1

Bit 11: Mailbox 1 transmit error.

Allowed values:
0: NoError: There was no error
1: Error: An error was detected

MST1

Bit 15: Mailbox 1 stop transmitting.

Allowed values:
0: NotStop: Mailbox is not stopped, or is empty
1: Stop: Stop mailbox transmitting

MTF2

Bit 16: Mailbox 2 transmit finished.

Allowed values:
0: InProgress: Mailbox transmission still in progress
1: Finished: Mailbox transmission finished

MTFNERR2

Bit 17: Mailbox 2 transmit finished and no error.

Allowed values:
0: FinishedWithError: Mailbox transmission finished with an error
1: FinishedNoError: Mailbox transmission finished with no error

MAL2

Bit 18: Mailbox 2 arbitration lost.

Allowed values:
0: NoArbitrationLost: Arbitration was not lost
1: ArbitrationLost: Arbitration lost

MTE2

Bit 19: Mailbox 2 transmit error.

Allowed values:
0: NoError: There was no error
1: Error: An error was detected

MST2

Bit 23: Mailbox 2 stop transmitting.

Allowed values:
0: NotStop: Mailbox is not stopped, or is empty
1: Stop: Stop mailbox transmitting

NUM

Bits 24-25: number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty.

Allowed values: 0-2

TME0

Bit 26: Transmit mailbox 0 empty.

Allowed values:
0: NotEmpty: Transmit mailbox not empty
1: Empty: Transmit mailbox is empty

TME1

Bit 27: Transmit mailbox 1 empty.

Allowed values:
0: NotEmpty: Transmit mailbox not empty
1: Empty: Transmit mailbox is empty

TME2

Bit 28: Transmit mailbox 2 empty.

Allowed values:
0: NotEmpty: Transmit mailbox not empty
1: Empty: Transmit mailbox is empty

TMLS0

Bit 29: Transmit mailbox 0 last sending in transmit FIFO.

Allowed values:
0: NotLast: The mailbox doesn't have the last sending order
1: Last: The mailbox has the last sending order with at least two frames pending

TMLS1

Bit 30: Transmit mailbox 1 last sending in transmit FIFO.

Allowed values:
0: NotLast: The mailbox doesn't have the last sending order
1: Last: The mailbox has the last sending order with at least two frames pending

TMLS2

Bit 31: Transmit mailbox 2 last sending in transmit FIFO.

Allowed values:
0: NotLast: The mailbox doesn't have the last sending order
1: Last: The mailbox has the last sending order with at least two frames pending

RFIFO0

Receive message FIFO0 register

Offset: 0xC, reset: 0x00000000, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFD0
rw 		RFO0
rw 		RFF0
rw 		RFL0
r
Toggle Fields.

RFL0

Bits 0-1: Receive FIFO0 length.

Allowed values: 0-3

RFF0

Bit 3: Receive FIFO0 full.

Allowed values:
0: NotFull: Receive FIFO is not full
1: Full: Receive FIFO is full

RFO0

Bit 4: Receive FIFO0 overfull.

Allowed values:
0: NotOverfull: Receive FIFO is not overfull
1: Overfull: Receive FIFO is overfull

RFD0

Bit 5: Receive FIFO0 dequeue.

Allowed values:
0: Finished: Dequeuing done
1: InProgress: Dequeuing in progress

RFIFO1

Receive message FIFO1 register

Offset: 0x10, reset: 0x00000000, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFD1
rw 		RFO1
rw 		RFF1
rw 		RFL1
r
Toggle Fields.

RFL1

Bits 0-1: Receive FIFO1 length.

Allowed values: 0-3

RFF1

Bit 3: Receive FIFO1 full.

Allowed values:
0: NotFull: Receive FIFO is not full
1: Full: Receive FIFO is full

RFO1

Bit 4: Receive FIFO1 overfull.

Allowed values:
0: NotOverfull: Receive FIFO is not overfull
1: Overfull: Receive FIFO is overfull

RFD1

Bit 5: Receive FIFO1 dequeue.

Allowed values:
0: Finished: Dequeuing done
1: InProgress: Dequeuing in progress

INTEN

Interrupt enable register

Offset: 0x14, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLPWIE
rw 		WIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE
rw 		ERRNIE
rw 		BOIE
rw 		PERRIE
rw 		WERRIE
rw 		RFOIE1
rw 		RFFIE1
rw 		RFNEIE1
rw 		RFOIE0
rw 		RFFIE0
rw 		RFNEIE0
rw 		TMEIE
rw
Toggle Fields.

TMEIE

Bit 0: Transmit mailbox empty interrupt enable.

Allowed values:
0: Disabled: Transmit mailbox empty interrupt is disabled
1: Enabled: Transmit mailbox empty interrupt is enabled

RFNEIE0

Bit 1: Receive FIFO0 not empty interrupt enable.

Allowed values:
0: Disabled: Receive FIFO not empty interrupt is disabled
1: Enabled: Receive FIFO not empty interrupt is enabled

RFFIE0

Bit 2: Receive FIFO0 full interrupt enable.

Allowed values:
0: Disabled: Receive FIFO full interrupt is disabled
1: Enabled: Receive FIFO full interrupt is enabled

RFOIE0

Bit 3: Receive FIFO0 overfull interrupt enable.

Allowed values:
0: Disabled: Receive FIFO overfull interrupt is disabled
1: Enabled: Receive FIFO overfull interrupt is enabled

RFNEIE1

Bit 4: Receive FIFO1 not empty interrupt enable.

Allowed values:
0: Disabled: Receive FIFO not empty interrupt is disabled
1: Enabled: Receive FIFO not empty interrupt is enabled

RFFIE1

Bit 5: Receive FIFO1 full interrupt enable.

Allowed values:
0: Disabled: Receive FIFO full interrupt is disabled
1: Enabled: Receive FIFO full interrupt is enabled

RFOIE1

Bit 6: Receive FIFO1 overfull interrupt enable.

Allowed values:
0: Disabled: Receive FIFO overfull interrupt is disabled
1: Enabled: Receive FIFO overfull interrupt is enabled

WERRIE

Bit 8: Warning error interrupt enable.

Allowed values:
0: Disabled: Warning error interrupt is disabled
1: Enabled: Warning error interrupt is enabled

PERRIE

Bit 9: Passive error interrupt enable.

Allowed values:
0: Disabled: Passive error interrupt is disabled
1: Enabled: Passive error interrupt is enabled

BOIE

Bit 10: Bus-off interrupt enable.

Allowed values:
0: Disabled: Bus-off interrupt is disabled
1: Enabled: Bus-off interrupt is enabled

ERRNIE

Bit 11: Error number interrupt enable.

Allowed values:
0: Disabled: Error number interrupt is disabled
1: Enabled: Error number interrupt is enabled

ERRIE

Bit 15: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt is disabled
1: Enabled: Error interrupt is enabled

WIE

Bit 16: Wakeup interrupt enable.

Allowed values:
0: Disabled: Wakeup interrupt is disabled
1: Enabled: Wakeup interrupt is enabled

SLPWIE

Bit 17: Sleep working interrupt enable.

Allowed values:
0: Disabled: Sleep working interrupt is disabled
1: Enabled: Sleep working interrupt is enabled

ERR

Error register

Offset: 0x18, reset: 0x00000000, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECNT
r 		TECNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRN
rw 		BOERR
r 		PERR
r 		WERR
r
Toggle Fields.

WERR

Bit 0: Warning error.

Allowed values:
0: NoError: No warning error
1: Error: Warning error

PERR

Bit 1: Passive error.

Allowed values:
0: NoError: No passive error
1: Error: Passive error

BOERR

Bit 2: Bus-off error.

Allowed values:
0: NoError: No bus-off error
1: Error: Bus-off error

ERRN

Bits 4-6: Error number.

Allowed values:
0: NoError: No Error
1: Stuff: Stuff Error
2: Form: Form Error
3: Ack: Acknowledgment Error
4: BitRecessive: Bit recessive Error
5: BitDominant: Bit dominant Error
6: Crc: CRC Error
7: Custom: Set by software

TECNT

Bits 16-23: Transmit Error Count defined by the CAN standard.

Allowed values: 0-255

RECNT

Bits 24-31: Receive Error Count defined by the CAN standard.

Allowed values: 0-255

BT

Bit timing register

Offset: 0x1C, reset: 0x01230000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCMOD
rw 		LCMOD
rw 		SJW
rw 		BS2
rw 		BS1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BAUDPSC
rw
Toggle Fields.

BAUDPSC

Bits 0-9: Baud rate prescaler.

Allowed values: 0-1023

BS1

Bits 16-19: Bit segment 1.

Allowed values: 0-3

BS2

Bits 20-22: Bit segment 2.

Allowed values: 0-3

SJW

Bits 24-25: Resynchronization jump width.

Allowed values: 0-3

LCMOD

Bit 30: Loopback communication mode.

Allowed values:
0: Disabled: Loop Back Mode disabled
1: Enabled: Loop Back Mode enabled

SCMOD

Bit 31: Silent communication mode.

Allowed values:
0: Normal: Normal operation
1: Silent: Silent Mode

TMI0

Transmit mailbox identifier register 0

Offset: 0x180, reset: 0x00000000, access: read-write

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

Allowed values:
0: Disabled: Transmit disabled
1: Enabled: Transmit enabled

FT

Bit 1: Frame type.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

FF

Bit 2: Frame format.

Allowed values:
0: Standard: Standard format frame
1: Extended: Extended format frame

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP0

Transmit mailbox property register 0

Offset: 0x184, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

Allowed values: 0-15

TSEN

Bit 8: Time stamp enable.

Allowed values:
0: Disabled: Timestamp disabled
1: Enabled: Timestamp enabled

TS

Bits 16-31: Time stamp.

Allowed values: 0-65535

TMDATA00

Transmit mailbox data0 register

Offset: 0x188, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

Allowed values: 0-255

DB1

Bits 8-15: Data byte 1.

Allowed values: 0-255

DB2

Bits 16-23: Data byte 2.

Allowed values: 0-255

DB3

Bits 24-31: Data byte 3.

Allowed values: 0-255

TMDATA10

Transmit mailbox data1 register

Offset: 0x18C, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

Allowed values: 0-255

DB5

Bits 8-15: Data byte 5.

Allowed values: 0-255

DB6

Bits 16-23: Data byte 6.

Allowed values: 0-255

DB7

Bits 24-31: Data byte 7.

Allowed values: 0-255

TMI1

Transmit mailbox identifier register 1

Offset: 0x190, reset: 0x00000000, access: read-write

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

Allowed values:
0: Disabled: Transmit disabled
1: Enabled: Transmit enabled

FT

Bit 1: Frame type.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

FF

Bit 2: Frame format.

Allowed values:
0: Standard: Standard format frame
1: Extended: Extended format frame

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP1

Transmit mailbox property register 1

Offset: 0x194, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

Allowed values: 0-15

TSEN

Bit 8: Time stamp enable.

Allowed values:
0: Disabled: Timestamp disabled
1: Enabled: Timestamp enabled

TS

Bits 16-31: Time stamp.

Allowed values: 0-65535

TMDATA01

Transmit mailbox data0 register

Offset: 0x198, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

Allowed values: 0-255

DB1

Bits 8-15: Data byte 1.

Allowed values: 0-255

DB2

Bits 16-23: Data byte 2.

Allowed values: 0-255

DB3

Bits 24-31: Data byte 3.

Allowed values: 0-255

TMDATA11

Transmit mailbox data1 register

Offset: 0x19C, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

Allowed values: 0-255

DB5

Bits 8-15: Data byte 5.

Allowed values: 0-255

DB6

Bits 16-23: Data byte 6.

Allowed values: 0-255

DB7

Bits 24-31: Data byte 7.

Allowed values: 0-255

TMI2

Transmit mailbox identifier register 2

Offset: 0x1A0, reset: 0x00000000, access: read-write

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

Allowed values:
0: Disabled: Transmit disabled
1: Enabled: Transmit enabled

FT

Bit 1: Frame type.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

FF

Bit 2: Frame format.

Allowed values:
0: Standard: Standard format frame
1: Extended: Extended format frame

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP2

Transmit mailbox property register 2

Offset: 0x1A4, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

Allowed values: 0-15

TSEN

Bit 8: Time stamp enable.

Allowed values:
0: Disabled: Timestamp disabled
1: Enabled: Timestamp enabled

TS

Bits 16-31: Time stamp.

Allowed values: 0-65535

TMDATA02

Transmit mailbox data0 register

Offset: 0x1A8, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

Allowed values: 0-255

DB1

Bits 8-15: Data byte 1.

Allowed values: 0-255

DB2

Bits 16-23: Data byte 2.

Allowed values: 0-255

DB3

Bits 24-31: Data byte 3.

Allowed values: 0-255

TMDATA12

Transmit mailbox data1 register

Offset: 0x1AC, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

Allowed values: 0-255

DB5

Bits 8-15: Data byte 5.

Allowed values: 0-255

DB6

Bits 16-23: Data byte 6.

Allowed values: 0-255

DB7

Bits 24-31: Data byte 7.

Allowed values: 0-255

RFIFOMI0

Receive FIFO mailbox identifier register

Offset: 0x1B0, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
r 		EFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
r 		FF
r 		FT
r
Toggle Fields.

FT

Bit 1: Frame type.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

FF

Bit 2: Frame format.

Allowed values:
0: Standard: Standard format frame
1: Extended: Extended format frame

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

RFIFOMP0

Receive FIFO0 mailbox property register

Offset: 0x1B4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FI
r 		DLENC
r
Toggle Fields.

DLENC

Bits 0-3: Data length code.

Allowed values: 0-15

FI

Bits 8-15: Filtering index.

Allowed values: 0-255

TS

Bits 16-31: Time stamp.

Allowed values: 0-65535

RFIFOMDATA00

Receive FIFO0 mailbox data0 register

Offset: 0x1B8, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
r 		DB2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
r 		DB0
r
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

Allowed values: 0-255

DB1

Bits 8-15: Data byte 1.

Allowed values: 0-255

DB2

Bits 16-23: Data byte 2.

Allowed values: 0-255

DB3

Bits 24-31: Data byte 3.

Allowed values: 0-255

RFIFOMDATA10

Receive FIFO0 mailbox data1 register

Offset: 0x1BC, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
r 		DB6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
r 		DB4
r
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

Allowed values: 0-255

DB5

Bits 8-15: Data byte 5.

Allowed values: 0-255

DB6

Bits 16-23: Data byte 6.

Allowed values: 0-255

DB7

Bits 24-31: Data byte 7.

Allowed values: 0-255

RFIFOMI1

Receive FIFO1 mailbox identifier register

Offset: 0x1C0, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
r 		EFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
r 		FF
r 		FT
r
Toggle Fields.

FT

Bit 1: Frame type.

Allowed values:
0: Data: Data frame
1: Remote: Remote frame

FF

Bit 2: Frame format.

Allowed values:
0: Standard: Standard format frame
1: Extended: Extended format frame

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

RFIFOMP1

Receive FIFO1 mailbox property register

Offset: 0x1C4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FI
r 		DLENC
r
Toggle Fields.

DLENC

Bits 0-3: Data length code.

Allowed values: 0-15

FI

Bits 8-15: Filtering index.

Allowed values: 0-255

TS

Bits 16-31: Time stamp.

Allowed values: 0-65535

RFIFOMDATA01

Receive FIFO1 mailbox data0 register

Offset: 0x1C8, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
r 		DB2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
r 		DB0
r
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

Allowed values: 0-255

DB1

Bits 8-15: Data byte 1.

Allowed values: 0-255

DB2

Bits 16-23: Data byte 2.

Allowed values: 0-255

DB3

Bits 24-31: Data byte 3.

Allowed values: 0-255

RFIFOMDATA11

Receive FIFO1 mailbox data1 register

Offset: 0x1CC, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
r 		DB6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
r 		DB4
r
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

Allowed values: 0-255

DB5

Bits 8-15: Data byte 5.

Allowed values: 0-255

DB6

Bits 16-23: Data byte 6.

Allowed values: 0-255

DB7

Bits 24-31: Data byte 7.

Allowed values: 0-255

FCTL

Filter control register

Offset: 0x200, reset: 0x2A1C0E01, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HBC1F
rw 		FLD
rw
Toggle Fields.

FLD

Bit 0: Filter lock disable.

Allowed values:
0: Disabled: Filter lock disabled
1: Enabled: Filter lock enabled

HBC1F

Bits 8-13: Header bank of CAN1 filter.

Allowed values: 0-28

FMCFG

Filter mode configuration register

Offset: 0x204, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FMOD27
rw 		FMOD26
rw 		FMOD25
rw 		FMOD24
rw 		FMOD23
rw 		FMOD22
rw 		FMOD21
rw 		FMOD20
rw 		FMOD19
rw 		FMOD18
rw 		FMOD17
rw 		FMOD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMOD15
rw 		FMOD14
rw 		FMOD13
rw 		FMOD12
rw 		FMOD11
rw 		FMOD10
rw 		FMOD9
rw 		FMOD8
rw 		FMOD7
rw 		FMOD6
rw 		FMOD5
rw 		FMOD4
rw 		FMOD3
rw 		FMOD2
rw 		FMOD1
rw 		FMOD0
rw
Toggle Fields.

FMOD0

Bit 0: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD1

Bit 1: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD2

Bit 2: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD3

Bit 3: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD4

Bit 4: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD5

Bit 5: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD6

Bit 6: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD7

Bit 7: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD8

Bit 8: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD9

Bit 9: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD10

Bit 10: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD11

Bit 11: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD12

Bit 12: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD13

Bit 13: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD14

Bit 14: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD15

Bit 15: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD16

Bit 16: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD17

Bit 17: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD18

Bit 18: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD19

Bit 19: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD20

Bit 20: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD21

Bit 21: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD22

Bit 22: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD23

Bit 23: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD24

Bit 24: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD25

Bit 25: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD26

Bit 26: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FMOD27

Bit 27: Filter mode.

Allowed values:
0: Mask: Mask mode
1: List: List mode

FSCFG

Filter scale configuration register

Offset: 0x20C, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FS27
rw 		FS26
rw 		FS25
rw 		FS24
rw 		FS23
rw 		FS22
rw 		FS21
rw 		FS20
rw 		FS19
rw 		FS18
rw 		FS17
rw 		FS16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FS15
rw 		FS14
rw 		FS13
rw 		FS12
rw 		FS11
rw 		FS10
rw 		FS9
rw 		FS8
rw 		FS7
rw 		FS6
rw 		FS5
rw 		FS4
rw 		FS3
rw 		FS2
rw 		FS1
rw 		FS0
rw
Toggle Fields.

FS0

Bit 0: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS1

Bit 1: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS2

Bit 2: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS3

Bit 3: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS4

Bit 4: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS5

Bit 5: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS6

Bit 6: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS7

Bit 7: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS8

Bit 8: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS9

Bit 9: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS10

Bit 10: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS11

Bit 11: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS12

Bit 12: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS13

Bit 13: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS14

Bit 14: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS15

Bit 15: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS16

Bit 16: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS17

Bit 17: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS18

Bit 18: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS19

Bit 19: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS20

Bit 20: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS21

Bit 21: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS22

Bit 22: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS23

Bit 23: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS24

Bit 24: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS25

Bit 25: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS26

Bit 26: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FS27

Bit 27: Filter scale configuration.

Allowed values:
0: Scale16: Filter with 16-bit scale
1: Scale32: Filter with 32-bit scale

FAFIFO

Filter associated FIFO register

Offset: 0x214, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FAF27
rw 		FAF26
rw 		FAF25
rw 		FAF24
rw 		FAF23
rw 		FAF22
rw 		FAF21
rw 		FAF20
rw 		FAF19
rw 		FAF18
rw 		FAF17
rw 		FAF16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAF15
rw 		FAF14
rw 		FAF13
rw 		FAF12
rw 		FAF11
rw 		FAF10
rw 		FAF9
rw 		FAF8
rw 		FAF7
rw 		FAF6
rw 		FAF5
rw 		FAF4
rw 		FAF3
rw 		FAF2
rw 		FAF1
rw 		FAF0
rw
Toggle Fields.

FAF0

Bit 0: Filter 0 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF1

Bit 1: Filter 1 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF2

Bit 2: Filter 2 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF3

Bit 3: Filter 3 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF4

Bit 4: Filter 4 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF5

Bit 5: Filter 5 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF6

Bit 6: Filter 6 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF7

Bit 7: Filter 7 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF8

Bit 8: Filter 8 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF9

Bit 9: Filter 9 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF10

Bit 10: Filter 10 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF11

Bit 11: Filter 11 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF12

Bit 12: Filter 12 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF13

Bit 13: Filter 13 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF14

Bit 14: Filter 14 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF15

Bit 15: Filter 15 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF16

Bit 16: Filter 16 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF17

Bit 17: Filter 17 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF18

Bit 18: Filter 18 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF19

Bit 19: Filter 19 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF20

Bit 20: Filter 20 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF21

Bit 21: Filter 21 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF22

Bit 22: Filter 22 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF23

Bit 23: Filter 23 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF24

Bit 24: Filter 24 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF25

Bit 25: Filter 25 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF26

Bit 26: Filter 26 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FAF27

Bit 27: Filter 27 associated with FIFO.

Allowed values:
0: FIFO0: Filter associated with FIFO0
1: FIFO1: Filter associated with FIFO1

FW

Filter working register

Offset: 0x21C, reset: 0x00000000, access: read-write

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FW27
rw 		FW26
rw 		FW25
rw 		FW24
rw 		FW23
rw 		FW22
rw 		FW21
rw 		FW20
rw 		FW19
rw 		FW18
rw 		FW17
rw 		FW16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FW15
rw 		FW14
rw 		FW13
rw 		FW12
rw 		FW11
rw 		FW10
rw 		FW9
rw 		FW8
rw 		FW7
rw 		FW6
rw 		FW5
rw 		FW4
rw 		FW3
rw 		FW2
rw 		FW1
rw 		FW0
rw
Toggle Fields.

FW0

Bit 0: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW1

Bit 1: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW2

Bit 2: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW3

Bit 3: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW4

Bit 4: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW5

Bit 5: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW6

Bit 6: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW7

Bit 7: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW8

Bit 8: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW9

Bit 9: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW10

Bit 10: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW11

Bit 11: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW12

Bit 12: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW13

Bit 13: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW14

Bit 14: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW15

Bit 15: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW16

Bit 16: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW17

Bit 17: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW18

Bit 18: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW19

Bit 19: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW20

Bit 20: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW21

Bit 21: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW22

Bit 22: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW23

Bit 23: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW24

Bit 24: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW25

Bit 25: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW26

Bit 26: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

FW27

Bit 27: Filter working.

Allowed values:
0: Disabled: Filter working disabled
1: Enabled: Filter working enabled

F0DATA0

Filter 0 data 0 register

Offset: 0x240, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F0DATA1

Filter 0 data 1 register

Offset: 0x244, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F1DATA0

Filter 1 data 0 register

Offset: 0x248, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F1DATA1

Filter 1 data 1 register

Offset: 0x24C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F2DATA0

Filter 2 data 0 register

Offset: 0x250, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F2DATA1

Filter 2 data 1 register

Offset: 0x254, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F3DATA0

Filter 3 data 0 register

Offset: 0x258, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F3DATA1

Filter 3 data 1 register

Offset: 0x25C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F4DATA0

Filter 4 data 0 register

Offset: 0x260, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F4DATA1

Filter 4 data 1 register

Offset: 0x264, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F5DATA0

Filter 5 data 0 register

Offset: 0x268, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F5DATA1

Filter 5 data 1 register

Offset: 0x26C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F6DATA0

Filter 6 data 0 register

Offset: 0x270, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F6DATA1

Filter 6 data 1 register

Offset: 0x274, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F7DATA0

Filter 7 data 0 register

Offset: 0x278, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F7DATA1

Filter 7 data 1 register

Offset: 0x27C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F8DATA0

Filter 8 data 0 register

Offset: 0x280, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F8DATA1

Filter 8 data 1 register

Offset: 0x284, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F9DATA0

Filter 9 data 0 register

Offset: 0x288, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F9DATA1

Filter 9 data 1 register

Offset: 0x28C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F10DATA0

Filter 10 data 0 register

Offset: 0x290, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F10DATA1

Filter 10 data 1 register

Offset: 0x294, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F11DATA0

Filter 11 data 0 register

Offset: 0x298, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F11DATA1

Filter 11 data 1 register

Offset: 0x29C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F12DATA0

Filter 12 data 0 register

Offset: 0x2A0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F12DATA1

Filter 12 data 1 register

Offset: 0x2A4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F13DATA0

Filter 13 data 0 register

Offset: 0x2A8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F13DATA1

Filter 13 data 1 register

Offset: 0x2AC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F14DATA0

Filter 14 data 0 register

Offset: 0x2B0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F14DATA1

Filter 14 data 1 register

Offset: 0x2B4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F15DATA0

Filter 15 data 0 register

Offset: 0x2B8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F15DATA1

Filter 15 data 1 register

Offset: 0x2BC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F16DATA0

Filter 16 data 0 register

Offset: 0x2C0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F16DATA1

Filter 16 data 1 register

Offset: 0x2C4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F17DATA0

Filter 17 data 0 register

Offset: 0x2C8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F17DATA1

Filter 17 data 1 register

Offset: 0x2CC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F18DATA0

Filter 18 data 0 register

Offset: 0x2D0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F18DATA1

Filter 18 data 1 register

Offset: 0x2D4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F19DATA0

Filter 19 data 0 register

Offset: 0x2D8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F19DATA1

Filter 19 data 1 register

Offset: 0x2DC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F20DATA0

Filter 20 data 0 register

Offset: 0x2E0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F20DATA1

Filter 20 data 1 register

Offset: 0x2E4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F21DATA0

Filter 21 data 0 register

Offset: 0x2E8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F21DATA1

Filter 21 data 1 register

Offset: 0x2EC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F22DATA0

Filter 22 data 0 register

Offset: 0x2F0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F22DATA1

Filter 22 data 1 register

Offset: 0x2F4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F23DATA0

Filter 23 data 0 register

Offset: 0x2F8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F23DATA1

Filter 23 data 1 register

Offset: 0x2FC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F24DATA0

Filter 24 data 0 register

Offset: 0x300, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F24DATA1

Filter 24 data 1 register

Offset: 0x304, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F25DATA0

Filter 25 data 0 register

Offset: 0x308, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F25DATA1

Filter 25 data 1 register

Offset: 0x30C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F26DATA0

Filter 26 data 0 register

Offset: 0x310, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F26DATA1

Filter 26 data 1 register

Offset: 0x314, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F27DATA0

Filter 27 data 0 register

Offset: 0x318, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F27DATA1

Filter 27 data 1 register

Offset: 0x31C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

CRC

0x40023000: cyclic redundancy check calculation unit

3/3 fields covered. Toggle Registers.

DATA

Data register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: CRC calculation result bits.

Allowed values: 0-4294967295

FDATA

Free data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDATA
rw
Toggle Fields.

FDATA

Bits 0-7: Free Data Register bits.

Allowed values: 0-255

CTL

Control register

Offset: 0x8, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RST
rw
Toggle Fields.

RST

Bit 0: reset bit.

Allowed values:
1: Reset: Resets the DATA register to IDATA, with no effect on FDATA

CTC

0x4000C800: Clock trim controller

9/26 fields covered. Toggle Registers.

CTL0

Control register 0

Offset: 0x0, reset: 0x00002000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMVALUE
rw 		SWREFPUL
rw 		AUTOTRIM
rw 		CNTEN
rw 		EREFIE
rw 		ERRIE
rw 		CKWARNIE
rw 		CKOKIE
rw
Toggle Fields.

CKOKIE

Bit 0: Clock trim ok interrupt enable.

CKWARNIE

Bit 1: Clock trim warning interrupt enable.

ERRIE

Bit 2: Error interrupt enable.

EREFIE

Bit 3: EREFIF interrupt enable.

CNTEN

Bit 5: CTC counter enable.

AUTOTRIM

Bit 6: Hardware automatically trim mode.

SWREFPUL

Bit 7: Software reference source sync pulse.

TRIMVALUE

Bits 8-13: IRC48M trim value.

CTL1

Control register 1

Offset: 0x4, reset: 0x2022BB7F, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REFPOL
rw 		REFSEL
rw 		REFPSC
rw 		CKLIM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RLVALUE
rw
Toggle Fields.

RLVALUE

Bits 0-15: CTC counter reload value.

CKLIM

Bits 16-23: Clock trim base limit value.

REFPSC

Bits 24-26: Reference signal source prescaler.

REFSEL

Bits 28-29: Reference signal source selection.

REFPOL

Bit 31: Reference signal source polarity.

STAT

Status register

Offset: 0x8, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REFCAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REFDIR
r 		TRIMERR
r 		REFMISS
r 		CKERR
r 		EREFIF
r 		ERRIF
r 		CKWARNIF
r 		CKOKIF
r
Toggle Fields.

CKOKIF

Bit 0: Clock trim OK interrupt flag.

CKWARNIF

Bit 1: Clock trim warning interrupt flag.

ERRIF

Bit 2: Error interrupt flag.

EREFIF

Bit 3: Expect reference interrupt flag.

CKERR

Bit 8: Clock trim error bit.

REFMISS

Bit 9: Reference sync pulse miss.

TRIMERR

Bit 10: Trim value error bit.

REFDIR

Bit 15: CTC trim counter direction when reference sync pulse.

REFCAP

Bits 16-31: CTC counter capture when reference sync pulse.

INTC

Interrupt clear register

Offset: 0xC, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EREFIC
w 		ERRIC
w 		CKWARNIC
w 		CKOKIC
w
Toggle Fields.

CKOKIC

Bit 0: CKOKIF interrupt clear bit.

CKWARNIC

Bit 1: CKWARNIF interrupt clear bit.

ERRIC

Bit 2: ERRIF interrupt clear bit.

EREFIC

Bit 3: EREFIF interrupt clear bit.

DAC

0x40007400: Digital-to-analog converter

26/30 fields covered. Toggle Registers.

CTL

control register

Offset: 0x0, reset: 0x00000000, access: read-write

10/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DDMAEN1
rw 		DWBW1
rw 		DWM1
rw 		DTSEL1
rw 		DTEN1
rw 		DBOFF1
rw 		DEN1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDMAEN0
rw 		DWBW0
rw 		DWM0
rw 		DTSEL0
rw 		DTEN0
rw 		DBOFF0
rw 		DEN0
rw
Toggle Fields.

DEN0

Bit 0: DAC0 enable.

Allowed values:
0: Disabled: DAC channel disabled
1: Enabled: DAC channel enabled

DBOFF0

Bit 1: DAC0 output buffer turn off.

Allowed values:
0: Enabled: DAC X output buffer enabled
1: Disabled: DAC X output buffer disabled

DTEN0

Bit 2: DAC0 trigger enable.

Allowed values:
0: Disabled: DAC trigger disabled
1: Enabled: DAC trigger enabled

DTSEL0

Bits 3-5: DAC0 trigger selection.

Allowed values:
0: TIMER5_TRGO: Timer 5 TRGO event
1: TIMER2_TRGO: Timer 2 TRGO event
3: TIMER14_TRGO: Timer 14 TRGO event
4: TIMER1_TRGO: Timer 1 TRGO event
6: EXTERNAL9: External line9
7: SOFTWARE: Software trigger

DWM0

Bits 6-7: DAC0 noise wave mode.

DWBW0

Bits 8-11: DAC0 noise wave bit width.

DDMAEN0

Bit 12: DAC0 DMA enable.

Allowed values:
0: Disabled: DAC DMA mode disabled
1: Enabled: DAC DMA mode enabled

DEN1

Bit 16: DAC1 enable.

Allowed values:
0: Disabled: DAC channel disabled
1: Enabled: DAC channel enabled

DBOFF1

Bit 17: DAC1 output buffer turn off.

Allowed values:
0: Enabled: DAC X output buffer enabled
1: Disabled: DAC X output buffer disabled

DTEN1

Bit 18: DAC1 trigger enable.

Allowed values:
0: Disabled: DAC trigger disabled
1: Enabled: DAC trigger enabled

DTSEL1

Bits 19-21: DAC1 trigger selection.

Allowed values:
0: TIMER5_TRGO: Timer 5 TRGO event
1: TIMER2_TRGO: Timer 2 TRGO event
3: TIMER14_TRGO: Timer 14 TRGO event
4: TIMER1_TRGO: Timer 1 TRGO event
6: EXTERNAL9: External line9
7: SOFTWARE: Software trigger

DWM1

Bits 22-23: DAC1 noise wave mode.

DWBW1

Bits 24-27: DAC1 noise wave bit width.

DDMAEN1

Bit 28: DAC1 DMA enable.

Allowed values:
0: Disabled: DAC DMA mode disabled
1: Enabled: DAC DMA mode enabled

SWT

software trigger register

Offset: 0x4, reset: 0x00000000, access: write-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTR1
w 		SWTR0
w
Toggle Fields.

SWTR0

Bit 0: DAC0 software trigger.

Allowed values:
0: Disabled: DAC channel X software trigger disabled
1: Enabled: DAC channel X software trigger enabled

SWTR1

Bit 1: DAC1 software trigger.

Allowed values:
0: Disabled: DAC channel X software trigger disabled
1: Enabled: DAC channel X software trigger enabled

DAC0_R12DH

DAC0 12-bit right-aligned data holding register

Offset: 0x8, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC0_DH
rw
Toggle Fields.

DAC0_DH

Bits 0-11: DAC0 12-bit right-aligned data.

Allowed values: 0-4095

DAC0_L12DH

DAC0 12-bit left-aligned data holding register

Offset: 0xC, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC0_DH
rw
Toggle Fields.

DAC0_DH

Bits 4-15: DAC0 12-bit left-aligned data.

Allowed values: 0-4095

DAC0_R8DH

DAC0 8-bit right aligned data holding register

Offset: 0x10, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC0_DH
rw
Toggle Fields.

DAC0_DH

Bits 0-7: DAC0 8-bit right-aligned data.

Allowed values: 0-255

DAC1_R12DH

DAC1 12-bit right-aligned data holding register

Offset: 0x14, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC1_DH
rw
Toggle Fields.

DAC1_DH

Bits 0-11: DAC1 12-bit right-aligned data.

Allowed values: 0-4095

DAC1_L12DH

DAC1 12-bit left aligned data holding register

Offset: 0x18, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC1_DH
rw
Toggle Fields.

DAC1_DH

Bits 4-15: DAC1 12-bit left-aligned data.

Allowed values: 0-4095

DAC1_R8DH

DAC1 8-bit right aligned data holding register

Offset: 0x1C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC1_DH
rw
Toggle Fields.

DAC1_DH

Bits 0-7: DAC1 8-bit right-aligned data.

Allowed values: 0-255

DACC_R12DH

DAC concurrent mode 12-bit right-aligned data holding register

Offset: 0x20, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAC1_DH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC0_DH
rw
Toggle Fields.

DAC0_DH

Bits 0-11: DAC0 12-bit right-aligned data.

Allowed values: 0-4095

DAC1_DH

Bits 16-27: DAC1 12-bit right-aligned data.

Allowed values: 0-4095

DACC_L12DH

DAC concurrent mode 12-bit left aligned data holding register

Offset: 0x24, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAC1_DH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC0_DH
rw
Toggle Fields.

DAC0_DH

Bits 4-15: DAC0 12-bit left-aligned data.

Allowed values: 0-4095

DAC1_DH

Bits 20-31: DAC1 12-bit left-aligned data.

Allowed values: 0-4095

DACC_R8DH

DAC concurrent mode 8-bit right aligned data holding register

Offset: 0x28, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC1_DH
rw 		DAC0_DH
rw
Toggle Fields.

DAC0_DH

Bits 0-7: DAC0 8-bit right-aligned data.

Allowed values: 0-255

DAC1_DH

Bits 8-15: DAC1 8-bit right-aligned data.

Allowed values: 0-255

DAC0_DO

DAC0 data output register

Offset: 0x2C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC0_DO
r
Toggle Fields.

DAC0_DO

Bits 0-11: DAC0 data output.

Allowed values: 0-4095

DAC1_DO

DAC1 data output register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC1_DO
r
Toggle Fields.

DAC1_DO

Bits 0-11: DAC1 data output.

Allowed values: 0-4095

DBG

0xE0042000: Debug support

24/26 fields covered. Toggle Registers.

ID

ID code register

Offset: 0x0, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID_CODE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID_CODE
r
Toggle Fields.

ID_CODE

Bits 0-31: DBG ID code register.

Allowed values: 0-4294967295

CTL0

Control register 0

Offset: 0x4, reset: 0x00000000, access: read-write

23/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIMER10_HOLD
rw 		TIMER9_HOLD
rw 		TIMER8_HOLD
rw 		TIMER13_HOLD
rw 		TIMER12_HOLD
rw 		TIMER11_HOLD
rw 		CAN1_HOLD
rw 		TIMER7_HOLD
rw 		TIMER6_HOLD
rw 		TIMER5_HOLD
rw 		TIMER4_HOLD
rw 		I2C1_HOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C0_HOLD
rw 		CAN0_HOLD
rw 		TIMER3_HOLD
rw 		TIMER2_HOLD
rw 		TIMER1_HOLD
rw 		TIMER0_HOLD
rw 		FWDGT_HOLD
rw 		WWDGT_HOLD
rw 		TRACE_MODE
rw 		TRACE_IOEN
rw 		STB_HOLD
rw 		DSLP_HOLD
rw 		SLP_HOLD
rw
Toggle Fields.

SLP_HOLD

Bit 0: Sleep mode hold register.

Allowed values:
0: Disabled: No effect
1: Enabled: In sleep mode the AHB clock is on

DSLP_HOLD

Bit 1: Deep-sleep mode hold register.

Allowed values:
0: Disabled: No effect
1: Enabled: In deep-sleep mode the AHB clock and system clock are provided by IRC8M

STB_HOLD

Bit 2: Standby mode hold register.

Allowed values:
0: Disabled: No effect
1: Enabled: In standby mode the AHB clock and system clock are provided by IRC8M

TRACE_IOEN

Bit 5: Trace pin allocation enable.

TRACE_MODE

Bits 6-7: Trace pin allocation mode.

WWDGT_HOLD

Bit 8: WWDGT hold bit.

Allowed values:
0: Continue: Continue running the watchdog timer as usual
1: Stop: Hold the watchdog timer for debug when the core is halted

FWDGT_HOLD

Bit 9: FWDGT hold bit.

Allowed values:
0: Continue: Continue running the watchdog timer as usual
1: Stop: Hold the watchdog timer for debug when the core is halted

TIMER0_HOLD

Bit 10: TIMER 0 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER1_HOLD

Bit 11: TIMER 1 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER2_HOLD

Bit 12: TIMER 2 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER3_HOLD

Bit 13: TIMER 23 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

CAN0_HOLD

Bit 14: CAN0 hold bit.

Allowed values:
0: Continue: Continue running CAN as usual
1: Stop: Hold the CAN for debug when the core is halted

I2C0_HOLD

Bit 15: I2C0 hold bit.

Allowed values:
0: Continue: Continue running I2C as usual
1: Stop: Hold the I2C timeout for debug when the core is halted

I2C1_HOLD

Bit 16: I2C1 hold bit.

Allowed values:
0: Continue: Continue running I2C as usual
1: Stop: Hold the I2C timeout for debug when the core is halted

TIMER4_HOLD

Bit 17: TIMER4_HOLD.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER5_HOLD

Bit 18: TIMER 5 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER6_HOLD

Bit 19: TIMER 6 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER7_HOLD

Bit 20: TIMER 7 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

CAN1_HOLD

Bit 21: CAN1 hold bit.

Allowed values:
0: Continue: Continue running CAN as usual
1: Stop: Hold the CAN for debug when the core is halted

TIMER11_HOLD

Bit 25: TIMER 11 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER12_HOLD

Bit 26: TIMER 12 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER13_HOLD

Bit 27: TIMER 13 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER8_HOLD

Bit 28: TIMER 8 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER9_HOLD

Bit 29: TIMER 9 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

TIMER10_HOLD

Bit 30: TIMER 10 hold bit.

Allowed values:
0: Continue: Continue running the timer as usual
1: Stop: Hold the timer counter for debug when the core is halted

DMA0

0x40020000: DMA controller

147/161 fields covered. Toggle Registers.

INTF

Interrupt flag register

Offset: 0x0, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERRIF6
r 		HTFIF6
r 		FTFIF6
r 		GIF6
r 		ERRIF5
r 		HTFIF5
r 		FTFIF5
r 		GIF5
r 		ERRIF4
r 		HTFIF4
r 		FTFIF4
r 		GIF4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIF3
r 		HTFIF3
r 		FTFIF3
r 		GIF3
r 		ERRIF2
r 		HTFIF2
r 		FTFIF2
r 		GIF2
r 		ERRIF1
r 		HTFIF1
r 		FTFIF1
r 		GIF1
r 		ERRIF0
r 		HTFIF0
r 		FTFIF0
r 		GIF0
r
Toggle Fields.

GIF0

Bit 0: Global interrupt flag of channel 0.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF0

Bit 1: Full Transfer finish flag of channe 0.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF0

Bit 2: Half transfer finish flag of channel 0.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF0

Bit 3: Error flag of channel 0.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF1

Bit 4: Global interrupt flag of channel 1.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF1

Bit 5: Full Transfer finish flag of channe 1.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF1

Bit 6: Half transfer finish flag of channel 1.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF1

Bit 7: Error flag of channel 1.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF2

Bit 8: Global interrupt flag of channel 2.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF2

Bit 9: Full Transfer finish flag of channe 2.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF2

Bit 10: Half transfer finish flag of channel 2.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF2

Bit 11: Error flag of channel 2.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF3

Bit 12: Global interrupt flag of channel 3.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF3

Bit 13: Full Transfer finish flag of channe 3.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF3

Bit 14: Half transfer finish flag of channel 3.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF3

Bit 15: Error flag of channel 3.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF4

Bit 16: Global interrupt flag of channel 4.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF4

Bit 17: Full Transfer finish flag of channe 4.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF4

Bit 18: Half transfer finish flag of channel 4.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF4

Bit 19: Error flag of channel 4.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF5

Bit 20: Global interrupt flag of channel 5.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF5

Bit 21: Full Transfer finish flag of channe 5.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF5

Bit 22: Half transfer finish flag of channel 5.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF5

Bit 23: Error flag of channel 5.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF6

Bit 24: Global interrupt flag of channel 6.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF6

Bit 25: Full Transfer finish flag of channe 6.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF6

Bit 26: Half transfer finish flag of channel 6.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF6

Bit 27: Error flag of channel 6.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

INTC

Interrupt flag clear register

Offset: 0x4, reset: 0x00000000, access: write-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERRIFC6
w 		HTFIFC6
w 		FTFIFC6
w 		GIFC6
w 		ERRIFC5
w 		HTFIFC5
w 		FTFIFC5
w 		GIFC5
w 		ERRIFC4
w 		HTFIFC4
w 		FTFIFC4
w 		GIFC4
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIFC3
w 		HTFIFC3
w 		FTFIFC3
w 		GIFC3
w 		ERRIFC2
w 		HTFIFC2
w 		FTFIFC2
w 		GIFC2
w 		ERRIFC1
w 		HTFIFC1
w 		FTFIFC1
w 		GIFC1
w 		ERRIFC0
w 		HTFIFC0
w 		FTFIFC0
w 		GIFC0
w
Toggle Fields.

GIFC0

Bit 0: Clear global interrupt flag of channel 0.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC0

Bit 1: Clear bit for full transfer finish flag of channel 0.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC0

Bit 2: Clear bit for half transfer finish flag of channel 0.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC0

Bit 3: Clear bit for error flag of channel 0.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC1

Bit 4: Clear global interrupt flag of channel 1.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC1

Bit 5: Clear bit for full transfer finish flag of channel 1.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC1

Bit 6: Clear bit for half transfer finish flag of channel 1.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC1

Bit 7: Clear bit for error flag of channel 1.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC2

Bit 8: Clear global interrupt flag of channel 2.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC2

Bit 9: Clear bit for full transfer finish flag of channel 2.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC2

Bit 10: Clear bit for half transfer finish flag of channel 2.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC2

Bit 11: Clear bit for error flag of channel 2.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC3

Bit 12: Clear global interrupt flag of channel 3.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC3

Bit 13: Clear bit for full transfer finish flag of channel 3.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC3

Bit 14: Clear bit for half transfer finish flag of channel 3.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC3

Bit 15: Clear bit for error flag of channel 3.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC4

Bit 16: Clear global interrupt flag of channel 4.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC4

Bit 17: Clear bit for full transfer finish flag of channel 4.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC4

Bit 18: Clear bit for half transfer finish flag of channel 4.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC4

Bit 19: Clear bit for error flag of channel 4.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC5

Bit 20: Clear global interrupt flag of channel 5.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC5

Bit 21: Clear bit for full transfer finish flag of channel 5.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC5

Bit 22: Clear bit for half transfer finish flag of channel 5.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC5

Bit 23: Clear bit for error flag of channel 5.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC6

Bit 24: Clear global interrupt flag of channel 6.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC6

Bit 25: Clear bit for full transfer finish flag of channel 6.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC6

Bit 26: Clear bit for half transfer finish flag of channel 6.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC6

Bit 27: Clear bit for error flag of channel 6.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

CH0CTL

Channel 0 control register

Offset: 0x8, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH0CNT

Channel 0 counter register

Offset: 0xC, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH0PADDR

Channel 0 peripheral base address register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH0MADDR

Channel 0 memory base address register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH1CTL

Channel 1 control register

Offset: 0x1C, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH1CNT

Channel 1 counter register

Offset: 0x20, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH1PADDR

Channel 1 peripheral base address register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH1MADDR

Channel 1 memory base address register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH2CTL

Channel 2 control register

Offset: 0x30, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH2CNT

Channel 2 counter register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH2PADDR

Channel 2 peripheral base address register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH2MADDR

Channel 2 memory base address register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH3CTL

Channel 3 control register

Offset: 0x44, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH3CNT

Channel 3 counter register

Offset: 0x48, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH3PADDR

Channel 3 peripheral base address register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH3MADDR

Channel 3 memory base address register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH4CTL

Channel 4 control register

Offset: 0x58, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH4CNT

Channel 4 counter register

Offset: 0x5C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH4PADDR

Channel 4 peripheral base address register

Offset: 0x60, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH4MADDR

Channel 4 memory base address register

Offset: 0x64, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH5CTL

Channel 5 control register

Offset: 0x6C, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH5CNT

Channel 5 counter register

Offset: 0x70, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH5PADDR

Channel 5 peripheral base address register

Offset: 0x74, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH5MADDR

Channel 5 memory base address register

Offset: 0x78, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH6CTL

Channel 6 control register

Offset: 0x80, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH6CNT

Channel 6 counter register

Offset: 0x84, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH6PADDR

Channel 6 peripheral base address register

Offset: 0x88, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH6MADDR

Channel 6 memory base address register

Offset: 0x8C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

DMA1

0x40020400: DMA controller

147/161 fields covered. Toggle Registers.

INTF

Interrupt flag register

Offset: 0x0, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERRIF6
r 		HTFIF6
r 		FTFIF6
r 		GIF6
r 		ERRIF5
r 		HTFIF5
r 		FTFIF5
r 		GIF5
r 		ERRIF4
r 		HTFIF4
r 		FTFIF4
r 		GIF4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIF3
r 		HTFIF3
r 		FTFIF3
r 		GIF3
r 		ERRIF2
r 		HTFIF2
r 		FTFIF2
r 		GIF2
r 		ERRIF1
r 		HTFIF1
r 		FTFIF1
r 		GIF1
r 		ERRIF0
r 		HTFIF0
r 		FTFIF0
r 		GIF0
r
Toggle Fields.

GIF0

Bit 0: Global interrupt flag of channel 0.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF0

Bit 1: Full Transfer finish flag of channe 0.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF0

Bit 2: Half transfer finish flag of channel 0.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF0

Bit 3: Error flag of channel 0.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF1

Bit 4: Global interrupt flag of channel 1.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF1

Bit 5: Full Transfer finish flag of channe 1.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF1

Bit 6: Half transfer finish flag of channel 1.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF1

Bit 7: Error flag of channel 1.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF2

Bit 8: Global interrupt flag of channel 2.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF2

Bit 9: Full Transfer finish flag of channe 2.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF2

Bit 10: Half transfer finish flag of channel 2.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF2

Bit 11: Error flag of channel 2.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF3

Bit 12: Global interrupt flag of channel 3.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF3

Bit 13: Full Transfer finish flag of channe 3.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF3

Bit 14: Half transfer finish flag of channel 3.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF3

Bit 15: Error flag of channel 3.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF4

Bit 16: Global interrupt flag of channel 4.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF4

Bit 17: Full Transfer finish flag of channe 4.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF4

Bit 18: Half transfer finish flag of channel 4.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF4

Bit 19: Error flag of channel 4.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF5

Bit 20: Global interrupt flag of channel 5.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF5

Bit 21: Full Transfer finish flag of channe 5.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF5

Bit 22: Half transfer finish flag of channel 5.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF5

Bit 23: Error flag of channel 5.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF6

Bit 24: Global interrupt flag of channel 6.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

FTFIF6

Bit 25: Full Transfer finish flag of channe 6.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTFIF6

Bit 26: Half transfer finish flag of channel 6.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

ERRIF6

Bit 27: Error flag of channel 6.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

INTC

Interrupt flag clear register

Offset: 0x4, reset: 0x00000000, access: write-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERRIFC6
w 		HTFIFC6
w 		FTFIFC6
w 		GIFC6
w 		ERRIFC5
w 		HTFIFC5
w 		FTFIFC5
w 		GIFC5
w 		ERRIFC4
w 		HTFIFC4
w 		FTFIFC4
w 		GIFC4
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIFC3
w 		HTFIFC3
w 		FTFIFC3
w 		GIFC3
w 		ERRIFC2
w 		HTFIFC2
w 		FTFIFC2
w 		GIFC2
w 		ERRIFC1
w 		HTFIFC1
w 		FTFIFC1
w 		GIFC1
w 		ERRIFC0
w 		HTFIFC0
w 		FTFIFC0
w 		GIFC0
w
Toggle Fields.

GIFC0

Bit 0: Clear global interrupt flag of channel 0.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC0

Bit 1: Clear bit for full transfer finish flag of channel 0.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC0

Bit 2: Clear bit for half transfer finish flag of channel 0.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC0

Bit 3: Clear bit for error flag of channel 0.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC1

Bit 4: Clear global interrupt flag of channel 1.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC1

Bit 5: Clear bit for full transfer finish flag of channel 1.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC1

Bit 6: Clear bit for half transfer finish flag of channel 1.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC1

Bit 7: Clear bit for error flag of channel 1.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC2

Bit 8: Clear global interrupt flag of channel 2.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC2

Bit 9: Clear bit for full transfer finish flag of channel 2.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC2

Bit 10: Clear bit for half transfer finish flag of channel 2.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC2

Bit 11: Clear bit for error flag of channel 2.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC3

Bit 12: Clear global interrupt flag of channel 3.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC3

Bit 13: Clear bit for full transfer finish flag of channel 3.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC3

Bit 14: Clear bit for half transfer finish flag of channel 3.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC3

Bit 15: Clear bit for error flag of channel 3.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC4

Bit 16: Clear global interrupt flag of channel 4.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC4

Bit 17: Clear bit for full transfer finish flag of channel 4.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC4

Bit 18: Clear bit for half transfer finish flag of channel 4.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC4

Bit 19: Clear bit for error flag of channel 4.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC5

Bit 20: Clear global interrupt flag of channel 5.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC5

Bit 21: Clear bit for full transfer finish flag of channel 5.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC5

Bit 22: Clear bit for half transfer finish flag of channel 5.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC5

Bit 23: Clear bit for error flag of channel 5.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

GIFC6

Bit 24: Clear global interrupt flag of channel 6.

Allowed values:
1: Clear: Clears the GIF flag in INTF

FTFIFC6

Bit 25: Clear bit for full transfer finish flag of channel 6.

Allowed values:
1: Clear: Clears the FDFIF flag in INTF

HTFIFC6

Bit 26: Clear bit for half transfer finish flag of channel 6.

Allowed values:
1: Clear: Clears the HTFIF flag in INTF

ERRIFC6

Bit 27: Clear bit for error flag of channel 6.

Allowed values:
1: Clear: Clears the ERRIF flag in INTF

CH0CTL

Channel 0 control register

Offset: 0x8, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH0CNT

Channel 0 counter register

Offset: 0xC, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH0PADDR

Channel 0 peripheral base address register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH0MADDR

Channel 0 memory base address register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH1CTL

Channel 1 control register

Offset: 0x1C, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH1CNT

Channel 1 counter register

Offset: 0x20, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH1PADDR

Channel 1 peripheral base address register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH1MADDR

Channel 1 memory base address register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH2CTL

Channel 2 control register

Offset: 0x30, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH2CNT

Channel 2 counter register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH2PADDR

Channel 2 peripheral base address register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH2MADDR

Channel 2 memory base address register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH3CTL

Channel 3 control register

Offset: 0x44, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH3CNT

Channel 3 counter register

Offset: 0x48, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH3PADDR

Channel 3 peripheral base address register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH3MADDR

Channel 3 memory base address register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH4CTL

Channel 4 control register

Offset: 0x58, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH4CNT

Channel 4 counter register

Offset: 0x5C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH4PADDR

Channel 4 peripheral base address register

Offset: 0x60, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH4MADDR

Channel 4 memory base address register

Offset: 0x64, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH5CTL

Channel 5 control register

Offset: 0x6C, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH5CNT

Channel 5 counter register

Offset: 0x70, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH5PADDR

Channel 5 peripheral base address register

Offset: 0x74, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH5MADDR

Channel 5 memory base address register

Offset: 0x78, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

CH6CTL

Channel 6 control register

Offset: 0x80, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M2M
rw 		PRIO
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		DIR
rw 		ERRIE
rw 		HTFIE
rw 		FTFIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

FTFIE

Bit 1: Enable bit for channel full transfer finish interrupt.

Allowed values:
0: Disabled: Full transfer interrupt disabled
1: Enabled: Full transfer interrupt enabled

HTFIE

Bit 2: Enable bit for channel half transfer finish interrupt.

Allowed values:
0: Disabled: Half transfer interrupt disabled
1: Enabled: Half transfer interrupt enabled

ERRIE

Bit 3: Enable bit for channel error interrupt.

Allowed values:
0: Disabled: Transfer error interrupt disabled
1: Enabled: Transfer error interrupt enabled

DIR

Bit 4: Transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CMEN

Bit 5: Circular mode enable.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PNAGA

Bit 6: Next address generation algorithm of peripheral.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

MNAGA

Bit 7: Next address generation algorithm of memory.

Allowed values:
0: Fixed: Fixed address mode
1: Increment: Increment address mode

PWIDTH

Bits 8-9: Transfer data size of peripheral.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MWIDTH

Bits 10-11: Transfer data size of memory.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PRIO

Bits 12-13: Priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

M2M

Bit 14: Memory to Memory Mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CH6CNT

Channel 6 counter register

Offset: 0x84, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

Allowed values: 0-65535

CH6PADDR

Channel 6 peripheral base address register

Offset: 0x88, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH6MADDR

Channel 6 memory base address register

Offset: 0x8C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MADDR
rw
Toggle Fields.

MADDR

Bits 0-31: Memory base address.

EXMC

0xA0000000: External memory controller

2/183 fields covered. Toggle Registers.

SNCTL0

SRAM/NOR flash control register 0

Offset: 0x0, reset: 0x000030DB, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCWR
rw 		CPS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXMODEN
rw 		NRWTEN
rw 		WREN
rw 		NRWTCFG
rw 		WRAPEN
rw 		NRWTPOL
rw 		SBRSTEN
rw 		NREN
rw 		NRW
rw 		NRTP
rw 		NRMUX
rw 		NRBKEN
rw
Toggle Fields.

NRBKEN

Bit 0: NOR bank enable.

NRMUX

Bit 1: NOR bank memory address/data multiplexing.

NRTP

Bits 2-3: NOR bank memory type.

NRW

Bits 4-5: NOR bank memory data bus width.

NREN

Bit 6: NOR Flash access enable.

SBRSTEN

Bit 8: Synchronous burst enable.

NRWTPOL

Bit 9: NWAIT signal polarity.

WRAPEN

Bit 10: Wrapped burst mode enable.

NRWTCFG

Bit 11: NWAIT signal configuration, only work in synchronous mode.

WREN

Bit 12: Write enable.

NRWTEN

Bit 13: NWAIT signal enable.

EXMODEN

Bit 14: Extended mode enable.

ASYNCWAIT

Bit 15: Asynchronous wait.

CPS

Bits 16-18: CRAM page size.

SYNCWR

Bit 19: Synchronous write.

SNTCFG0

SRAM/NOR flash timing configuration register 0

Offset: 0x4, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ASYNCMOD
rw 		DLAT
rw 		CKDIV
rw 		BUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSET
rw 		AHLD
rw 		ASET
rw
Toggle Fields.

ASET

Bits 0-3: Address setup time.

AHLD

Bits 4-7: Address hold time.

DSET

Bits 8-15: Data setup time.

BUSLAT

Bits 16-19: Bus latency.

CKDIV

Bits 20-23: Synchronous clock divide ratio.

DLAT

Bits 24-27: Data latency for NOR Flash.

ASYNCMOD

Bits 28-29: Asynchronous access mode.

SNCTL1

SRAM/NOR flash control register 1

Offset: 0x8, reset: 0x000030D2, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCWR
rw 		CPS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXMODEN
rw 		NRWTEN
rw 		WREN
rw 		NRWTCFG
rw 		WRAPEN
rw 		NRWTPOL
rw 		SBRSTEN
rw 		NREN
rw 		NRW
rw 		NRTP
rw 		NRMUX
rw 		NRBKEN
rw
Toggle Fields.

NRBKEN

Bit 0: NOR bank enable.

NRMUX

Bit 1: NOR bank memory address/data multiplexing.

NRTP

Bits 2-3: NOR bank memory type.

NRW

Bits 4-5: NOR bank memory data bus width.

NREN

Bit 6: NOR Flash access enable.

SBRSTEN

Bit 8: Synchronous burst enable.

NRWTPOL

Bit 9: NWAIT signal polarity.

WRAPEN

Bit 10: Wrapped burst mode enable.

NRWTCFG

Bit 11: NWAIT signal configuration, only work in synchronous mode.

WREN

Bit 12: Write enable.

NRWTEN

Bit 13: NWAIT signal enable.

EXMODEN

Bit 14: Extended mode enable.

ASYNCWAIT

Bit 15: Asynchronous wait.

CPS

Bits 16-18: CRAM page size.

SYNCWR

Bit 19: Synchronous write.

SNTCFG1

SRAM/NOR flash timing configuration register 1

Offset: 0xC, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ASYNCMOD
rw 		DLAT
rw 		CKDIV
rw 		BUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSET
rw 		AHLD
rw 		ASET
rw
Toggle Fields.

ASET

Bits 0-3: Address setup time.

AHLD

Bits 4-7: Address hold time.

DSET

Bits 8-15: Data setup time.

BUSLAT

Bits 16-19: Bus latency.

CKDIV

Bits 20-23: Synchronous clock divide ratio.

DLAT

Bits 24-27: Data latency for NOR Flash.

ASYNCMOD

Bits 28-29: Asynchronous access mode.

SNCTL2

SRAM/NOR flash control register 2

Offset: 0x10, reset: 0x000030D2, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCWR
rw 		CPS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXMODEN
rw 		NRWTEN
rw 		WREN
rw 		NRWTCFG
rw 		WRAPEN
rw 		NRWTPOL
rw 		SBRSTEN
rw 		NREN
rw 		NRW
rw 		NRTP
rw 		NRMUX
rw 		NRBKEN
rw
Toggle Fields.

NRBKEN

Bit 0: NOR bank enable.

NRMUX

Bit 1: NOR bank memory address/data multiplexing.

NRTP

Bits 2-3: NOR bank memory type.

NRW

Bits 4-5: NOR bank memory data bus width.

NREN

Bit 6: NOR Flash access enable.

SBRSTEN

Bit 8: Synchronous burst enable.

NRWTPOL

Bit 9: NWAIT signal polarity.

WRAPEN

Bit 10: Wrapped burst mode enable.

NRWTCFG

Bit 11: NWAIT signal configuration, only work in synchronous mode.

WREN

Bit 12: Write enable.

NRWTEN

Bit 13: NWAIT signal enable.

EXMODEN

Bit 14: Extended mode enable.

ASYNCWAIT

Bit 15: Asynchronous wait.

CPS

Bits 16-18: CRAM page size.

SYNCWR

Bit 19: Synchronous write.

SNTCFG2

SRAM/NOR flash timing configuration register 2

Offset: 0x14, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ASYNCMOD
rw 		DLAT
rw 		CKDIV
rw 		BUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSET
rw 		AHLD
rw 		ASET
rw
Toggle Fields.

ASET

Bits 0-3: Address setup time.

AHLD

Bits 4-7: Address hold time.

DSET

Bits 8-15: Data setup time.

BUSLAT

Bits 16-19: Bus latency.

CKDIV

Bits 20-23: Synchronous clock divide ratio.

DLAT

Bits 24-27: Data latency for NOR Flash.

ASYNCMOD

Bits 28-29: Asynchronous access mode.

SNCTL3

SRAM/NOR flash control register 3

Offset: 0x18, reset: 0x000030D2, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCWR
rw 		CPS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXMODEN
rw 		NRWTEN
rw 		WREN
rw 		NRWTCFG
rw 		WRAPEN
rw 		NRWTPOL
rw 		SBRSTEN
rw 		NREN
rw 		NRW
rw 		NRTP
rw 		NRMUX
rw 		NRBKEN
rw
Toggle Fields.

NRBKEN

Bit 0: NOR bank enable.

NRMUX

Bit 1: NOR bank memory address/data multiplexing.

NRTP

Bits 2-3: NOR bank memory type.

NRW

Bits 4-5: NOR bank memory data bus width.

NREN

Bit 6: NOR Flash access enable.

SBRSTEN

Bit 8: Synchronous burst enable.

NRWTPOL

Bit 9: NWAIT signal polarity.

WRAPEN

Bit 10: Wrapped burst mode enable.

NRWTCFG

Bit 11: NWAIT signal configuration, only work in synchronous mode.

WREN

Bit 12: Write enable.

NRWTEN

Bit 13: NWAIT signal enable.

EXMODEN

Bit 14: Extended mode enable.

ASYNCWAIT

Bit 15: Asynchronous wait.

CPS

Bits 16-18: CRAM page size.

SYNCWR

Bit 19: Synchronous write.

SNTCFG3

SRAM/NOR flash timing configuration register 3

Offset: 0x1C, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ASYNCMOD
rw 		DLAT
rw 		CKDIV
rw 		BUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSET
rw 		AHLD
rw 		ASET
rw
Toggle Fields.

ASET

Bits 0-3: Address setup time.

AHLD

Bits 4-7: Address hold time.

DSET

Bits 8-15: Data setup time.

BUSLAT

Bits 16-19: Bus latency.

CKDIV

Bits 20-23: Synchronous clock divide ratio.

DLAT

Bits 24-27: Data latency for NOR Flash.

ASYNCMOD

Bits 28-29: Asynchronous access mode.

NPCTL1

NAND flash/PC card control register 1

Offset: 0x60, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCSZ
rw 		ATR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATR
rw 		CTR
rw 		ECCEN
rw 		NDW
rw 		NDTP
rw 		NDBKEN
rw 		NDWTEN
rw
Toggle Fields.

NDWTEN

Bit 1: Wait feature enable.

NDBKEN

Bit 2: NAND bank enable.

NDTP

Bit 3: NAND bank memory type.

NDW

Bits 4-5: NAND bank memory data bus width.

ECCEN

Bit 6: ECC enable.

CTR

Bits 9-12: CLE to RE delay.

ATR

Bits 13-16: ALE to RE delay.

ECCSZ

Bits 17-19: ECC size.

NPINTEN1

NAND flash/PC card interrupt enable register 1

Offset: 0x64, reset: 0x00000040, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFEPT
rw 		INTFEN
rw 		INTHEN
rw 		INTREN
rw 		INTFS
rw 		INTHS
rw 		INTRS
rw
Toggle Fields.

INTRS

Bit 0: Interrupt rising edge status.

INTHS

Bit 1: Interrupt high-level status.

INTFS

Bit 2: Interrupt falling edge status.

INTREN

Bit 3: Interrupt rising edge detection enable bit.

INTHEN

Bit 4: Interrupt high-level detection enable.

INTFEN

Bit 5: Interrupt falling edge detection enable.

FFEPT

Bit 6: FIFO empty flag.

NPCTCFG1

NAND flash/PC card common space timing configuration register 1

Offset: 0x68, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMHIZ
rw 		COMHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMWAIT
rw 		COMSET
rw
Toggle Fields.

COMSET

Bits 0-7: Common memory setup time.

COMWAIT

Bits 8-15: Common memory wait time.

COMHLD

Bits 16-23: Common memory hold time.

COMHIZ

Bits 24-31: Common memory data bus HiZ time.

NPATCFG1

NAND flash/PC card attribute space timing configuration register 1

Offset: 0x6C, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw 		ATTHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw 		ATTSET
rw
Toggle Fields.

ATTSET

Bits 0-7: Attribute memory setup time.

ATTWAIT

Bits 8-15: Attribute memory wait time.

ATTHLD

Bits 16-23: Attribute memory hold time.

ATTHIZ

Bits 24-31: Attribute memory data bus HiZ time.

NECC1

NAND flash ECC register 1

Offset: 0x74, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC
r
Toggle Fields.

ECC

Bits 0-31: ECC result.

NPCTL2

NAND flash/PC card control register 2

Offset: 0x80, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCSZ
rw 		ATR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATR
rw 		CTR
rw 		ECCEN
rw 		NDW
rw 		NDTP
rw 		NDBKEN
rw 		NDWTEN
rw
Toggle Fields.

NDWTEN

Bit 1: Wait feature enable.

NDBKEN

Bit 2: NAND bank enable.

NDTP

Bit 3: NAND bank memory type.

NDW

Bits 4-5: NAND bank memory data bus width.

ECCEN

Bit 6: ECC enable.

CTR

Bits 9-12: CLE to RE delay.

ATR

Bits 13-16: ALE to RE delay.

ECCSZ

Bits 17-19: ECC size.

NPINTEN2

NAND flash/PC card interrupt enable register 2

Offset: 0x84, reset: 0x00000040, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFEPT
rw 		INTFEN
rw 		INTHEN
rw 		INTREN
rw 		INTFS
rw 		INTHS
rw 		INTRS
rw
Toggle Fields.

INTRS

Bit 0: Interrupt rising edge status.

INTHS

Bit 1: Interrupt high-level status.

INTFS

Bit 2: Interrupt falling edge status.

INTREN

Bit 3: Interrupt rising edge detection enable bit.

INTHEN

Bit 4: Interrupt high-level detection enable.

INTFEN

Bit 5: Interrupt falling edge detection enable.

FFEPT

Bit 6: FIFO empty flag.

NPCTCFG2

NAND flash/PC card common space timing configuration register 2

Offset: 0x88, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMHIZ
rw 		COMHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMWAIT
rw 		COMSET
rw
Toggle Fields.

COMSET

Bits 0-7: Common memory setup time.

COMWAIT

Bits 8-15: Common memory wait time.

COMHLD

Bits 16-23: Common memory hold time.

COMHIZ

Bits 24-31: Common memory data bus HiZ time.

NPATCFG2

NAND flash/PC card attribute space timing configuration register 2

Offset: 0x8C, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw 		ATTHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw 		ATTSET
rw
Toggle Fields.

ATTSET

Bits 0-7: Attribute memory setup time.

ATTWAIT

Bits 8-15: Attribute memory wait time.

ATTHLD

Bits 16-23: Attribute memory hold time.

ATTHIZ

Bits 24-31: Attribute memory data bus HiZ time.

NECC2

NAND flash ECC register 2

Offset: 0x94, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC
r
Toggle Fields.

ECC

Bits 0-31: ECC result.

NPCTL3

NAND flash/PC card control register 3

Offset: 0xA0, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCSZ
rw 		ATR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATR
rw 		CTR
rw 		ECCEN
rw 		NDW
rw 		NDTP
rw 		NDBKEN
rw 		NDWTEN
rw
Toggle Fields.

NDWTEN

Bit 1: Wait feature enable.

NDBKEN

Bit 2: NAND bank enable.

NDTP

Bit 3: NAND bank memory type.

NDW

Bits 4-5: NAND bank memory data bus width.

ECCEN

Bit 6: ECC enable.

CTR

Bits 9-12: CLE to RE delay.

ATR

Bits 13-16: ALE to RE delay.

ECCSZ

Bits 17-19: ECC size.

NPINTEN3

NAND flash/PC card interrupt enable register 3

Offset: 0xA4, reset: 0x00000040, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFEPT
rw 		INTFEN
rw 		INTHEN
rw 		INTREN
rw 		INTFS
rw 		INTHS
rw 		INTRS
rw
Toggle Fields.

INTRS

Bit 0: Interrupt rising edge status.

INTHS

Bit 1: Interrupt high-level status.

INTFS

Bit 2: Interrupt falling edge status.

INTREN

Bit 3: Interrupt rising edge detection enable bit.

INTHEN

Bit 4: Interrupt high-level detection enable.

INTFEN

Bit 5: Interrupt falling edge detection enable.

FFEPT

Bit 6: FIFO empty flag.

NPCTCFG3

NAND flash/PC card common space timing configuration register 3

Offset: 0xA8, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMHIZ
rw 		COMHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMWAIT
rw 		COMSET
rw
Toggle Fields.

COMSET

Bits 0-7: Common memory setup time.

COMWAIT

Bits 8-15: Common memory wait time.

COMHLD

Bits 16-23: Common memory hold time.

COMHIZ

Bits 24-31: Common memory data bus HiZ time.

NPATCFG3

NAND flash/PC card attribute space timing configuration register 3

Offset: 0xAC, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw 		ATTHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw 		ATTSET
rw
Toggle Fields.

ATTSET

Bits 0-7: Attribute memory setup time.

ATTWAIT

Bits 8-15: Attribute memory wait time.

ATTHLD

Bits 16-23: Attribute memory hold time.

ATTHIZ

Bits 24-31: Attribute memory data bus HiZ time.

PIOTCFG3

PC card I/O space timing configuration register

Offset: 0xB0, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOHIZ
rw 		IOHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOWAIT
rw 		IOSET
rw
Toggle Fields.

IOSET

Bits 0-7: IO space setup time.

IOWAIT

Bits 8-15: IO space wait time.

IOHLD

Bits 16-23: IO space hold time.

IOHIZ

Bits 24-31: IO space data bus HiZ time.

SNWTCFG0

SRAM/NOR flash write timing configuration register 0

Offset: 0x104, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WASYNCMOD
rw 		WBUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDSET
rw 		WAHLD
rw 		WASET
rw
Toggle Fields.

WASET

Bits 0-3: Address setup time.

WAHLD

Bits 4-7: Address hold time.

WDSET

Bits 8-15: Data setup time.

WBUSLAT

Bits 16-19: Bus latency.

WASYNCMOD

Bits 28-29: Asynchronous access mode.

SNWTCFG1

SRAM/NOR flash write timing configuration register 1

Offset: 0x10C, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WASYNCMOD
rw 		WBUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDSET
rw 		WAHLD
rw 		WASET
rw
Toggle Fields.

WASET

Bits 0-3: Address setup time.

WAHLD

Bits 4-7: Address hold time.

WDSET

Bits 8-15: Data setup time.

WBUSLAT

Bits 16-19: Bus latency.

WASYNCMOD

Bits 28-29: Asynchronous access mode.

SNWTCFG2

SRAM/NOR flash write timing configuration register 2

Offset: 0x114, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WASYNCMOD
rw 		WBUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDSET
rw 		WAHLD
rw 		WASET
rw
Toggle Fields.

WASET

Bits 0-3: Address setup time.

WAHLD

Bits 4-7: Address hold time.

WDSET

Bits 8-15: Data setup time.

WBUSLAT

Bits 16-19: Bus latency.

WASYNCMOD

Bits 28-29: Asynchronous access mode.

SNWTCFG3

SRAM/NOR flash write timing configuration register 3

Offset: 0x11C, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WASYNCMOD
rw 		WBUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDSET
rw 		WAHLD
rw 		WASET
rw
Toggle Fields.

WASET

Bits 0-3: Address setup time.

WAHLD

Bits 4-7: Address hold time.

WDSET

Bits 8-15: Data setup time.

WBUSLAT

Bits 16-19: Bus latency.

WASYNCMOD

Bits 28-29: Asynchronous access mode.

EXTI

0x40010400: External interrupt/event controller

120/120 fields covered. Toggle Registers.

INTEN

Interrupt enable register (EXTI_INTEN)

Offset: 0x0, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INTEN19
rw 		INTEN18
rw 		INTEN17
rw 		INTEN16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTEN15
rw 		INTEN14
rw 		INTEN13
rw 		INTEN12
rw 		INTEN11
rw 		INTEN10
rw 		INTEN9
rw 		INTEN8
rw 		INTEN7
rw 		INTEN6
rw 		INTEN5
rw 		INTEN4
rw 		INTEN3
rw 		INTEN2
rw 		INTEN1
rw 		INTEN0
rw
Toggle Fields.

INTEN0

Bit 0: Enable Interrupt on line 0.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN1

Bit 1: Enable Interrupt on line 1.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN2

Bit 2: Enable Interrupt on line 2.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN3

Bit 3: Enable Interrupt on line 3.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN4

Bit 4: Enable Interrupt on line 4.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN5

Bit 5: Enable Interrupt on line 5.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN6

Bit 6: Enable Interrupt on line 6.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN7

Bit 7: Enable Interrupt on line 7.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN8

Bit 8: Enable Interrupt on line 8.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN9

Bit 9: Enable Interrupt on line 9.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN10

Bit 10: Enable Interrupt on line 10.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN11

Bit 11: Enable Interrupt on line 11.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN12

Bit 12: Enable Interrupt on line 12.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN13

Bit 13: Enable Interrupt on line 13.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN14

Bit 14: Enable Interrupt on line 14.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN15

Bit 15: Enable Interrupt on line 15.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN16

Bit 16: Enable Interrupt on line 16.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN17

Bit 17: Enable Interrupt on line 17.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN18

Bit 18: Enable Interrupt on line 18.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

INTEN19

Bit 19: Enable Interrupt on line 19.

Allowed values:
0: Masked: Interrupt from line is disabled
1: Unmasked: Interrupt from line is enabled

EVEN

Event enable register (EXTI_EVEN)

Offset: 0x4, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EVEN19
rw 		EVEN18
rw 		EVEN17
rw 		EVEN16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EVEN15
rw 		EVEN14
rw 		EVEN13
rw 		EVEN12
rw 		EVEN11
rw 		EVEN10
rw 		EVEN9
rw 		EVEN8
rw 		EVEN7
rw 		EVEN6
rw 		EVEN5
rw 		EVEN4
rw 		EVEN3
rw 		EVEN2
rw 		EVEN1
rw 		EVEN0
rw
Toggle Fields.

EVEN0

Bit 0: Enable Event on line 0.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN1

Bit 1: Enable Event on line 1.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN2

Bit 2: Enable Event on line 2.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN3

Bit 3: Enable Event on line 3.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN4

Bit 4: Enable Event on line 4.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN5

Bit 5: Enable Event on line 5.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN6

Bit 6: Enable Event on line 6.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN7

Bit 7: Enable Event on line 7.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN8

Bit 8: Enable Event on line 8.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN9

Bit 9: Enable Event on line 9.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN10

Bit 10: Enable Event on line 10.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN11

Bit 11: Enable Event on line 11.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN12

Bit 12: Enable Event on line 12.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN13

Bit 13: Enable Event on line 13.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN14

Bit 14: Enable Event on line 14.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN15

Bit 15: Enable Event on line 15.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN16

Bit 16: Enable Event on line 16.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN17

Bit 17: Enable Event on line 17.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN18

Bit 18: Enable Event on line 18.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

EVEN19

Bit 19: Enable Event on line 19.

Allowed values:
0: Masked: Event from line is disabled
1: Unmasked: Event from line is enabled

RTEN

Rising Edge Trigger Enable register (EXTI_RTEN)

Offset: 0x8, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTEN19
rw 		RTEN18
rw 		RTEN17
rw 		RTEN16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTEN15
rw 		RTEN14
rw 		RTEN13
rw 		RTEN12
rw 		RTEN11
rw 		RTEN10
rw 		RTEN9
rw 		RTEN8
rw 		RTEN7
rw 		RTEN6
rw 		RTEN5
rw 		RTEN4
rw 		RTEN3
rw 		RTEN2
rw 		RTEN1
rw 		RTEN0
rw
Toggle Fields.

RTEN0

Bit 0: Rising edge trigger enable of line 0.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN1

Bit 1: Rising edge trigger enable of line 1.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN2

Bit 2: Rising edge trigger enable of line 2.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN3

Bit 3: Rising edge trigger enable of line 3.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN4

Bit 4: Rising edge trigger enable of line 4.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN5

Bit 5: Rising edge trigger enable of line 5.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN6

Bit 6: Rising edge trigger enable of line 6.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN7

Bit 7: Rising edge trigger enable of line 7.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN8

Bit 8: Rising edge trigger enable of line 8.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN9

Bit 9: Rising edge trigger enable of line 9.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN10

Bit 10: Rising edge trigger enable of line 10.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN11

Bit 11: Rising edge trigger enable of line 11.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN12

Bit 12: Rising edge trigger enable of line 12.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN13

Bit 13: Rising edge trigger enable of line 13.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN14

Bit 14: Rising edge trigger enable of line 14.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN15

Bit 15: Rising edge trigger enable of line 15.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN16

Bit 16: Rising edge trigger enable of line 16.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN17

Bit 17: Rising edge trigger enable of line 17.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN18

Bit 18: Rising edge trigger enable of line 18.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RTEN19

Bit 19: Rising edge trigger enable of line 19.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTEN

Falling Egde Trigger Enable register (EXTI_FTEN)

Offset: 0xC, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTEN19
rw 		FTEN18
rw 		FTEN17
rw 		FTEN16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTEN15
rw 		FTEN14
rw 		FTEN13
rw 		FTEN12
rw 		FTEN11
rw 		FTEN10
rw 		FTEN9
rw 		FTEN8
rw 		FTEN7
rw 		FTEN6
rw 		FTEN5
rw 		FTEN4
rw 		FTEN3
rw 		FTEN2
rw 		FTEN1
rw 		FTEN0
rw
Toggle Fields.

FTEN0

Bit 0: Falling edge trigger enable of line 0.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN1

Bit 1: Falling edge trigger enable of line 1.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN2

Bit 2: Falling edge trigger enable of line 2.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN3

Bit 3: Falling edge trigger enable of line 3.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN4

Bit 4: Falling edge trigger enable of line 4.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN5

Bit 5: Falling edge trigger enable of line 5.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN6

Bit 6: Falling edge trigger enable of line 6.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN7

Bit 7: Falling edge trigger enable of line 7.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN8

Bit 8: Falling edge trigger enable of line 8.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN9

Bit 9: Falling edge trigger enable of line 9.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN10

Bit 10: Falling edge trigger enable of line 10.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN11

Bit 11: Falling edge trigger enable of line 11.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN12

Bit 12: Falling edge trigger enable of line 12.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN13

Bit 13: Falling edge trigger enable of line 13.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN14

Bit 14: Falling edge trigger enable of line 14.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN15

Bit 15: Falling edge trigger enable of line 15.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN16

Bit 16: Falling edge trigger enable of line 16.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN17

Bit 17: Falling edge trigger enable of line 17.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN18

Bit 18: Falling edge trigger enable of line 18.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FTEN19

Bit 19: Falling edge trigger enable of line 19.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIEV

Software interrupt event register (EXTI_SWIEV)

Offset: 0x10, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWIEV19
rw 		SWIEV18
rw 		SWIEV17
rw 		SWIEV16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWIEV15
rw 		SWIEV14
rw 		SWIEV13
rw 		SWIEV12
rw 		SWIEV11
rw 		SWIEV10
rw 		SWIEV9
rw 		SWIEV8
rw 		SWIEV7
rw 		SWIEV6
rw 		SWIEV5
rw 		SWIEV4
rw 		SWIEV3
rw 		SWIEV2
rw 		SWIEV1
rw 		SWIEV0
rw
Toggle Fields.

SWIEV0

Bit 0: Interrupt/Event software trigger on line 0.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV1

Bit 1: Interrupt/Event software trigger on line 1.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV2

Bit 2: Interrupt/Event software trigger on line 2.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV3

Bit 3: Interrupt/Event software trigger on line 3.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV4

Bit 4: Interrupt/Event software trigger on line 4.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV5

Bit 5: Interrupt/Event software trigger on line 5.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV6

Bit 6: Interrupt/Event software trigger on line 6.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV7

Bit 7: Interrupt/Event software trigger on line 7.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV8

Bit 8: Interrupt/Event software trigger on line 8.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV9

Bit 9: Interrupt/Event software trigger on line 9.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV10

Bit 10: Interrupt/Event software trigger on line 10.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV11

Bit 11: Interrupt/Event software trigger on line 11.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV12

Bit 12: Interrupt/Event software trigger on line 12.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV13

Bit 13: Interrupt/Event software trigger on line 13.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV14

Bit 14: Interrupt/Event software trigger on line 14.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV15

Bit 15: Interrupt/Event software trigger on line 15.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV16

Bit 16: Interrupt/Event software trigger on line 16.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV17

Bit 17: Interrupt/Event software trigger on line 17.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV18

Bit 18: Interrupt/Event software trigger on line 18.

Allowed values:
1: Pend: Generates an interrupt request

SWIEV19

Bit 19: Interrupt/Event software trigger on line 19.

Allowed values:
1: Pend: Generates an interrupt request

PD

Pending register (EXTI_PD)

Offset: 0x14, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PD19
rw 		PD18
rw 		PD17
rw 		PD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle Fields.

PD0

Bit 0: Interrupt pending status of line 0.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD1

Bit 1: Interrupt pending status of line 1.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD2

Bit 2: Interrupt pending status of line 2.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD3

Bit 3: Interrupt pending status of line 3.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD4

Bit 4: Interrupt pending status of line 4.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD5

Bit 5: Interrupt pending status of line 5.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD6

Bit 6: Interrupt pending status of line 6.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD7

Bit 7: Interrupt pending status of line 7.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD8

Bit 8: Interrupt pending status of line 8.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD9

Bit 9: Interrupt pending status of line 9.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD10

Bit 10: Interrupt pending status of line 10.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD11

Bit 11: Interrupt pending status of line 11.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD12

Bit 12: Interrupt pending status of line 12.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD13

Bit 13: Interrupt pending status of line 13.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD14

Bit 14: Interrupt pending status of line 14.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD15

Bit 15: Interrupt pending status of line 15.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD16

Bit 16: Interrupt pending status of line 16.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD17

Bit 17: Interrupt pending status of line 17.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD18

Bit 18: Interrupt pending status of line 18.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PD19

Bit 19: Interrupt pending status of line 19.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FMC

0x40022000: FMC

38/38 fields covered. Toggle Registers.

WS

wait state counter register

Offset: 0x0, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WSCNT
rw
Toggle Fields.

WSCNT

Bits 0-2: wait state counter register.

Allowed values:
0: WS0: 0 wait states added
1: WS1: 1 wait state added
2: WS2: 2 wait states added

KEY

Unlock key register

Offset: 0x4, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-31: FMC_CTL unlock register.

Allowed values: 0-4294967295

OBKEY

Option byte unlock key register

Offset: 0x8, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OBKEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OBKEY
w
Toggle Fields.

OBKEY

Bits 0-31: FMC_ OBCTL0 option byte operation unlock register.

Allowed values: 0-4294967295

STAT0

Status register 0

Offset: 0xC, reset: 0x00000000, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENDF
rw 		WPERR
rw 		PGERR
rw 		BUSY
r
Toggle Fields.

BUSY

Bit 0: The flash is busy bit.

Allowed values:
0: Inactive: No operation is in progress
1: Active: An operation is in progress

PGERR

Bit 2: Program error flag bit.

Allowed values:
0: NoError: There was no error
1: Error: There was an error programming flash

WPERR

Bit 4: Erase/Program protection error flag bit.

Allowed values:
0: NoError: There was no error
1: Error: There was an error erasing/programming protected pages

ENDF

Bit 5: End of operation flag bit.

Allowed values:
0: NoEvent: No end of operation occurred
1: Event: An end of operation event occurred

CTL0

Control register 0

Offset: 0x10, reset: 0x00000080, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENDIE
rw 		ERRIE
rw 		OBWEN
rw 		LK
rw 		START
rw 		OBER
rw 		OBPG
rw 		MER
rw 		PER
rw 		PG
rw
Toggle Fields.

PG

Bit 0: Main flash program for bank0 command bit.

Allowed values:
1: Program: Flash programming activated

PER

Bit 1: Main flash page erase for bank0 command bit.

Allowed values:
1: PageErase: Erase activated for selected page

MER

Bit 2: Main flash mass erase for bank0 command bit.

Allowed values:
1: MassErase: Erase activated for all user sectors

OBPG

Bit 4: Option bytes program command bit.

Allowed values:
1: OptionByteProgramming: Program option byte activated

OBER

Bit 5: Option bytes erase command bit.

Allowed values:
1: OptionByteErase: Erase option byte activated

START

Bit 6: Send erase command to FMC bit.

Allowed values:
1: Start: Trigger an erase operation

LK

Bit 7: FMC_CTL0 lock bit.

Allowed values:
0: Unlocked: CTL register is unlocked
1: Locked: CTL register is locked

OBWEN

Bit 9: Option byte erase/program enable bit.

Allowed values:
0: Disabled: Option byte write disabled
1: Enabled: Option byte write enabled

ERRIE

Bit 10: Error interrupt enable bit.

Allowed values:
0: Disabled: Error interrupt generation disabled
1: Enabled: Error interrupt generation enabled

ENDIE

Bit 12: End of operation interrupt enable bit.

Allowed values:
0: Disabled: End of operation interrupt disabled
1: Enabled: End of operation interrupt enabled

ADDR0

Address register 0

Offset: 0x14, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
w
Toggle Fields.

ADDR

Bits 0-31: Flash erase/program command address bits.

Allowed values: 0-4294967295

OBCTL

Option byte control register

Offset: 0x1C, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r 		USER
r 		SPC
r 		RERR
r
Toggle Fields.

RERR

Bit 0: Option bytes read error bit.

SPC

Bit 1: Option bytes security protection code.

USER

Bits 2-9: Store USER of option bytes block after system reset.

DATA

Bits 10-25: Store DATA[15:0] of option bytes block after system reset.

WP

Erase/Program Protection register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WP
r
Toggle Fields.

WP

Bits 0-31: Store WP[31:0] of option bytes block after system reset.

KEY1

Unlock key register 1

Offset: 0x44, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-31: FMC_CTL unlock register.

Allowed values: 0-4294967295

STAT1

Status register 1

Offset: 0x4C, reset: 0x00000000, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENDF
rw 		WPERR
rw 		PGERR
rw 		BUSY
r
Toggle Fields.

BUSY

Bit 0: The flash is busy bit.

Allowed values:
0: Inactive: No operation is in progress
1: Active: An operation is in progress

PGERR

Bit 2: Program error flag bit.

Allowed values:
0: NoError: There was no error
1: Error: There was an error programming flash

WPERR

Bit 4: Erase/Program protection error flag bit.

Allowed values:
0: NoError: There was no error
1: Error: There was an error erasing/programming protected pages

ENDF

Bit 5: End of operation flag bit.

Allowed values:
0: NoEvent: No end of operation occurred
1: Event: An end of operation event occurred

CTL1

Control register 1

Offset: 0x50, reset: 0x00000080, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENDIE
rw 		ERRIE
rw 		LK
rw 		START
rw 		MER
rw 		PER
rw 		PG
rw
Toggle Fields.

PG

Bit 0: Main flash program for bank0 command bit.

Allowed values:
1: Program: Flash programming activated

PER

Bit 1: Main flash page erase for bank0 command bit.

Allowed values:
1: PageErase: Erase activated for selected page

MER

Bit 2: Main flash mass erase for bank0 command bit.

Allowed values:
1: MassErase: Erase activated for all user sectors

START

Bit 6: Send erase command to FMC bit.

Allowed values:
1: Start: Trigger an erase operation

LK

Bit 7: FMC_CTL0 lock bit.

Allowed values:
0: Unlocked: CTL register is unlocked
1: Locked: CTL register is locked

ERRIE

Bit 10: Error interrupt enable bit.

Allowed values:
0: Disabled: Error interrupt generation disabled
1: Enabled: Error interrupt generation enabled

ENDIE

Bit 12: End of operation interrupt enable bit.

Allowed values:
0: Disabled: End of operation interrupt disabled
1: Enabled: End of operation interrupt enabled

ADDR1

Address register 1

Offset: 0x54, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
w
Toggle Fields.

ADDR

Bits 0-31: Flash erase/program command address bits.

Allowed values: 0-4294967295

WSEN

Wait state enable register

Offset: 0xFC, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WSEN
rw
Toggle Fields.

WSEN

Bit 0: FMC wait state enable register.

Allowed values:
0: NoWaitState: No wait state added
1: WaitState: Wait state added

PID

Product ID register

Offset: 0x100, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PID
r
Toggle Fields.

PID

Bits 0-31: Product reserved ID code register.

Allowed values: 0-4294967295

FWDGT

0x40003000: free watchdog timer

5/5 fields covered. Toggle Registers.

CTL

Control register

Offset: 0x0, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMD
w
Toggle Fields.

CMD

Bits 0-15: Key value.

Allowed values:
21845: Enable: Enable access to PR, RLR and WINR registers (0x5555)
43690: Reset: Reset the watchdog value (0xAAAA)
52428: Start: Start the watchdog (0xCCCC)

PSC

Prescaler register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-2: Free watchdog timer prescaler selection.

Allowed values:
0: DivideBy4: Divider /4
1: DivideBy8: Divider /8
2: DivideBy16: Divider /16
3: DivideBy32: Divider /32
4: DivideBy64: Divider /64
5: DivideBy128: Divider /128
6: DivideBy256: Divider /256
7: DivideBy256bis: Divider /256

RLD

Reload register

Offset: 0x8, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RLD
rw
Toggle Fields.

RLD

Bits 0-11: Free watchdog timer counter reload value.

Allowed values: 0-4095

STAT

Status register

Offset: 0xC, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RUD
r 		PUD
r
Toggle Fields.

PUD

Bit 0: Free watchdog timer prescaler value update.

Allowed values:
0: Valid: The value read from the PSC register is valid
1: Ongoing: A write operation to to the PSC register is ongoing, so the value read is invalid

RUD

Bit 1: Free watchdog timer counter reload value update.

Allowed values:
0: Valid: The value read from the RLD register is valid
1: Ongoing: A write operation to to the RLD register is ongoing, so the value read is invalid

GPIOA

0x40010800: General-purpose I/Os

129/145 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK1

Bit 1: Port Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK2

Bit 2: Port Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK3

Bit 3: Port Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK4

Bit 4: Port Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK5

Bit 5: Port Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK6

Bit 6: Port Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK7

Bit 7: Port Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK8

Bit 8: Port Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK9

Bit 9: Port Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK10

Bit 10: Port Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK11

Bit 11: Port Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK12

Bit 12: Port Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK13

Bit 13: Port Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK14

Bit 14: Port Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK15

Bit 15: Port Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LKK

Bit 16: Lock sequence key .

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

SPD

Port bit speed register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPD15
rw 		SPD14
rw 		SPD13
rw 		SPD12
rw 		SPD11
rw 		SPD10
rw 		SPD9
rw 		SPD8
rw 		SPD7
rw 		SPD6
rw 		SPD5
rw 		SPD4
rw 		SPD3
rw 		SPD2
rw 		SPD1
rw 		SPD0
rw
Toggle Fields.

SPD0

Bit 0: Port 0 output max speed bits.

SPD1

Bit 1: Port 1 output max speed bits.

SPD2

Bit 2: Port 2 output max speed bits.

SPD3

Bit 3: Port 3 output max speed bits.

SPD4

Bit 4: Port 4 output max speed bits.

SPD5

Bit 5: Port 5 output max speed bits.

SPD6

Bit 6: Port 6 output max speed bits.

SPD7

Bit 7: Port 7 output max speed bits.

SPD8

Bit 8: Port 8 output max speed bits.

SPD9

Bit 9: Port 9 output max speed bits.

SPD10

Bit 10: Port 10 output max speed bits.

SPD11

Bit 11: Port 11 output max speed bits.

SPD12

Bit 12: Port 12 output max speed bits.

SPD13

Bit 13: Port 13 output max speed bits.

SPD14

Bit 14: Port 14 output max speed bits.

SPD15

Bit 15: Port 15 output max speed bits.

GPIOB

0x40010C00: General-purpose I/Os

129/145 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK1

Bit 1: Port Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK2

Bit 2: Port Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK3

Bit 3: Port Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK4

Bit 4: Port Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK5

Bit 5: Port Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK6

Bit 6: Port Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK7

Bit 7: Port Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK8

Bit 8: Port Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK9

Bit 9: Port Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK10

Bit 10: Port Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK11

Bit 11: Port Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK12

Bit 12: Port Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK13

Bit 13: Port Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK14

Bit 14: Port Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK15

Bit 15: Port Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LKK

Bit 16: Lock sequence key .

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

SPD

Port bit speed register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPD15
rw 		SPD14
rw 		SPD13
rw 		SPD12
rw 		SPD11
rw 		SPD10
rw 		SPD9
rw 		SPD8
rw 		SPD7
rw 		SPD6
rw 		SPD5
rw 		SPD4
rw 		SPD3
rw 		SPD2
rw 		SPD1
rw 		SPD0
rw
Toggle Fields.

SPD0

Bit 0: Port 0 output max speed bits.

SPD1

Bit 1: Port 1 output max speed bits.

SPD2

Bit 2: Port 2 output max speed bits.

SPD3

Bit 3: Port 3 output max speed bits.

SPD4

Bit 4: Port 4 output max speed bits.

SPD5

Bit 5: Port 5 output max speed bits.

SPD6

Bit 6: Port 6 output max speed bits.

SPD7

Bit 7: Port 7 output max speed bits.

SPD8

Bit 8: Port 8 output max speed bits.

SPD9

Bit 9: Port 9 output max speed bits.

SPD10

Bit 10: Port 10 output max speed bits.

SPD11

Bit 11: Port 11 output max speed bits.

SPD12

Bit 12: Port 12 output max speed bits.

SPD13

Bit 13: Port 13 output max speed bits.

SPD14

Bit 14: Port 14 output max speed bits.

SPD15

Bit 15: Port 15 output max speed bits.

GPIOC

0x40011000: General-purpose I/Os

129/145 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK1

Bit 1: Port Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK2

Bit 2: Port Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK3

Bit 3: Port Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK4

Bit 4: Port Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK5

Bit 5: Port Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK6

Bit 6: Port Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK7

Bit 7: Port Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK8

Bit 8: Port Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK9

Bit 9: Port Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK10

Bit 10: Port Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK11

Bit 11: Port Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK12

Bit 12: Port Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK13

Bit 13: Port Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK14

Bit 14: Port Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK15

Bit 15: Port Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LKK

Bit 16: Lock sequence key .

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

SPD

Port bit speed register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPD15
rw 		SPD14
rw 		SPD13
rw 		SPD12
rw 		SPD11
rw 		SPD10
rw 		SPD9
rw 		SPD8
rw 		SPD7
rw 		SPD6
rw 		SPD5
rw 		SPD4
rw 		SPD3
rw 		SPD2
rw 		SPD1
rw 		SPD0
rw
Toggle Fields.

SPD0

Bit 0: Port 0 output max speed bits.

SPD1

Bit 1: Port 1 output max speed bits.

SPD2

Bit 2: Port 2 output max speed bits.

SPD3

Bit 3: Port 3 output max speed bits.

SPD4

Bit 4: Port 4 output max speed bits.

SPD5

Bit 5: Port 5 output max speed bits.

SPD6

Bit 6: Port 6 output max speed bits.

SPD7

Bit 7: Port 7 output max speed bits.

SPD8

Bit 8: Port 8 output max speed bits.

SPD9

Bit 9: Port 9 output max speed bits.

SPD10

Bit 10: Port 10 output max speed bits.

SPD11

Bit 11: Port 11 output max speed bits.

SPD12

Bit 12: Port 12 output max speed bits.

SPD13

Bit 13: Port 13 output max speed bits.

SPD14

Bit 14: Port 14 output max speed bits.

SPD15

Bit 15: Port 15 output max speed bits.

GPIOD

0x40011400: General-purpose I/Os

129/145 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK1

Bit 1: Port Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK2

Bit 2: Port Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK3

Bit 3: Port Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK4

Bit 4: Port Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK5

Bit 5: Port Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK6

Bit 6: Port Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK7

Bit 7: Port Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK8

Bit 8: Port Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK9

Bit 9: Port Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK10

Bit 10: Port Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK11

Bit 11: Port Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK12

Bit 12: Port Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK13

Bit 13: Port Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK14

Bit 14: Port Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK15

Bit 15: Port Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LKK

Bit 16: Lock sequence key .

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

SPD

Port bit speed register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPD15
rw 		SPD14
rw 		SPD13
rw 		SPD12
rw 		SPD11
rw 		SPD10
rw 		SPD9
rw 		SPD8
rw 		SPD7
rw 		SPD6
rw 		SPD5
rw 		SPD4
rw 		SPD3
rw 		SPD2
rw 		SPD1
rw 		SPD0
rw
Toggle Fields.

SPD0

Bit 0: Port 0 output max speed bits.

SPD1

Bit 1: Port 1 output max speed bits.

SPD2

Bit 2: Port 2 output max speed bits.

SPD3

Bit 3: Port 3 output max speed bits.

SPD4

Bit 4: Port 4 output max speed bits.

SPD5

Bit 5: Port 5 output max speed bits.

SPD6

Bit 6: Port 6 output max speed bits.

SPD7

Bit 7: Port 7 output max speed bits.

SPD8

Bit 8: Port 8 output max speed bits.

SPD9

Bit 9: Port 9 output max speed bits.

SPD10

Bit 10: Port 10 output max speed bits.

SPD11

Bit 11: Port 11 output max speed bits.

SPD12

Bit 12: Port 12 output max speed bits.

SPD13

Bit 13: Port 13 output max speed bits.

SPD14

Bit 14: Port 14 output max speed bits.

SPD15

Bit 15: Port 15 output max speed bits.

GPIOE

0x40011800: General-purpose I/Os

129/145 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK1

Bit 1: Port Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK2

Bit 2: Port Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK3

Bit 3: Port Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK4

Bit 4: Port Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK5

Bit 5: Port Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK6

Bit 6: Port Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK7

Bit 7: Port Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK8

Bit 8: Port Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK9

Bit 9: Port Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK10

Bit 10: Port Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK11

Bit 11: Port Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK12

Bit 12: Port Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK13

Bit 13: Port Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK14

Bit 14: Port Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK15

Bit 15: Port Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LKK

Bit 16: Lock sequence key .

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

SPD

Port bit speed register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPD15
rw 		SPD14
rw 		SPD13
rw 		SPD12
rw 		SPD11
rw 		SPD10
rw 		SPD9
rw 		SPD8
rw 		SPD7
rw 		SPD6
rw 		SPD5
rw 		SPD4
rw 		SPD3
rw 		SPD2
rw 		SPD1
rw 		SPD0
rw
Toggle Fields.

SPD0

Bit 0: Port 0 output max speed bits.

SPD1

Bit 1: Port 1 output max speed bits.

SPD2

Bit 2: Port 2 output max speed bits.

SPD3

Bit 3: Port 3 output max speed bits.

SPD4

Bit 4: Port 4 output max speed bits.

SPD5

Bit 5: Port 5 output max speed bits.

SPD6

Bit 6: Port 6 output max speed bits.

SPD7

Bit 7: Port 7 output max speed bits.

SPD8

Bit 8: Port 8 output max speed bits.

SPD9

Bit 9: Port 9 output max speed bits.

SPD10

Bit 10: Port 10 output max speed bits.

SPD11

Bit 11: Port 11 output max speed bits.

SPD12

Bit 12: Port 12 output max speed bits.

SPD13

Bit 13: Port 13 output max speed bits.

SPD14

Bit 14: Port 14 output max speed bits.

SPD15

Bit 15: Port 15 output max speed bits.

GPIOF

0x40011C00: General-purpose I/Os

129/145 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK1

Bit 1: Port Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK2

Bit 2: Port Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK3

Bit 3: Port Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK4

Bit 4: Port Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK5

Bit 5: Port Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK6

Bit 6: Port Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK7

Bit 7: Port Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK8

Bit 8: Port Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK9

Bit 9: Port Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK10

Bit 10: Port Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK11

Bit 11: Port Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK12

Bit 12: Port Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK13

Bit 13: Port Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK14

Bit 14: Port Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK15

Bit 15: Port Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LKK

Bit 16: Lock sequence key .

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

SPD

Port bit speed register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPD15
rw 		SPD14
rw 		SPD13
rw 		SPD12
rw 		SPD11
rw 		SPD10
rw 		SPD9
rw 		SPD8
rw 		SPD7
rw 		SPD6
rw 		SPD5
rw 		SPD4
rw 		SPD3
rw 		SPD2
rw 		SPD1
rw 		SPD0
rw
Toggle Fields.

SPD0

Bit 0: Port 0 output max speed bits.

SPD1

Bit 1: Port 1 output max speed bits.

SPD2

Bit 2: Port 2 output max speed bits.

SPD3

Bit 3: Port 3 output max speed bits.

SPD4

Bit 4: Port 4 output max speed bits.

SPD5

Bit 5: Port 5 output max speed bits.

SPD6

Bit 6: Port 6 output max speed bits.

SPD7

Bit 7: Port 7 output max speed bits.

SPD8

Bit 8: Port 8 output max speed bits.

SPD9

Bit 9: Port 9 output max speed bits.

SPD10

Bit 10: Port 10 output max speed bits.

SPD11

Bit 11: Port 11 output max speed bits.

SPD12

Bit 12: Port 12 output max speed bits.

SPD13

Bit 13: Port 13 output max speed bits.

SPD14

Bit 14: Port 14 output max speed bits.

SPD15

Bit 15: Port 15 output max speed bits.

GPIOG

0x40012000: General-purpose I/Os

129/145 fields covered. Toggle Registers.

CTL0

port control register 0

Offset: 0x0, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL7
rw 		MD7
rw 		CTL6
rw 		MD6
rw 		CTL5
rw 		MD5
rw 		CTL4
rw 		MD4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL3
rw 		MD3
rw 		CTL2
rw 		MD2
rw 		CTL1
rw 		MD1
rw 		CTL0
rw 		MD0
rw
Toggle Fields.

MD0

Bits 0-1: Port x mode bits (x = 0).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL0

Bits 2-3: Port x configuration bits (x = 0).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD1

Bits 4-5: Port x mode bits (x = 1).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL1

Bits 6-7: Port x configuration bits (x = 1).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD2

Bits 8-9: Port x mode bits (x = 2 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL2

Bits 10-11: Port x configuration bits (x = 2).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD3

Bits 12-13: Port x mode bits (x = 3 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL3

Bits 14-15: Port x configuration bits (x = 3).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD4

Bits 16-17: Port x mode bits (x = 4).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL4

Bits 18-19: Port x configuration bits (x = 4).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD5

Bits 20-21: Port x mode bits (x = 5).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL5

Bits 22-23: Port x configuration bits (x = 5).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD6

Bits 24-25: Port x mode bits (x = 6).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL6

Bits 26-27: Port x configuration bits (x = 6).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD7

Bits 28-29: Port x mode bits (x = 7).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL7

Bits 30-31: Port x configuration bits (x = 7).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

CTL1

port control register 1

Offset: 0x4, reset: 0x44444444, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		MD15
rw 		CTL14
rw 		MD14
rw 		CTL13
rw 		MD13
rw 		CTL12
rw 		MD12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL11
rw 		MD11
rw 		CTL10
rw 		MD10
rw 		CTL9
rw 		MD9
rw 		CTL8
rw 		MD8
rw
Toggle Fields.

MD8

Bits 0-1: Port x mode bits (x = 8).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL8

Bits 2-3: Port x configuration bits (x = 8).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD9

Bits 4-5: Port x mode bits (x = 9).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL9

Bits 6-7: Port x configuration bits (x = 9).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD10

Bits 8-9: Port x mode bits (x = 10 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL10

Bits 10-11: Port x configuration bits (x = 10).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD11

Bits 12-13: Port x mode bits (x = 11 ).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL11

Bits 14-15: Port x configuration bits (x = 11).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD12

Bits 16-17: Port x mode bits (x = 12).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL12

Bits 18-19: Port x configuration bits (x = 12).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD13

Bits 20-21: Port x mode bits (x = 13).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL13

Bits 22-23: Port x configuration bits (x = 13).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD14

Bits 24-25: Port x mode bits (x = 14).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL14

Bits 26-27: Port x configuration bits (x = 14).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

MD15

Bits 28-29: Port x mode bits (x = 15).

Allowed values:
0: Input: Input mode (reset state)
1: Speed10M: Output mode ,max speed 10MHz
2: Speed2M: Output mode ,max speed 2MHz
3: Speed50M: Output mode ,max speed 50MHz

CTL15

Bits 30-31: Port x configuration bits (x = 15).

Allowed values:
0: AnalogOrPushPull: Analog mode/GPIO output with push-pull
1: FloatingOrOpenDrain: Floating input/GPIO output with open-drain
2: InputOrAfioPP: Input with pull-up pull-down/AFIO output with push-pull
3: RSVDOrAfioOD: Reserved/AFIO output with open-drain

ISTAT

Port input status register

Offset: 0x8, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT1

Bit 1: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT2

Bit 2: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT3

Bit 3: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT4

Bit 4: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT5

Bit 5: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT6

Bit 6: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT7

Bit 7: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT8

Bit 8: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT9

Bit 9: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT10

Bit 10: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT11

Bit 11: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT12

Bit 12: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT13

Bit 13: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT14

Bit 14: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ISTAT15

Bit 15: Port input status.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

OCTL

Port output control register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL1

Bit 1: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL2

Bit 2: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL3

Bit 3: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL4

Bit 4: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL5

Bit 5: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL6

Bit 6: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL7

Bit 7: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL8

Bit 8: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL9

Bit 9: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL10

Bit 10: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL11

Bit 11: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL12

Bit 12: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL13

Bit 13: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL14

Bit 14: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

OCTL15

Bit 15: Port output control.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BOP

Port bit operate register

Offset: 0x10, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port 0 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP1

Bit 1: Port 1 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP2

Bit 2: Port 2 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP3

Bit 3: Port 3 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP4

Bit 4: Port 4 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP5

Bit 5: Port 5 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP6

Bit 6: Port 6 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP7

Bit 7: Port 7 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP8

Bit 8: Port 8 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP9

Bit 9: Port 9 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP10

Bit 10: Port 10 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP11

Bit 11: Port 11 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP12

Bit 12: Port 12 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP13

Bit 13: Port 13 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP14

Bit 14: Port 14 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

BOP15

Bit 15: Port 15 Set bit.

Allowed values:
1: Set: Sets the corresponding OCTLx bit

CR0

Bit 16: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 17: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 18: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 19: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 20: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 21: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 22: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 23: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 24: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 25: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 26: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 27: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 28: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 29: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 30: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 31: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

BC

Port bit clear register

Offset: 0x14, reset: 0x00000000, access: write-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port 0 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR1

Bit 1: Port 1 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR2

Bit 2: Port 2 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR3

Bit 3: Port 3 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR4

Bit 4: Port 4 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR5

Bit 5: Port 5 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR6

Bit 6: Port 6 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR7

Bit 7: Port 7 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR8

Bit 8: Port 8 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR9

Bit 9: Port 9 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR10

Bit 10: Port 10 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR11

Bit 11: Port 11 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR12

Bit 12: Port 12 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR13

Bit 13: Port 13 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR14

Bit 14: Port 14 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

CR15

Bit 15: Port 15 Clear bit.

Allowed values:
1: Reset: Resets the corresponding OCTLx bit

LOCK

GPIO port configuration lock register

Offset: 0x18, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK1

Bit 1: Port Lock bit 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK2

Bit 2: Port Lock bit 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK3

Bit 3: Port Lock bit 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK4

Bit 4: Port Lock bit 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK5

Bit 5: Port Lock bit 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK6

Bit 6: Port Lock bit 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK7

Bit 7: Port Lock bit 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK8

Bit 8: Port Lock bit 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK9

Bit 9: Port Lock bit 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK10

Bit 10: Port Lock bit 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK11

Bit 11: Port Lock bit 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK12

Bit 12: Port Lock bit 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK13

Bit 13: Port Lock bit 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK14

Bit 14: Port Lock bit 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LK15

Bit 15: Port Lock bit 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LKK

Bit 16: Lock sequence key .

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

SPD

Port bit speed register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPD15
rw 		SPD14
rw 		SPD13
rw 		SPD12
rw 		SPD11
rw 		SPD10
rw 		SPD9
rw 		SPD8
rw 		SPD7
rw 		SPD6
rw 		SPD5
rw 		SPD4
rw 		SPD3
rw 		SPD2
rw 		SPD1
rw 		SPD0
rw
Toggle Fields.

SPD0

Bit 0: Port 0 output max speed bits.

SPD1

Bit 1: Port 1 output max speed bits.

SPD2

Bit 2: Port 2 output max speed bits.

SPD3

Bit 3: Port 3 output max speed bits.

SPD4

Bit 4: Port 4 output max speed bits.

SPD5

Bit 5: Port 5 output max speed bits.

SPD6

Bit 6: Port 6 output max speed bits.

SPD7

Bit 7: Port 7 output max speed bits.

SPD8

Bit 8: Port 8 output max speed bits.

SPD9

Bit 9: Port 9 output max speed bits.

SPD10

Bit 10: Port 10 output max speed bits.

SPD11

Bit 11: Port 11 output max speed bits.

SPD12

Bit 12: Port 12 output max speed bits.

SPD13

Bit 13: Port 13 output max speed bits.

SPD14

Bit 14: Port 14 output max speed bits.

SPD15

Bit 15: Port 15 output max speed bits.

I2C0

0x40005400: Inter integrated circuit

51/52 fields covered. Toggle Registers.

CTL0

Control register 0

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRESET
rw 		SALT
rw 		PECTRANS
rw 		POAP
rw 		ACKEN
rw 		STOP
rw 		START
rw 		SS
rw 		GCEN
rw 		PECEN
rw 		ARPEN
rw 		SMBSEL
rw 		SMBEN
rw 		I2CEN
rw
Toggle Fields.

I2CEN

Bit 0: I2C peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

SMBEN

Bit 1: SMBus/I2C mode switch.

Allowed values:
0: I2C: I2C Mode
1: SMBus: SMBus

SMBSEL

Bit 3: SMBusType Selection.

Allowed values:
0: Device: SMBus Device
1: Host: SMBus Host

ARPEN

Bit 4: ARP protocol in SMBus switch.

Allowed values:
0: Disabled: ARP disabled
1: Enabled: ARP enabled

PECEN

Bit 5: PEC Calculation Switch.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

GCEN

Bit 6: Whether or not to response to a General Call (0x00).

Allowed values:
0: NotRespond: Slave won't respond to General Call
1: Respond: Slave will respond to General Call

SS

Bit 7: Whether to stretch SCL low when data is not ready in slave mode.

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

START

Bit 8: Generate a START condition on I2C bus.

Allowed values:
0: NoStart: START will not be sent
1: Start: START will be sent

STOP

Bit 9: Generate a STOP condition on I2C bus.

Allowed values:
0: NoStop: STOP will not be sent
1: Stop: STOP will be sent

ACKEN

Bit 10: Whether or not to send an ACK.

Allowed values:
0: NAK: No acknowledge returned
1: ACK: Acknowledge returned after a byte is received

POAP

Bit 11: Position of ACK and PEC when receiving.

Allowed values:
0: Current: ACK bit controls the (N)ACK of the current byte being received
1: Next: ACK bit controls the (N)ACK of the next byte to be received

PECTRANS

Bit 12: PEC Transfer.

Allowed values:
0: Disabled: No PEC transfer
1: Enabled: PEC transfer

SALT

Bit 13: SMBus alert.

Allowed values:
0: Release: SMBA pin released high
1: Drive: SMBA pin driven low

SRESET

Bit 15: Software reset.

Allowed values:
0: NotReset: I2C peripheral not under reset
1: Reset: I2C peripheral under reset

CTL1

Control register 1

Offset: 0x4, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMALST
rw 		DMAON
rw 		BUFIE
rw 		EVIE
rw 		ERRIE
rw 		I2CCLK
rw
Toggle Fields.

I2CCLK

Bits 0-6: I2C Peripheral clock frequency.

Allowed values: 2-72

ERRIE

Bit 8: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

EVIE

Bit 9: Event interrupt enable.

Allowed values:
0: Disabled: Event interrupt disabled
1: Enabled: Event interrupt enabled

BUFIE

Bit 10: Buffer interrupt enable.

Allowed values:
0: Disabled: TBE=1 or RBNE=1 does not generate any interrupt
1: Enabled: TBE=1 or RBNE=1 generates Event interrupt

DMAON

Bit 11: DMA mode switch.

Allowed values:
0: Disabled: DMA requests disabled
1: Enabled: DMA requests enabled

DMALST

Bit 12: Flag indicating DMA last transfer.

Allowed values:
0: NotLast: Next DMA EOT is not the last transfer
1: Last: Next DMA EOT is the last transfer

SADDR0

Slave address register 0

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDFORMAT
rw 		ADDRESS
rw
Toggle Fields.

ADDRESS

Bits 0-9: Bit 0 of a 10-bit address.

Allowed values: 0-1023

ADDFORMAT

Bit 15: Address mode for the I2C slave.

Allowed values:
0: Add7: 7-bit slave address (note that you'll need to shift the address by 1b)
1: Add10: 10-bit slave address

SADDR1

Slave address register 1

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS2
rw 		DUADEN
rw
Toggle Fields.

DUADEN

Bit 0: Dual-Address mode switch.

Allowed values:
0: Single: Single addressing mode
1: Dual: Dual addressing mode

ADDRESS2

Bits 1-7: Second I2C address for the slave in Dual-Address mode.

Allowed values: 0-127

DATA

Transfer buffer register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRB
rw
Toggle Fields.

TRB

Bits 0-7: Transmission or reception data buffer register.

Allowed values: 0-255

STAT0

Transfer status register 0

Offset: 0x14, reset: 0x0000, access: Unspecified

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALT
rw 		SMBTO
rw 		PECERR
rw 		OUERR
rw 		AERR
rw 		LOSTARB
rw 		BERR
rw 		TBE
r 		RBNE
r 		STPDET
r 		ADD10SEND
r 		BTC
r 		ADDSEND
r 		SBSEND
r
Toggle Fields.

SBSEND

Bit 0: START condition sent out in master mode.

Allowed values:
0: NoStart: No Start condition
1: Start: Start condition generated

ADDSEND

Bit 1: Address is sent in master mode or received and matches in slave mode.

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

BTC

Bit 2: Byte transmission completed.

Allowed values:
0: NotFinished: Data byte transfer not done
1: Finished: Data byte transfer successful

ADD10SEND

Bit 3: Header of 10-bit address is sent in master mode.

Allowed values:
0: NoHeader: No header of 10-bit address is sent
1: Header: Header of 10-bit address is sent

STPDET

Bit 4: STOP condition detected in slave mode.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

RBNE

Bit 6: I2C_DATA is not Empty during receiving.

Allowed values:
0: Empty: Data register empty
1: NotEmpty: Data register not empty, software can read

TBE

Bit 7: I2C_DATA is Empty during transmitting.

Allowed values:
0: NotEmpty: Data register not empty
1: Empty: Data register empty, software can write

BERR

Bit 8: A bus error occurs indication a unexpected START or STOP condition on I2C bus.

Allowed values:
0: NoError: No misplaced Start or Stop condition
1: Error: Misplaced Start or Stop condition

LOSTARB

Bit 9: Arbitration Lost in master mode.

Allowed values:
0: NoLost: No Arbitration Lost detected
1: Lost: Arbitration Lost detected

AERR

Bit 10: Acknowledge error.

Allowed values:
0: NoError: No acknowledge error
1: Error: Acknowledge error

OUERR

Bit 11: Over-run or under-run situation occurs in slave mode.

Allowed values:
0: NoOverrun: No overrun/underrun occured
1: Overrun: Overrun/underrun occured

PECERR

Bit 12: PEC error when receiving data.

Allowed values:
0: NoError: No PEC error
1: Error: PEC error

SMBTO

Bit 14: Timeout signal in SMBus mode.

Allowed values:
0: NoTimeout: No Timeout error
1: Timeout: SCL remained low for 25 ms

SMBALT

Bit 15: SMBus Alert status.

Allowed values:
0: NoAlert: SMBA not pulled down or no alert occured
1: Alert: SMBA pulled down or alert occurred

STAT1

Transfer status register 1

Offset: 0x18, reset: 0x0000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PECV
r 		DUMODF
r 		HSTSMB
r 		DEFSMB
r 		RXGC
r 		TR
r 		I2CBSY
r 		MASTER
r
Toggle Fields.

MASTER

Bit 0: A flag indicating whether I2C block is in master or slave mode.

Allowed values:
0: Slave: Slave mode
1: Master: Master mode

I2CBSY

Bit 1: Busy flag.

Allowed values:
0: NotBusy: No I2C communication
1: Busy: I2C communication active

TR

Bit 2: Whether the I2C is a transmitter or a receiver.

Allowed values:
0: Receiver: Receiver
1: Transmitter: Transmitter

RXGC

Bit 4: General call address (00h) received.

Allowed values:
0: NotReceived: No general call address received
1: Received: General call address received

DEFSMB

Bit 5: Default address of SMBusDevice.

Allowed values:
0: NotReceived: Default address has not been received
1: Received: Default address has been received

HSTSMB

Bit 6: SMBus Host Header detected in slave mode.

Allowed values:
0: NoHeader: No SMBus host header detected
1: Header: SMBus host header detected

DUMODF

Bit 7: Dual Flag in slave mode.

Allowed values:
0: SADDR0: The address matches SADDR0
1: SADDR1: The address matches SADDR1

PECV

Bits 8-15: Packet Error Checking Value that calculated by hardware when PEC is enabled.

Allowed values: 0-127

CKCFG

Clock configure register

Offset: 0x1C, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAST
rw 		DTCY
rw 		CLKC
rw
Toggle Fields.

CLKC

Bits 0-11: I2C Clock control in master mode.

Allowed values: 0-4095

DTCY

Bit 14: Duty cycle in fast mode.

Allowed values:
0: Duty2: Duty cycle t_low/t_high = 2
1: Duty16_9: Duty cycle t_low/t_high = 16/9

FAST

Bit 15: I2C speed selection in master mode.

Allowed values:
0: Standard: Standard mode I2C
1: Fast: Fast mode I2C

RT

Rise time register

Offset: 0x20, reset: 0x0002, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RISETIME
rw
Toggle Fields.

RISETIME

Bits 0-6: Maximum rise time in master mode.

Allowed values: 0-127

FMPCFG

Fast-mode-plus configure register

Offset: 0x90, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMPEN
rw
Toggle Fields.

FMPEN

Bit 0: Fast-mode-plus enable.

I2C1

0x40005800: Inter integrated circuit

51/52 fields covered. Toggle Registers.

CTL0

Control register 0

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRESET
rw 		SALT
rw 		PECTRANS
rw 		POAP
rw 		ACKEN
rw 		STOP
rw 		START
rw 		SS
rw 		GCEN
rw 		PECEN
rw 		ARPEN
rw 		SMBSEL
rw 		SMBEN
rw 		I2CEN
rw
Toggle Fields.

I2CEN

Bit 0: I2C peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

SMBEN

Bit 1: SMBus/I2C mode switch.

Allowed values:
0: I2C: I2C Mode
1: SMBus: SMBus

SMBSEL

Bit 3: SMBusType Selection.

Allowed values:
0: Device: SMBus Device
1: Host: SMBus Host

ARPEN

Bit 4: ARP protocol in SMBus switch.

Allowed values:
0: Disabled: ARP disabled
1: Enabled: ARP enabled

PECEN

Bit 5: PEC Calculation Switch.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

GCEN

Bit 6: Whether or not to response to a General Call (0x00).

Allowed values:
0: NotRespond: Slave won't respond to General Call
1: Respond: Slave will respond to General Call

SS

Bit 7: Whether to stretch SCL low when data is not ready in slave mode.

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

START

Bit 8: Generate a START condition on I2C bus.

Allowed values:
0: NoStart: START will not be sent
1: Start: START will be sent

STOP

Bit 9: Generate a STOP condition on I2C bus.

Allowed values:
0: NoStop: STOP will not be sent
1: Stop: STOP will be sent

ACKEN

Bit 10: Whether or not to send an ACK.

Allowed values:
0: NAK: No acknowledge returned
1: ACK: Acknowledge returned after a byte is received

POAP

Bit 11: Position of ACK and PEC when receiving.

Allowed values:
0: Current: ACK bit controls the (N)ACK of the current byte being received
1: Next: ACK bit controls the (N)ACK of the next byte to be received

PECTRANS

Bit 12: PEC Transfer.

Allowed values:
0: Disabled: No PEC transfer
1: Enabled: PEC transfer

SALT

Bit 13: SMBus alert.

Allowed values:
0: Release: SMBA pin released high
1: Drive: SMBA pin driven low

SRESET

Bit 15: Software reset.

Allowed values:
0: NotReset: I2C peripheral not under reset
1: Reset: I2C peripheral under reset

CTL1

Control register 1

Offset: 0x4, reset: 0x0000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMALST
rw 		DMAON
rw 		BUFIE
rw 		EVIE
rw 		ERRIE
rw 		I2CCLK
rw
Toggle Fields.

I2CCLK

Bits 0-6: I2C Peripheral clock frequency.

Allowed values: 2-72

ERRIE

Bit 8: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

EVIE

Bit 9: Event interrupt enable.

Allowed values:
0: Disabled: Event interrupt disabled
1: Enabled: Event interrupt enabled

BUFIE

Bit 10: Buffer interrupt enable.

Allowed values:
0: Disabled: TBE=1 or RBNE=1 does not generate any interrupt
1: Enabled: TBE=1 or RBNE=1 generates Event interrupt

DMAON

Bit 11: DMA mode switch.

Allowed values:
0: Disabled: DMA requests disabled
1: Enabled: DMA requests enabled

DMALST

Bit 12: Flag indicating DMA last transfer.

Allowed values:
0: NotLast: Next DMA EOT is not the last transfer
1: Last: Next DMA EOT is the last transfer

SADDR0

Slave address register 0

Offset: 0x8, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDFORMAT
rw 		ADDRESS
rw
Toggle Fields.

ADDRESS

Bits 0-9: Bit 0 of a 10-bit address.

Allowed values: 0-1023

ADDFORMAT

Bit 15: Address mode for the I2C slave.

Allowed values:
0: Add7: 7-bit slave address (note that you'll need to shift the address by 1b)
1: Add10: 10-bit slave address

SADDR1

Slave address register 1

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS2
rw 		DUADEN
rw
Toggle Fields.

DUADEN

Bit 0: Dual-Address mode switch.

Allowed values:
0: Single: Single addressing mode
1: Dual: Dual addressing mode

ADDRESS2

Bits 1-7: Second I2C address for the slave in Dual-Address mode.

Allowed values: 0-127

DATA

Transfer buffer register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRB
rw
Toggle Fields.

TRB

Bits 0-7: Transmission or reception data buffer register.

Allowed values: 0-255

STAT0

Transfer status register 0

Offset: 0x14, reset: 0x0000, access: Unspecified

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALT
rw 		SMBTO
rw 		PECERR
rw 		OUERR
rw 		AERR
rw 		LOSTARB
rw 		BERR
rw 		TBE
r 		RBNE
r 		STPDET
r 		ADD10SEND
r 		BTC
r 		ADDSEND
r 		SBSEND
r
Toggle Fields.

SBSEND

Bit 0: START condition sent out in master mode.

Allowed values:
0: NoStart: No Start condition
1: Start: Start condition generated

ADDSEND

Bit 1: Address is sent in master mode or received and matches in slave mode.

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

BTC

Bit 2: Byte transmission completed.

Allowed values:
0: NotFinished: Data byte transfer not done
1: Finished: Data byte transfer successful

ADD10SEND

Bit 3: Header of 10-bit address is sent in master mode.

Allowed values:
0: NoHeader: No header of 10-bit address is sent
1: Header: Header of 10-bit address is sent

STPDET

Bit 4: STOP condition detected in slave mode.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

RBNE

Bit 6: I2C_DATA is not Empty during receiving.

Allowed values:
0: Empty: Data register empty
1: NotEmpty: Data register not empty, software can read

TBE

Bit 7: I2C_DATA is Empty during transmitting.

Allowed values:
0: NotEmpty: Data register not empty
1: Empty: Data register empty, software can write

BERR

Bit 8: A bus error occurs indication a unexpected START or STOP condition on I2C bus.

Allowed values:
0: NoError: No misplaced Start or Stop condition
1: Error: Misplaced Start or Stop condition

LOSTARB

Bit 9: Arbitration Lost in master mode.

Allowed values:
0: NoLost: No Arbitration Lost detected
1: Lost: Arbitration Lost detected

AERR

Bit 10: Acknowledge error.

Allowed values:
0: NoError: No acknowledge error
1: Error: Acknowledge error

OUERR

Bit 11: Over-run or under-run situation occurs in slave mode.

Allowed values:
0: NoOverrun: No overrun/underrun occured
1: Overrun: Overrun/underrun occured

PECERR

Bit 12: PEC error when receiving data.

Allowed values:
0: NoError: No PEC error
1: Error: PEC error

SMBTO

Bit 14: Timeout signal in SMBus mode.

Allowed values:
0: NoTimeout: No Timeout error
1: Timeout: SCL remained low for 25 ms

SMBALT

Bit 15: SMBus Alert status.

Allowed values:
0: NoAlert: SMBA not pulled down or no alert occured
1: Alert: SMBA pulled down or alert occurred

STAT1

Transfer status register 1

Offset: 0x18, reset: 0x0000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PECV
r 		DUMODF
r 		HSTSMB
r 		DEFSMB
r 		RXGC
r 		TR
r 		I2CBSY
r 		MASTER
r
Toggle Fields.

MASTER

Bit 0: A flag indicating whether I2C block is in master or slave mode.

Allowed values:
0: Slave: Slave mode
1: Master: Master mode

I2CBSY

Bit 1: Busy flag.

Allowed values:
0: NotBusy: No I2C communication
1: Busy: I2C communication active

TR

Bit 2: Whether the I2C is a transmitter or a receiver.

Allowed values:
0: Receiver: Receiver
1: Transmitter: Transmitter

RXGC

Bit 4: General call address (00h) received.

Allowed values:
0: NotReceived: No general call address received
1: Received: General call address received

DEFSMB

Bit 5: Default address of SMBusDevice.

Allowed values:
0: NotReceived: Default address has not been received
1: Received: Default address has been received

HSTSMB

Bit 6: SMBus Host Header detected in slave mode.

Allowed values:
0: NoHeader: No SMBus host header detected
1: Header: SMBus host header detected

DUMODF

Bit 7: Dual Flag in slave mode.

Allowed values:
0: SADDR0: The address matches SADDR0
1: SADDR1: The address matches SADDR1

PECV

Bits 8-15: Packet Error Checking Value that calculated by hardware when PEC is enabled.

Allowed values: 0-127

CKCFG

Clock configure register

Offset: 0x1C, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAST
rw 		DTCY
rw 		CLKC
rw
Toggle Fields.

CLKC

Bits 0-11: I2C Clock control in master mode.

Allowed values: 0-4095

DTCY

Bit 14: Duty cycle in fast mode.

Allowed values:
0: Duty2: Duty cycle t_low/t_high = 2
1: Duty16_9: Duty cycle t_low/t_high = 16/9

FAST

Bit 15: I2C speed selection in master mode.

Allowed values:
0: Standard: Standard mode I2C
1: Fast: Fast mode I2C

RT

Rise time register

Offset: 0x20, reset: 0x0002, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RISETIME
rw
Toggle Fields.

RISETIME

Bits 0-6: Maximum rise time in master mode.

Allowed values: 0-127

FMPCFG

Fast-mode-plus configure register

Offset: 0x90, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMPEN
rw
Toggle Fields.

FMPEN

Bit 0: Fast-mode-plus enable.

NVIC

0xE000E100: Nested Vectored Interrupt Controller

0/74 fields covered. Toggle Registers.

ISER

Interrupt Set Enable Register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ICER

Interrupt Clear Enable Register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ISPR

Interrupt Set-Pending Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ICPR

Interrupt Clear-Pending Register

Offset: 0x180, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

IABR

Interrupt Active bit Register

Offset: 0x200, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IABR
rw
Toggle Fields.

IABR

Bits 0-31: IABR.

IPR0

Interrupt Priority Register 0

Offset: 0x300, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_00
rw
Toggle Fields.

PRI_00

Bits 0-7: PRI_00.

IPR1

Interrupt Priority Register 1

Offset: 0x301, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_01
rw
Toggle Fields.

PRI_01

Bits 0-7: PRI_01.

IPR2

Interrupt Priority Register 2

Offset: 0x302, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_02
rw
Toggle Fields.

PRI_02

Bits 0-7: PRI_02.

IPR3

Interrupt Priority Register 3

Offset: 0x303, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_03
rw
Toggle Fields.

PRI_03

Bits 0-7: PRI_03.

IPR4

Interrupt Priority Register 4

Offset: 0x304, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_04
rw
Toggle Fields.

PRI_04

Bits 0-7: PRI_04.

IPR5

Interrupt Priority Register 5

Offset: 0x305, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_05
rw
Toggle Fields.

PRI_05

Bits 0-7: PRI_05.

IPR6

Interrupt Priority Register 6

Offset: 0x306, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_06
rw
Toggle Fields.

PRI_06

Bits 0-7: PRI_06.

IPR7

Interrupt Priority Register 7

Offset: 0x307, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_07
rw
Toggle Fields.

PRI_07

Bits 0-7: PRI_07.

IPR8

Interrupt Priority Register 8

Offset: 0x308, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_08
rw
Toggle Fields.

PRI_08

Bits 0-7: PRI_08.

IPR9

Interrupt Priority Register 9

Offset: 0x309, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_09
rw
Toggle Fields.

PRI_09

Bits 0-7: PRI_09.

IPR10

Interrupt Priority Register 10

Offset: 0x30A, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_10
rw
Toggle Fields.

PRI_10

Bits 0-7: PRI_10.

IPR11

Interrupt Priority Register 11

Offset: 0x30B, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_11
rw
Toggle Fields.

PRI_11

Bits 0-7: PRI_11.

IPR12

Interrupt Priority Register 12

Offset: 0x30C, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_12
rw
Toggle Fields.

PRI_12

Bits 0-7: PRI_12.

IPR13

Interrupt Priority Register 13

Offset: 0x30D, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_13
rw
Toggle Fields.

PRI_13

Bits 0-7: PRI_13.

IPR14

Interrupt Priority Register 14

Offset: 0x30E, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_14
rw
Toggle Fields.

PRI_14

Bits 0-7: PRI_14.

IPR15

Interrupt Priority Register 15

Offset: 0x30F, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_15
rw
Toggle Fields.

PRI_15

Bits 0-7: PRI_15.

IPR16

Interrupt Priority Register 16

Offset: 0x310, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_16
rw
Toggle Fields.

PRI_16

Bits 0-7: PRI_16.

IPR17

Interrupt Priority Register 17

Offset: 0x311, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_17
rw
Toggle Fields.

PRI_17

Bits 0-7: PRI_17.

IPR18

Interrupt Priority Register 18

Offset: 0x312, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_18
rw
Toggle Fields.

PRI_18

Bits 0-7: PRI_18.

IPR19

Interrupt Priority Register 19

Offset: 0x313, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_19
rw
Toggle Fields.

PRI_19

Bits 0-7: PRI_19.

IPR20

Interrupt Priority Register 20

Offset: 0x314, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_20
rw
Toggle Fields.

PRI_20

Bits 0-7: PRI_20.

IPR21

Interrupt Priority Register 21

Offset: 0x315, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_21
rw
Toggle Fields.

PRI_21

Bits 0-7: PRI_21.

IPR22

Interrupt Priority Register 22

Offset: 0x316, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_22
rw
Toggle Fields.

PRI_22

Bits 0-7: PRI_22.

IPR23

Interrupt Priority Register 23

Offset: 0x317, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_23
rw
Toggle Fields.

PRI_23

Bits 0-7: PRI_23.

IPR24

Interrupt Priority Register 24

Offset: 0x318, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_24
rw
Toggle Fields.

PRI_24

Bits 0-7: PRI_24.

IPR25

Interrupt Priority Register 25

Offset: 0x319, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_25
rw
Toggle Fields.

PRI_25

Bits 0-7: PRI_25.

IPR26

Interrupt Priority Register 26

Offset: 0x31A, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_26
rw
Toggle Fields.

PRI_26

Bits 0-7: PRI_26.

IPR27

Interrupt Priority Register 27

Offset: 0x31B, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_27
rw
Toggle Fields.

PRI_27

Bits 0-7: PRI_27.

IPR28

Interrupt Priority Register 28

Offset: 0x31C, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_28
rw
Toggle Fields.

PRI_28

Bits 0-7: PRI_28.

IPR29

Interrupt Priority Register 29

Offset: 0x31D, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_29
rw
Toggle Fields.

PRI_29

Bits 0-7: PRI_29.

IPR30

Interrupt Priority Register 30

Offset: 0x31E, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_30
rw
Toggle Fields.

PRI_30

Bits 0-7: PRI_30.

IPR31

Interrupt Priority Register 31

Offset: 0x31F, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_31
rw
Toggle Fields.

PRI_31

Bits 0-7: PRI_31.

IPR32

Interrupt Priority Register 32

Offset: 0x320, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_32
rw
Toggle Fields.

PRI_32

Bits 0-7: PRI_32.

IPR33

Interrupt Priority Register 33

Offset: 0x321, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_33
rw
Toggle Fields.

PRI_33

Bits 0-7: PRI_33.

IPR34

Interrupt Priority Register 34

Offset: 0x322, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_34
rw
Toggle Fields.

PRI_34

Bits 0-7: PRI_34.

IPR35

Interrupt Priority Register 35

Offset: 0x323, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_35
rw
Toggle Fields.

PRI_35

Bits 0-7: PRI_35.

IPR36

Interrupt Priority Register 36

Offset: 0x324, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_36
rw
Toggle Fields.

PRI_36

Bits 0-7: PRI_36.

IPR37

Interrupt Priority Register 37

Offset: 0x325, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_37
rw
Toggle Fields.

PRI_37

Bits 0-7: PRI_37.

IPR38

Interrupt Priority Register 38

Offset: 0x326, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_38
rw
Toggle Fields.

PRI_38

Bits 0-7: PRI_38.

IPR39

Interrupt Priority Register 39

Offset: 0x327, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_39
rw
Toggle Fields.

PRI_39

Bits 0-7: PRI_39.

IPR40

Interrupt Priority Register 40

Offset: 0x328, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_40
rw
Toggle Fields.

PRI_40

Bits 0-7: PRI_40.

IPR41

Interrupt Priority Register 41

Offset: 0x329, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_41
rw
Toggle Fields.

PRI_41

Bits 0-7: PRI_41.

IPR42

Interrupt Priority Register 42

Offset: 0x32A, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_42
rw
Toggle Fields.

PRI_42

Bits 0-7: PRI_42.

IPR43

Interrupt Priority Register 43

Offset: 0x32B, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_43
rw
Toggle Fields.

PRI_43

Bits 0-7: PRI_43.

IPR44

Interrupt Priority Register 44

Offset: 0x32C, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_44
rw
Toggle Fields.

PRI_44

Bits 0-7: PRI_44.

IPR45

Interrupt Priority Register 45

Offset: 0x32D, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_45
rw
Toggle Fields.

PRI_45

Bits 0-7: PRI_45.

IPR46

Interrupt Priority Register 46

Offset: 0x32E, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_46
rw
Toggle Fields.

PRI_46

Bits 0-7: PRI_46.

IPR47

Interrupt Priority Register 47

Offset: 0x32F, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_47
rw
Toggle Fields.

PRI_47

Bits 0-7: PRI_47.

IPR48

Interrupt Priority Register 48

Offset: 0x330, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_48
rw
Toggle Fields.

PRI_48

Bits 0-7: PRI_48.

IPR49

Interrupt Priority Register 49

Offset: 0x331, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_49
rw
Toggle Fields.

PRI_49

Bits 0-7: PRI_49.

IPR50

Interrupt Priority Register 50

Offset: 0x332, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_50
rw
Toggle Fields.

PRI_50

Bits 0-7: PRI_50.

IPR51

Interrupt Priority Register 51

Offset: 0x333, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_51
rw
Toggle Fields.

PRI_51

Bits 0-7: PRI_51.

IPR52

Interrupt Priority Register 52

Offset: 0x334, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_52
rw
Toggle Fields.

PRI_52

Bits 0-7: PRI_52.

IPR53

Interrupt Priority Register 53

Offset: 0x335, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_53
rw
Toggle Fields.

PRI_53

Bits 0-7: PRI_53.

IPR54

Interrupt Priority Register 54

Offset: 0x336, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_54
rw
Toggle Fields.

PRI_54

Bits 0-7: PRI_54.

IPR55

Interrupt Priority Register 55

Offset: 0x337, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_55
rw
Toggle Fields.

PRI_55

Bits 0-7: PRI_55.

IPR56

Interrupt Priority Register 56

Offset: 0x338, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_56
rw
Toggle Fields.

PRI_56

Bits 0-7: PRI_56.

IPR57

Interrupt Priority Register 57

Offset: 0x339, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_57
rw
Toggle Fields.

PRI_57

Bits 0-7: PRI_57.

IPR58

Interrupt Priority Register 58

Offset: 0x33A, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_58
rw
Toggle Fields.

PRI_58

Bits 0-7: PRI_58.

IPR59

Interrupt Priority Register 59

Offset: 0x33B, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_59
rw
Toggle Fields.

PRI_59

Bits 0-7: PRI_59.

IPR60

Interrupt Priority Register 60

Offset: 0x33C, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_60
rw
Toggle Fields.

PRI_60

Bits 0-7: PRI_60.

IPR61

Interrupt Priority Register 61

Offset: 0x33D, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_61
rw
Toggle Fields.

PRI_61

Bits 0-7: PRI_61.

IPR62

Interrupt Priority Register 62

Offset: 0x33E, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_62
rw
Toggle Fields.

PRI_62

Bits 0-7: PRI_62.

IPR63

Interrupt Priority Register 63

Offset: 0x33F, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_63
rw
Toggle Fields.

PRI_63

Bits 0-7: PRI_63.

IPR64

Interrupt Priority Register 64

Offset: 0x340, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_64
rw
Toggle Fields.

PRI_64

Bits 0-7: PRI_64.

IPR65

Interrupt Priority Register 65

Offset: 0x341, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_65
rw
Toggle Fields.

PRI_65

Bits 0-7: PRI_65.

IPR66

Interrupt Priority Register 66

Offset: 0x342, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_66
rw
Toggle Fields.

PRI_66

Bits 0-7: PRI_66.

IPR67

Interrupt Priority Register 67

Offset: 0x343, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_67
rw
Toggle Fields.

PRI_67

Bits 0-7: PRI_67.

STIR

Software Trigger Interrupt Register

Offset: 0xE00, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STIR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STIR
w
Toggle Fields.

STIR

Bits 0-31: STIR.

PMU

0x40007000: Power management unit

14/21 fields covered. Toggle Registers.

CTL

power control register

Offset: 0x0, reset: 0x0000C000, access: read-write

7/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LDEN
rw 		HDS
rw 		HDEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDOVS
rw 		LDNP
rw 		LDLP
rw 		BKPWEN
rw 		LVDT
rw 		LVDEN
rw 		STBRST
rw 		WURST
rw 		STBMOD
rw 		LDOLP
rw
Toggle Fields.

LDOLP

Bit 0: LDO Low Power Mode.

Allowed values:
0: Normal: LDO operates normally during Deepsleep mode
1: LowPower: LDO in low-power mode during Deepsleep mode

STBMOD

Bit 1: Standby Mode.

Allowed values:
0: DeepSleep: Enter Deep-sleep mode when the CPU enters deepsleep
1: Standby: Enter Standby mode when the CPU enters deepsleep

WURST

Bit 2: Wakeup Flag Reset.

Allowed values:
1: Clear: Clear the wakeup flag

STBRST

Bit 3: Standby Flag Reset.

Allowed values:
1: Clear: Clear the standby flag

LVDEN

Bit 4: Low Voltage Detector Enable.

Allowed values:
0: Disabled: Low voltage detector disabled
1: Enabled: Low voltage detector enabled

LVDT

Bits 5-7: Low Voltage Detector Threshold.

Allowed values:
0: V2_2: 2.2 V
1: V2_3: 2.3 V
2: V2_4: 2.4 V
3: V2_5: 2.5 V
4: V2_6: 2.6 V
5: V2_7: 2.7 V
6: V2_8: 2.8 V
7: V2_9: 2.9 V

BKPWEN

Bit 8: Backup Domain Write Enable.

Allowed values:
0: Disabled: Access to backup domain registers disabled
1: Enabled: Access to backup domain registers enabled

LDLP

Bit 10: Low-driver mode when use low power LDO..

LDNP

Bit 11: Low-driver mode when use normal power LDO.

LDOVS

Bits 14-15: LDO output voltage select.

HDEN

Bit 16: High-driver mode enable.

HDS

Bit 17: High-driver mode switch.

LDEN

Bits 18-19: Low-driver mode enable in Deep-sleep mode.

CS

power control/status register

Offset: 0x4, reset: 0x00000000, access: Unspecified

7/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LDRF
rw 		HDSRF
r 		HDRF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDOVSRF
r 		WUPEN0
rw 		LVDF
r 		STBF
r 		WUF
r
Toggle Fields.

WUF

Bit 0: Wakeup flag.

Allowed values:
0: NoWakeupEvent: No wakeup event occurred
1: WakeupEvent: A wakeup event was received from the WKUP pin or from the RTC wakeup event (RTC Tamper event, RTC TimeStamp event or RTC alarm)

STBF

Bit 1: Standby flag.

Allowed values:
0: NoStandbyEvent: Device has not been in Standby mode
1: StandbyEvent: Device has been in Standby mode

LVDF

Bit 2: Low Voltage Detector Status Flag.

Allowed values:
0: AboveThreshold: VDD is higher than the LVD threshold
1: BelowThreshold: VDD is lower than or equal to the LVD threshold

WUPEN0

Bit 8: Enable WKUP pin.

Allowed values:
0: Disabled: WKUP pin 0 is used for general purpose I/Os. An event on the WKUP pin 0 does not wakeup the device from Standby mode
1: Enabled: WKUP pin 0 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 0 wakes-up the system from Standby mode)

LDOVSRF

Bit 14: LDO voltage select ready flag.

HDRF

Bit 16: High-driver ready flag.

HDSRF

Bit 17: High-driver switch ready flag.

LDRF

Bits 18-19: Low-driver mode ready flag.

RCU

0x40021000: Reset and clock unit

22/159 fields covered. Toggle Registers.

CTL0

Control register

Offset: 0x0, reset: 0x00000083, access: Unspecified

4/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSTB
r 		PLLEN
rw 		CKMEN
rw 		HXTALBPS
rw 		HXTALSTB
r 		HXTALEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRC8MCALIB
r 		IRC8MADJ
rw 		IRC8MSTB
r 		IRC8MEN
rw
Toggle Fields.

IRC8MEN

Bit 0: Internal 8MHz RC oscillator Enable.

IRC8MSTB

Bit 1: IRC8M Internal 8MHz RC Oscillator stabilization Flag.

IRC8MADJ

Bits 3-7: Internal 8MHz RC Oscillator clock trim adjust value.

IRC8MCALIB

Bits 8-15: Internal 8MHz RC Oscillator calibration value register.

HXTALEN

Bit 16: External High Speed oscillator Enable.

HXTALSTB

Bit 17: External crystal oscillator (HXTAL) clock stabilization flag.

HXTALBPS

Bit 18: External crystal oscillator (HXTAL) clock bypass mode enable.

CKMEN

Bit 19: HXTAL Clock Monitor Enable.

PLLEN

Bit 24: PLL enable.

PLLSTB

Bit 25: PLL Clock Stabilization Flag.

CFG0

Clock configuration register 0 (RCU_CFG0)

Offset: 0x4, reset: 0x00000000, access: Unspecified

1/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USBDPSC_2
rw 		PLLMF_5
rw 		ADCPSC_2
rw 		PLLMF_4
rw 		CKOUT0SEL
rw 		USBDPSC_1_0
rw 		PLLMF_3_0
rw 		PREDV0
rw 		PLLSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCPSC_1_0
rw 		APB2PSC
rw 		APB1PSC
rw 		AHBPSC
rw 		SCSS
r 		SCS
rw
Toggle Fields.

SCS

Bits 0-1: System clock switch.

SCSS

Bits 2-3: System clock switch status.

AHBPSC

Bits 4-7: AHB prescaler selection.

APB1PSC

Bits 8-10: APB1 prescaler selection.

APB2PSC

Bits 11-13: APB2 prescaler selection.

ADCPSC_1_0

Bits 14-15: ADC clock prescaler selection.

PLLSEL

Bit 16: PLL Clock Source Selection.

PREDV0

Bit 17: PREDV0 division factor.

PLLMF_3_0

Bits 18-21: The PLL clock multiplication factor.

USBDPSC_1_0

Bits 22-23: USBD clock prescaler selection.

CKOUT0SEL

Bits 24-26: CKOUT0 Clock Source Selection.

PLLMF_4

Bit 27: Bit 4 of PLLMF.

ADCPSC_2

Bit 28: Bit 2 of ADCPSC.

PLLMF_5

Bit 30: Bit 5 of PLLMF.

USBDPSC_2

Bit 31: Bit 2 of USBDPSC.

INT

Clock interrupt register (RCU_INT)

Offset: 0x8, reset: 0x00000000, access: Unspecified

6/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKMIC
w 		PLLSTBIC
w 		HXTALSTBIC
w 		IRC8MSTBIC
w 		LXTALSTBIC
w 		IRC40KSTBIC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLSTBIE
rw 		HXTALSTBIE
rw 		IRC8MSTBIE
rw 		LXTALSTBIE
rw 		IRC40KSTBIE
rw 		CKMIF
r 		PLLSTBIF
r 		HXTALSTBIF
r 		IRC8MSTBIF
r 		LXTALSTBIF
r 		IRC40KSTBIF
r
Toggle Fields.

IRC40KSTBIF

Bit 0: IRC40K stabilization interrupt flag.

LXTALSTBIF

Bit 1: LXTAL stabilization interrupt flag.

IRC8MSTBIF

Bit 2: IRC8M stabilization interrupt flag.

HXTALSTBIF

Bit 3: HXTAL stabilization interrupt flag.

PLLSTBIF

Bit 4: PLL stabilization interrupt flag.

CKMIF

Bit 7: HXTAL Clock Stuck Interrupt Flag.

IRC40KSTBIE

Bit 8: IRC40K Stabilization interrupt enable.

LXTALSTBIE

Bit 9: LXTAL Stabilization Interrupt Enable.

IRC8MSTBIE

Bit 10: IRC8M Stabilization Interrupt Enable.

HXTALSTBIE

Bit 11: HXTAL Stabilization Interrupt Enable.

PLLSTBIE

Bit 12: PLL Stabilization Interrupt Enable.

IRC40KSTBIC

Bit 16: IRC40K Stabilization Interrupt Clear.

LXTALSTBIC

Bit 17: LXTAL Stabilization Interrupt Clear.

IRC8MSTBIC

Bit 18: IRC8M Stabilization Interrupt Clear.

HXTALSTBIC

Bit 19: HXTAL Stabilization Interrupt Clear.

PLLSTBIC

Bit 20: PLL stabilization Interrupt Clear.

CKMIC

Bit 23: HXTAL Clock Stuck Interrupt Clear.

APB2RST

APB2 reset register (RCU_APB2RST)

Offset: 0xC, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIMER10RST
rw 		TIMER9RST
rw 		TIMER8RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC2RST
rw 		USART0RST
rw 		TIMER7RST
rw 		SPI0RST
rw 		TIMER0RST
rw 		ADC1RST
rw 		ADC0RST
rw 		PGRST
rw 		PFRST
rw 		PERST
rw 		PDRST
rw 		PCRST
rw 		PBRST
rw 		PARST
rw 		AFRST
rw
Toggle Fields.

AFRST

Bit 0: Alternate function I/O reset.

PARST

Bit 2: GPIO port A reset.

PBRST

Bit 3: GPIO port B reset.

PCRST

Bit 4: GPIO port C reset.

PDRST

Bit 5: GPIO port D reset.

PERST

Bit 6: GPIO port E reset.

PFRST

Bit 7: GPIO portF reset.

PGRST

Bit 8: GPIO port G reset.

ADC0RST

Bit 9: ADC0 reset.

ADC1RST

Bit 10: ADC1 reset.

TIMER0RST

Bit 11: Timer 0 reset.

SPI0RST

Bit 12: SPI0 reset.

TIMER7RST

Bit 13: Timer 7 reset.

USART0RST

Bit 14: USART0 Reset.

ADC2RST

Bit 15: ADC2 reset.

TIMER8RST

Bit 19: Timer 8 reset.

TIMER9RST

Bit 20: Timer 9 reset.

TIMER10RST

Bit 21: Timer 10 reset.

APB1RST

APB1 reset register (RCU_APB1RST)

Offset: 0x10, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACRST
rw 		PMURST
rw 		BKPIRST
rw 		CAN0RST
rw 		USBDRST
rw 		I2C1RST
rw 		I2C0RST
rw 		UART4RST
rw 		UART3RST
rw 		USART2RST
rw 		USART1RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2RST
rw 		SPI1RST
rw 		WWDGTRST
rw 		TIMER13RST
rw 		TIMER12RST
rw 		TIMER11RST
rw 		TIMER6RST
rw 		TIMER5RST
rw 		TIMER4RST
rw 		TIMER3RST
rw 		TIMER2RST
rw 		TIMER1RST
rw
Toggle Fields.

TIMER1RST

Bit 0: TIMER1 timer reset.

TIMER2RST

Bit 1: TIMER2 timer reset.

TIMER3RST

Bit 2: TIMER3 timer reset.

TIMER4RST

Bit 3: TIMER4 timer reset.

TIMER5RST

Bit 4: TIMER5 timer reset.

TIMER6RST

Bit 5: TIMER6 timer reset.

TIMER11RST

Bit 6: TIMER11 timer reset.

TIMER12RST

Bit 7: TIMER12 timer reset.

TIMER13RST

Bit 8: TIMER13 timer reset.

WWDGTRST

Bit 11: Window watchdog timer reset.

SPI1RST

Bit 14: SPI1 reset.

SPI2RST

Bit 15: SPI2 reset.

USART1RST

Bit 17: USART1 reset.

USART2RST

Bit 18: USART2 reset.

UART3RST

Bit 19: UART3 reset.

UART4RST

Bit 20: UART4 reset.

I2C0RST

Bit 21: I2C0 reset.

I2C1RST

Bit 22: I2C1 reset.

USBDRST

Bit 23: USBD reset.

CAN0RST

Bit 25: CAN0 reset.

BKPIRST

Bit 27: Backup interface reset.

PMURST

Bit 28: Power control reset.

DACRST

Bit 29: DAC reset.

AHBEN

AHB enable register

Offset: 0x14, reset: 0x00000014, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDIOEN
rw 		EXMCEN
rw 		CRCEN
rw 		FMCSPEN
rw 		SRAMSPEN
rw 		DMA1EN
rw 		DMA0EN
rw
Toggle Fields.

DMA0EN

Bit 0: DMA0 clock enable.

DMA1EN

Bit 1: DMA1 clock enable.

SRAMSPEN

Bit 2: SRAM interface clock enable when sleep mode.

FMCSPEN

Bit 4: FMC clock enable when sleep mode.

CRCEN

Bit 6: CRC clock enable.

EXMCEN

Bit 8: EXMC clock enable.

SDIOEN

Bit 10: SDIO clock enable.

APB2EN

APB2 clock enable register (RCU_APB2EN)

Offset: 0x18, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIMER10EN
rw 		TIMER9EN
rw 		TIMER8EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC2EN
rw 		USART0EN
rw 		TIMER7EN
rw 		SPI0EN
rw 		TIMER0EN
rw 		ADC1EN
rw 		ADC0EN
rw 		PGEN
rw 		PFEN
rw 		PEEN
rw 		PDEN
rw 		PCEN
rw 		PBEN
rw 		PAEN
rw 		AFEN
rw
Toggle Fields.

AFEN

Bit 0: Alternate function IO clock enable .

PAEN

Bit 2: GPIO port A clock enable.

PBEN

Bit 3: GPIO port B clock enable.

PCEN

Bit 4: GPIO port C clock enable.

PDEN

Bit 5: GPIO port D clock enable .

PEEN

Bit 6: GPIO port E clock enable .

PFEN

Bit 7: GPIO port F clock enable .

PGEN

Bit 8: GPIO port G clock enable.

ADC0EN

Bit 9: ADC0 clock enable.

ADC1EN

Bit 10: ADC1 clock enable.

TIMER0EN

Bit 11: TIMER0 clock enable .

SPI0EN

Bit 12: SPI0 clock enable.

TIMER7EN

Bit 13: TIMER7 clock enable.

USART0EN

Bit 14: USART0 clock enable.

ADC2EN

Bit 15: ADC2 clock enable.

TIMER8EN

Bit 19: TIMER8 clock enable.

TIMER9EN

Bit 20: TIMER9 clock enable .

TIMER10EN

Bit 21: TIMER10 clock enable .

APB1EN

APB1 clock enable register (RCU_APB1EN)

Offset: 0x1C, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACEN
rw 		PMUEN
rw 		BKPIEN
rw 		CAN0EN
rw 		USBDEN
rw 		I2C1EN
rw 		I2C0EN
rw 		UART4EN
rw 		UART3EN
rw 		USART2EN
rw 		USART1EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2EN
rw 		SPI1EN
rw 		WWDGTEN
rw 		TIMER13EN
rw 		TIMER12EN
rw 		TIMER11EN
rw 		TIMER6EN
rw 		TIMER5EN
rw 		TIMER4EN
rw 		TIMER3EN
rw 		TIMER2EN
rw 		TIMER1EN
rw
Toggle Fields.

TIMER1EN

Bit 0: TIMER1 timer clock enable.

TIMER2EN

Bit 1: TIMER2 timer clock enable.

TIMER3EN

Bit 2: TIMER3 timer clock enable.

TIMER4EN

Bit 3: TIMER4 timer clock enable.

TIMER5EN

Bit 4: TIMER5 timer clock enable.

TIMER6EN

Bit 5: TIMER6 timer clock enable.

TIMER11EN

Bit 6: TIMER11 timer clock enable.

TIMER12EN

Bit 7: TIMER12 timer clock enable.

TIMER13EN

Bit 8: TIMER13 timer clock enable.

WWDGTEN

Bit 11: Window watchdog timer clock enable.

SPI1EN

Bit 14: SPI1 clock enable.

SPI2EN

Bit 15: SPI2 clock enable.

USART1EN

Bit 17: USART1 clock enable.

USART2EN

Bit 18: USART2 clock enable.

UART3EN

Bit 19: UART3 clock enable.

UART4EN

Bit 20: UART4 clock enable.

I2C0EN

Bit 21: I2C0 clock enable.

I2C1EN

Bit 22: I2C1 clock enable.

USBDEN

Bit 23: USBD clock enable.

CAN0EN

Bit 25: CAN0 clock enable.

BKPIEN

Bit 27: Backup interface clock enable .

PMUEN

Bit 28: Power control clock enable .

DACEN

Bit 29: DAC clock enable.

BDCTL

Backup domain control register (RCU_BDCTL)

Offset: 0x20, reset: 0x00000018, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKPRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCEN
rw 		RTCSRC
rw 		LXTALDRI
rw 		LXTALBPS
rw 		LXTALSTB
r 		LXTALEN
rw
Toggle Fields.

LXTALEN

Bit 0: LXTAL enable.

LXTALSTB

Bit 1: External low-speed oscillator stabilization.

LXTALBPS

Bit 2: LXTAL bypass mode enable.

LXTALDRI

Bits 3-4: LXTAL drive capability.

RTCSRC

Bits 8-9: RTC clock entry selection.

RTCEN

Bit 15: RTC clock enable.

BKPRST

Bit 16: Backup domain reset.

RSTSCK

Reset source /clock register (RCU_RSTSCK)

Offset: 0x24, reset: 0x0C000000, access: Unspecified

7/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPRSTF
r 		WWDGTRSTF
r 		FWDGTRSTF
r 		SWRSTF
r 		PORRSTF
r 		EPRSTF
r 		RSTFC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRC40KSTB
r 		IRC40KEN
rw
Toggle Fields.

IRC40KEN

Bit 0: IRC40K enable.

IRC40KSTB

Bit 1: IRC40K stabilization.

RSTFC

Bit 24: Reset flag clear.

EPRSTF

Bit 26: External PIN reset flag.

PORRSTF

Bit 27: Power reset flag.

SWRSTF

Bit 28: Software reset flag.

FWDGTRSTF

Bit 29: Free Watchdog timer reset flag.

WWDGTRSTF

Bit 30: Window watchdog timer reset flag.

LPRSTF

Bit 31: Low-power reset flag.

CFG1

Clock Configuration register 1

Offset: 0x2C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLPRESEL
rw 		ADCPSC_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

ADCPSC_3

Bit 29: Bit 3 of ADCPSC.

PLLPRESEL

Bit 30: PLL Clock Source Selection.

DSV

Deep sleep mode Voltage register

Offset: 0x34, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSLPVS
rw
Toggle Fields.

DSLPVS

Bits 0-2: Deep-sleep mode voltage select.

ADDCTL

Additional clock control register

Offset: 0xC0, reset: 0x80000000, access: Unspecified

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IRC48MCALIB
r 		IRC48MSTB
r 		IRC48MEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CK48MSEL
rw
Toggle Fields.

CK48MSEL

Bit 0: 48MHz clock selection.

IRC48MEN

Bit 16: Internal 48MHz RC oscillator enable.

IRC48MSTB

Bit 17: Internal 48MHz RC oscillator clock stabilization Flag.

IRC48MCALIB

Bits 24-31: Internal 48MHz RC oscillator calibration value register.

ADDINT

Additional clock interrupt register

Offset: 0xCC, reset: 0x00000000, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IRC48MSTBIC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRC48MSTBIE
rw 		IRC48MSTBIF
r
Toggle Fields.

IRC48MSTBIF

Bit 6: IRC48M stabilization interrupt flag.

IRC48MSTBIE

Bit 14: Internal 48 MHz RC oscillator Stabilization Interrupt Enable.

IRC48MSTBIC

Bit 22: Internal 48 MHz RC oscillator Stabilization Interrupt Clear.

ADDAPB1RST

APB1 additional reset register

Offset: 0xE0, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTCRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

CTCRST

Bit 27: CTC reset.

ADDAPB1EN

APB1 additional enable register

Offset: 0xE4, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

CTCEN

Bit 27: CTC clock enable.

RTC

0x40002800: Real-time clock

2/17 fields covered. Toggle Registers.

INTEN

RTC interrupt enable register

Offset: 0x0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVIE
rw 		ALRMIE
rw 		SCIE
rw
Toggle Fields.

SCIE

Bit 0: Second interrupt.

ALRMIE

Bit 1: Alarm interrupt enable.

OVIE

Bit 2: Overflow interrupt enable.

CTL

control register

Offset: 0x4, reset: 0x00000020, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LWOFF
rw 		CMF
rw 		RSYNF
rw 		OVIF
rw 		ALRMIF
rw 		SCIF
rw
Toggle Fields.

SCIF

Bit 0: Sencond interrupt flag.

ALRMIF

Bit 1: Alarm interrupt flag.

OVIF

Bit 2: Overflow interrupt flag.

RSYNF

Bit 3: Registers synchronized flag.

CMF

Bit 4: Configuration mode flag.

LWOFF

Bit 5: Last write operation finished flag.

PSCH

RTC prescaler high register

Offset: 0x8, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
w
Toggle Fields.

PSC

Bits 0-3: RTC prescaler value high.

PSCL

RTC prescaler low register

Offset: 0xC, reset: 0x00008000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
w
Toggle Fields.

PSC

Bits 0-15: RTC prescaler value low.

DIVH

RTC divider high register

Offset: 0x10, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
r
Toggle Fields.

DIV

Bits 0-3: RTC divider value high.

DIVL

RTC divider low register

Offset: 0x14, reset: 0x00008000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIV
r
Toggle Fields.

DIV

Bits 0-15: RTC divider value low.

CNTH

RTC counter high register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: RTC counter value high.

CNTL

RTC counter low register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: RTC conuter value low.

ALRMH

Alarm high register

Offset: 0x20, reset: 0x0000FFFF, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALRM
w
Toggle Fields.

ALRM

Bits 0-15: Alarm value high.

ALRML

RTC alarm low register

Offset: 0x24, reset: 0x0000FFFF, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALRM
w
Toggle Fields.

ALRM

Bits 0-15: alarm value low.

SDIO

0x40018000: Secure digital input/output interface

31/99 fields covered. Toggle Registers.

PWRCTL

Power control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWRCTL
rw
Toggle Fields.

PWRCTL

Bits 0-1: SDIO power control bits.

CLKCTL

Clock control register

Offset: 0x4, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIV_8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HWCLKEN
rw 		CLKEDGE
rw 		BUSMODE
rw 		CLKBYP
rw 		CLKPWRSAV
rw 		CLKEN
rw 		DIV_0_7
rw
Toggle Fields.

DIV_0_7

Bits 0-7: Clock division.

CLKEN

Bit 8: SDIO_CLK clock output enable bit.

CLKPWRSAV

Bit 9: SDIO_CLK clock dynamic switch on/off for power saving.

CLKBYP

Bit 10: Clock bypass enable bit.

BUSMODE

Bits 11-12: SDIO card bus mode control bit.

CLKEDGE

Bit 13: SDIO_CLK clock edge selection bit.

HWCLKEN

Bit 14: Hardware Clock Control enable bit.

DIV_8

Bit 31: MSB of Clock division.

CMDAGMT

Command argument register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDAGMT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDAGMT
rw
Toggle Fields.

CMDAGMT

Bits 0-31: SDIO card command argument.

CMDCTL

Command control register

Offset: 0xC, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATAEN
rw 		NINTEN
rw 		ENCMDC
rw 		SUSPEND
rw 		CSMEN
rw 		WAITDEND
rw 		INTWAIT
rw 		CMDRESP
rw 		CMDIDX
rw
Toggle Fields.

CMDIDX

Bits 0-5: Command index.

CMDRESP

Bits 6-7: Command response type bits.

INTWAIT

Bit 8: Interrupt wait instead of timeout.

WAITDEND

Bit 9: Waits for ends of data transfer.

CSMEN

Bit 10: Command state machine (CSM) enable bit.

SUSPEND

Bit 11: SD I/O suspend command(SD I/O only).

ENCMDC

Bit 12: CMD completion signal enabled (CE-ATA only).

NINTEN

Bit 13: No CE-ATA Interrupt (CE-ATA only).

ATAEN

Bit 14: CE-ATA command enable(CE-ATA only).

RSPCMDIDX

Command index response register

Offset: 0x10, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSPCMDIDX
r
Toggle Fields.

RSPCMDIDX

Bits 0-5: Last response command index.

RESP0

Response register 0

Offset: 0x14, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESP0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESP0
r
Toggle Fields.

RESP0

Bits 0-31: Card state.

RESP1

Response register 1

Offset: 0x18, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESP1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESP1
r
Toggle Fields.

RESP1

Bits 0-31: Card state.

RESP2

Response register 2

Offset: 0x1C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESP2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESP2
r
Toggle Fields.

RESP2

Bits 0-31: Card state.

RESP3

Response register 3

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESP3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESP3
r
Toggle Fields.

RESP3

Bits 0-31: Response register 3.

DATATO

Data timeout register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATATO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATATO
rw
Toggle Fields.

DATATO

Bits 0-31: Data timeout period.

DATALEN

Data length register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATALEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATALEN
rw
Toggle Fields.

DATALEN

Bits 0-24: Data transfer length.

DATACTL

Data control register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOEN
rw 		RWTYPE
rw 		RWSTOP
rw 		RWEN
rw 		BLKSZ
rw 		DMAEN
rw 		TRANSMOD
rw 		DATADIR
rw 		DATAEN
rw
Toggle Fields.

DATAEN

Bit 0: Data transfer enabled bit.

DATADIR

Bit 1: Data transfer direction.

TRANSMOD

Bit 2: Data transfer mode.

DMAEN

Bit 3: DMA enable bit.

BLKSZ

Bits 4-7: Data block size.

RWEN

Bit 8: Read wait mode enabled.

RWSTOP

Bit 9: Read wait stop.

RWTYPE

Bit 10: Read wait type.

IOEN

Bit 11: SD I/O specific function enable.

DATACNT

Data counter register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATACNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATACNT
r
Toggle Fields.

DATACNT

Bits 0-24: Data count value.

STAT

Status register

Offset: 0x34, reset: 0x00000000, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATAEND
r 		SDIOINT
r 		RXDTVAL
r 		TXDTVAL
r 		RFE
r 		TFE
r 		RFF
r 		TFF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFH
r 		TFH
r 		RXRUN
r 		TXRUN
r 		CMDRUN
r 		DTBLKEND
r 		STBITE
r 		DTEND
r 		CMDSEND
r 		CMDRECV
r 		RXORE
r 		TXURE
r 		DTTMOUT
r 		CMDTMOUT
r 		DTCRCERR
r 		CCRCERR
r
Toggle Fields.

CCRCERR

Bit 0: Command response received.

DTCRCERR

Bit 1: Data block sent/received.

CMDTMOUT

Bit 2: Command response timeout.

DTTMOUT

Bit 3: Data timeout.

TXURE

Bit 4: Transmit FIFO underrun error occurs.

RXORE

Bit 5: Received FIFO overrun error occurs.

CMDRECV

Bit 6: Command response received.

CMDSEND

Bit 7: Command sent.

DTEND

Bit 8: Data end.

STBITE

Bit 9: Start bit error in the bus.

DTBLKEND

Bit 10: Data block sent/received.

CMDRUN

Bit 11: Command transmission in progress.

TXRUN

Bit 12: Data transmission in progress.

RXRUN

Bit 13: Data reception in progress.

TFH

Bit 14: Transmit FIFO is half empty.

RFH

Bit 15: Receive FIFO is half full.

TFF

Bit 16: Transmit FIFO is full.

RFF

Bit 17: Receive FIFO is full.

TFE

Bit 18: Transmit FIFO is empty.

RFE

Bit 19: Receive FIFO is empty.

TXDTVAL

Bit 20: Data is valid in transmit FIFO.

RXDTVAL

Bit 21: Data is valid in receive FIFO.

SDIOINT

Bit 22: SD I/O interrupt received.

ATAEND

Bit 23: CE-ATA command completion signal received.

INTC

Interrupt clear register

Offset: 0x38, reset: 0x00000000, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATAENDC
w 		SDIOINTC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTBLKENDC
w 		STBITEC
w 		DTENDC
w 		CMDSENDC
w 		CMDRECVC
w 		RXOREC
w 		TXUREC
w 		DTTMOUTC
w 		CMDTMOUTC
w 		DTCRCERRC
w 		CCRCERRC
w
Toggle Fields.

CCRCERRC

Bit 0: CCRCERR flag clear bit.

DTCRCERRC

Bit 1: DTCRCERR flag clear bit.

CMDTMOUTC

Bit 2: CMDTMOUT flag clear bit.

DTTMOUTC

Bit 3: DTTMOUT flag clear bit.

TXUREC

Bit 4: TXURE flag clear bit.

RXOREC

Bit 5: RXORE flag clear bit.

CMDRECVC

Bit 6: CMDRECV flag clear bit.

CMDSENDC

Bit 7: CMDSEND flag clear bit.

DTENDC

Bit 8: DTEND flag clear bit.

STBITEC

Bit 9: STBITE flag clear bit.

DTBLKENDC

Bit 10: DTBLKEND flag clear bit.

SDIOINTC

Bit 22: SDIOINT flag clear bit.

ATAENDC

Bit 23: ATAEND flag clear bit.

INTEN

Interrupt enable register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATAENDIE
rw 		SDIOINTIE
rw 		RXDTVALIE
rw 		TXDTVALIE
rw 		RFEIE
rw 		TFEIE
rw 		RFFIE
rw 		TFFIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFHIE
rw 		TFHIE
rw 		RXRUNIE
rw 		TXRUNIE
rw 		CMDRUNIE
rw 		DTBLKENDIE
rw 		STBITEIE
rw 		DTENDIE
rw 		CMDSENDIE
rw 		CMDRECVIE
rw 		RXOREIE
rw 		TXUREIE
rw 		DTTMOUTIE
rw 		CMDTMOUTIE
rw 		DTCRCERRIE
rw 		CCRCERRIE
rw
Toggle Fields.

CCRCERRIE

Bit 0: Command response CRC fail interrupt enable.

DTCRCERRIE

Bit 1: Data CRC fail interrupt enable.

CMDTMOUTIE

Bit 2: Command response timeout interrupt enable.

DTTMOUTIE

Bit 3: Data timeout interrupt enable.

TXUREIE

Bit 4: Transmit FIFO underrun error interrupt enable.

RXOREIE

Bit 5: Received FIFO overrun error interrupt enable.

CMDRECVIE

Bit 6: Command response received interrupt enable.

CMDSENDIE

Bit 7: Command sent interrupt enable.

DTENDIE

Bit 8: Data end interrupt enable.

STBITEIE

Bit 9: Start bit error interrupt enable.

DTBLKENDIE

Bit 10: Data block end interrupt enable.

CMDRUNIE

Bit 11: Command transmission interrupt enable.

TXRUNIE

Bit 12: Data transmission interrupt enable.

RXRUNIE

Bit 13: Data reception interrupt enable.

TFHIE

Bit 14: Transmit FIFO half empty interrupt enable.

RFHIE

Bit 15: Receive FIFO half full interrupt enable.

TFFIE

Bit 16: Transmit FIFO full interrupt enable.

RFFIE

Bit 17: Receive FIFO full interrupt enable.

TFEIE

Bit 18: Transmit FIFO empty interrupt enable.

RFEIE

Bit 19: Receive FIFO empty interrupt enable.

TXDTVALIE

Bit 20: Data valid in transmit FIFO interrupt enable.

RXDTVALIE

Bit 21: Data valid in receive FIFO interrupt enable.

SDIOINTIE

Bit 22: SD I/O interrupt received interrupt enable.

ATAENDIE

Bit 23: CE-ATA command completion signal received interrupt enable.

FIFOCNT

FIFO counter register

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCNT
r
Toggle Fields.

FIFOCNT

Bits 0-23: FIFO counter.

FIFO

FIFO data register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODT
rw
Toggle Fields.

FIFODT

Bits 0-31: Receive FIFO data or transmit FIFO data.

SPI0

0x40013000: Serial peripheral interface

43/49 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDEN
rw 		BDOEN
rw 		CRCEN
rw 		CRCNT
rw 		FF16
rw 		RO
rw 		SWNSSEN
rw 		SWNSS
rw 		LF
rw 		SPIEN
rw 		PSC
rw 		MSTMOD
rw 		CKPL
rw 		CKPH
rw
Toggle Fields.

CKPH

Bit 0: Clock Phase Selection.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CKPL

Bit 1: Clock polarity Selection.

Allowed values:
0: IdleLow: CLK pulled low when idle
1: IdleHigh: CLK pulled high when idle

MSTMOD

Bit 2: Master Mode Enable.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

PSC

Bits 3-5: Master Clock Prescaler Selection.

Allowed values:
0: Div2: PCLK / 2
1: Div4: PCLK / 4
2: Div8: PCLK / 8
3: Div16: PCLK / 16
4: Div32: PCLK / 32
5: Div64: PCLK / 64
6: Div128: PCLK / 128
7: Div256: PCLK / 256

SPIEN

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LF

Bit 7: LSB First Mode.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SWNSS

Bit 8: NSS Pin Selection In NSS Software Mode.

Allowed values:
0: SlaveSelected: NSS is pulled low
1: SlaveNotSelected: NSS is pulled high

SWNSSEN

Bit 9: NSS Software Mode Selection.

Allowed values:
0: Hardware: Software slave management disabled
1: Software: Software slave management enabled

RO

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: ReceiveOnly: Output disabled (Receive-only mode)

FF16

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNT

Bit 12: CRC Next Transfer.

Allowed values:
0: Data: Next transmit value is data from Tx buffer
1: CRC: Next transmit value is CRC value from TCRC

CRCEN

Bit 13: CRC Calculation Enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BDOEN

Bit 14: Bidirectional Transmit output enable .

Allowed values:
0: ReceiveOnly: Receive-only mode
1: TransmitOnly: Transmit-only mode

BDEN

Bit 15: Bidirectional enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

6/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBEIE
rw 		RBNEIE
rw 		ERRIE
rw 		TMOD
rw 		NSSP
rw 		NSSDRV
rw 		DMATEN
rw 		DMAREN
rw
Toggle Fields.

DMAREN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

DMATEN

Bit 1: Transmit Buffer DMA Enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

NSSDRV

Bit 2: Drive NSS Output.

Allowed values:
0: Disabled: NSS output is disabled in master mode
1: Enabled: NSS output is enabled in master mode

NSSP

Bit 3: SPI NSS pulse mode Enable.

TMOD

Bit 4: SPI TI Mode Enable.

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

RBNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Disabled: RBNE interrupt disabled
1: Enabled: RBNE interrupt enabled

TBEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Disabled: TBE interrupt disabled
1: Enabled: TBE interrupt enabled

STAT

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FERR
rw 		TRANS
r 		RXORERR
r 		CONFERR
r 		CRCERR
rw 		TXURERR
r 		I2SCH
r 		TBE
r 		RBNE
r
Toggle Fields.

RBNE

Bit 0: Receive Buffer Not Empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TBE

Bit 1: Transmit Buffer Empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

I2SCH

Bit 2: I2S channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

TXURERR

Bit 3: Transmission underrun error bit.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: SPI CRC Error Bit.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

CONFERR

Bit 5: SPI Configuration error.

Allowed values:
0: NoFault: No configuration fault occurred
1: Fault: Configuration fault occurred

RXORERR

Bit 6: Reception Overrun Error Bit.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

TRANS

Bit 7: Transmitting On-going Bit.

Allowed values:
0: Idle: SPI or I2S is idle
1: Busy: SPI or I2S is currently transmitting or receiving

FERR

Bit 8: Format Error.

DATA

data register

Offset: 0xC, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Data transfer register.

Allowed values: 0-65535

CRCPOLY

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0-65535

RCRC

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCRC
r
Toggle Fields.

RCRC

Bits 0-15: RX CRC register.

Allowed values: 0-65535

TCRC

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRC
r
Toggle Fields.

TCRC

Bits 0-15: Tx CRC register.

Allowed values: 0-65535

I2SCTL

I2S control register

Offset: 0x1C, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SSEL
rw 		I2SEN
rw 		I2SOPMOD
rw 		PCMSMOD
rw 		I2SSTD
rw 		CKPL
rw 		DTLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DTLEN

Bits 1-2: Data length.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPL

Bit 3: Idle state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSMOD

Bit 7: PCM frame synchronization mode.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SOPMOD

Bits 8-9: I2S operation mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SEN

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SSEL

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPSC

I2S prescaler register

Offset: 0x20, reset: 0x0002, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOEN
rw 		OF
rw 		DIV
rw
Toggle Fields.

DIV

Bits 0-7: Dividing factor for the prescaler.

Allowed values: 1-255

OF

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is DIV * 2
1: Odd: Real divider value is (DIV * 2) + 1

MCKOEN

Bit 9: I2S_MCK output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

QCTL

Quad-SPI mode control register

Offset: 0x80, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IO23_DRV
rw 		QRD
rw 		QMOD
rw
Toggle Fields.

QMOD

Bit 0: Quad-SPI mode enable.

QRD

Bit 1: Quad-SPI mode read select.

IO23_DRV

Bit 2: Drive IO2 and IO3 enable.

SPI1

0x40003800: Serial peripheral interface

43/49 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDEN
rw 		BDOEN
rw 		CRCEN
rw 		CRCNT
rw 		FF16
rw 		RO
rw 		SWNSSEN
rw 		SWNSS
rw 		LF
rw 		SPIEN
rw 		PSC
rw 		MSTMOD
rw 		CKPL
rw 		CKPH
rw
Toggle Fields.

CKPH

Bit 0: Clock Phase Selection.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CKPL

Bit 1: Clock polarity Selection.

Allowed values:
0: IdleLow: CLK pulled low when idle
1: IdleHigh: CLK pulled high when idle

MSTMOD

Bit 2: Master Mode Enable.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

PSC

Bits 3-5: Master Clock Prescaler Selection.

Allowed values:
0: Div2: PCLK / 2
1: Div4: PCLK / 4
2: Div8: PCLK / 8
3: Div16: PCLK / 16
4: Div32: PCLK / 32
5: Div64: PCLK / 64
6: Div128: PCLK / 128
7: Div256: PCLK / 256

SPIEN

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LF

Bit 7: LSB First Mode.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SWNSS

Bit 8: NSS Pin Selection In NSS Software Mode.

Allowed values:
0: SlaveSelected: NSS is pulled low
1: SlaveNotSelected: NSS is pulled high

SWNSSEN

Bit 9: NSS Software Mode Selection.

Allowed values:
0: Hardware: Software slave management disabled
1: Software: Software slave management enabled

RO

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: ReceiveOnly: Output disabled (Receive-only mode)

FF16

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNT

Bit 12: CRC Next Transfer.

Allowed values:
0: Data: Next transmit value is data from Tx buffer
1: CRC: Next transmit value is CRC value from TCRC

CRCEN

Bit 13: CRC Calculation Enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BDOEN

Bit 14: Bidirectional Transmit output enable .

Allowed values:
0: ReceiveOnly: Receive-only mode
1: TransmitOnly: Transmit-only mode

BDEN

Bit 15: Bidirectional enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

6/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBEIE
rw 		RBNEIE
rw 		ERRIE
rw 		TMOD
rw 		NSSP
rw 		NSSDRV
rw 		DMATEN
rw 		DMAREN
rw
Toggle Fields.

DMAREN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

DMATEN

Bit 1: Transmit Buffer DMA Enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

NSSDRV

Bit 2: Drive NSS Output.

Allowed values:
0: Disabled: NSS output is disabled in master mode
1: Enabled: NSS output is enabled in master mode

NSSP

Bit 3: SPI NSS pulse mode Enable.

TMOD

Bit 4: SPI TI Mode Enable.

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

RBNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Disabled: RBNE interrupt disabled
1: Enabled: RBNE interrupt enabled

TBEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Disabled: TBE interrupt disabled
1: Enabled: TBE interrupt enabled

STAT

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FERR
rw 		TRANS
r 		RXORERR
r 		CONFERR
r 		CRCERR
rw 		TXURERR
r 		I2SCH
r 		TBE
r 		RBNE
r
Toggle Fields.

RBNE

Bit 0: Receive Buffer Not Empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TBE

Bit 1: Transmit Buffer Empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

I2SCH

Bit 2: I2S channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

TXURERR

Bit 3: Transmission underrun error bit.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: SPI CRC Error Bit.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

CONFERR

Bit 5: SPI Configuration error.

Allowed values:
0: NoFault: No configuration fault occurred
1: Fault: Configuration fault occurred

RXORERR

Bit 6: Reception Overrun Error Bit.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

TRANS

Bit 7: Transmitting On-going Bit.

Allowed values:
0: Idle: SPI or I2S is idle
1: Busy: SPI or I2S is currently transmitting or receiving

FERR

Bit 8: Format Error.

DATA

data register

Offset: 0xC, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Data transfer register.

Allowed values: 0-65535

CRCPOLY

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0-65535

RCRC

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCRC
r
Toggle Fields.

RCRC

Bits 0-15: RX CRC register.

Allowed values: 0-65535

TCRC

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRC
r
Toggle Fields.

TCRC

Bits 0-15: Tx CRC register.

Allowed values: 0-65535

I2SCTL

I2S control register

Offset: 0x1C, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SSEL
rw 		I2SEN
rw 		I2SOPMOD
rw 		PCMSMOD
rw 		I2SSTD
rw 		CKPL
rw 		DTLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DTLEN

Bits 1-2: Data length.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPL

Bit 3: Idle state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSMOD

Bit 7: PCM frame synchronization mode.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SOPMOD

Bits 8-9: I2S operation mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SEN

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SSEL

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPSC

I2S prescaler register

Offset: 0x20, reset: 0x0002, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOEN
rw 		OF
rw 		DIV
rw
Toggle Fields.

DIV

Bits 0-7: Dividing factor for the prescaler.

Allowed values: 1-255

OF

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is DIV * 2
1: Odd: Real divider value is (DIV * 2) + 1

MCKOEN

Bit 9: I2S_MCK output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

QCTL

Quad-SPI mode control register

Offset: 0x80, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IO23_DRV
rw 		QRD
rw 		QMOD
rw
Toggle Fields.

QMOD

Bit 0: Quad-SPI mode enable.

QRD

Bit 1: Quad-SPI mode read select.

IO23_DRV

Bit 2: Drive IO2 and IO3 enable.

SPI2

0x40003C00: Serial peripheral interface

43/49 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDEN
rw 		BDOEN
rw 		CRCEN
rw 		CRCNT
rw 		FF16
rw 		RO
rw 		SWNSSEN
rw 		SWNSS
rw 		LF
rw 		SPIEN
rw 		PSC
rw 		MSTMOD
rw 		CKPL
rw 		CKPH
rw
Toggle Fields.

CKPH

Bit 0: Clock Phase Selection.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CKPL

Bit 1: Clock polarity Selection.

Allowed values:
0: IdleLow: CLK pulled low when idle
1: IdleHigh: CLK pulled high when idle

MSTMOD

Bit 2: Master Mode Enable.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

PSC

Bits 3-5: Master Clock Prescaler Selection.

Allowed values:
0: Div2: PCLK / 2
1: Div4: PCLK / 4
2: Div8: PCLK / 8
3: Div16: PCLK / 16
4: Div32: PCLK / 32
5: Div64: PCLK / 64
6: Div128: PCLK / 128
7: Div256: PCLK / 256

SPIEN

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LF

Bit 7: LSB First Mode.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SWNSS

Bit 8: NSS Pin Selection In NSS Software Mode.

Allowed values:
0: SlaveSelected: NSS is pulled low
1: SlaveNotSelected: NSS is pulled high

SWNSSEN

Bit 9: NSS Software Mode Selection.

Allowed values:
0: Hardware: Software slave management disabled
1: Software: Software slave management enabled

RO

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: ReceiveOnly: Output disabled (Receive-only mode)

FF16

Bit 11: Data frame format.

Allowed values:
0: EightBit: 8-bit data frame format is selected for transmission/reception
1: SixteenBit: 16-bit data frame format is selected for transmission/reception

CRCNT

Bit 12: CRC Next Transfer.

Allowed values:
0: Data: Next transmit value is data from Tx buffer
1: CRC: Next transmit value is CRC value from TCRC

CRCEN

Bit 13: CRC Calculation Enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BDOEN

Bit 14: Bidirectional Transmit output enable .

Allowed values:
0: ReceiveOnly: Receive-only mode
1: TransmitOnly: Transmit-only mode

BDEN

Bit 15: Bidirectional enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

6/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBEIE
rw 		RBNEIE
rw 		ERRIE
rw 		TMOD
rw 		NSSP
rw 		NSSDRV
rw 		DMATEN
rw 		DMAREN
rw
Toggle Fields.

DMAREN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

DMATEN

Bit 1: Transmit Buffer DMA Enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

NSSDRV

Bit 2: Drive NSS Output.

Allowed values:
0: Disabled: NSS output is disabled in master mode
1: Enabled: NSS output is enabled in master mode

NSSP

Bit 3: SPI NSS pulse mode Enable.

TMOD

Bit 4: SPI TI Mode Enable.

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt disabled
1: Enabled: Error interrupt enabled

RBNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Disabled: RBNE interrupt disabled
1: Enabled: RBNE interrupt enabled

TBEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Disabled: TBE interrupt disabled
1: Enabled: TBE interrupt enabled

STAT

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FERR
rw 		TRANS
r 		RXORERR
r 		CONFERR
r 		CRCERR
rw 		TXURERR
r 		I2SCH
r 		TBE
r 		RBNE
r
Toggle Fields.

RBNE

Bit 0: Receive Buffer Not Empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TBE

Bit 1: Transmit Buffer Empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

I2SCH

Bit 2: I2S channel side.

Allowed values:
0: Left: Channel left has to be transmitted or has been received
1: Right: Channel right has to be transmitted or has been received

TXURERR

Bit 3: Transmission underrun error bit.

Allowed values:
0: NoUnderrun: No underrun occurred
1: Underrun: Underrun occurred

CRCERR

Bit 4: SPI CRC Error Bit.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

CONFERR

Bit 5: SPI Configuration error.

Allowed values:
0: NoFault: No configuration fault occurred
1: Fault: Configuration fault occurred

RXORERR

Bit 6: Reception Overrun Error Bit.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

TRANS

Bit 7: Transmitting On-going Bit.

Allowed values:
0: Idle: SPI or I2S is idle
1: Busy: SPI or I2S is currently transmitting or receiving

FERR

Bit 8: Format Error.

DATA

data register

Offset: 0xC, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-15: Data transfer register.

Allowed values: 0-65535

CRCPOLY

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0-65535

RCRC

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCRC
r
Toggle Fields.

RCRC

Bits 0-15: RX CRC register.

Allowed values: 0-65535

TCRC

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRC
r
Toggle Fields.

TCRC

Bits 0-15: Tx CRC register.

Allowed values: 0-65535

I2SCTL

I2S control register

Offset: 0x1C, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SSEL
rw 		I2SEN
rw 		I2SOPMOD
rw 		PCMSMOD
rw 		I2SSTD
rw 		CKPL
rw 		DTLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

Allowed values:
0: SixteenBit: 16-bit wide
1: ThirtyTwoBit: 32-bit wide

DTLEN

Bits 1-2: Data length.

Allowed values:
0: SixteenBit: 16-bit data length
1: TwentyFourBit: 24-bit data length
2: ThirtyTwoBit: 32-bit data length

CKPL

Bit 3: Idle state clock polarity.

Allowed values:
0: IdleLow: I2S clock inactive state is low level
1: IdleHigh: I2S clock inactive state is high level

I2SSTD

Bits 4-5: I2S standard selection.

Allowed values:
0: Philips: I2S Philips standard
1: MSB: MSB justified standard
2: LSB: LSB justified standard
3: PCM: PCM standard

PCMSMOD

Bit 7: PCM frame synchronization mode.

Allowed values:
0: Short: Short frame synchronisation
1: Long: Long frame synchronisation

I2SOPMOD

Bits 8-9: I2S operation mode.

Allowed values:
0: SlaveTx: Slave - transmit
1: SlaveRx: Slave - receive
2: MasterTx: Master - transmit
3: MasterRx: Master - receive

I2SEN

Bit 10: I2S Enable.

Allowed values:
0: Disabled: I2S peripheral is disabled
1: Enabled: I2S peripheral is enabled

I2SSEL

Bit 11: I2S mode selection.

Allowed values:
0: SPIMode: SPI mode is selected
1: I2SMode: I2S mode is selected

I2SPSC

I2S prescaler register

Offset: 0x20, reset: 0x0002, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOEN
rw 		OF
rw 		DIV
rw
Toggle Fields.

DIV

Bits 0-7: Dividing factor for the prescaler.

Allowed values: 1-255

OF

Bit 8: Odd factor for the prescaler.

Allowed values:
0: Even: Real divider value is DIV * 2
1: Odd: Real divider value is (DIV * 2) + 1

MCKOEN

Bit 9: I2S_MCK output enable.

Allowed values:
0: Disabled: Master clock output is disabled
1: Enabled: Master clock output is enabled

QCTL

Quad-SPI mode control register

Offset: 0x80, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IO23_DRV
rw 		QRD
rw 		QMOD
rw
Toggle Fields.

QMOD

Bit 0: Quad-SPI mode enable.

QRD

Bit 1: Quad-SPI mode read select.

IO23_DRV

Bit 2: Drive IO2 and IO3 enable.

TIMER0

0x40012c00: Advanced-timers

0/129 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

SPM

Bit 3: Single pulse mode.

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISO3
rw 		ISO2N
rw 		ISO2
rw 		ISO1N
rw 		ISO1
rw 		ISO0N
rw 		ISO0
rw 		TI0S
rw 		MMC
rw 		DMAS
rw 		CCUC
rw 		CCSE
rw
Toggle Fields.

CCSE

Bit 0: Commutation control shadow enable.

CCUC

Bit 2: Commutation control shadow register update control.

DMAS

Bit 3: DMA request source selection.

MMC

Bits 4-6: Master mode control.

TI0S

Bit 7: Channel 0 trigger input selection.

ISO0

Bit 8: Idle state of channel 0 output.

ISO0N

Bit 9: Idle state of channel 0 complementary output.

ISO1

Bit 10: Idle state of channel 1 output.

ISO1N

Bit 11: Idle state of channel 1 complementary output.

ISO2

Bit 12: Idle state of channel 2 output.

ISO2N

Bit 13: Idle state of channel 2 complementary output.

ISO3

Bit 14: Idle state of channel 3 output.

SMCFG

slave mode configuration register

Offset: 0x8, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode selection.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETFC

Bits 8-11: External trigger filter control.

ETPSC

Bits 12-13: External trigger prescaler.

SMC1

Bit 14: Part of SMC for enable External clock mode1.

ETP

Bit 15: External trigger polarity.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CMTDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		BRKIE
rw 		TRGIE
rw 		CMTIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

CMTIE

Bit 5: commutation interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

BRKIE

Bit 7: Break interrupt enable.

UPDEN

Bit 8: Update DMA request enable.

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

CMTDEN

Bit 13: Commutation DMA request enable.

TRGDEN

Bit 14: Trigger DMA request enable.

INTF

Interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		BRKIF
rw 		TRGIF
rw 		CMTIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

CH2IF

Bit 3: Channel 2 capture/compare interrupt flag.

CH3IF

Bit 4: Channel 3 capture/compare interrupt flag.

CMTIF

Bit 5: Channel commutation interrupt flag.

TRGIF

Bit 6: Trigger interrupt flag.

BRKIF

Bit 7: Break interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

CH2OF

Bit 11: Channel 2 over capture flag.

CH3OF

Bit 12: Channel 3 over capture flag.

SWEVG

Software event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRKG
w 		TRGG
w 		CMTG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update event generation.

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

CH2G

Bit 3: Channel 2 capture or compare event generation.

CH3G

Bit 4: Channel 3 capture or compare event generation.

CMTG

Bit 5: Channel commutation event generation.

TRGG

Bit 6: Trigger event generation.

BRKG

Bit 7: Break event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

CH3MS

Bits 8-9: Channel 3 mode selection.

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2NEN
rw 		CH2P
rw 		CH2EN
rw 		CH1NP
rw 		CH1NEN
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0NEN
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH0NEN

Bit 2: Channel 0 complementary output enable.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CH1NEN

Bit 6: Channel 1 complementary output enable.

CH1NP

Bit 7: Channel 1 complementary output polarity.

CH2EN

Bit 8: Channel 2 capture/compare function enable.

CH2P

Bit 9: Channel 2 capture/compare function polarity.

CH2NEN

Bit 10: Channel 2 complementary output enable.

CH2NP

Bit 11: Channel 2 complementary output polarity.

CH3EN

Bit 12: Channel 3 capture/compare function enable.

CH3P

Bit 13: Channel 3 capture/compare function polarity.

CNT

counter

Offset: 0x24, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

CREP

Counter repetition register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CREP
rw
Toggle Fields.

CREP

Bits 0-7: Counter repetition value.

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel0.

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: Capture or compare value of channel 2.

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: Capture or compare value of channel 3.

CCHP

channel complementary protection register

Offset: 0x44, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POEN
rw 		OAEN
rw 		BRKP
rw 		BRKEN
rw 		ROS
rw 		IOS
rw 		PROT
rw 		DTCFG
rw
Toggle Fields.

DTCFG

Bits 0-7: Dead time configure.

PROT

Bits 8-9: Complementary register protect control.

IOS

Bit 10: Idle mode off-state configure.

ROS

Bit 11: Run mode off-state configure.

BRKEN

Bit 12: Break enable.

BRKP

Bit 13: Break polarity.

OAEN

Bit 14: Output automatic enable.

POEN

Bit 15: Primary output enable.

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

DMATC

Bits 8-12: DMA transfer count.

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

CFG

Configuration register

Offset: 0xFC, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw 		OUTSEL
rw
Toggle Fields.

OUTSEL

Bit 0: The output value selection.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER1

0x40000000: General-purpose-timers

0/98 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

SPM

Bit 3: Single pulse mode.

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI0S
rw 		MMC
rw 		DMAS
rw
Toggle Fields.

DMAS

Bit 3: DMA request source selection.

MMC

Bits 4-6: Master mode control.

TI0S

Bit 7: Channel 0 trigger input selection.

SMCFG

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master-slave mode.

ETFC

Bits 8-11: External trigger filter control.

ETPSC

Bits 12-13: External trigger prescaler.

SMC1

Bit 14: Part of SMC for enable External clock mode1.

ETP

Bit 15: External trigger polarity.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		TRGIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

UPDEN

Bit 8: Update DMA request enable.

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

TRGDEN

Bit 14: Trigger DMA request enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

CH2IF

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IF

Bit 4: Channel 3 capture/compare interrupt enable.

TRGIF

Bit 6: Trigger interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

CH2OF

Bit 11: Channel 2 over capture flag.

CH3OF

Bit 12: Channel 3 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

CH2G

Bit 3: Channel 2 capture or compare event generation.

CH3G

Bit 4: Channel 3 capture or compare event generation.

TRGG

Bit 6: Trigger event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

CH3MS

Bits 8-9: Channel 3 mode selection.

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2P
rw 		CH2EN
rw 		CH1P
rw 		CH1EN
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CH2EN

Bit 8: Channel 2 capture/compare function enable.

CH2P

Bit 9: Channel 2 capture/compare function polarity.

CH2NP

Bit 11: Channel 2 complementary output polarity.

CH3EN

Bit 12: Channel 3 capture/compare function enable.

CH3P

Bit 13: Channel 3 capture/compare function polarity.

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-31: counter value.

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-31: Counter auto reload value.

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: Capture or compare value of channel 2.

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: Capture or compare value of channel 3.

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

DMATC

Bits 8-12: DMA transfer count.

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

CFG

Configuration

Offset: 0xFC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER2

0x40000400: General-purpose-timers

0/98 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

SPM

Bit 3: Single pulse mode.

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI0S
rw 		MMC
rw 		DMAS
rw
Toggle Fields.

DMAS

Bit 3: DMA request source selection.

MMC

Bits 4-6: Master mode control.

TI0S

Bit 7: Channel 0 trigger input selection.

SMCFG

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master-slave mode.

ETFC

Bits 8-11: External trigger filter control.

ETPSC

Bits 12-13: External trigger prescaler.

SMC1

Bit 14: Part of SMC for enable External clock mode1.

ETP

Bit 15: External trigger polarity.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		TRGIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

UPDEN

Bit 8: Update DMA request enable.

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

TRGDEN

Bit 14: Trigger DMA request enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

CH2IF

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IF

Bit 4: Channel 3 capture/compare interrupt enable.

TRGIF

Bit 6: Trigger interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

CH2OF

Bit 11: Channel 2 over capture flag.

CH3OF

Bit 12: Channel 3 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

CH2G

Bit 3: Channel 2 capture or compare event generation.

CH3G

Bit 4: Channel 3 capture or compare event generation.

TRGG

Bit 6: Trigger event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

CH3MS

Bits 8-9: Channel 3 mode selection.

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2P
rw 		CH2EN
rw 		CH1P
rw 		CH1EN
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CH2EN

Bit 8: Channel 2 capture/compare function enable.

CH2P

Bit 9: Channel 2 capture/compare function polarity.

CH2NP

Bit 11: Channel 2 complementary output polarity.

CH3EN

Bit 12: Channel 3 capture/compare function enable.

CH3P

Bit 13: Channel 3 capture/compare function polarity.

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-31: counter value.

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-31: Counter auto reload value.

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: Capture or compare value of channel 2.

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: Capture or compare value of channel 3.

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

DMATC

Bits 8-12: DMA transfer count.

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

CFG

Configuration

Offset: 0xFC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER3

0x40000800: General-purpose-timers

0/98 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

SPM

Bit 3: Single pulse mode.

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI0S
rw 		MMC
rw 		DMAS
rw
Toggle Fields.

DMAS

Bit 3: DMA request source selection.

MMC

Bits 4-6: Master mode control.

TI0S

Bit 7: Channel 0 trigger input selection.

SMCFG

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master-slave mode.

ETFC

Bits 8-11: External trigger filter control.

ETPSC

Bits 12-13: External trigger prescaler.

SMC1

Bit 14: Part of SMC for enable External clock mode1.

ETP

Bit 15: External trigger polarity.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		TRGIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

UPDEN

Bit 8: Update DMA request enable.

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

TRGDEN

Bit 14: Trigger DMA request enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

CH2IF

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IF

Bit 4: Channel 3 capture/compare interrupt enable.

TRGIF

Bit 6: Trigger interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

CH2OF

Bit 11: Channel 2 over capture flag.

CH3OF

Bit 12: Channel 3 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

CH2G

Bit 3: Channel 2 capture or compare event generation.

CH3G

Bit 4: Channel 3 capture or compare event generation.

TRGG

Bit 6: Trigger event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

CH3MS

Bits 8-9: Channel 3 mode selection.

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2P
rw 		CH2EN
rw 		CH1P
rw 		CH1EN
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CH2EN

Bit 8: Channel 2 capture/compare function enable.

CH2P

Bit 9: Channel 2 capture/compare function polarity.

CH2NP

Bit 11: Channel 2 complementary output polarity.

CH3EN

Bit 12: Channel 3 capture/compare function enable.

CH3P

Bit 13: Channel 3 capture/compare function polarity.

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-31: counter value.

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-31: Counter auto reload value.

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: Capture or compare value of channel 2.

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: Capture or compare value of channel 3.

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

DMATC

Bits 8-12: DMA transfer count.

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

CFG

Configuration

Offset: 0xFC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER4

0x40000C00: General-purpose-timers

0/98 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

SPM

Bit 3: Single pulse mode.

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI0S
rw 		MMC
rw 		DMAS
rw
Toggle Fields.

DMAS

Bit 3: DMA request source selection.

MMC

Bits 4-6: Master mode control.

TI0S

Bit 7: Channel 0 trigger input selection.

SMCFG

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master-slave mode.

ETFC

Bits 8-11: External trigger filter control.

ETPSC

Bits 12-13: External trigger prescaler.

SMC1

Bit 14: Part of SMC for enable External clock mode1.

ETP

Bit 15: External trigger polarity.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		TRGIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

UPDEN

Bit 8: Update DMA request enable.

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

TRGDEN

Bit 14: Trigger DMA request enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

CH2IF

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IF

Bit 4: Channel 3 capture/compare interrupt enable.

TRGIF

Bit 6: Trigger interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

CH2OF

Bit 11: Channel 2 over capture flag.

CH3OF

Bit 12: Channel 3 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

CH2G

Bit 3: Channel 2 capture or compare event generation.

CH3G

Bit 4: Channel 3 capture or compare event generation.

TRGG

Bit 6: Trigger event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

CH3MS

Bits 8-9: Channel 3 mode selection.

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2P
rw 		CH2EN
rw 		CH1P
rw 		CH1EN
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CH2EN

Bit 8: Channel 2 capture/compare function enable.

CH2P

Bit 9: Channel 2 capture/compare function polarity.

CH2NP

Bit 11: Channel 2 complementary output polarity.

CH3EN

Bit 12: Channel 3 capture/compare function enable.

CH3P

Bit 13: Channel 3 capture/compare function polarity.

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-31: counter value.

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-31: Counter auto reload value.

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: Capture or compare value of channel 2.

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: Capture or compare value of channel 3.

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

DMATC

Bits 8-12: DMA transfer count.

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

CFG

Configuration

Offset: 0xFC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER5

0x40001000: Basic-timers

0/13 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARSE
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

SPM

Bit 3: Single pulse mode.

ARSE

Bit 7: Auto-reload shadow enable.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMC
rw
Toggle Fields.

MMC

Bits 4-6: Master mode control.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPDEN
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

UPDEN

Bit 8: Update DMA request enable.

INTF

Interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Low counter value.

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

TIMER6

0x40001400: Basic-timers

0/13 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARSE
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

SPM

Bit 3: Single pulse mode.

ARSE

Bit 7: Auto-reload shadow enable.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMC
rw
Toggle Fields.

MMC

Bits 4-6: Master mode control.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPDEN
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

UPDEN

Bit 8: Update DMA request enable.

INTF

Interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Low counter value.

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

TIMER7

0x40013400: Advanced-timers

0/129 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

SPM

Bit 3: Single pulse mode.

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISO3
rw 		ISO2N
rw 		ISO2
rw 		ISO1N
rw 		ISO1
rw 		ISO0N
rw 		ISO0
rw 		TI0S
rw 		MMC
rw 		DMAS
rw 		CCUC
rw 		CCSE
rw
Toggle Fields.

CCSE

Bit 0: Commutation control shadow enable.

CCUC

Bit 2: Commutation control shadow register update control.

DMAS

Bit 3: DMA request source selection.

MMC

Bits 4-6: Master mode control.

TI0S

Bit 7: Channel 0 trigger input selection.

ISO0

Bit 8: Idle state of channel 0 output.

ISO0N

Bit 9: Idle state of channel 0 complementary output.

ISO1

Bit 10: Idle state of channel 1 output.

ISO1N

Bit 11: Idle state of channel 1 complementary output.

ISO2

Bit 12: Idle state of channel 2 output.

ISO2N

Bit 13: Idle state of channel 2 complementary output.

ISO3

Bit 14: Idle state of channel 3 output.

SMCFG

slave mode configuration register

Offset: 0x8, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode selection.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETFC

Bits 8-11: External trigger filter control.

ETPSC

Bits 12-13: External trigger prescaler.

SMC1

Bit 14: Part of SMC for enable External clock mode1.

ETP

Bit 15: External trigger polarity.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CMTDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		BRKIE
rw 		TRGIE
rw 		CMTIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

CMTIE

Bit 5: commutation interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

BRKIE

Bit 7: Break interrupt enable.

UPDEN

Bit 8: Update DMA request enable.

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

CMTDEN

Bit 13: Commutation DMA request enable.

TRGDEN

Bit 14: Trigger DMA request enable.

INTF

Interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		BRKIF
rw 		TRGIF
rw 		CMTIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

CH2IF

Bit 3: Channel 2 capture/compare interrupt flag.

CH3IF

Bit 4: Channel 3 capture/compare interrupt flag.

CMTIF

Bit 5: Channel commutation interrupt flag.

TRGIF

Bit 6: Trigger interrupt flag.

BRKIF

Bit 7: Break interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

CH2OF

Bit 11: Channel 2 over capture flag.

CH3OF

Bit 12: Channel 3 over capture flag.

SWEVG

Software event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRKG
w 		TRGG
w 		CMTG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update event generation.

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

CH2G

Bit 3: Channel 2 capture or compare event generation.

CH3G

Bit 4: Channel 3 capture or compare event generation.

CMTG

Bit 5: Channel commutation event generation.

TRGG

Bit 6: Trigger event generation.

BRKG

Bit 7: Break event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

CH3MS

Bits 8-9: Channel 3 mode selection.

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2NEN
rw 		CH2P
rw 		CH2EN
rw 		CH1NP
rw 		CH1NEN
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0NEN
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH0NEN

Bit 2: Channel 0 complementary output enable.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CH1NEN

Bit 6: Channel 1 complementary output enable.

CH1NP

Bit 7: Channel 1 complementary output polarity.

CH2EN

Bit 8: Channel 2 capture/compare function enable.

CH2P

Bit 9: Channel 2 capture/compare function polarity.

CH2NEN

Bit 10: Channel 2 complementary output enable.

CH2NP

Bit 11: Channel 2 complementary output polarity.

CH3EN

Bit 12: Channel 3 capture/compare function enable.

CH3P

Bit 13: Channel 3 capture/compare function polarity.

CNT

counter

Offset: 0x24, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

CREP

Counter repetition register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CREP
rw
Toggle Fields.

CREP

Bits 0-7: Counter repetition value.

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel0.

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: Capture or compare value of channel 2.

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: Capture or compare value of channel 3.

CCHP

channel complementary protection register

Offset: 0x44, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POEN
rw 		OAEN
rw 		BRKP
rw 		BRKEN
rw 		ROS
rw 		IOS
rw 		PROT
rw 		DTCFG
rw
Toggle Fields.

DTCFG

Bits 0-7: Dead time configure.

PROT

Bits 8-9: Complementary register protect control.

IOS

Bit 10: Idle mode off-state configure.

ROS

Bit 11: Run mode off-state configure.

BRKEN

Bit 12: Break enable.

BRKP

Bit 13: Break polarity.

OAEN

Bit 14: Output automatic enable.

POEN

Bit 15: Primary output enable.

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

DMATC

Bits 8-12: DMA transfer count.

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

CFG

Configuration register

Offset: 0xFC, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw 		OUTSEL
rw
Toggle Fields.

OUTSEL

Bit 0: The output value selection.

CHVSEL

Bit 1: Write CHxVAL register selection.

UART3

0x40004C00: Universal asynchronous receiver transmitter

10/50 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSF
r 		LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS change flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

INTDIV

Bits 4-15: Integer part of baud-rate divider.

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

RWU

Bit 1: Receiver wakeup from mute mode.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE line detected interrupt enable.

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

PERRIE

Bit 8: Parity error interrupt enable.

PM

Bit 9: Parity mode.

PCEN

Bit 10: Parity check function enable.

WM

Bit 11: Wakeup method in mute mode.

WL

Bit 12: Word length.

UEN

Bit 13: USART enable.

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

LBLEN

Bit 5: LIN break frame length.

LBDIE

Bit 6: LIN break detection interrupt enable.

CLEN

Bit 8: CK Length.

CPH

Bit 9: Clock phase.

CPL

Bit 10: Clock polarity.

CKEN

Bit 11: CK pin enable.

STB

Bits 12-13: STOP bits length.

LMEN

Bit 14: LIN mode enable.

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSB
rw 		CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDEN

Bit 3: Half-duplex selection.

NKEN

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DENR

Bit 6: DMA request enable for reception.

DENT

Bit 7: DMA request enable for transmission.

RTSEN

Bit 8: RTS enable.

CTSEN

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

OSB

Bit 11: One sample bit method enable.

GP

Guard time and prescaler register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GUAT

Bits 8-15: Guard time value in Smartcard mode.

UART4

0x40005000: Universal asynchronous receiver transmitter

10/50 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSF
r 		LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS change flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

INTDIV

Bits 4-15: Integer part of baud-rate divider.

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

RWU

Bit 1: Receiver wakeup from mute mode.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE line detected interrupt enable.

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

PERRIE

Bit 8: Parity error interrupt enable.

PM

Bit 9: Parity mode.

PCEN

Bit 10: Parity check function enable.

WM

Bit 11: Wakeup method in mute mode.

WL

Bit 12: Word length.

UEN

Bit 13: USART enable.

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

LBLEN

Bit 5: LIN break frame length.

LBDIE

Bit 6: LIN break detection interrupt enable.

CLEN

Bit 8: CK Length.

CPH

Bit 9: Clock phase.

CPL

Bit 10: Clock polarity.

CKEN

Bit 11: CK pin enable.

STB

Bits 12-13: STOP bits length.

LMEN

Bit 14: LIN mode enable.

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSB
rw 		CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDEN

Bit 3: Half-duplex selection.

NKEN

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DENR

Bit 6: DMA request enable for reception.

DENT

Bit 7: DMA request enable for transmission.

RTSEN

Bit 8: RTS enable.

CTSEN

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

OSB

Bit 11: One sample bit method enable.

GP

Guard time and prescaler register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GUAT

Bits 8-15: Guard time value in Smartcard mode.

USART0

0x40013800: Universal synchronous asynchronous receiver transmitter

52/62 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSF
r 		LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS change flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

Allowed values: 0-255

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

Allowed values: 0-15

INTDIV

Bits 4-15: Integer part of baud-rate divider.

Allowed values: 0-4095

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

Allowed values:
0: Disabled: Do not transmit a break frame
1: Enabled: Do not transmit a break frame

RWU

Bit 1: Receiver wakeup from mute mode.

Allowed values:
0: Disabled: Receiver wakeup from mute mode
1: Enabled: Receiver in mute mode

REN

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TEN

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE line detected interrupt enable.

Allowed values:
0: Disabled: Idle line detected interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLEF=1 in the STAT register

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

Allowed values:
0: Disabled: Read data buffer not empty and overrrun error interrupts are disabled
1: Enabled: Interrupt is generated whenever ORERR=1 or RBNE=1 in the STAT register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Transmission complete interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the STAT register

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

Allowed values:
0: Disabled: Transmission register empty interrupt is disabled
1: Enabled: Interrupt is generated whenever TBE=1 in the STAT register

PERRIE

Bit 8: Parity error interrupt enable.

Allowed values:
0: Disabled: Parity error interrupt is disabled
1: Enabled: Interrupt is generated whenever PERR=1 in the STAT register

PM

Bit 9: Parity mode.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCEN

Bit 10: Parity check function enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WM

Bit 11: Wakeup method in mute mode.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

WL

Bit 12: Word length.

Allowed values:
0: Bit8: 8 data bits
1: Bit9: 9 data bits

UEN

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART prescaler and outputs enabled

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

Allowed values:
0: Bit4: 4-bit address detection
1: Full: Full-bit address detection

LBLEN

Bit 5: LIN break frame length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: An interrupt is generated whenever LBDF=1 in the STAT register

CLEN

Bit 8: CK Length.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPH

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPL

Bit 10: Clock polarity.

Allowed values:
0: NotInverted: Steady low value on CK pin outside tranmission window
1: Inverted: Steady high value on CK pin outside tranmission window

CKEN

Bit 11: CK pin enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STB

Bits 12-13: STOP bits length.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LMEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt is disabled
1: Enabled: An interrupt is generated when FERR=1 or ORERR=1 or NERR=1 in the STAT register

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDEN

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NKEN

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DENR

Bit 6: DMA request enable for reception.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DENT

Bit 7: DMA request enable for transmission.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSEN

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSEN

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: An interrupt is generated whenever CTS=1 in the STAT register

GP

Guard time and prescaler register

Offset: 0x1C, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

Allowed values: 0-255

GUAT

Bits 8-15: Guard time value in Smartcard mode.

Allowed values: 0-255

CTL3

Control register 3

Offset: 0x80, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSBF
rw 		DINV
rw 		TINV
rw 		RINV
rw 		EBIE
rw 		RTIE
rw 		SCRTNUM
rw 		RTEN
rw
Toggle Fields.

RTEN

Bit 0: Receiver timeout enable.

SCRTNUM

Bits 1-3: Smartcard auto-retry number.

RTIE

Bit 4: Interrupt enable bit of receive timeout event.

EBIE

Bit 5: Interrupt enable bit of end of block event.

RINV

Bit 8: RX pin level inversion.

TINV

Bit 9: TX pin level inversion.

DINV

Bit 10: Data bit level inversion.

MSBF

Bit 11: Most significant bit first.

RT

Receiver timeout register

Offset: 0x84, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BL
rw 		RT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT
rw
Toggle Fields.

RT

Bits 0-23: Receiver timeout threshold.

Allowed values: 0-16777215

BL

Bits 24-31: Block Length.

Allowed values: 0-255

STAT1

Status register 1

Offset: 0x88, reset: 0x000000C0, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBF
w 		RTF
w
Toggle Fields.

RTF

Bit 11: Receiver timeout flag.

EBF

Bit 12: End of block flag.

BSY

Bit 16: Busy flag.

USART1

0x40004400: Universal synchronous asynchronous receiver transmitter

52/62 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSF
r 		LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS change flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

Allowed values: 0-255

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

Allowed values: 0-15

INTDIV

Bits 4-15: Integer part of baud-rate divider.

Allowed values: 0-4095

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

Allowed values:
0: Disabled: Do not transmit a break frame
1: Enabled: Do not transmit a break frame

RWU

Bit 1: Receiver wakeup from mute mode.

Allowed values:
0: Disabled: Receiver wakeup from mute mode
1: Enabled: Receiver in mute mode

REN

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TEN

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE line detected interrupt enable.

Allowed values:
0: Disabled: Idle line detected interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLEF=1 in the STAT register

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

Allowed values:
0: Disabled: Read data buffer not empty and overrrun error interrupts are disabled
1: Enabled: Interrupt is generated whenever ORERR=1 or RBNE=1 in the STAT register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Transmission complete interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the STAT register

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

Allowed values:
0: Disabled: Transmission register empty interrupt is disabled
1: Enabled: Interrupt is generated whenever TBE=1 in the STAT register

PERRIE

Bit 8: Parity error interrupt enable.

Allowed values:
0: Disabled: Parity error interrupt is disabled
1: Enabled: Interrupt is generated whenever PERR=1 in the STAT register

PM

Bit 9: Parity mode.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCEN

Bit 10: Parity check function enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WM

Bit 11: Wakeup method in mute mode.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

WL

Bit 12: Word length.

Allowed values:
0: Bit8: 8 data bits
1: Bit9: 9 data bits

UEN

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART prescaler and outputs enabled

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

Allowed values:
0: Bit4: 4-bit address detection
1: Full: Full-bit address detection

LBLEN

Bit 5: LIN break frame length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: An interrupt is generated whenever LBDF=1 in the STAT register

CLEN

Bit 8: CK Length.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPH

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPL

Bit 10: Clock polarity.

Allowed values:
0: NotInverted: Steady low value on CK pin outside tranmission window
1: Inverted: Steady high value on CK pin outside tranmission window

CKEN

Bit 11: CK pin enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STB

Bits 12-13: STOP bits length.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LMEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt is disabled
1: Enabled: An interrupt is generated when FERR=1 or ORERR=1 or NERR=1 in the STAT register

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDEN

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NKEN

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DENR

Bit 6: DMA request enable for reception.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DENT

Bit 7: DMA request enable for transmission.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSEN

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSEN

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: An interrupt is generated whenever CTS=1 in the STAT register

GP

Guard time and prescaler register

Offset: 0x1C, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

Allowed values: 0-255

GUAT

Bits 8-15: Guard time value in Smartcard mode.

Allowed values: 0-255

CTL3

Control register 3

Offset: 0x80, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSBF
rw 		DINV
rw 		TINV
rw 		RINV
rw 		EBIE
rw 		RTIE
rw 		SCRTNUM
rw 		RTEN
rw
Toggle Fields.

RTEN

Bit 0: Receiver timeout enable.

SCRTNUM

Bits 1-3: Smartcard auto-retry number.

RTIE

Bit 4: Interrupt enable bit of receive timeout event.

EBIE

Bit 5: Interrupt enable bit of end of block event.

RINV

Bit 8: RX pin level inversion.

TINV

Bit 9: TX pin level inversion.

DINV

Bit 10: Data bit level inversion.

MSBF

Bit 11: Most significant bit first.

RT

Receiver timeout register

Offset: 0x84, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BL
rw 		RT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT
rw
Toggle Fields.

RT

Bits 0-23: Receiver timeout threshold.

Allowed values: 0-16777215

BL

Bits 24-31: Block Length.

Allowed values: 0-255

STAT1

Status register 1

Offset: 0x88, reset: 0x000000C0, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBF
w 		RTF
w
Toggle Fields.

RTF

Bit 11: Receiver timeout flag.

EBF

Bit 12: End of block flag.

BSY

Bit 16: Busy flag.

USART2

0x40004800: Universal synchronous asynchronous receiver transmitter

52/62 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSF
r 		LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS change flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

Allowed values: 0-255

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

Allowed values: 0-15

INTDIV

Bits 4-15: Integer part of baud-rate divider.

Allowed values: 0-4095

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

Allowed values:
0: Disabled: Do not transmit a break frame
1: Enabled: Do not transmit a break frame

RWU

Bit 1: Receiver wakeup from mute mode.

Allowed values:
0: Disabled: Receiver wakeup from mute mode
1: Enabled: Receiver in mute mode

REN

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TEN

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE line detected interrupt enable.

Allowed values:
0: Disabled: Idle line detected interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLEF=1 in the STAT register

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

Allowed values:
0: Disabled: Read data buffer not empty and overrrun error interrupts are disabled
1: Enabled: Interrupt is generated whenever ORERR=1 or RBNE=1 in the STAT register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Transmission complete interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the STAT register

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

Allowed values:
0: Disabled: Transmission register empty interrupt is disabled
1: Enabled: Interrupt is generated whenever TBE=1 in the STAT register

PERRIE

Bit 8: Parity error interrupt enable.

Allowed values:
0: Disabled: Parity error interrupt is disabled
1: Enabled: Interrupt is generated whenever PERR=1 in the STAT register

PM

Bit 9: Parity mode.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCEN

Bit 10: Parity check function enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WM

Bit 11: Wakeup method in mute mode.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

WL

Bit 12: Word length.

Allowed values:
0: Bit8: 8 data bits
1: Bit9: 9 data bits

UEN

Bit 13: USART enable.

Allowed values:
0: Disabled: USART prescaler and outputs disabled
1: Enabled: USART prescaler and outputs enabled

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

Allowed values:
0: Bit4: 4-bit address detection
1: Full: Full-bit address detection

LBLEN

Bit 5: LIN break frame length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: An interrupt is generated whenever LBDF=1 in the STAT register

CLEN

Bit 8: CK Length.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPH

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPL

Bit 10: Clock polarity.

Allowed values:
0: NotInverted: Steady low value on CK pin outside tranmission window
1: Inverted: Steady high value on CK pin outside tranmission window

CKEN

Bit 11: CK pin enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STB

Bits 12-13: STOP bits length.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LMEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Error interrupt is disabled
1: Enabled: An interrupt is generated when FERR=1 or ORERR=1 or NERR=1 in the STAT register

IREN

Bit 1: IrDA mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: IrDA low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDEN

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NKEN

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DENR

Bit 6: DMA request enable for reception.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DENT

Bit 7: DMA request enable for transmission.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSEN

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSEN

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: An interrupt is generated whenever CTS=1 in the STAT register

GP

Guard time and prescaler register

Offset: 0x1C, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

Allowed values: 0-255

GUAT

Bits 8-15: Guard time value in Smartcard mode.

Allowed values: 0-255

CTL3

Control register 3

Offset: 0x80, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSBF
rw 		DINV
rw 		TINV
rw 		RINV
rw 		EBIE
rw 		RTIE
rw 		SCRTNUM
rw 		RTEN
rw
Toggle Fields.

RTEN

Bit 0: Receiver timeout enable.

SCRTNUM

Bits 1-3: Smartcard auto-retry number.

RTIE

Bit 4: Interrupt enable bit of receive timeout event.

EBIE

Bit 5: Interrupt enable bit of end of block event.

RINV

Bit 8: RX pin level inversion.

TINV

Bit 9: TX pin level inversion.

DINV

Bit 10: Data bit level inversion.

MSBF

Bit 11: Most significant bit first.

RT

Receiver timeout register

Offset: 0x84, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BL
rw 		RT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT
rw
Toggle Fields.

RT

Bits 0-23: Receiver timeout threshold.

Allowed values: 0-16777215

BL

Bits 24-31: Block Length.

Allowed values: 0-255

STAT1

Status register 1

Offset: 0x88, reset: 0x000000C0, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBF
w 		RTF
w
Toggle Fields.

RTF

Bit 11: Receiver timeout flag.

EBF

Bit 12: End of block flag.

BSY

Bit 16: Busy flag.

USBD

0x40005C00: Universal serial bus full-speed device interface

5/118 fields covered. Toggle Registers.

EP0CS

endpoint 0 register

Offset: 0x0, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_ST
rw 		RX_DTG
rw 		RX_STA
rw 		SETUP
rw 		EP_CTL
rw 		EP_KCTL
rw 		TX_ST
rw 		TX_DTG
rw 		TX_STA
rw 		EP_AR
rw
Toggle Fields.

EP_AR

Bits 0-3: Endpoint address.

TX_STA

Bits 4-5: Status bits, for transmission transfers.

TX_DTG

Bit 6: Data PID Toggle, for transmission transfers.

TX_ST

Bit 7: Correct Transfer for transmission.

EP_KCTL

Bit 8: Endpoint kind.

EP_CTL

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

RX_STA

Bits 12-13: Status bits, for reception transfers.

RX_DTG

Bit 14: Data Toggle, for reception transfers.

RX_ST

Bit 15: Correct transfer for reception.

EP1CS

endpoint 1 register

Offset: 0x4, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_ST
rw 		RX_DTG
rw 		RX_STA
rw 		SETUP
rw 		EP_CTL
rw 		EP_KCTL
rw 		TX_ST
rw 		TX_DTG
rw 		TX_STA
rw 		EP_AR
rw
Toggle Fields.

EP_AR

Bits 0-3: Endpoint address.

TX_STA

Bits 4-5: Status bits, for transmission transfers.

TX_DTG

Bit 6: Data Toggle, for transmission transfers.

TX_ST

Bit 7: Correct Transfer for transmission.

EP_KCTL

Bit 8: Endpoint kind.

EP_CTL

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

RX_STA

Bits 12-13: Status bits, for reception transfers.

RX_DTG

Bit 14: Data Toggle, for reception transfers.

RX_ST

Bit 15: Correct transfer for reception.

EP2CS

endpoint 2 register

Offset: 0x8, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_ST
rw 		RX_DTG
rw 		RX_STA
rw 		SETUP
rw 		EP_CTL
rw 		EP_KCTL
rw 		TX_ST
rw 		TX_DTG
rw 		TX_STA
rw 		EP_AR
rw
Toggle Fields.

EP_AR

Bits 0-3: Endpoint address.

TX_STA

Bits 4-5: Status bits, for transmission transfers.

TX_DTG

Bit 6: Data Toggle, for transmission transfers.

TX_ST

Bit 7: Correct Transfer for transmission.

EP_KCTL

Bit 8: Endpoint kind.

EP_CTL

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

RX_STA

Bits 12-13: Status bits, for reception transfers.

RX_DTG

Bit 14: Data Toggle, for reception transfers.

RX_ST

Bit 15: Correct transfer for reception.

EP3CS

endpoint 3 register

Offset: 0xC, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_ST
rw 		RX_DTG
rw 		RX_STA
rw 		SETUP
rw 		EP_CTL
rw 		EP_KCTL
rw 		TX_ST
rw 		TX_DTG
rw 		TX_STA
rw 		EP_AR
rw
Toggle Fields.

EP_AR

Bits 0-3: Endpoint address.

TX_STA

Bits 4-5: Status bits, for transmission transfers.

TX_DTG

Bit 6: Data Toggle, for transmission transfers.

TX_ST

Bit 7: Correct Transfer for transmission.

EP_KCTL

Bit 8: Endpoint kind.

EP_CTL

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

RX_STA

Bits 12-13: Status bits, for reception transfers.

RX_DTG

Bit 14: Data Toggle, for reception transfers.

RX_ST

Bit 15: Correct transfer for reception.

EP4CS

endpoint 4 register

Offset: 0x10, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_ST
rw 		RX_DTG
rw 		RX_STA
rw 		SETUP
rw 		EP_CTL
rw 		EP_KCTL
rw 		TX_ST
rw 		TX_DTG
rw 		TX_STA
rw 		EP_AR
rw
Toggle Fields.

EP_AR

Bits 0-3: Endpoint address.

TX_STA

Bits 4-5: Status bits, for transmission transfers.

TX_DTG

Bit 6: Data Toggle, for transmission transfers.

TX_ST

Bit 7: Correct Transfer for transmission.

EP_KCTL

Bit 8: Endpoint kind.

EP_CTL

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

RX_STA

Bits 12-13: Status bits, for reception transfers.

RX_DTG

Bit 14: Data Toggle, for reception transfers.

RX_ST

Bit 15: Correct transfer for reception.

EP5CS

endpoint 5 register

Offset: 0x14, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_ST
rw 		RX_DTG
rw 		RX_STA
rw 		SETUP
rw 		EP_CTL
rw 		EP_KCTL
rw 		TX_ST
rw 		TX_DTG
rw 		TX_STA
rw 		EP_AR
rw
Toggle Fields.

EP_AR

Bits 0-3: Endpoint address.

TX_STA

Bits 4-5: Status bits, for transmission transfers.

TX_DTG

Bit 6: Data Toggle, for transmission transfers.

TX_ST

Bit 7: Correct Transfer for transmission.

EP_KCTL

Bit 8: Endpoint kind.

EP_CTL

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

RX_STA

Bits 12-13: Status bits, for reception transfers.

RX_DTG

Bit 14: Data Toggle, for reception transfers.

RX_ST

Bit 15: Correct transfer for reception.

EP6CS

endpoint 6 register

Offset: 0x18, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_ST
rw 		RX_DTG
rw 		RX_STA
rw 		SETUP
rw 		EP_CTL
rw 		EP_KCTL
rw 		TX_ST
rw 		TX_DTG
rw 		TX_STA
rw 		EP_AR
rw
Toggle Fields.

EP_AR

Bits 0-3: Endpoint address.

TX_STA

Bits 4-5: Status bits, for transmission transfers.

TX_DTG

Bit 6: Data Toggle, for transmission transfers.

TX_ST

Bit 7: Correct Transfer for transmission.

EP_KCTL

Bit 8: Endpoint kind.

EP_CTL

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

RX_STA

Bits 12-13: Status bits, for reception transfers.

RX_DTG

Bit 14: Data Toggle, for reception transfers.

RX_ST

Bit 15: Correct transfer for reception.

EP7CS

endpoint 7 register

Offset: 0x1C, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_ST
rw 		RX_DTG
rw 		RX_STA
rw 		SETUP
rw 		EP_CTL
rw 		EP_KCTL
rw 		TX_ST
rw 		TX_DTG
rw 		TX_STA
rw 		EP_AR
rw
Toggle Fields.

EP_AR

Bits 0-3: Endpoint address.

TX_STA

Bits 4-5: Status bits, for transmission transfers.

TX_DTG

Bit 6: Data Toggle, for transmission transfers.

TX_ST

Bit 7: Correct Transfer for transmission.

EP_KCTL

Bit 8: Endpoint kind.

EP_CTL

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

RX_STA

Bits 12-13: Status bits, for reception transfers.

RX_DTG

Bit 14: Data Toggle, for reception transfers.

RX_ST

Bit 15: Correct transfer for reception.

CTL

control register

Offset: 0x40, reset: 0x0003, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STIE
rw 		PMOUIE
rw 		ERRIE
rw 		WKUPIE
rw 		SPSIE
rw 		RSTIE
rw 		SOFIE
rw 		ESOFIE
rw 		L1REQIE
rw 		L1RSREQ
rw 		RSREQ
rw 		SETSPS
rw 		LOWM
rw 		CLOSE
rw 		SETRST
rw
Toggle Fields.

SETRST

Bit 0: Set reset.

CLOSE

Bit 1: Close state.

LOWM

Bit 2: Low-power mode.

SETSPS

Bit 3: Set suspend.

RSREQ

Bit 4: Resume request.

L1RSREQ

Bit 5: LPM L1 resume request.

L1REQIE

Bit 7: LPM L1 state request interrupt enable.

ESOFIE

Bit 8: Expected start of frame interrupt enable.

SOFIE

Bit 9: Start of frame interrupt mask.

RSTIE

Bit 10: USB reset interrupt mask.

SPSIE

Bit 11: Suspend mode interrupt mask.

WKUPIE

Bit 12: Wakeup interrupt enable.

ERRIE

Bit 13: Error interrupt mask.

PMOUIE

Bit 14: Packet memory area over / underrun interrupt enable.

STIE

Bit 15: Successful transfer interrupt enable.

INTF

interrupt flag register

Offset: 0x44, reset: 0x0000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STIF
rw 		PMOUIF
rw 		ERRIF
rw 		WKUPIF
rw 		SPSIF
rw 		RSTIF
rw 		SOFIF
rw 		ESOFIF
rw 		L1REQ
rw 		DIR
rw 		EPNUM
rw
Toggle Fields.

EPNUM

Bits 0-3: Endpoint Identifier.

DIR

Bit 4: Direction of transaction.

L1REQ

Bit 7: LPM L1 transaction is successful .

ESOFIF

Bit 8: Expected start of frame interrupt flag.

SOFIF

Bit 9: start of frame interrupt flag.

RSTIF

Bit 10: reset interrupt flag.

SPSIF

Bit 11: Suspend mode interrupt flag.

WKUPIF

Bit 12: Wakeup interrupt flag.

ERRIF

Bit 13: Error interrupt flag.

PMOUIF

Bit 14: Packet memory area over / underrun interrupt flag.

STIF

Bit 15: Successful transfer interrupt flag.

STAT

Status register

Offset: 0x48, reset: 0x0000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX_DP
r 		RX_DM
r 		LOCK
r 		SOFLN
r 		FCNT
r
Toggle Fields.

FCNT

Bits 0-10: Frame number counter.

SOFLN

Bits 11-12: Lost SOF number.

LOCK

Bit 13: Locked the USB.

RX_DM

Bit 14: Receive data - line status.

RX_DP

Bit 15: Receive data + line status.

ADDR

device address register

Offset: 0x4C, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBEN
rw 		USBDAR
rw
Toggle Fields.

USBDAR

Bits 0-6: Device address.

USBEN

Bit 7: USB device enable.

BADDR

Buffer address register

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BAR
rw
Toggle Fields.

BAR

Bits 3-15: Buffer address.

LPMCS

USB LPM control and status register

Offset: 0x54, reset: 0x0000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BLSTAT
rw 		REMWK
rw 		LPMACK
rw 		LPMEN
rw
Toggle Fields.

LPMEN

Bit 0: LPM support enable.

LPMACK

Bit 1: LPM token acknowledge enable.

REMWK

Bit 3: bRemoteWake value.

BLSTAT

Bits 4-7: bLinkState value.

WWDGT

0x40002C00: Window watchdog timer

6/6 fields covered. Toggle Registers.

CTL

Control register

Offset: 0x0, reset: 0x0000007F, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGTEN
rw 		CNT
rw
Toggle Fields.

CNT

Bits 0-6: 7-bit counter.

Allowed values: 0-127

WDGTEN

Bit 7: Activation bit.

Allowed values:
0: Disabled: Watchdog disabled
1: Enabled: Watchdog enabled

CFG

Configuration register

Offset: 0x4, reset: 0x0000007F, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIE
rw 		PSC
rw 		WIN
rw
Toggle Fields.

WIN

Bits 0-6: 7-bit window value.

Allowed values: 0-127

PSC

Bits 7-8: Prescaler.

Allowed values:
0: Div1: Counter clock (PCLK1 div 4096) div 1
1: Div2: Counter clock (PCLK1 div 4096) div 2
2: Div4: Counter clock (PCLK1 div 4096) div 4
3: Div8: Counter clock (PCLK1 div 4096) div 8

EWIE

Bit 9: Early wakeup interrupt.

Allowed values:
1: Enable: interrupt occurs whenever the counter reaches the value 0x40

STAT

Status register

Offset: 0x8, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
rw
Toggle Fields.

EWIF

Bit 0: Early wakeup interrupt flag.

Allowed values:
1: Pending: The EWI Interrupt Service Routine has been triggered
0: Finished: The EWI Interrupt Service Routine has been serviced