Overall: 943/11896 fields covered

ADC0

0x40012000: Analog to digital converter

9/90 fields covered. Toggle Registers.

STAT

status register

Offset: 0x0, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROVF
rw 		STRC
rw 		STIC
rw 		EOIC
rw 		EOC
rw 		WDE
rw
Toggle Fields.

WDE

Bit 0: Analog watchdog event flag.

EOC

Bit 1: End of group conversion flag.

EOIC

Bit 2: End of inserted group conversion flag.

STIC

Bit 3: Start flag of inserted channel group.

STRC

Bit 4: Start flag of regular channel group.

ROVF

Bit 5: Regular data register overflow.

CTL0

control register 0

Offset: 0x4, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ROVFIE
rw 		DRES
rw 		RWDEN
rw 		IWDEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISNUM
rw 		DISIC
rw 		DISRC
rw 		ICA
rw 		WDSC
rw 		SM
rw 		EOICIE
rw 		WDEIE
rw 		EOCIE
rw 		WDCHSEL
rw
Toggle Fields.

WDCHSEL

Bits 0-4: Analog watchdog channel select.

EOCIE

Bit 5: Interrupt enable for EOC.

WDEIE

Bit 6: Analog watchdog WDE.

EOICIE

Bit 7: Interrupt enable for EOIC.

SM

Bit 8: Scan mode.

WDSC

Bit 9: When in scan mode, analog watchdog is effective on a single channel.

ICA

Bit 10: Inserted channel group convert automatically.

DISRC

Bit 11: Discontinuous mode on regular channels.

DISIC

Bit 12: Discontinuous mode on inserted channels.

DISNUM

Bits 13-15: Number of conversions in discontinuous mode.

IWDEN

Bit 22: Inserted channel analog watchdog enable.

RWDEN

Bit 23: Regular channel analog watchdog enable.

DRES

Bits 24-25: ADC data resolution.

ROVFIE

Bit 26: Interrupt enable for ROVF.

CTL1

control register 1

Offset: 0x8, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRCST
rw 		ETMRC
rw 		ETSRC
rw 		SWICST
rw 		ETMIC
rw 		ETSIC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAL
rw 		EOCM
rw 		DDM
rw 		DMA
rw 		RSTCLB
rw 		CLB
rw 		CTN
rw 		ADCON
rw
Toggle Fields.

ADCON

Bit 0: ADC on.

CTN

Bit 1: Continuous mode.

CLB

Bit 2: ADC calibration.

RSTCLB

Bit 3: Reset calibration.

DMA

Bit 8: DMA request enable.

DDM

Bit 9: DMA disable mode.

EOCM

Bit 10: End of conversion mode.

DAL

Bit 11: Data alignment.

ETSIC

Bits 16-19: External trigger select for inserted channel.

ETMIC

Bits 20-21: External trigger mode for inserted channel.

SWICST

Bit 22: Software start on inserted channel.

ETSRC

Bits 24-27: External trigger select for regular channel.

ETMRC

Bits 28-29: External trigger mode for regular channel.

SWRCST

Bit 30: Software start on regular channel.

SAMPT0

Sample time register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT18
rw 		SPT17
rw 		SPT16
rw 		SPT15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT15
rw 		SPT14
rw 		SPT13
rw 		SPT12
rw 		SPT11
rw 		SPT10
rw
Toggle Fields.

SPT10

Bits 0-2: Channel 10 sample time selection.

SPT11

Bits 3-5: Channel 11 sample time selection.

SPT12

Bits 6-8: Channel 12 sample time selection.

SPT13

Bits 9-11: Channel 13 sample time selection.

SPT14

Bits 12-14: Channel 14 sample time selection.

SPT15

Bits 15-17: Channel 15 sample time selection.

SPT16

Bits 18-20: Channel 16 sample time selection.

SPT17

Bits 21-23: Channel 17 sample time selection.

SPT18

Bits 24-26: Channel 18 sample time selection.

SAMPT1

Sample time register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT9
rw 		SPT8
rw 		SPT7
rw 		SPT6
rw 		SPT5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT5
rw 		SPT4
rw 		SPT3
rw 		SPT2
rw 		SPT1
rw 		SPT0
rw
Toggle Fields.

SPT0

Bits 0-2: Channel 0 sample time selection.

SPT1

Bits 3-5: Channel 1 sample time selection.

SPT2

Bits 6-8: Channel 2 sample time selection.

SPT3

Bits 9-11: Channel 3 sample time selection.

SPT4

Bits 12-14: Channel 4 sample time selection.

SPT5

Bits 15-17: Channel 5 sample time selection.

SPT6

Bits 18-20: Channel 6 sample time selection.

SPT7

Bits 21-23: Channel 7 sample time selection.

SPT8

Bits 24-26: Channel 8 sample time selection.

SPT9

Bits 27-29: Channel 9 sample time selection.

IOFF0

Inserted channel data offset register 0

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 0.

IOFF1

Inserted channel data offset register 1

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 1.

IOFF2

Inserted channel data offset register 2

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 2.

IOFF3

Inserted channel data offset register 3

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 3.

WDHT

watchdog higher threshold register

Offset: 0x24, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDHT
rw
Toggle Fields.

WDHT

Bits 0-11: Analog watchdog higher threshold.

WDLT

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDLT
rw
Toggle Fields.

WDLT

Bits 0-11: Analog watchdog lower threshold.

RSQ0

regular sequence register 0

Offset: 0x2C, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RL
rw 		RSQ15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ15
rw 		RSQ14
rw 		RSQ13
rw 		RSQ12
rw
Toggle Fields.

RSQ12

Bits 0-4: 13th conversion in regular sequence.

RSQ13

Bits 5-9: 14th conversion in regular sequence.

RSQ14

Bits 10-14: 15th conversion in regular sequence.

RSQ15

Bits 15-19: 16th conversion in regular sequence.

RL

Bits 20-23: Regular channel group length.

RSQ1

regular sequence register 1

Offset: 0x30, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ11
rw 		RSQ10
rw 		RSQ9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ9
rw 		RSQ8
rw 		RSQ7
rw 		RSQ6
rw
Toggle Fields.

RSQ6

Bits 0-4: 7th conversion in regular sequence.

RSQ7

Bits 5-9: 8th conversion in regular sequence.

RSQ8

Bits 10-14: 9th conversion in regular sequence.

RSQ9

Bits 15-19: 10th conversion in regular sequence.

RSQ10

Bits 20-24: 11th conversion in regular sequence.

RSQ11

Bits 25-29: 12th conversion in regular sequence.

RSQ2

regular sequence register 2

Offset: 0x34, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ5
rw 		RSQ4
rw 		RSQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ3
rw 		RSQ2
rw 		RSQ1
rw 		RSQ0
rw
Toggle Fields.

RSQ0

Bits 0-4: 1st conversion in regular sequence.

RSQ1

Bits 5-9: 2nd conversion in regular sequence.

RSQ2

Bits 10-14: 3rd conversion in regular sequence.

RSQ3

Bits 15-19: 4th conversion in regular sequence.

RSQ4

Bits 20-24: 5th conversion in regular sequence.

RSQ5

Bits 25-29: 6th conversion in regular sequence.

ISQ

Inserted sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IL
rw 		ISQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISQ3
rw 		ISQ2
rw 		ISQ1
rw 		ISQ0
rw
Toggle Fields.

ISQ0

Bits 0-4: 1st conversion in inserted sequence.

ISQ1

Bits 5-9: 2nd conversion in inserted sequence.

ISQ2

Bits 10-14: 3rd conversion in inserted sequence.

ISQ3

Bits 15-19: 4th conversion in inserted sequence.

IL

Bits 20-21: Inserted channel group length.

IDATA0

Inserted data register 0

Offset: 0x3C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

IDATA1

Inserted data register 1

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

IDATA2

Inserted data register 2

Offset: 0x44, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

IDATA3

Inserted data register 3

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

RDATA

regular data register

Offset: 0x4C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle Fields.

RDATA

Bits 0-15: Regular channel data.

OVSAMPCTL

Oversample control register

Offset: 0x80, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOVS
r 		OVSS
r 		OVSR
r 		OVSEN
r
Toggle Fields.

OVSEN

Bit 0: Oversampling Enable.

OVSR

Bits 2-4: Oversampling ratio.

OVSS

Bits 5-8: Oversampling shift.

TOVS

Bit 9: Triggered Oversampling.

ADC1

0x40012100: Analog to digital converter

9/90 fields covered. Toggle Registers.

STAT

status register

Offset: 0x0, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROVF
rw 		STRC
rw 		STIC
rw 		EOIC
rw 		EOC
rw 		WDE
rw
Toggle Fields.

WDE

Bit 0: Analog watchdog event flag.

EOC

Bit 1: End of group conversion flag.

EOIC

Bit 2: End of inserted group conversion flag.

STIC

Bit 3: Start flag of inserted channel group.

STRC

Bit 4: Start flag of regular channel group.

ROVF

Bit 5: Regular data register overflow.

CTL0

control register 0

Offset: 0x4, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ROVFIE
rw 		DRES
rw 		RWDEN
rw 		IWDEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISNUM
rw 		DISIC
rw 		DISRC
rw 		ICA
rw 		WDSC
rw 		SM
rw 		EOICIE
rw 		WDEIE
rw 		EOCIE
rw 		WDCHSEL
rw
Toggle Fields.

WDCHSEL

Bits 0-4: Analog watchdog channel select.

EOCIE

Bit 5: Interrupt enable for EOC.

WDEIE

Bit 6: Analog watchdog WDE.

EOICIE

Bit 7: Interrupt enable for EOIC.

SM

Bit 8: Scan mode.

WDSC

Bit 9: When in scan mode, analog watchdog is effective on a single channel.

ICA

Bit 10: Inserted channel group convert automatically.

DISRC

Bit 11: Discontinuous mode on regular channels.

DISIC

Bit 12: Discontinuous mode on inserted channels.

DISNUM

Bits 13-15: Number of conversions in discontinuous mode.

IWDEN

Bit 22: Inserted channel analog watchdog enable.

RWDEN

Bit 23: Regular channel analog watchdog enable.

DRES

Bits 24-25: ADC data resolution.

ROVFIE

Bit 26: Interrupt enable for ROVF.

CTL1

control register 1

Offset: 0x8, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRCST
rw 		ETMRC
rw 		ETSRC
rw 		SWICST
rw 		ETMIC
rw 		ETSIC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAL
rw 		EOCM
rw 		DDM
rw 		DMA
rw 		RSTCLB
rw 		CLB
rw 		CTN
rw 		ADCON
rw
Toggle Fields.

ADCON

Bit 0: ADC on.

CTN

Bit 1: Continuous mode.

CLB

Bit 2: ADC calibration.

RSTCLB

Bit 3: Reset calibration.

DMA

Bit 8: DMA request enable.

DDM

Bit 9: DMA disable mode.

EOCM

Bit 10: End of conversion mode.

DAL

Bit 11: Data alignment.

ETSIC

Bits 16-19: External trigger select for inserted channel.

ETMIC

Bits 20-21: External trigger mode for inserted channel.

SWICST

Bit 22: Software start on inserted channel.

ETSRC

Bits 24-27: External trigger select for regular channel.

ETMRC

Bits 28-29: External trigger mode for regular channel.

SWRCST

Bit 30: Software start on regular channel.

SAMPT0

Sample time register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT18
rw 		SPT17
rw 		SPT16
rw 		SPT15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT15
rw 		SPT14
rw 		SPT13
rw 		SPT12
rw 		SPT11
rw 		SPT10
rw
Toggle Fields.

SPT10

Bits 0-2: Channel 10 sample time selection.

SPT11

Bits 3-5: Channel 11 sample time selection.

SPT12

Bits 6-8: Channel 12 sample time selection.

SPT13

Bits 9-11: Channel 13 sample time selection.

SPT14

Bits 12-14: Channel 14 sample time selection.

SPT15

Bits 15-17: Channel 15 sample time selection.

SPT16

Bits 18-20: Channel 16 sample time selection.

SPT17

Bits 21-23: Channel 17 sample time selection.

SPT18

Bits 24-26: Channel 18 sample time selection.

SAMPT1

Sample time register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT9
rw 		SPT8
rw 		SPT7
rw 		SPT6
rw 		SPT5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT5
rw 		SPT4
rw 		SPT3
rw 		SPT2
rw 		SPT1
rw 		SPT0
rw
Toggle Fields.

SPT0

Bits 0-2: Channel 0 sample time selection.

SPT1

Bits 3-5: Channel 1 sample time selection.

SPT2

Bits 6-8: Channel 2 sample time selection.

SPT3

Bits 9-11: Channel 3 sample time selection.

SPT4

Bits 12-14: Channel 4 sample time selection.

SPT5

Bits 15-17: Channel 5 sample time selection.

SPT6

Bits 18-20: Channel 6 sample time selection.

SPT7

Bits 21-23: Channel 7 sample time selection.

SPT8

Bits 24-26: Channel 8 sample time selection.

SPT9

Bits 27-29: Channel 9 sample time selection.

IOFF0

Inserted channel data offset register 0

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 0.

IOFF1

Inserted channel data offset register 1

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 1.

IOFF2

Inserted channel data offset register 2

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 2.

IOFF3

Inserted channel data offset register 3

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 3.

WDHT

watchdog higher threshold register

Offset: 0x24, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDHT
rw
Toggle Fields.

WDHT

Bits 0-11: Analog watchdog higher threshold.

WDLT

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDLT
rw
Toggle Fields.

WDLT

Bits 0-11: Analog watchdog lower threshold.

RSQ0

regular sequence register 0

Offset: 0x2C, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RL
rw 		RSQ15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ15
rw 		RSQ14
rw 		RSQ13
rw 		RSQ12
rw
Toggle Fields.

RSQ12

Bits 0-4: 13th conversion in regular sequence.

RSQ13

Bits 5-9: 14th conversion in regular sequence.

RSQ14

Bits 10-14: 15th conversion in regular sequence.

RSQ15

Bits 15-19: 16th conversion in regular sequence.

RL

Bits 20-23: Regular channel group length.

RSQ1

regular sequence register 1

Offset: 0x30, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ11
rw 		RSQ10
rw 		RSQ9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ9
rw 		RSQ8
rw 		RSQ7
rw 		RSQ6
rw
Toggle Fields.

RSQ6

Bits 0-4: 7th conversion in regular sequence.

RSQ7

Bits 5-9: 8th conversion in regular sequence.

RSQ8

Bits 10-14: 9th conversion in regular sequence.

RSQ9

Bits 15-19: 10th conversion in regular sequence.

RSQ10

Bits 20-24: 11th conversion in regular sequence.

RSQ11

Bits 25-29: 12th conversion in regular sequence.

RSQ2

regular sequence register 2

Offset: 0x34, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ5
rw 		RSQ4
rw 		RSQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ3
rw 		RSQ2
rw 		RSQ1
rw 		RSQ0
rw
Toggle Fields.

RSQ0

Bits 0-4: 1st conversion in regular sequence.

RSQ1

Bits 5-9: 2nd conversion in regular sequence.

RSQ2

Bits 10-14: 3rd conversion in regular sequence.

RSQ3

Bits 15-19: 4th conversion in regular sequence.

RSQ4

Bits 20-24: 5th conversion in regular sequence.

RSQ5

Bits 25-29: 6th conversion in regular sequence.

ISQ

Inserted sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IL
rw 		ISQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISQ3
rw 		ISQ2
rw 		ISQ1
rw 		ISQ0
rw
Toggle Fields.

ISQ0

Bits 0-4: 1st conversion in inserted sequence.

ISQ1

Bits 5-9: 2nd conversion in inserted sequence.

ISQ2

Bits 10-14: 3rd conversion in inserted sequence.

ISQ3

Bits 15-19: 4th conversion in inserted sequence.

IL

Bits 20-21: Inserted channel group length.

IDATA0

Inserted data register 0

Offset: 0x3C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

IDATA1

Inserted data register 1

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

IDATA2

Inserted data register 2

Offset: 0x44, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

IDATA3

Inserted data register 3

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

RDATA

regular data register

Offset: 0x4C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle Fields.

RDATA

Bits 0-15: Regular channel data.

OVSAMPCTL

Oversample control register

Offset: 0x80, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOVS
r 		OVSS
r 		OVSR
r 		OVSEN
r
Toggle Fields.

OVSEN

Bit 0: Oversampling Enable.

OVSR

Bits 2-4: Oversampling ratio.

OVSS

Bits 5-8: Oversampling shift.

TOVS

Bit 9: Triggered Oversampling.

ADC2

0x40012200: Analog to digital converter

9/90 fields covered. Toggle Registers.

STAT

status register

Offset: 0x0, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROVF
rw 		STRC
rw 		STIC
rw 		EOIC
rw 		EOC
rw 		WDE
rw
Toggle Fields.

WDE

Bit 0: Analog watchdog event flag.

EOC

Bit 1: End of group conversion flag.

EOIC

Bit 2: End of inserted group conversion flag.

STIC

Bit 3: Start flag of inserted channel group.

STRC

Bit 4: Start flag of regular channel group.

ROVF

Bit 5: Regular data register overflow.

CTL0

control register 0

Offset: 0x4, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ROVFIE
rw 		DRES
rw 		RWDEN
rw 		IWDEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISNUM
rw 		DISIC
rw 		DISRC
rw 		ICA
rw 		WDSC
rw 		SM
rw 		EOICIE
rw 		WDEIE
rw 		EOCIE
rw 		WDCHSEL
rw
Toggle Fields.

WDCHSEL

Bits 0-4: Analog watchdog channel select.

EOCIE

Bit 5: Interrupt enable for EOC.

WDEIE

Bit 6: Analog watchdog WDE.

EOICIE

Bit 7: Interrupt enable for EOIC.

SM

Bit 8: Scan mode.

WDSC

Bit 9: When in scan mode, analog watchdog is effective on a single channel.

ICA

Bit 10: Inserted channel group convert automatically.

DISRC

Bit 11: Discontinuous mode on regular channels.

DISIC

Bit 12: Discontinuous mode on inserted channels.

DISNUM

Bits 13-15: Number of conversions in discontinuous mode.

IWDEN

Bit 22: Inserted channel analog watchdog enable.

RWDEN

Bit 23: Regular channel analog watchdog enable.

DRES

Bits 24-25: ADC data resolution.

ROVFIE

Bit 26: Interrupt enable for ROVF.

CTL1

control register 1

Offset: 0x8, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRCST
rw 		ETMRC
rw 		ETSRC
rw 		SWICST
rw 		ETMIC
rw 		ETSIC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAL
rw 		EOCM
rw 		DDM
rw 		DMA
rw 		RSTCLB
rw 		CLB
rw 		CTN
rw 		ADCON
rw
Toggle Fields.

ADCON

Bit 0: ADC on.

CTN

Bit 1: Continuous mode.

CLB

Bit 2: ADC calibration.

RSTCLB

Bit 3: Reset calibration.

DMA

Bit 8: DMA request enable.

DDM

Bit 9: DMA disable mode.

EOCM

Bit 10: End of conversion mode.

DAL

Bit 11: Data alignment.

ETSIC

Bits 16-19: External trigger select for inserted channel.

ETMIC

Bits 20-21: External trigger mode for inserted channel.

SWICST

Bit 22: Software start on inserted channel.

ETSRC

Bits 24-27: External trigger select for regular channel.

ETMRC

Bits 28-29: External trigger mode for regular channel.

SWRCST

Bit 30: Software start on regular channel.

SAMPT0

Sample time register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT18
rw 		SPT17
rw 		SPT16
rw 		SPT15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT15
rw 		SPT14
rw 		SPT13
rw 		SPT12
rw 		SPT11
rw 		SPT10
rw
Toggle Fields.

SPT10

Bits 0-2: Channel 10 sample time selection.

SPT11

Bits 3-5: Channel 11 sample time selection.

SPT12

Bits 6-8: Channel 12 sample time selection.

SPT13

Bits 9-11: Channel 13 sample time selection.

SPT14

Bits 12-14: Channel 14 sample time selection.

SPT15

Bits 15-17: Channel 15 sample time selection.

SPT16

Bits 18-20: Channel 16 sample time selection.

SPT17

Bits 21-23: Channel 17 sample time selection.

SPT18

Bits 24-26: Channel 18 sample time selection.

SAMPT1

Sample time register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPT9
rw 		SPT8
rw 		SPT7
rw 		SPT6
rw 		SPT5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPT5
rw 		SPT4
rw 		SPT3
rw 		SPT2
rw 		SPT1
rw 		SPT0
rw
Toggle Fields.

SPT0

Bits 0-2: Channel 0 sample time selection.

SPT1

Bits 3-5: Channel 1 sample time selection.

SPT2

Bits 6-8: Channel 2 sample time selection.

SPT3

Bits 9-11: Channel 3 sample time selection.

SPT4

Bits 12-14: Channel 4 sample time selection.

SPT5

Bits 15-17: Channel 5 sample time selection.

SPT6

Bits 18-20: Channel 6 sample time selection.

SPT7

Bits 21-23: Channel 7 sample time selection.

SPT8

Bits 24-26: Channel 8 sample time selection.

SPT9

Bits 27-29: Channel 9 sample time selection.

IOFF0

Inserted channel data offset register 0

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 0.

IOFF1

Inserted channel data offset register 1

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 1.

IOFF2

Inserted channel data offset register 2

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 2.

IOFF3

Inserted channel data offset register 3

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOFF
rw
Toggle Fields.

IOFF

Bits 0-11: Data offset for inserted channel 3.

WDHT

watchdog higher threshold register

Offset: 0x24, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDHT
rw
Toggle Fields.

WDHT

Bits 0-11: Analog watchdog higher threshold.

WDLT

watchdog lower threshold register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDLT
rw
Toggle Fields.

WDLT

Bits 0-11: Analog watchdog lower threshold.

RSQ0

regular sequence register 0

Offset: 0x2C, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RL
rw 		RSQ15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ15
rw 		RSQ14
rw 		RSQ13
rw 		RSQ12
rw
Toggle Fields.

RSQ12

Bits 0-4: 13th conversion in regular sequence.

RSQ13

Bits 5-9: 14th conversion in regular sequence.

RSQ14

Bits 10-14: 15th conversion in regular sequence.

RSQ15

Bits 15-19: 16th conversion in regular sequence.

RL

Bits 20-23: Regular channel group length.

RSQ1

regular sequence register 1

Offset: 0x30, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ11
rw 		RSQ10
rw 		RSQ9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ9
rw 		RSQ8
rw 		RSQ7
rw 		RSQ6
rw
Toggle Fields.

RSQ6

Bits 0-4: 7th conversion in regular sequence.

RSQ7

Bits 5-9: 8th conversion in regular sequence.

RSQ8

Bits 10-14: 9th conversion in regular sequence.

RSQ9

Bits 15-19: 10th conversion in regular sequence.

RSQ10

Bits 20-24: 11th conversion in regular sequence.

RSQ11

Bits 25-29: 12th conversion in regular sequence.

RSQ2

regular sequence register 2

Offset: 0x34, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQ5
rw 		RSQ4
rw 		RSQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQ3
rw 		RSQ2
rw 		RSQ1
rw 		RSQ0
rw
Toggle Fields.

RSQ0

Bits 0-4: 1st conversion in regular sequence.

RSQ1

Bits 5-9: 2nd conversion in regular sequence.

RSQ2

Bits 10-14: 3rd conversion in regular sequence.

RSQ3

Bits 15-19: 4th conversion in regular sequence.

RSQ4

Bits 20-24: 5th conversion in regular sequence.

RSQ5

Bits 25-29: 6th conversion in regular sequence.

ISQ

Inserted sequence register

Offset: 0x38, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IL
rw 		ISQ3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISQ3
rw 		ISQ2
rw 		ISQ1
rw 		ISQ0
rw
Toggle Fields.

ISQ0

Bits 0-4: 1st conversion in inserted sequence.

ISQ1

Bits 5-9: 2nd conversion in inserted sequence.

ISQ2

Bits 10-14: 3rd conversion in inserted sequence.

ISQ3

Bits 15-19: 4th conversion in inserted sequence.

IL

Bits 20-21: Inserted channel group length.

IDATA0

Inserted data register 0

Offset: 0x3C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

IDATA1

Inserted data register 1

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

IDATA2

Inserted data register 2

Offset: 0x44, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

IDATA3

Inserted data register 3

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDATAn
r
Toggle Fields.

IDATAn

Bits 0-15: Inserted number n conversion data.

RDATA

regular data register

Offset: 0x4C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle Fields.

RDATA

Bits 0-15: Regular channel data.

OVSAMPCTL

Oversample control register

Offset: 0x80, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOVS
r 		OVSS
r 		OVSR
r 		OVSEN
r
Toggle Fields.

OVSEN

Bit 0: Oversampling Enable.

OVSR

Bits 2-4: Oversampling ratio.

OVSS

Bits 5-8: Oversampling shift.

TOVS

Bit 9: Triggered Oversampling.

ADC_Common

0x40012300: common ADC register

20/27 fields covered. Toggle Registers.

SSTAT

summary status register

Offset: 0x0, reset: 0x00000000, access: read-only

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ROVF2
r 		STRC2
r 		STIC2
r 		EOIC2
r 		EOC2
r 		WDE2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROVF1
r 		STRC1
r 		STIC1
r 		EOIC1
r 		EOC1
r 		WDE1
r 		ROVF0
r 		STRC0
r 		STIC0
r 		EOIC0
r 		EOC0
r 		WDE0
r
Toggle Fields.

WDE0

Bit 0: This bit equals to the WDE bit of ADC0.

EOC0

Bit 1: This bit equals to the EOC bit of ADC0.

EOIC0

Bit 2: This bit equals to the EOIC bit of ADC0.

STIC0

Bit 3: This bit equals to the STIC bit of ADC0.

STRC0

Bit 4: This bit equals to the STRC bit of ADC0.

ROVF0

Bit 5: This bit equals to the ROVF bit of ADC0.

WDE1

Bit 8: This bit equals to the WDE bit of ADC1.

EOC1

Bit 9: This bit equals to the EOC bit of ADC1.

EOIC1

Bit 10: This bit equals to the EOIC bit of ADC1.

STIC1

Bit 11: This bit equals to the STIC bit of ADC1.

STRC1

Bit 12: This bit equals to the STRC bit of ADC1.

ROVF1

Bit 13: This bit equals to the ROVF bit of ADC1.

WDE2

Bit 16: This bit equals to the WDE bit of ADC2.

EOC2

Bit 17: This bit equals to the EOC bit of ADC2.

EOIC2

Bit 18: This bit equals to the EOIC bit of ADC2.

STIC2

Bit 19: This bit equals to the STIC bit of ADC2.

STRC2

Bit 20: This bit equals to the STRC bit of ADC2.

ROVF2

Bit 21: This bit equals to the ROVF bit of ADC2.

SYNCCTL

sync control register

Offset: 0x4, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSVREN
rw 		VBATEN
rw 		ADCCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNCDMA
rw 		SYNCDDM
rw 		SYNCDLY
rw 		SYNCM
rw
Toggle Fields.

SYNCM

Bits 0-4: ADC sync mode.

SYNCDLY

Bits 8-11: ADC sync delay.

SYNCDDM

Bit 13: ADC sync DMA disable mode.

SYNCDMA

Bits 14-15: ADC sync DMA mode selection.

ADCCK

Bits 16-18: ADC clock.

VBATEN

Bit 22: Channel 18 (1/4 voltate of external battery) enable of ADC0.

TSVREN

Bit 23: Channel 16 (temperature sensor) and 17 (internal reference voltage) enable of ADC0.

SYNCDATA

Sync regular data register

Offset: 0x8, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCDATA2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNCDATA1
r
Toggle Fields.

SYNCDATA1

Bits 0-15: Regular data1 in ADC sync mode.

SYNCDATA2

Bits 16-31: Regular data2 in ADC sync mode.

CAN0

0x40006400: Controller area network

50/2059 fields covered. Toggle Registers.

CTL

Control register

Offset: 0x0, reset: 0x00010002, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
rw 		TTC
rw 		ABOR
rw 		AWU
rw 		ARD
rw 		RFOD
rw 		TFO
rw 		SLPWMOD
rw 		IWMOD
rw
Toggle Fields.

IWMOD

Bit 0: Initial working mode.

SLPWMOD

Bit 1: Sleep working mode.

TFO

Bit 2: Transmit FIFO order.

RFOD

Bit 3: Receive FIFO overwrite disable.

ARD

Bit 4: Automatic retransmission disable.

AWU

Bit 5: Automatic wakeup.

ABOR

Bit 6: Automatic bus-off recovery.

TTC

Bit 7: Time-triggered communication.

SWRST

Bit 15: Software reset.

DFZ

Bit 16: Debug freeze.

STAT

Status register

Offset: 0x4, reset: 0x00000C02, access: Unspecified

6/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXL
r 		LASTRX
r 		RS
r 		TS
r 		SLPIF
rw 		WUIF
rw 		ERRIF
rw 		SLPWS
r 		IWS
r
Toggle Fields.

IWS

Bit 0: Initial working state.

SLPWS

Bit 1: Sleep working state.

ERRIF

Bit 2: Error interrupt flag.

WUIF

Bit 3: Status change interrupt flag of wakeup from sleep working mode.

SLPIF

Bit 4: Status change interrupt flag of sleep working mode entering.

TS

Bit 8: Transmitting state.

RS

Bit 9: Receiving state.

LASTRX

Bit 10: Last sample value of RX pin.

RXL

Bit 11: RX level.

TSTAT

Transmit status register

Offset: 0x8, reset: 0x1C000000, access: Unspecified

7/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TMLS2
r 		TMLS1
r 		TMLS0
r 		TME2
r 		TME1
r 		TME0
r 		NUM
r 		MST2
rw 		MTE2
rw 		MAL2
rw 		MTFNERR2
rw 		MTF2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MST1
rw 		MTE1
rw 		MAL1
rw 		MTFNERR1
rw 		MTF1
rw 		MST0
rw 		MTE0
rw 		MAL0
rw 		MTFNERR0
rw 		MTF0
rw
Toggle Fields.

MTF0

Bit 0: Mailbox 0 transmit finished.

MTFNERR0

Bit 1: Mailbox 0 transmit finished and no error.

MAL0

Bit 2: Mailbox 0 arbitration lost.

MTE0

Bit 3: Mailbox 0 transmit error.

MST0

Bit 7: Mailbox 0 stop transmitting.

MTF1

Bit 8: Mailbox 1 transmit finished.

MTFNERR1

Bit 9: Mailbox 1 transmit finished and no error.

MAL1

Bit 10: Mailbox 1 arbitration lost.

MTE1

Bit 11: Mailbox 1 transmit error.

MST1

Bit 15: Mailbox 1 stop transmitting.

MTF2

Bit 16: Mailbox 2 transmit finished.

MTFNERR2

Bit 17: Mailbox 2 transmit finished and no error.

MAL2

Bit 18: Mailbox 2 arbitration lost.

MTE2

Bit 19: Mailbox 2 transmit error.

MST2

Bit 23: Mailbox 2 stop transmitting.

NUM

Bits 24-25: number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty.

TME0

Bit 26: Transmit mailbox 0 empty.

TME1

Bit 27: Transmit mailbox 1 empty.

TME2

Bit 28: Transmit mailbox 2 empty.

TMLS0

Bit 29: Transmit mailbox 0 last sending in transmit FIFO.

TMLS1

Bit 30: Transmit mailbox 1 last sending in transmit FIFO.

TMLS2

Bit 31: Transmit mailbox 2 last sending in transmit FIFO.

RFIFO0

Receive message FIFO0 register

Offset: 0xC, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFD0
rw 		RFO0
rw 		RFF0
rw 		RFL0
r
Toggle Fields.

RFL0

Bits 0-1: Receive FIFO0 length.

RFF0

Bit 3: Receive FIFO0 full.

RFO0

Bit 4: Receive FIFO0 overfull.

RFD0

Bit 5: Receive FIFO0 dequeue.

RFIFO1

Receive message FIFO1 register

Offset: 0x10, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFD1
rw 		RFO1
rw 		RFF1
rw 		RFL1
r
Toggle Fields.

RFL1

Bits 0-1: Receive FIFO1 length.

RFF1

Bit 3: Receive FIFO1 full.

RFO1

Bit 4: Receive FIFO1 overfull.

RFD1

Bit 5: Receive FIFO1 dequeue.

INTEN

Interrupt enable register

Offset: 0x14, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLPWIE
rw 		WIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE
rw 		ERRNIE
rw 		BOIE
rw 		PERRIE
rw 		WERRIE
rw 		RFOIE1
rw 		RFFIE1
rw 		RFNEIE1
rw 		RFOIE0
rw 		RFFIE0
rw 		RFNEIE0
rw 		TMEIE
rw
Toggle Fields.

TMEIE

Bit 0: Transmit mailbox empty interrupt enable.

RFNEIE0

Bit 1: Receive FIFO0 not empty interrupt enable.

RFFIE0

Bit 2: Receive FIFO0 full interrupt enable.

RFOIE0

Bit 3: Receive FIFO0 overfull interrupt enable.

RFNEIE1

Bit 4: Receive FIFO1 not empty interrupt enable.

RFFIE1

Bit 5: Receive FIFO1 full interrupt enable.

RFOIE1

Bit 6: Receive FIFO1 overfull interrupt enable.

WERRIE

Bit 8: Warning error interrupt enable.

PERRIE

Bit 9: Passive error interrupt enable.

BOIE

Bit 10: Bus-off interrupt enable.

ERRNIE

Bit 11: Error number interrupt enable.

ERRIE

Bit 15: Error interrupt enable.

WIE

Bit 16: Wakeup interrupt enable.

SLPWIE

Bit 17: Sleep working interrupt enable.

ERR

Error register

Offset: 0x18, reset: 0x00000000, access: Unspecified

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECNT
r 		TECNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRN
rw 		BOERR
r 		PERR
r 		WERR
r
Toggle Fields.

WERR

Bit 0: Warning error.

PERR

Bit 1: Passive error.

BOERR

Bit 2: Bus-off error.

ERRN

Bits 4-6: Error number.

TECNT

Bits 16-23: Transmit Error Count defined by the CAN standard.

RECNT

Bits 24-31: Receive Error Count defined by the CAN standard.

BT

Bit timing register

Offset: 0x1C, reset: 0x01230000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCMOD
rw 		LCMOD
rw 		SJW
rw 		BS2
rw 		BS1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUADPSC
rw
Toggle Fields.

BUADPSC

Bits 0-9: Baud rate prescaler.

BS1

Bits 16-19: Bit segment 1.

BS2

Bits 20-22: Bit segment 2.

SJW

Bits 24-25: Resynchronization jump width.

LCMOD

Bit 30: Loopback communication mode.

SCMOD

Bit 31: Silent communication mode.

TMI0

Transmit mailbox identifier register 0

Offset: 0x180, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

FT

Bit 1: Frame type.

FF

Bit 2: Frame format.

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP0

Transmit mailbox property register 0

Offset: 0x184, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

TSEN

Bit 8: Time stamp enable.

TS

Bits 16-31: Time stamp.

TMDATA00

Transmit mailbox data0 register

Offset: 0x188, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

DB1

Bits 8-15: Data byte 1.

DB2

Bits 16-23: Data byte 2.

DB3

Bits 24-31: Data byte 3.

TMDATA10

Transmit mailbox data1 register

Offset: 0x18C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

DB5

Bits 8-15: Data byte 5.

DB6

Bits 16-23: Data byte 6.

DB7

Bits 24-31: Data byte 7.

TMI1

Transmit mailbox identifier register 1

Offset: 0x190, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

FT

Bit 1: Frame type.

FF

Bit 2: Frame format.

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP1

Transmit mailbox property register 1

Offset: 0x194, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

TSEN

Bit 8: Time stamp enable.

TS

Bits 16-31: Time stamp.

TMDATA01

Transmit mailbox data0 register

Offset: 0x198, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

DB1

Bits 8-15: Data byte 1.

DB2

Bits 16-23: Data byte 2.

DB3

Bits 24-31: Data byte 3.

TMDATA11

Transmit mailbox data1 register

Offset: 0x19C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

DB5

Bits 8-15: Data byte 5.

DB6

Bits 16-23: Data byte 6.

DB7

Bits 24-31: Data byte 7.

TMI2

Transmit mailbox identifier register 2

Offset: 0x1A0, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

FT

Bit 1: Frame type.

FF

Bit 2: Frame format.

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP2

Transmit mailbox property register 2

Offset: 0x1A4, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

TSEN

Bit 8: Time stamp enable.

TS

Bits 16-31: Time stamp.

TMDATA02

Transmit mailbox data0 register

Offset: 0x1A8, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

DB1

Bits 8-15: Data byte 1.

DB2

Bits 16-23: Data byte 2.

DB3

Bits 24-31: Data byte 3.

TMDATA12

Transmit mailbox data1 register

Offset: 0x1AC, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

DB5

Bits 8-15: Data byte 5.

DB6

Bits 16-23: Data byte 6.

DB7

Bits 24-31: Data byte 7.

RFIFOMI0

Receive FIFO mailbox identifier register

Offset: 0x1B0, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
r 		EFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
r 		FF
r 		FT
r
Toggle Fields.

FT

Bit 1: Frame type.

FF

Bit 2: Frame format.

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

RFIFOMP0

Receive FIFO0 mailbox property register

Offset: 0x1B4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FI
r 		DLENC
r
Toggle Fields.

DLENC

Bits 0-3: Data length code.

FI

Bits 8-15: Filtering index.

TS

Bits 16-31: Time stamp.

RFIFOMDATA00

Receive FIFO0 mailbox data0 register

Offset: 0x1B8, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
r 		DB2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
r 		DB0
r
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

DB1

Bits 8-15: Data byte 1.

DB2

Bits 16-23: Data byte 2.

DB3

Bits 24-31: Data byte 3.

RFIFOMDATA10

Receive FIFO0 mailbox data1 register

Offset: 0x1BC, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
r 		DB6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
r 		DB4
r
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

DB5

Bits 8-15: Data byte 5.

DB6

Bits 16-23: Data byte 6.

DB7

Bits 24-31: Data byte 7.

RFIFOMI1

Receive FIFO1 mailbox identifier register

Offset: 0x1C0, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
r 		EFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
r 		FF
r 		FT
r
Toggle Fields.

FT

Bit 1: Frame type.

FF

Bit 2: Frame format.

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

RFIFOMP1

Receive FIFO1 mailbox property register

Offset: 0x1C4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FI
r 		DLENC
r
Toggle Fields.

DLENC

Bits 0-3: Data length code.

FI

Bits 8-15: Filtering index.

TS

Bits 16-31: Time stamp.

RFIFOMDATA01

Receive FIFO1 mailbox data0 register

Offset: 0x1C8, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
r 		DB2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
r 		DB0
r
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

DB1

Bits 8-15: Data byte 1.

DB2

Bits 16-23: Data byte 2.

DB3

Bits 24-31: Data byte 3.

RFIFOMDATA11

Receive FIFO1 mailbox data1 register

Offset: 0x1CC, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
r 		DB6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
r 		DB4
r
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

DB5

Bits 8-15: Data byte 5.

DB6

Bits 16-23: Data byte 6.

DB7

Bits 24-31: Data byte 7.

FCTL

Filter control register

Offset: 0x200, reset: 0x2A1C0E01, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HBC1F
rw 		FLD
rw
Toggle Fields.

FLD

Bit 0: Filter lock disable.

HBC1F

Bits 8-13: Header bank of CAN1 filter.

FMCFG

Filter mode configuration register

Offset: 0x204, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FMOD27
rw 		FMOD26
rw 		FMOD25
rw 		FMOD24
rw 		FMOD23
rw 		FMOD22
rw 		FMOD21
rw 		FMOD20
rw 		FMOD19
rw 		FMOD18
rw 		FMOD17
rw 		FMOD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMOD15
rw 		FMOD14
rw 		FMOD13
rw 		FMOD12
rw 		FMOD11
rw 		FMOD10
rw 		FMOD9
rw 		FMOD8
rw 		FMOD7
rw 		FMOD6
rw 		FMOD5
rw 		FMOD4
rw 		FMOD3
rw 		FMOD2
rw 		FMOD1
rw 		FMOD0
rw
Toggle Fields.

FMOD0

Bit 0: Filter mode.

FMOD1

Bit 1: Filter mode.

FMOD2

Bit 2: Filter mode.

FMOD3

Bit 3: Filter mode.

FMOD4

Bit 4: Filter mode.

FMOD5

Bit 5: Filter mode.

FMOD6

Bit 6: Filter mode.

FMOD7

Bit 7: Filter mode.

FMOD8

Bit 8: Filter mode.

FMOD9

Bit 9: Filter mode.

FMOD10

Bit 10: Filter mode.

FMOD11

Bit 11: Filter mode.

FMOD12

Bit 12: Filter mode.

FMOD13

Bit 13: Filter mode.

FMOD14

Bit 14: Filter mode.

FMOD15

Bit 15: Filter mode.

FMOD16

Bit 16: Filter mode.

FMOD17

Bit 17: Filter mode.

FMOD18

Bit 18: Filter mode.

FMOD19

Bit 19: Filter mode.

FMOD20

Bit 20: Filter mode.

FMOD21

Bit 21: Filter mode.

FMOD22

Bit 22: Filter mode.

FMOD23

Bit 23: Filter mode.

FMOD24

Bit 24: Filter mode.

FMOD25

Bit 25: Filter mode.

FMOD26

Bit 26: Filter mode.

FMOD27

Bit 27: Filter mode.

FSCFG

Filter scale configuration register

Offset: 0x20C, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FS27
rw 		FS26
rw 		FS25
rw 		FS24
rw 		FS23
rw 		FS22
rw 		FS21
rw 		FS20
rw 		FS19
rw 		FS18
rw 		FS17
rw 		FS16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FS15
rw 		FS14
rw 		FS13
rw 		FS12
rw 		FS11
rw 		FS10
rw 		FS9
rw 		FS8
rw 		FS7
rw 		FS6
rw 		FS5
rw 		FS4
rw 		FS3
rw 		FS2
rw 		FS1
rw 		FS0
rw
Toggle Fields.

FS0

Bit 0: Filter scale configuration.

FS1

Bit 1: Filter scale configuration.

FS2

Bit 2: Filter scale configuration.

FS3

Bit 3: Filter scale configuration.

FS4

Bit 4: Filter scale configuration.

FS5

Bit 5: Filter scale configuration.

FS6

Bit 6: Filter scale configuration.

FS7

Bit 7: Filter scale configuration.

FS8

Bit 8: Filter scale configuration.

FS9

Bit 9: Filter scale configuration.

FS10

Bit 10: Filter scale configuration.

FS11

Bit 11: Filter scale configuration.

FS12

Bit 12: Filter scale configuration.

FS13

Bit 13: Filter scale configuration.

FS14

Bit 14: Filter scale configuration.

FS15

Bit 15: Filter scale configuration.

FS16

Bit 16: Filter scale configuration.

FS17

Bit 17: Filter scale configuration.

FS18

Bit 18: Filter scale configuration.

FS19

Bit 19: Filter scale configuration.

FS20

Bit 20: Filter scale configuration.

FS21

Bit 21: Filter scale configuration.

FS22

Bit 22: Filter scale configuration.

FS23

Bit 23: Filter scale configuration.

FS24

Bit 24: Filter scale configuration.

FS25

Bit 25: Filter scale configuration.

FS26

Bit 26: Filter scale configuration.

FS27

Bit 27: Filter scale configuration.

FAFIFO

Filter associated FIFO register

Offset: 0x214, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FAF27
rw 		FAF26
rw 		FAF25
rw 		FAF24
rw 		FAF23
rw 		FAF22
rw 		FAF21
rw 		FAF20
rw 		FAF19
rw 		FAF18
rw 		FAF17
rw 		FAF16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAF15
rw 		FAF14
rw 		FAF13
rw 		FAF12
rw 		FAF11
rw 		FAF10
rw 		FAF9
rw 		FAF8
rw 		FAF7
rw 		FAF6
rw 		FAF5
rw 		FAF4
rw 		FAF3
rw 		FAF2
rw 		FAF1
rw 		FAF0
rw
Toggle Fields.

FAF0

Bit 0: Filter 0 associated with FIFO.

FAF1

Bit 1: Filter 1 associated with FIFO.

FAF2

Bit 2: Filter 2 associated with FIFO.

FAF3

Bit 3: Filter 3 associated with FIFO.

FAF4

Bit 4: Filter 4 associated with FIFO.

FAF5

Bit 5: Filter 5 associated with FIFO.

FAF6

Bit 6: Filter 6 associated with FIFO.

FAF7

Bit 7: Filter 7 associated with FIFO.

FAF8

Bit 8: Filter 8 associated with FIFO.

FAF9

Bit 9: Filter 9 associated with FIFO.

FAF10

Bit 10: Filter 10 associated with FIFO.

FAF11

Bit 11: Filter 11 associated with FIFO.

FAF12

Bit 12: Filter 12 associated with FIFO.

FAF13

Bit 13: Filter 13 associated with FIFO.

FAF14

Bit 14: Filter 14 associated with FIFO.

FAF15

Bit 15: Filter 15 associated with FIFO.

FAF16

Bit 16: Filter 16 associated with FIFO.

FAF17

Bit 17: Filter 17 associated with FIFO.

FAF18

Bit 18: Filter 18 associated with FIFO.

FAF19

Bit 19: Filter 19 associated with FIFO.

FAF20

Bit 20: Filter 20 associated with FIFO.

FAF21

Bit 21: Filter 21 associated with FIFO.

FAF22

Bit 22: Filter 22 associated with FIFO.

FAF23

Bit 23: Filter 23 associated with FIFO.

FAF24

Bit 24: Filter 24 associated with FIFO.

FAF25

Bit 25: Filter 25 associated with FIFO.

FAF26

Bit 26: Filter 26 associated with FIFO.

FAF27

Bit 27: Filter 27 associated with FIFO.

FW

Filter working register

Offset: 0x21C, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FW27
rw 		FW26
rw 		FW25
rw 		FW24
rw 		FW23
rw 		FW22
rw 		FW21
rw 		FW20
rw 		FW19
rw 		FW18
rw 		FW17
rw 		FW16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FW15
rw 		FW14
rw 		FW13
rw 		FW12
rw 		FW11
rw 		FW10
rw 		FW9
rw 		FW8
rw 		FW7
rw 		FW6
rw 		FW5
rw 		FW4
rw 		FW3
rw 		FW2
rw 		FW1
rw 		FW0
rw
Toggle Fields.

FW0

Bit 0: Filter working.

FW1

Bit 1: Filter working.

FW2

Bit 2: Filter working.

FW3

Bit 3: Filter working.

FW4

Bit 4: Filter working.

FW5

Bit 5: Filter working.

FW6

Bit 6: Filter working.

FW7

Bit 7: Filter working.

FW8

Bit 8: Filter working.

FW9

Bit 9: Filter working.

FW10

Bit 10: Filter working.

FW11

Bit 11: Filter working.

FW12

Bit 12: Filter working.

FW13

Bit 13: Filter working.

FW14

Bit 14: Filter working.

FW15

Bit 15: Filter working.

FW16

Bit 16: Filter working.

FW17

Bit 17: Filter working.

FW18

Bit 18: Filter working.

FW19

Bit 19: Filter working.

FW20

Bit 20: Filter working.

FW21

Bit 21: Filter working.

FW22

Bit 22: Filter working.

FW23

Bit 23: Filter working.

FW24

Bit 24: Filter working.

FW25

Bit 25: Filter working.

FW26

Bit 26: Filter working.

FW27

Bit 27: Filter working.

F0DATA0

Filter 0 data 0 register

Offset: 0x240, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F0DATA1

Filter 0 data 1 register

Offset: 0x244, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F1DATA0

Filter 1 data 0 register

Offset: 0x248, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F1DATA1

Filter 1 data 1 register

Offset: 0x24C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F2DATA0

Filter 2 data 0 register

Offset: 0x250, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F2DATA1

Filter 2 data 1 register

Offset: 0x254, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F3DATA0

Filter 3 data 0 register

Offset: 0x258, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F3DATA1

Filter 3 data 1 register

Offset: 0x25C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F4DATA0

Filter 4 data 0 register

Offset: 0x260, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F4DATA1

Filter 4 data 1 register

Offset: 0x264, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F5DATA0

Filter 5 data 0 register

Offset: 0x268, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F5DATA1

Filter 5 data 1 register

Offset: 0x26C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F6DATA0

Filter 6 data 0 register

Offset: 0x270, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F6DATA1

Filter 6 data 1 register

Offset: 0x274, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F7DATA0

Filter 7 data 0 register

Offset: 0x278, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F7DATA1

Filter 7 data 1 register

Offset: 0x27C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F8DATA0

Filter 8 data 0 register

Offset: 0x280, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F8DATA1

Filter 8 data 1 register

Offset: 0x284, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F9DATA0

Filter 9 data 0 register

Offset: 0x288, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F9DATA1

Filter 9 data 1 register

Offset: 0x28C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F10DATA0

Filter 10 data 0 register

Offset: 0x290, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F10DATA1

Filter 10 data 1 register

Offset: 0x294, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F11DATA0

Filter 11 data 0 register

Offset: 0x298, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F11DATA1

Filter 11 data 1 register

Offset: 0x29C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F12DATA0

Filter 12 data 0 register

Offset: 0x2A0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F12DATA1

Filter 12 data 1 register

Offset: 0x2A4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F13DATA0

Filter 13 data 0 register

Offset: 0x2A8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F13DATA1

Filter 13 data 1 register

Offset: 0x2AC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F14DATA0

Filter 14 data 0 register

Offset: 0x2B0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F14DATA1

Filter 14 data 1 register

Offset: 0x2B4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F15DATA0

Filter 15 data 0 register

Offset: 0x2B8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F15DATA1

Filter 15 data 1 register

Offset: 0x2BC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F16DATA0

Filter 16 data 0 register

Offset: 0x2C0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F16DATA1

Filter 16 data 1 register

Offset: 0x2C4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F17DATA0

Filter 17 data 0 register

Offset: 0x2C8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F17DATA1

Filter 17 data 1 register

Offset: 0x2CC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F18DATA0

Filter 18 data 0 register

Offset: 0x2D0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F18DATA1

Filter 18 data 1 register

Offset: 0x2D4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F19DATA0

Filter 19 data 0 register

Offset: 0x2D8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F19DATA1

Filter 19 data 1 register

Offset: 0x2DC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F20DATA0

Filter 20 data 0 register

Offset: 0x2E0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F20DATA1

Filter 20 data 1 register

Offset: 0x2E4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F21DATA0

Filter 21 data 0 register

Offset: 0x2E8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F21DATA1

Filter 21 data 1 register

Offset: 0x2EC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F22DATA0

Filter 22 data 0 register

Offset: 0x2F0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F22DATA1

Filter 22 data 1 register

Offset: 0x2F4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F23DATA0

Filter 23 data 0 register

Offset: 0x2F8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F23DATA1

Filter 23 data 1 register

Offset: 0x2FC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F24DATA0

Filter 24 data 0 register

Offset: 0x300, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F24DATA1

Filter 24 data 1 register

Offset: 0x304, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F25DATA0

Filter 25 data 0 register

Offset: 0x308, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F25DATA1

Filter 25 data 1 register

Offset: 0x30C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F26DATA0

Filter 26 data 0 register

Offset: 0x310, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F26DATA1

Filter 26 data 1 register

Offset: 0x314, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F27DATA0

Filter 27 data 0 register

Offset: 0x318, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F27DATA1

Filter 27 data 1 register

Offset: 0x31C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

CAN1

0x40006800: Controller area network

50/2059 fields covered. Toggle Registers.

CTL

Control register

Offset: 0x0, reset: 0x00010002, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRST
rw 		TTC
rw 		ABOR
rw 		AWU
rw 		ARD
rw 		RFOD
rw 		TFO
rw 		SLPWMOD
rw 		IWMOD
rw
Toggle Fields.

IWMOD

Bit 0: Initial working mode.

SLPWMOD

Bit 1: Sleep working mode.

TFO

Bit 2: Transmit FIFO order.

RFOD

Bit 3: Receive FIFO overwrite disable.

ARD

Bit 4: Automatic retransmission disable.

AWU

Bit 5: Automatic wakeup.

ABOR

Bit 6: Automatic bus-off recovery.

TTC

Bit 7: Time-triggered communication.

SWRST

Bit 15: Software reset.

DFZ

Bit 16: Debug freeze.

STAT

Status register

Offset: 0x4, reset: 0x00000C02, access: Unspecified

6/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXL
r 		LASTRX
r 		RS
r 		TS
r 		SLPIF
rw 		WUIF
rw 		ERRIF
rw 		SLPWS
r 		IWS
r
Toggle Fields.

IWS

Bit 0: Initial working state.

SLPWS

Bit 1: Sleep working state.

ERRIF

Bit 2: Error interrupt flag.

WUIF

Bit 3: Status change interrupt flag of wakeup from sleep working mode.

SLPIF

Bit 4: Status change interrupt flag of sleep working mode entering.

TS

Bit 8: Transmitting state.

RS

Bit 9: Receiving state.

LASTRX

Bit 10: Last sample value of RX pin.

RXL

Bit 11: RX level.

TSTAT

Transmit status register

Offset: 0x8, reset: 0x1C000000, access: Unspecified

7/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TMLS2
r 		TMLS1
r 		TMLS0
r 		TME2
r 		TME1
r 		TME0
r 		NUM
r 		MST2
rw 		MTE2
rw 		MAL2
rw 		MTFNERR2
rw 		MTF2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MST1
rw 		MTE1
rw 		MAL1
rw 		MTFNERR1
rw 		MTF1
rw 		MST0
rw 		MTE0
rw 		MAL0
rw 		MTFNERR0
rw 		MTF0
rw
Toggle Fields.

MTF0

Bit 0: Mailbox 0 transmit finished.

MTFNERR0

Bit 1: Mailbox 0 transmit finished and no error.

MAL0

Bit 2: Mailbox 0 arbitration lost.

MTE0

Bit 3: Mailbox 0 transmit error.

MST0

Bit 7: Mailbox 0 stop transmitting.

MTF1

Bit 8: Mailbox 1 transmit finished.

MTFNERR1

Bit 9: Mailbox 1 transmit finished and no error.

MAL1

Bit 10: Mailbox 1 arbitration lost.

MTE1

Bit 11: Mailbox 1 transmit error.

MST1

Bit 15: Mailbox 1 stop transmitting.

MTF2

Bit 16: Mailbox 2 transmit finished.

MTFNERR2

Bit 17: Mailbox 2 transmit finished and no error.

MAL2

Bit 18: Mailbox 2 arbitration lost.

MTE2

Bit 19: Mailbox 2 transmit error.

MST2

Bit 23: Mailbox 2 stop transmitting.

NUM

Bits 24-25: number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty.

TME0

Bit 26: Transmit mailbox 0 empty.

TME1

Bit 27: Transmit mailbox 1 empty.

TME2

Bit 28: Transmit mailbox 2 empty.

TMLS0

Bit 29: Transmit mailbox 0 last sending in transmit FIFO.

TMLS1

Bit 30: Transmit mailbox 1 last sending in transmit FIFO.

TMLS2

Bit 31: Transmit mailbox 2 last sending in transmit FIFO.

RFIFO0

Receive message FIFO0 register

Offset: 0xC, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFD0
rw 		RFO0
rw 		RFF0
rw 		RFL0
r
Toggle Fields.

RFL0

Bits 0-1: Receive FIFO0 length.

RFF0

Bit 3: Receive FIFO0 full.

RFO0

Bit 4: Receive FIFO0 overfull.

RFD0

Bit 5: Receive FIFO0 dequeue.

RFIFO1

Receive message FIFO1 register

Offset: 0x10, reset: 0x00000000, access: Unspecified

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFD1
rw 		RFO1
rw 		RFF1
rw 		RFL1
r
Toggle Fields.

RFL1

Bits 0-1: Receive FIFO1 length.

RFF1

Bit 3: Receive FIFO1 full.

RFO1

Bit 4: Receive FIFO1 overfull.

RFD1

Bit 5: Receive FIFO1 dequeue.

INTEN

Interrupt enable register

Offset: 0x14, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLPWIE
rw 		WIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE
rw 		ERRNIE
rw 		BOIE
rw 		PERRIE
rw 		WERRIE
rw 		RFOIE1
rw 		RFFIE1
rw 		RFNEIE1
rw 		RFOIE0
rw 		RFFIE0
rw 		RFNEIE0
rw 		TMEIE
rw
Toggle Fields.

TMEIE

Bit 0: Transmit mailbox empty interrupt enable.

RFNEIE0

Bit 1: Receive FIFO0 not empty interrupt enable.

RFFIE0

Bit 2: Receive FIFO0 full interrupt enable.

RFOIE0

Bit 3: Receive FIFO0 overfull interrupt enable.

RFNEIE1

Bit 4: Receive FIFO1 not empty interrupt enable.

RFFIE1

Bit 5: Receive FIFO1 full interrupt enable.

RFOIE1

Bit 6: Receive FIFO1 overfull interrupt enable.

WERRIE

Bit 8: Warning error interrupt enable.

PERRIE

Bit 9: Passive error interrupt enable.

BOIE

Bit 10: Bus-off interrupt enable.

ERRNIE

Bit 11: Error number interrupt enable.

ERRIE

Bit 15: Error interrupt enable.

WIE

Bit 16: Wakeup interrupt enable.

SLPWIE

Bit 17: Sleep working interrupt enable.

ERR

Error register

Offset: 0x18, reset: 0x00000000, access: Unspecified

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECNT
r 		TECNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRN
rw 		BOERR
r 		PERR
r 		WERR
r
Toggle Fields.

WERR

Bit 0: Warning error.

PERR

Bit 1: Passive error.

BOERR

Bit 2: Bus-off error.

ERRN

Bits 4-6: Error number.

TECNT

Bits 16-23: Transmit Error Count defined by the CAN standard.

RECNT

Bits 24-31: Receive Error Count defined by the CAN standard.

BT

Bit timing register

Offset: 0x1C, reset: 0x01230000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCMOD
rw 		LCMOD
rw 		SJW
rw 		BS2
rw 		BS1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUADPSC
rw
Toggle Fields.

BUADPSC

Bits 0-9: Baud rate prescaler.

BS1

Bits 16-19: Bit segment 1.

BS2

Bits 20-22: Bit segment 2.

SJW

Bits 24-25: Resynchronization jump width.

LCMOD

Bit 30: Loopback communication mode.

SCMOD

Bit 31: Silent communication mode.

TMI0

Transmit mailbox identifier register 0

Offset: 0x180, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

FT

Bit 1: Frame type.

FF

Bit 2: Frame format.

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP0

Transmit mailbox property register 0

Offset: 0x184, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

TSEN

Bit 8: Time stamp enable.

TS

Bits 16-31: Time stamp.

TMDATA00

Transmit mailbox data0 register

Offset: 0x188, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

DB1

Bits 8-15: Data byte 1.

DB2

Bits 16-23: Data byte 2.

DB3

Bits 24-31: Data byte 3.

TMDATA10

Transmit mailbox data1 register

Offset: 0x18C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

DB5

Bits 8-15: Data byte 5.

DB6

Bits 16-23: Data byte 6.

DB7

Bits 24-31: Data byte 7.

TMI1

Transmit mailbox identifier register 1

Offset: 0x190, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

FT

Bit 1: Frame type.

FF

Bit 2: Frame format.

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP1

Transmit mailbox property register 1

Offset: 0x194, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

TSEN

Bit 8: Time stamp enable.

TS

Bits 16-31: Time stamp.

TMDATA01

Transmit mailbox data0 register

Offset: 0x198, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

DB1

Bits 8-15: Data byte 1.

DB2

Bits 16-23: Data byte 2.

DB3

Bits 24-31: Data byte 3.

TMDATA11

Transmit mailbox data1 register

Offset: 0x19C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

DB5

Bits 8-15: Data byte 5.

DB6

Bits 16-23: Data byte 6.

DB7

Bits 24-31: Data byte 7.

TMI2

Transmit mailbox identifier register 2

Offset: 0x1A0, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
rw 		EFID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
rw 		FF
rw 		FT
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transmit enable.

FT

Bit 1: Frame type.

FF

Bit 2: Frame format.

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

TMP2

Transmit mailbox property register 2

Offset: 0x1A4, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEN
rw 		DLENC
rw
Toggle Fields.

DLENC

Bits 0-3: Data length code.

TSEN

Bit 8: Time stamp enable.

TS

Bits 16-31: Time stamp.

TMDATA02

Transmit mailbox data0 register

Offset: 0x1A8, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
rw 		DB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
rw 		DB0
rw
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

DB1

Bits 8-15: Data byte 1.

DB2

Bits 16-23: Data byte 2.

DB3

Bits 24-31: Data byte 3.

TMDATA12

Transmit mailbox data1 register

Offset: 0x1AC, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
rw 		DB6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
rw 		DB4
rw
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

DB5

Bits 8-15: Data byte 5.

DB6

Bits 16-23: Data byte 6.

DB7

Bits 24-31: Data byte 7.

RFIFOMI0

Receive FIFO mailbox identifier register

Offset: 0x1B0, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
r 		EFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
r 		FF
r 		FT
r
Toggle Fields.

FT

Bit 1: Frame type.

FF

Bit 2: Frame format.

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

RFIFOMP0

Receive FIFO0 mailbox property register

Offset: 0x1B4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FI
r 		DLENC
r
Toggle Fields.

DLENC

Bits 0-3: Data length code.

FI

Bits 8-15: Filtering index.

TS

Bits 16-31: Time stamp.

RFIFOMDATA00

Receive FIFO0 mailbox data0 register

Offset: 0x1B8, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
r 		DB2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
r 		DB0
r
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

DB1

Bits 8-15: Data byte 1.

DB2

Bits 16-23: Data byte 2.

DB3

Bits 24-31: Data byte 3.

RFIFOMDATA10

Receive FIFO0 mailbox data1 register

Offset: 0x1BC, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
r 		DB6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
r 		DB4
r
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

DB5

Bits 8-15: Data byte 5.

DB6

Bits 16-23: Data byte 6.

DB7

Bits 24-31: Data byte 7.

RFIFOMI1

Receive FIFO1 mailbox identifier register

Offset: 0x1C0, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SFID_EFID
r 		EFID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFID
r 		FF
r 		FT
r
Toggle Fields.

FT

Bit 1: Frame type.

FF

Bit 2: Frame format.

EFID

Bits 3-20: The frame identifier.

SFID_EFID

Bits 21-31: The frame identifier.

RFIFOMP1

Receive FIFO1 mailbox property register

Offset: 0x1C4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FI
r 		DLENC
r
Toggle Fields.

DLENC

Bits 0-3: Data length code.

FI

Bits 8-15: Filtering index.

TS

Bits 16-31: Time stamp.

RFIFOMDATA01

Receive FIFO1 mailbox data0 register

Offset: 0x1C8, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB3
r 		DB2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB1
r 		DB0
r
Toggle Fields.

DB0

Bits 0-7: Data byte 0.

DB1

Bits 8-15: Data byte 1.

DB2

Bits 16-23: Data byte 2.

DB3

Bits 24-31: Data byte 3.

RFIFOMDATA11

Receive FIFO1 mailbox data1 register

Offset: 0x1CC, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DB7
r 		DB6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DB5
r 		DB4
r
Toggle Fields.

DB4

Bits 0-7: Data byte 4.

DB5

Bits 8-15: Data byte 5.

DB6

Bits 16-23: Data byte 6.

DB7

Bits 24-31: Data byte 7.

FCTL

Filter control register

Offset: 0x200, reset: 0x2A1C0E01, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HBC1F
rw 		FLD
rw
Toggle Fields.

FLD

Bit 0: Filter lock disable.

HBC1F

Bits 8-13: Header bank of CAN1 filter.

FMCFG

Filter mode configuration register

Offset: 0x204, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FMOD27
rw 		FMOD26
rw 		FMOD25
rw 		FMOD24
rw 		FMOD23
rw 		FMOD22
rw 		FMOD21
rw 		FMOD20
rw 		FMOD19
rw 		FMOD18
rw 		FMOD17
rw 		FMOD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMOD15
rw 		FMOD14
rw 		FMOD13
rw 		FMOD12
rw 		FMOD11
rw 		FMOD10
rw 		FMOD9
rw 		FMOD8
rw 		FMOD7
rw 		FMOD6
rw 		FMOD5
rw 		FMOD4
rw 		FMOD3
rw 		FMOD2
rw 		FMOD1
rw 		FMOD0
rw
Toggle Fields.

FMOD0

Bit 0: Filter mode.

FMOD1

Bit 1: Filter mode.

FMOD2

Bit 2: Filter mode.

FMOD3

Bit 3: Filter mode.

FMOD4

Bit 4: Filter mode.

FMOD5

Bit 5: Filter mode.

FMOD6

Bit 6: Filter mode.

FMOD7

Bit 7: Filter mode.

FMOD8

Bit 8: Filter mode.

FMOD9

Bit 9: Filter mode.

FMOD10

Bit 10: Filter mode.

FMOD11

Bit 11: Filter mode.

FMOD12

Bit 12: Filter mode.

FMOD13

Bit 13: Filter mode.

FMOD14

Bit 14: Filter mode.

FMOD15

Bit 15: Filter mode.

FMOD16

Bit 16: Filter mode.

FMOD17

Bit 17: Filter mode.

FMOD18

Bit 18: Filter mode.

FMOD19

Bit 19: Filter mode.

FMOD20

Bit 20: Filter mode.

FMOD21

Bit 21: Filter mode.

FMOD22

Bit 22: Filter mode.

FMOD23

Bit 23: Filter mode.

FMOD24

Bit 24: Filter mode.

FMOD25

Bit 25: Filter mode.

FMOD26

Bit 26: Filter mode.

FMOD27

Bit 27: Filter mode.

FSCFG

Filter scale configuration register

Offset: 0x20C, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FS27
rw 		FS26
rw 		FS25
rw 		FS24
rw 		FS23
rw 		FS22
rw 		FS21
rw 		FS20
rw 		FS19
rw 		FS18
rw 		FS17
rw 		FS16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FS15
rw 		FS14
rw 		FS13
rw 		FS12
rw 		FS11
rw 		FS10
rw 		FS9
rw 		FS8
rw 		FS7
rw 		FS6
rw 		FS5
rw 		FS4
rw 		FS3
rw 		FS2
rw 		FS1
rw 		FS0
rw
Toggle Fields.

FS0

Bit 0: Filter scale configuration.

FS1

Bit 1: Filter scale configuration.

FS2

Bit 2: Filter scale configuration.

FS3

Bit 3: Filter scale configuration.

FS4

Bit 4: Filter scale configuration.

FS5

Bit 5: Filter scale configuration.

FS6

Bit 6: Filter scale configuration.

FS7

Bit 7: Filter scale configuration.

FS8

Bit 8: Filter scale configuration.

FS9

Bit 9: Filter scale configuration.

FS10

Bit 10: Filter scale configuration.

FS11

Bit 11: Filter scale configuration.

FS12

Bit 12: Filter scale configuration.

FS13

Bit 13: Filter scale configuration.

FS14

Bit 14: Filter scale configuration.

FS15

Bit 15: Filter scale configuration.

FS16

Bit 16: Filter scale configuration.

FS17

Bit 17: Filter scale configuration.

FS18

Bit 18: Filter scale configuration.

FS19

Bit 19: Filter scale configuration.

FS20

Bit 20: Filter scale configuration.

FS21

Bit 21: Filter scale configuration.

FS22

Bit 22: Filter scale configuration.

FS23

Bit 23: Filter scale configuration.

FS24

Bit 24: Filter scale configuration.

FS25

Bit 25: Filter scale configuration.

FS26

Bit 26: Filter scale configuration.

FS27

Bit 27: Filter scale configuration.

FAFIFO

Filter associated FIFO register

Offset: 0x214, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FAF27
rw 		FAF26
rw 		FAF25
rw 		FAF24
rw 		FAF23
rw 		FAF22
rw 		FAF21
rw 		FAF20
rw 		FAF19
rw 		FAF18
rw 		FAF17
rw 		FAF16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAF15
rw 		FAF14
rw 		FAF13
rw 		FAF12
rw 		FAF11
rw 		FAF10
rw 		FAF9
rw 		FAF8
rw 		FAF7
rw 		FAF6
rw 		FAF5
rw 		FAF4
rw 		FAF3
rw 		FAF2
rw 		FAF1
rw 		FAF0
rw
Toggle Fields.

FAF0

Bit 0: Filter 0 associated with FIFO.

FAF1

Bit 1: Filter 1 associated with FIFO.

FAF2

Bit 2: Filter 2 associated with FIFO.

FAF3

Bit 3: Filter 3 associated with FIFO.

FAF4

Bit 4: Filter 4 associated with FIFO.

FAF5

Bit 5: Filter 5 associated with FIFO.

FAF6

Bit 6: Filter 6 associated with FIFO.

FAF7

Bit 7: Filter 7 associated with FIFO.

FAF8

Bit 8: Filter 8 associated with FIFO.

FAF9

Bit 9: Filter 9 associated with FIFO.

FAF10

Bit 10: Filter 10 associated with FIFO.

FAF11

Bit 11: Filter 11 associated with FIFO.

FAF12

Bit 12: Filter 12 associated with FIFO.

FAF13

Bit 13: Filter 13 associated with FIFO.

FAF14

Bit 14: Filter 14 associated with FIFO.

FAF15

Bit 15: Filter 15 associated with FIFO.

FAF16

Bit 16: Filter 16 associated with FIFO.

FAF17

Bit 17: Filter 17 associated with FIFO.

FAF18

Bit 18: Filter 18 associated with FIFO.

FAF19

Bit 19: Filter 19 associated with FIFO.

FAF20

Bit 20: Filter 20 associated with FIFO.

FAF21

Bit 21: Filter 21 associated with FIFO.

FAF22

Bit 22: Filter 22 associated with FIFO.

FAF23

Bit 23: Filter 23 associated with FIFO.

FAF24

Bit 24: Filter 24 associated with FIFO.

FAF25

Bit 25: Filter 25 associated with FIFO.

FAF26

Bit 26: Filter 26 associated with FIFO.

FAF27

Bit 27: Filter 27 associated with FIFO.

FW

Filter working register

Offset: 0x21C, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FW27
rw 		FW26
rw 		FW25
rw 		FW24
rw 		FW23
rw 		FW22
rw 		FW21
rw 		FW20
rw 		FW19
rw 		FW18
rw 		FW17
rw 		FW16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FW15
rw 		FW14
rw 		FW13
rw 		FW12
rw 		FW11
rw 		FW10
rw 		FW9
rw 		FW8
rw 		FW7
rw 		FW6
rw 		FW5
rw 		FW4
rw 		FW3
rw 		FW2
rw 		FW1
rw 		FW0
rw
Toggle Fields.

FW0

Bit 0: Filter working.

FW1

Bit 1: Filter working.

FW2

Bit 2: Filter working.

FW3

Bit 3: Filter working.

FW4

Bit 4: Filter working.

FW5

Bit 5: Filter working.

FW6

Bit 6: Filter working.

FW7

Bit 7: Filter working.

FW8

Bit 8: Filter working.

FW9

Bit 9: Filter working.

FW10

Bit 10: Filter working.

FW11

Bit 11: Filter working.

FW12

Bit 12: Filter working.

FW13

Bit 13: Filter working.

FW14

Bit 14: Filter working.

FW15

Bit 15: Filter working.

FW16

Bit 16: Filter working.

FW17

Bit 17: Filter working.

FW18

Bit 18: Filter working.

FW19

Bit 19: Filter working.

FW20

Bit 20: Filter working.

FW21

Bit 21: Filter working.

FW22

Bit 22: Filter working.

FW23

Bit 23: Filter working.

FW24

Bit 24: Filter working.

FW25

Bit 25: Filter working.

FW26

Bit 26: Filter working.

FW27

Bit 27: Filter working.

F0DATA0

Filter 0 data 0 register

Offset: 0x240, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F0DATA1

Filter 0 data 1 register

Offset: 0x244, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F1DATA0

Filter 1 data 0 register

Offset: 0x248, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F1DATA1

Filter 1 data 1 register

Offset: 0x24C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F2DATA0

Filter 2 data 0 register

Offset: 0x250, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F2DATA1

Filter 2 data 1 register

Offset: 0x254, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F3DATA0

Filter 3 data 0 register

Offset: 0x258, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F3DATA1

Filter 3 data 1 register

Offset: 0x25C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F4DATA0

Filter 4 data 0 register

Offset: 0x260, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F4DATA1

Filter 4 data 1 register

Offset: 0x264, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F5DATA0

Filter 5 data 0 register

Offset: 0x268, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F5DATA1

Filter 5 data 1 register

Offset: 0x26C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F6DATA0

Filter 6 data 0 register

Offset: 0x270, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F6DATA1

Filter 6 data 1 register

Offset: 0x274, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F7DATA0

Filter 7 data 0 register

Offset: 0x278, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F7DATA1

Filter 7 data 1 register

Offset: 0x27C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F8DATA0

Filter 8 data 0 register

Offset: 0x280, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F8DATA1

Filter 8 data 1 register

Offset: 0x284, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F9DATA0

Filter 9 data 0 register

Offset: 0x288, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F9DATA1

Filter 9 data 1 register

Offset: 0x28C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F10DATA0

Filter 10 data 0 register

Offset: 0x290, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F10DATA1

Filter 10 data 1 register

Offset: 0x294, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F11DATA0

Filter 11 data 0 register

Offset: 0x298, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F11DATA1

Filter 11 data 1 register

Offset: 0x29C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F12DATA0

Filter 12 data 0 register

Offset: 0x2A0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F12DATA1

Filter 12 data 1 register

Offset: 0x2A4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F13DATA0

Filter 13 data 0 register

Offset: 0x2A8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F13DATA1

Filter 13 data 1 register

Offset: 0x2AC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F14DATA0

Filter 14 data 0 register

Offset: 0x2B0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F14DATA1

Filter 14 data 1 register

Offset: 0x2B4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F15DATA0

Filter 15 data 0 register

Offset: 0x2B8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F15DATA1

Filter 15 data 1 register

Offset: 0x2BC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F16DATA0

Filter 16 data 0 register

Offset: 0x2C0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F16DATA1

Filter 16 data 1 register

Offset: 0x2C4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F17DATA0

Filter 17 data 0 register

Offset: 0x2C8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F17DATA1

Filter 17 data 1 register

Offset: 0x2CC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F18DATA0

Filter 18 data 0 register

Offset: 0x2D0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F18DATA1

Filter 18 data 1 register

Offset: 0x2D4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F19DATA0

Filter 19 data 0 register

Offset: 0x2D8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F19DATA1

Filter 19 data 1 register

Offset: 0x2DC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F20DATA0

Filter 20 data 0 register

Offset: 0x2E0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F20DATA1

Filter 20 data 1 register

Offset: 0x2E4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F21DATA0

Filter 21 data 0 register

Offset: 0x2E8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F21DATA1

Filter 21 data 1 register

Offset: 0x2EC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F22DATA0

Filter 22 data 0 register

Offset: 0x2F0, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F22DATA1

Filter 22 data 1 register

Offset: 0x2F4, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F23DATA0

Filter 23 data 0 register

Offset: 0x2F8, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F23DATA1

Filter 23 data 1 register

Offset: 0x2FC, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F24DATA0

Filter 24 data 0 register

Offset: 0x300, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F24DATA1

Filter 24 data 1 register

Offset: 0x304, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F25DATA0

Filter 25 data 0 register

Offset: 0x308, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F25DATA1

Filter 25 data 1 register

Offset: 0x30C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F26DATA0

Filter 26 data 0 register

Offset: 0x310, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F26DATA1

Filter 26 data 1 register

Offset: 0x314, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F27DATA0

Filter 27 data 0 register

Offset: 0x318, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

F27DATA1

Filter 27 data 1 register

Offset: 0x31C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD31
rw 		FD30
rw 		FD29
rw 		FD28
rw 		FD27
rw 		FD26
rw 		FD25
rw 		FD24
rw 		FD23
rw 		FD22
rw 		FD21
rw 		FD20
rw 		FD19
rw 		FD18
rw 		FD17
rw 		FD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FD15
rw 		FD14
rw 		FD13
rw 		FD12
rw 		FD11
rw 		FD10
rw 		FD9
rw 		FD8
rw 		FD7
rw 		FD6
rw 		FD5
rw 		FD4
rw 		FD3
rw 		FD2
rw 		FD1
rw 		FD0
rw
Toggle Fields.

FD0

Bit 0: Filter bits.

FD1

Bit 1: Filter bits.

FD2

Bit 2: Filter bits.

FD3

Bit 3: Filter bits.

FD4

Bit 4: Filter bits.

FD5

Bit 5: Filter bits.

FD6

Bit 6: Filter bits.

FD7

Bit 7: Filter bits.

FD8

Bit 8: Filter bits.

FD9

Bit 9: Filter bits.

FD10

Bit 10: Filter bits.

FD11

Bit 11: Filter bits.

FD12

Bit 12: Filter bits.

FD13

Bit 13: Filter bits.

FD14

Bit 14: Filter bits.

FD15

Bit 15: Filter bits.

FD16

Bit 16: Filter bits.

FD17

Bit 17: Filter bits.

FD18

Bit 18: Filter bits.

FD19

Bit 19: Filter bits.

FD20

Bit 20: Filter bits.

FD21

Bit 21: Filter bits.

FD22

Bit 22: Filter bits.

FD23

Bit 23: Filter bits.

FD24

Bit 24: Filter bits.

FD25

Bit 25: Filter bits.

FD26

Bit 26: Filter bits.

FD27

Bit 27: Filter bits.

FD28

Bit 28: Filter bits.

FD29

Bit 29: Filter bits.

FD30

Bit 30: Filter bits.

FD31

Bit 31: Filter bits.

CRC

0x40023000: cyclic redundancy check calculation unit

0/3 fields covered. Toggle Registers.

DATA

Data register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: CRC calculation result bits.

FDATA

Free data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDATA
rw
Toggle Fields.

FDATA

Bits 0-7: Free Data Register bits.

CTL

Control register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RST
rw
Toggle Fields.

RST

Bit 0: reset bit.

CTC

0x40006C00: Clock trim controller

9/27 fields covered. Toggle Registers.

CTL0

Control register 0

Offset: 0x0, reset: 0x00002000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMVALUE
rw 		SWREFPUL
rw 		AUTOTRIM
rw 		CNTEN
rw 		EREFIE
rw 		ERRIE
rw 		CKWARNIE
rw 		CKOKIE
rw
Toggle Fields.

CKOKIE

Bit 0: Clock trim ok interrupt enable.

CKWARNIE

Bit 1: Clock trim warning interrupt enable.

ERRIE

Bit 2: Error interrupt enable.

EREFIE

Bit 3: EREFIF interrupt enable.

CNTEN

Bit 5: CTC counter enable.

AUTOTRIM

Bit 6: Hardware automatically trim mode.

SWREFPUL

Bit 7: Software reference source sync pulse.

TRIMVALUE

Bits 8-13: IRC48M trim value.

CTL1

Control register 1

Offset: 0x4, reset: 0x2022BB7F, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REFPOL
rw 		USBSOFSEL
rw 		REFSEL
rw 		REFPSC
rw 		CKLIM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RLVALUE
rw
Toggle Fields.

RLVALUE

Bits 0-15: CTC counter reload value.

CKLIM

Bits 16-23: Clock trim base limit value.

REFPSC

Bits 24-26: Reference signal source prescaler.

REFSEL

Bits 28-29: Reference signal source selection.

USBSOFSEL

Bit 30: SOF signal selection.

REFPOL

Bit 31: Reference signal source polarity.

STAT

Status register

Offset: 0x8, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REFCAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REFDIR
r 		TRIMERR
r 		REFMISS
r 		CKERR
r 		EREFIF
r 		ERRIF
r 		CKWARNIF
r 		CKOKIF
r
Toggle Fields.

CKOKIF

Bit 0: Clock trim OK interrupt flag.

CKWARNIF

Bit 1: Clock trim warning interrupt flag.

ERRIF

Bit 2: Error interrupt flag.

EREFIF

Bit 3: Expect reference interrupt flag.

CKERR

Bit 8: Clock trim error bit.

REFMISS

Bit 9: Reference sync pulse miss.

TRIMERR

Bit 10: Trim value error bit.

REFDIR

Bit 15: CTC trim counter direction when reference sync pulse.

REFCAP

Bits 16-31: CTC counter capture when reference sync pulse.

INTC

Interrupt clear register

Offset: 0xC, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EREFIC
rw 		ERRIC
rw 		CKWARNIC
rw 		CKOKIC
rw
Toggle Fields.

CKOKIC

Bit 0: CKOKIF interrupt clear bit.

CKWARNIC

Bit 1: CKWARNIF interrupt clear bit.

ERRIC

Bit 2: ERRIF interrupt clear bit.

EREFIC

Bit 3: EREFIF interrupt clear bit.

DAC

0x40007400: Digital-to-analog converter

2/34 fields covered. Toggle Registers.

CTL

control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DDUDRIE1
rw 		DDMAEN1
rw 		DWBW1
rw 		DWM1
rw 		DTSEL1
rw 		DTEN1
rw 		DBOFF1
rw 		DEN1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDUDRIE0
rw 		DDMAEN0
rw 		DWBW0
rw 		DWM0
rw 		DTSEL0
rw 		DTEN0
rw 		DBOFF0
rw 		DEN0
rw
Toggle Fields.

DEN0

Bit 0: DAC0 enable.

DBOFF0

Bit 1: DAC0 output buffer turn off.

DTEN0

Bit 2: DAC0 trigger enable.

DTSEL0

Bits 3-5: DAC0 trigger selection.

DWM0

Bits 6-7: DAC0 noise wave mode.

DWBW0

Bits 8-11: DAC0 noise wave bit width.

DDMAEN0

Bit 12: DAC0 DMA enable.

DDUDRIE0

Bit 13: DAC0 DMA Underrun Interrupt enable.

DEN1

Bit 16: DAC1 enable.

DBOFF1

Bit 17: DAC1 output buffer turn off.

DTEN1

Bit 18: DAC1 trigger enable.

DTSEL1

Bits 19-21: DAC1 trigger selection.

DWM1

Bits 22-23: DAC1 noise wave mode.

DWBW1

Bits 24-27: DAC1 noise wave bit width.

DDMAEN1

Bit 28: DAC1 DMA enable.

DDUDRIE1

Bit 29: DAC1 DMA Underrun Interrupt enable.

SWT

software trigger register

Offset: 0x4, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTR1
w 		SWTR0
w
Toggle Fields.

SWTR0

Bit 0: DAC0 software trigger.

SWTR1

Bit 1: DAC1 software trigger.

DAC0_R12DH

DAC0 12-bit right-aligned data holding register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC0_DH
rw
Toggle Fields.

DAC0_DH

Bits 0-11: DAC0 12-bit right-aligned data.

DAC0_L12DH

DAC0 12-bit left-aligned data holding register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC0_DH
rw
Toggle Fields.

DAC0_DH

Bits 4-15: DAC0 12-bit left-aligned data.

DAC0_R8DH

DAC0 8-bit right aligned data holding register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC0_DH
rw
Toggle Fields.

DAC0_DH

Bits 0-7: DAC0 8-bit right-aligned data.

DAC1_R12DH

DAC1 12-bit right-aligned data holding register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC1_DH
rw
Toggle Fields.

DAC1_DH

Bits 0-11: DAC1 12-bit right-aligned data.

DAC1_L12DH

DAC1 12-bit left aligned data holding register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC1_DH
rw
Toggle Fields.

DAC1_DH

Bits 4-15: DAC1 12-bit left-aligned data.

DAC1_R8DH

DAC1 8-bit right aligned data holding register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC1_DH
rw
Toggle Fields.

DAC1_DH

Bits 0-7: DAC1 8-bit right-aligned data.

DACC_R12DH

DAC concurrent mode 12-bit right-aligned data holding register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAC1_DH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC0_DH
rw
Toggle Fields.

DAC0_DH

Bits 0-11: DAC0 12-bit right-aligned data.

DAC1_DH

Bits 16-27: DAC1 12-bit right-aligned data.

DACC_L12DH

DAC concurrent mode 12-bit left aligned data holding register

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAC1_DH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC0_DH
rw
Toggle Fields.

DAC0_DH

Bits 4-15: DAC0 12-bit left-aligned data.

DAC1_DH

Bits 20-31: DAC1 12-bit left-aligned data.

DACC_R8DH

DAC concurrent mode 8-bit right aligned data holding register

Offset: 0x28, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC1_DH
rw 		DAC0_DH
rw
Toggle Fields.

DAC0_DH

Bits 0-7: DAC0 8-bit right-aligned data.

DAC1_DH

Bits 8-15: DAC1 8-bit right-aligned data.

DAC0_DO

DAC0 data output register

Offset: 0x2C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC0_DO
r
Toggle Fields.

DAC0_DO

Bits 0-11: DAC0 data output.

DAC1_DO

DAC1 data output register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC1_DO
r
Toggle Fields.

DAC1_DO

Bits 0-11: DAC1 data output.

STAT

status register

Offset: 0x34, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DDUDR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDUDR0
rw
Toggle Fields.

DDUDR0

Bit 13: DAC0 DMA underrun flag.

DDUDR1

Bit 29: DAC1 DMA underrun flag.

DBG

0xE0042000: Debug support

1/28 fields covered. Toggle Registers.

ID

ID code register

Offset: 0x0, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID_CODE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID_CODE
r
Toggle Fields.

ID_CODE

Bits 0-31: DBG ID code register.

CTL0

Control register 0

Offset: 0x4, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRACE_MODE
rw 		TRACE_IOEN
rw 		STB_HOLD
rw 		DSLP_HOLD
rw 		SLP_HOLD
rw
Toggle Fields.

SLP_HOLD

Bit 0: Sleep mode hold register.

DSLP_HOLD

Bit 1: Deep-sleep mode hold register.

STB_HOLD

Bit 2: Standby mode hold register.

TRACE_IOEN

Bit 5: Trace pin allocation enable.

TRACE_MODE

Bits 6-7: Trace pin allocation mode.

CTL1

Control register 1

Offset: 0x8, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CAN1_HOLD
rw 		CAN0_HOLD
rw 		I2C2_HOLD
rw 		I2C1_HOLD
rw 		I2C0_HOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FWDGT_HOLD
rw 		WWDGT_HOLD
rw 		RTC_HOLD
rw 		TIMER13_HOLD
rw 		TIMER12_HOLD
rw 		TIMER11_HOLD
rw 		TIMER6_HOLD
rw 		TIMER5_HOLD
rw 		TIMER4_HOLD
rw 		TIMER3_HOLD
rw 		TIMER2_HOLD
rw 		TIMER1_HOLD
rw
Toggle Fields.

TIMER1_HOLD

Bit 0: TIMER 1 hold register.

TIMER2_HOLD

Bit 1: TIMER 2 hold register.

TIMER3_HOLD

Bit 2: TIMER 3 hold register.

TIMER4_HOLD

Bit 3: TIMER 4 hold register.

TIMER5_HOLD

Bit 4: TIMER 5 hold register.

TIMER6_HOLD

Bit 5: TIMER 6 hold register.

TIMER11_HOLD

Bit 6: TIMER 11 hold register.

TIMER12_HOLD

Bit 7: TIMER 12 hold register.

TIMER13_HOLD

Bit 8: TIMER 13 hold register.

RTC_HOLD

Bit 10: RTC hold register.

WWDGT_HOLD

Bit 11: WWDGT hold register.

FWDGT_HOLD

Bit 12: FWDGT hold register.

I2C0_HOLD

Bit 21: I2C0 hold register.

I2C1_HOLD

Bit 22: I2C1 hold register.

I2C2_HOLD

Bit 23: I2C2 hold register.

CAN0_HOLD

Bit 25: CAN0 hold register.

CAN1_HOLD

Bit 26: CAN1 hold register.

CTL2

Control register 2

Offset: 0xC, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIMER10_HOLD
rw 		TIMER9_HOLD
rw 		TIMER8_HOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMER7_HOLD
rw 		TIMER0_HOLD
rw
Toggle Fields.

TIMER0_HOLD

Bit 0: TIMER 0 hold register.

TIMER7_HOLD

Bit 1: TIMER 7 hold register.

TIMER8_HOLD

Bit 16: TIMER 8 hold register.

TIMER9_HOLD

Bit 17: TIMER 9 hold register.

TIMER10_HOLD

Bit 18: TIMER 10 hold register.

DCI

0x50050000: Digital Camera Interface

17/50 fields covered. Toggle Registers.

CTL

Control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCIEN
rw 		DCIF
rw 		FR
rw 		VPS
rw 		HPS
rw 		CKS
rw 		ESM
rw 		JM
rw 		WDEN
rw 		SNAP
rw 		CAP
rw
Toggle Fields.

CAP

Bit 0: Capture Enable.

SNAP

Bit 1: Snapshot mode.

WDEN

Bit 2: Window Enable.

JM

Bit 3: JPEG mode.

ESM

Bit 4: Embedded Synchronous Mode.

CKS

Bit 5: Clock Polarity Selection.

HPS

Bit 6: Horizontal Polarity Selection.

VPS

Bit 7: Vertical Polarity Selection.

FR

Bits 8-9: Frame rate.

DCIF

Bits 10-11: Digital camera interface format.

DCIEN

Bit 14: DCI Enable.

STAT0

Status register 0

Offset: 0x4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FV
r 		VS
r 		HS
r
Toggle Fields.

HS

Bit 0: HS line status.

VS

Bit 1: VS line status.

FV

Bit 2: FIFO Valid.

STAT1

Status register 1

Offset: 0x8, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ELF
r 		VSF
r 		ESEF
r 		OVRF
r 		EFF
r
Toggle Fields.

EFF

Bit 0: End of Frame Flag.

OVRF

Bit 1: FIFO Overrun Flag.

ESEF

Bit 2: Embedded Synchronous Error Flag.

VSF

Bit 3: Vsync Flag.

ELF

Bit 4: End of Line Flag.

INTEN

Interrupt enable register

Offset: 0xC, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ELIE
rw 		VSIE
rw 		ESEIE
rw 		OVRIE
rw 		EFIE
rw
Toggle Fields.

EFIE

Bit 0: End of Frame Interrupt Enable.

OVRIE

Bit 1: FIFO Overrun Interrupt Enable.

ESEIE

Bit 2: Embedded Synchronous Error Interrupt Enable.

VSIE

Bit 3: Vsync Interrupt Enable.

ELIE

Bit 4: End of Line Interrupt Enable.

INTF

Interrupt flag register

Offset: 0x10, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ELIF
r 		VSIF
r 		ESEIF
r 		OVRIF
r 		EFIF
r
Toggle Fields.

EFIF

Bit 0: End of Frame Interrupt Flag.

OVRIF

Bit 1: FIFO Overrun Interrupt Flag.

ESEIF

Bit 2: Embedded Synchronous Error Interrupt Flag.

VSIF

Bit 3: Vsync Interrupt Flag.

ELIF

Bit 4: End of Line Interrupt Flag.

INTC

Interrupt flag clear register

Offset: 0x14, reset: 0x00000000, access: write-only

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ELFC
w 		VSFC
w 		ESEFC
w 		OVRFC
w 		EFFC
w
Toggle Fields.

EFFC

Bit 0: Clear End of Frame Flag.

OVRFC

Bit 1: Clear FIFO Overrun Flag.

ESEFC

Bit 2: Clear embedded synchronous Error Flag.

VSFC

Bit 3: Vsync flag clear.

ELFC

Bit 4: End of Line Flag Clear.

SC

Synchronization codes register

Offset: 0x18, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FE
rw 		LE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LS
rw 		FS
rw
Toggle Fields.

FS

Bits 0-7: Frame Start Code in Embedded Synchronous Mode.

LS

Bits 8-15: Line Start Code in Embedded Synchronous Mode.

LE

Bits 16-23: Line End Code in Embedded Synchronous Mode.

FE

Bits 24-31: Frame End Code in Embedded Synchronous Mode.

SCUMSK

Synchronization codes unmask register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEM
rw 		LEM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSM
rw 		FSM
rw
Toggle Fields.

FSM

Bits 0-7: Frame Start Code unMask Bits in Embedded Synchronous Mode.

LSM

Bits 8-15: Line Start Code unMask Bits in Embedded Synchronous Mode.

LEM

Bits 16-23: Line End Code unMask Bits in Embedded Synchronous Mode.

FEM

Bits 24-31: Frame End Code unMask Bits in Embedded Synchronous Mode.

CWSPOS

Cropping window start position register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WVSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WHSP
rw
Toggle Fields.

WHSP

Bits 0-13: Window Horizontal Start Position.

WVSP

Bits 16-28: Window Vertical Start Position.

CWSZ

Cropping window size register

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WVSZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WHSZ
rw
Toggle Fields.

WHSZ

Bits 0-13: Window Horizontal Size.

WVSZ

Bits 16-29: Window Vertical Size.

DATA

DATA register

Offset: 0x28, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DT3
r 		DT2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DT1
r 		DT0
r
Toggle Fields.

DT0

Bits 0-7: Pixel Data 0.

DT1

Bits 8-15: Pixel Data 1.

DT2

Bits 16-23: Pixel Data 2.

DT3

Bits 24-31: Pixel Data 3 .

DMA0

0x40026000: DMA controller

40/296 fields covered. Toggle Registers.

INTF0

Interrupt flag register 0

Offset: 0x0, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTFIF3
r 		HTFIF3
r 		TAEIF3
r 		SDEIF3
r 		FEEIF3
r 		FTFIF2
r 		HTFIF2
r 		TAEIF2
r 		SDEIF2
r 		FEEIF2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTFIF1
r 		HTFIF1
r 		TAEIF1
r 		SDEIF1
r 		FEEIF1
r 		FTFIF0
r 		HTFIF0
r 		TAEIF0
r 		SDEIF0
r 		FEEIF0
r
Toggle Fields.

FEEIF0

Bit 0: FIFO error and exception of channel 0.

SDEIF0

Bit 2: Single data mode exception of channel 0.

TAEIF0

Bit 3: Transfer access error flag of channel 0.

HTFIF0

Bit 4: Half transfer finish flag of channel 0.

FTFIF0

Bit 5: Full Transfer finish flag of channel 0.

FEEIF1

Bit 6: FIFO error and exception of channel 1.

SDEIF1

Bit 8: Single data mode exception of channel 1.

TAEIF1

Bit 9: Transfer access error flag of channel 1.

HTFIF1

Bit 10: Half transfer finish flag of channel 1.

FTFIF1

Bit 11: Full Transfer finish flag of channel 1.

FEEIF2

Bit 16: FIFO error and exception of channel 2.

SDEIF2

Bit 18: Single data mode exception of channel 2.

TAEIF2

Bit 19: Transfer access error flag of channel 2.

HTFIF2

Bit 20: Half transfer finish flag of channel 2.

FTFIF2

Bit 21: Full Transfer finish flag of channel 2.

FEEIF3

Bit 22: FIFO error and exception of channel 3.

SDEIF3

Bit 24: Single data mode exception of channel 3.

TAEIF3

Bit 25: Transfer access error flag of channel 3.

HTFIF3

Bit 26: Half transfer finish flag of channel 3.

FTFIF3

Bit 27: Full Transfer finish flag of channel 3.

INTF1

Interrupt flag register 1

Offset: 0x4, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTFIF7
r 		HTFIF7
r 		TAEIF7
r 		SDEIF7
r 		FEEIF7
r 		FTFIF6
r 		HTFIF6
r 		TAEIF6
r 		SDEIF6
r 		FEEIF6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTFIF5
r 		HTFIF5
r 		TAEIF5
r 		SDEIF5
r 		FEEIF5
r 		FTFIF4
r 		HTFIF4
r 		TAEIF4
r 		SDEIF4
r 		FEEIF4
r
Toggle Fields.

FEEIF4

Bit 0: FIFO error and exception of channel 4.

SDEIF4

Bit 2: Single data mode exception of channel 4.

TAEIF4

Bit 3: Transfer access error flag of channel 4.

HTFIF4

Bit 4: Half transfer finish flag of channel 4.

FTFIF4

Bit 5: Full Transfer finish flag of channel 4.

FEEIF5

Bit 6: FIFO error and exception of channel 5.

SDEIF5

Bit 8: Single data mode exception of channel 5.

TAEIF5

Bit 9: Transfer access error flag of channel 5.

HTFIF5

Bit 10: Half transfer finish flag of channel 5.

FTFIF5

Bit 11: Full Transfer finish flag of channel 5.

FEEIF6

Bit 16: FIFO error and exception of channel 6.

SDEIF6

Bit 18: Single data mode exception of channel 6.

TAEIF6

Bit 19: Transfer access error flag of channel 6.

HTFIF6

Bit 20: Half transfer finish flag of channel 6.

FTFIF6

Bit 21: Full Transfer finish flag of channel 6.

FEEIF7

Bit 22: FIFO error and exception of channel 7.

SDEIF7

Bit 24: Single data mode exception of channel 7.

TAEIF7

Bit 25: Transfer access error flag of channel 7.

HTFIF7

Bit 26: Half transfer finish flag of channel 7.

FTFIF7

Bit 27: Full Transfer finish flag of channel 7.

INTC0

Interrupt flag clear register 0

Offset: 0x8, reset: 0x00000000, access: write-only

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTFIFC3
w 		HTFIFC3
w 		TAEIFC3
w 		SDEIFC3
w 		FEEIFC3
w 		FTFIFC2
w 		HTFIFC2
w 		TAEIFC2
w 		SDEIFC2
w 		FEEIFC2
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTFIFC1
w 		HTFIFC1
w 		TAEIFC1
w 		SDEIFC1
w 		FEEIFC1
w 		FTFIFC0
w 		HTFIFC0
w 		TAEIFC0
w 		SDEIFC0
w 		FEEIFC0
w
Toggle Fields.

FEEIFC0

Bit 0: Clear bit for FIFO error and exception of channel 0.

SDEIFC0

Bit 2: Clear bit for single data mode exception of channel 0.

TAEIFC0

Bit 3: Clear bit for transfer access error flag of channel 0.

HTFIFC0

Bit 4: Clear bit for half transfer finish flag of channel 0.

FTFIFC0

Bit 5: Clear bit for Full transfer finish flag of channel 0.

FEEIFC1

Bit 6: Clear bit for FIFO error and exception of channel 1.

SDEIFC1

Bit 8: Clear bit for single data mode exception of channel 1.

TAEIFC1

Bit 9: Clear bit for transfer access error flag of channel 1.

HTFIFC1

Bit 10: Clear bit for half transfer finish flag of channel 1.

FTFIFC1

Bit 11: Clear bit for Full transfer finish flag of channel 1.

FEEIFC2

Bit 16: Clear bit for FIFO error and exception of channel 2.

SDEIFC2

Bit 18: Clear bit for single data mode exception of channel 2.

TAEIFC2

Bit 19: Clear bit for transfer access error flag of channel 2.

HTFIFC2

Bit 20: Clear bit for half transfer finish flag of channel 2.

FTFIFC2

Bit 21: Clear bit for Full transfer finish flag of channel 2.

FEEIFC3

Bit 22: Clear bit for FIFO error and exception of channel 3.

SDEIFC3

Bit 24: Clear bit for single data mode exception of channel 3.

TAEIFC3

Bit 25: Clear bit for transfer access error flag of channel 3.

HTFIFC3

Bit 26: Clear bit for half transfer finish flag of channel 3.

FTFIFC3

Bit 27: Clear bit for Full transfer finish flag of channel 3.

INTC1

Interrupt flag clear register 1

Offset: 0xC, reset: 0x00000000, access: write-only

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTFIFC7
w 		HTFIFC7
w 		TAEIFC7
w 		SDEIFC7
w 		FEEIFC7
w 		FTFIFC6
w 		HTFIFC6
w 		TAEIFC6
w 		SDEIFC6
w 		FEEIFC6
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTFIFC5
w 		HTFIFC5
w 		TAEIFC5
w 		SDEIFC5
w 		FEEIFC5
w 		FTFIFC4
w 		HTFIFC4
w 		TAEIFC4
w 		SDEIFC4
w 		FEEIFC4
w
Toggle Fields.

FEEIFC4

Bit 0: Clear bit for FIFO error and exception of channel 4.

SDEIFC4

Bit 2: Clear bit for single data mode exception of channel 4.

TAEIFC4

Bit 3: Clear bit for transfer access error flag of channel 4.

HTFIFC4

Bit 4: Clear bit for half transfer finish flag of channel 4.

FTFIFC4

Bit 5: Clear bit for Full transfer finish flag of channel 4.

FEEIFC5

Bit 6: Clear bit for FIFO error and exception of channel 5.

SDEIFC5

Bit 8: Clear bit for single data mode exception of channel 5.

TAEIFC5

Bit 9: Clear bit for transfer access error flag of channel 5.

HTFIFC5

Bit 10: Clear bit for half transfer finish flag of channel 5.

FTFIFC5

Bit 11: Clear bit for Full transfer finish flag of channel 5.

FEEIFC6

Bit 16: Clear bit for FIFO error and exception of channel 6.

SDEIFC6

Bit 18: Clear bit for single data mode exception of channel 6.

TAEIFC6

Bit 19: Clear bit for transfer access error flag of channel 6.

HTFIFC6

Bit 20: Clear bit for half transfer finish flag of channel 6.

FTFIFC6

Bit 21: Clear bit for Full transfer finish flag of channel 6.

FEEIFC7

Bit 22: Clear bit for FIFO error and exception of channel 7.

SDEIFC7

Bit 24: Clear bit for single data mode exception of channel 7.

TAEIFC7

Bit 25: Clear bit for transfer access error flag of channel 7.

HTFIFC7

Bit 26: Clear bit for half transfer finish flag of channel 7.

FTFIFC7

Bit 27: Clear bit for Full transfer finish flag of channel 7.

CH0CTL

Channel 0 control register

Offset: 0x10, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERIEN
rw 		MBURST
rw 		PBURST
rw 		MBS
rw 		SBMEN
rw 		PRIO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAIF
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		TM
rw 		TFCS
rw 		FTFIE
rw 		HTFIE
rw 		TAEIE
rw 		SDEIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

SDEIE

Bit 1: Enable bit for single data mode exception interrupt.

TAEIE

Bit 2: Enable bit for tranfer access error interrupt.

HTFIE

Bit 3: Enable bit for half transfer finish interrupt.

FTFIE

Bit 4: Enable bit for full transfer finish interrupt.

TFCS

Bit 5: Transfer flow controller select.

TM

Bits 6-7: Transfer mode.

CMEN

Bit 8: Circulation mode enable.

PNAGA

Bit 9: Next address generation algorithm of peripheral.

MNAGA

Bit 10: Next address generation algorithm of memory.

PWIDTH

Bits 11-12: Transfer width of peripheral.

MWIDTH

Bits 13-14: Transfer width of memory.

PAIF

Bit 15: Peripheral address increment fixed.

PRIO

Bits 16-17: Priority level.

SBMEN

Bit 18: Switch-buffer mode enable.

MBS

Bit 19: Memory buffer select.

PBURST

Bits 21-22: Transfer burst type of peripheral.

MBURST

Bits 23-24: Transfer burst type of memory.

PERIEN

Bits 25-27: Peripheral enable.

CH0CNT

Channel 0 counter register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

CH0PADDR

Channel 0 peripheral base address register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH0M0ADDR

Channel 0 memory 0 base address register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0ADDR
rw
Toggle Fields.

M0ADDR

Bits 0-31: Memory 0 base address.

CH0M1ADDR

Channel 0 memory 1 base address register

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1ADDR
rw
Toggle Fields.

M1ADDR

Bits 0-31: Memory 1 base address.

CH0FCTL

Channel 0 FIFO control register

Offset: 0x24, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEEIE
rw 		FCNT
rw 		MDMEN
rw 		FCCV
rw
Toggle Fields.

FCCV

Bits 0-1: FIFO counter critical value.

MDMEN

Bit 2: Multi-data mode enable.

FCNT

Bits 3-5: FIFO counter.

FEEIE

Bit 7: Enable bit for FIFO error and exception interrupt.

CH1CTL

Channel 1 control register

Offset: 0x28, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERIEN
rw 		MBURST
rw 		PBURST
rw 		MBS
rw 		SBMEN
rw 		PRIO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAIF
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		TM
rw 		TFCS
rw 		FTFIE
rw 		HTFIE
rw 		TAEIE
rw 		SDEIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

SDEIE

Bit 1: Enable bit for single data mode exception interrupt.

TAEIE

Bit 2: Enable bit for tranfer access error interrupt.

HTFIE

Bit 3: Enable bit for half transfer finish interrupt.

FTFIE

Bit 4: Enable bit for full transfer finish interrupt.

TFCS

Bit 5: Transfer flow controller select.

TM

Bits 6-7: Transfer mode.

CMEN

Bit 8: Circulation mode enable.

PNAGA

Bit 9: Next address generation algorithm of peripheral.

MNAGA

Bit 10: Next address generation algorithm of memory.

PWIDTH

Bits 11-12: Transfer width of peripheral.

MWIDTH

Bits 13-14: Transfer width of memory.

PAIF

Bit 15: Peripheral address increment fixed.

PRIO

Bits 16-17: Priority level.

SBMEN

Bit 18: Switch-buffer mode enable.

MBS

Bit 19: Memory buffer select.

PBURST

Bits 21-22: Transfer burst type of peripheral.

MBURST

Bits 23-24: Transfer burst type of memory.

PERIEN

Bits 25-27: Peripheral enable.

CH1CNT

Channel 1 counter register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

CH1PADDR

Channel 1 peripheral base address register

Offset: 0x30, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH1M0ADDR

Channel 1 memory 0 base address register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0ADDR
rw
Toggle Fields.

M0ADDR

Bits 0-31: Memory 0 base address.

CH1M1ADDR

Channel 1 memory 1 base address register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1ADDR
rw
Toggle Fields.

M1ADDR

Bits 0-31: Memory 1 base address.

CH1FCTL

Channel 1 FIFO control register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEEIE
rw 		FCNT
rw 		MDMEN
rw 		FCCV
rw
Toggle Fields.

FCCV

Bits 0-1: FIFO counter critical value.

MDMEN

Bit 2: Multi-data mode enable.

FCNT

Bits 3-5: FIFO counter.

FEEIE

Bit 7: Enable bit for FIFO error and exception interrupt.

CH2CTL

Channel 2 control register

Offset: 0x40, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERIEN
rw 		MBURST
rw 		PBURST
rw 		MBS
rw 		SBMEN
rw 		PRIO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAIF
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		TM
rw 		TFCS
rw 		FTFIE
rw 		HTFIE
rw 		TAEIE
rw 		SDEIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

SDEIE

Bit 1: Enable bit for single data mode exception interrupt.

TAEIE

Bit 2: Enable bit for tranfer access error interrupt.

HTFIE

Bit 3: Enable bit for half transfer finish interrupt.

FTFIE

Bit 4: Enable bit for full transfer finish interrupt.

TFCS

Bit 5: Transfer flow controller select.

TM

Bits 6-7: Transfer mode.

CMEN

Bit 8: Circulation mode enable.

PNAGA

Bit 9: Next address generation algorithm of peripheral.

MNAGA

Bit 10: Next address generation algorithm of memory.

PWIDTH

Bits 11-12: Transfer width of peripheral.

MWIDTH

Bits 13-14: Transfer width of memory.

PAIF

Bit 15: Peripheral address increment fixed.

PRIO

Bits 16-17: Priority level.

SBMEN

Bit 18: Switch-buffer mode enable.

MBS

Bit 19: Memory buffer select.

PBURST

Bits 21-22: Transfer burst type of peripheral.

MBURST

Bits 23-24: Transfer burst type of memory.

PERIEN

Bits 25-27: Peripheral enable.

CH2CNT

Channel 2 counter register

Offset: 0x44, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

CH2PADDR

Channel 2 peripheral base address register

Offset: 0x48, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH2M0ADDR

Channel 2 memory 0 base address register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0ADDR
rw
Toggle Fields.

M0ADDR

Bits 0-31: Memory 0 base address.

CH2M1ADDR

Channel 2 memory 1 base address register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1ADDR
rw
Toggle Fields.

M1ADDR

Bits 0-31: Memory 1 base address.

CH2FCTL

Channel 2 FIFO control register

Offset: 0x54, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEEIE
rw 		FCNT
rw 		MDMEN
rw 		FCCV
rw
Toggle Fields.

FCCV

Bits 0-1: FIFO counter critical value.

MDMEN

Bit 2: Multi-data mode enable.

FCNT

Bits 3-5: FIFO counter.

FEEIE

Bit 7: Enable bit for FIFO error and exception interrupt.

CH3CTL

Channel 3 control register

Offset: 0x58, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERIEN
rw 		MBURST
rw 		PBURST
rw 		MBS
rw 		SBMEN
rw 		PRIO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAIF
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		TM
rw 		TFCS
rw 		FTFIE
rw 		HTFIE
rw 		TAEIE
rw 		SDEIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

SDEIE

Bit 1: Enable bit for single data mode exception interrupt.

TAEIE

Bit 2: Enable bit for tranfer access error interrupt.

HTFIE

Bit 3: Enable bit for half transfer finish interrupt.

FTFIE

Bit 4: Enable bit for full transfer finish interrupt.

TFCS

Bit 5: Transfer flow controller select.

TM

Bits 6-7: Transfer mode.

CMEN

Bit 8: Circulation mode enable.

PNAGA

Bit 9: Next address generation algorithm of peripheral.

MNAGA

Bit 10: Next address generation algorithm of memory.

PWIDTH

Bits 11-12: Transfer width of peripheral.

MWIDTH

Bits 13-14: Transfer width of memory.

PAIF

Bit 15: Peripheral address increment fixed.

PRIO

Bits 16-17: Priority level.

SBMEN

Bit 18: Switch-buffer mode enable.

MBS

Bit 19: Memory buffer select.

PBURST

Bits 21-22: Transfer burst type of peripheral.

MBURST

Bits 23-24: Transfer burst type of memory.

PERIEN

Bits 25-27: Peripheral enable.

CH3CNT

Channel 3 counter register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

CH3PADDR

Channel 3 peripheral base address register

Offset: 0x60, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH3M0ADDR

Channel 3 memory 0 base address register

Offset: 0x64, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0ADDR
rw
Toggle Fields.

M0ADDR

Bits 0-31: Memory 0 base address.

CH3M1ADDR

Channel 3 memory 1 base address register

Offset: 0x68, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1ADDR
rw
Toggle Fields.

M1ADDR

Bits 0-31: Memory 1 base address.

CH3FCTL

Channel 3 FIFO control register

Offset: 0x6C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEEIE
rw 		FCNT
rw 		MDMEN
rw 		FCCV
rw
Toggle Fields.

FCCV

Bits 0-1: FIFO counter critical value.

MDMEN

Bit 2: Multi-data mode enable.

FCNT

Bits 3-5: FIFO counter.

FEEIE

Bit 7: Enable bit for FIFO error and exception interrupt.

CH4CTL

Channel 4 control register

Offset: 0x70, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERIEN
rw 		MBURST
rw 		PBURST
rw 		MBS
rw 		SBMEN
rw 		PRIO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAIF
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		TM
rw 		TFCS
rw 		FTFIE
rw 		HTFIE
rw 		TAEIE
rw 		SDEIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

SDEIE

Bit 1: Enable bit for single data mode exception interrupt.

TAEIE

Bit 2: Enable bit for tranfer access error interrupt.

HTFIE

Bit 3: Enable bit for half transfer finish interrupt.

FTFIE

Bit 4: Enable bit for full transfer finish interrupt.

TFCS

Bit 5: Transfer flow controller select.

TM

Bits 6-7: Transfer mode.

CMEN

Bit 8: Circulation mode enable.

PNAGA

Bit 9: Next address generation algorithm of peripheral.

MNAGA

Bit 10: Next address generation algorithm of memory.

PWIDTH

Bits 11-12: Transfer width of peripheral.

MWIDTH

Bits 13-14: Transfer width of memory.

PAIF

Bit 15: Peripheral address increment fixed.

PRIO

Bits 16-17: Priority level.

SBMEN

Bit 18: Switch-buffer mode enable.

MBS

Bit 19: Memory buffer select.

PBURST

Bits 21-22: Transfer burst type of peripheral.

MBURST

Bits 23-24: Transfer burst type of memory.

PERIEN

Bits 25-27: Peripheral enable.

CH4CNT

Channel 4 counter register

Offset: 0x74, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

CH4PADDR

Channel 4 peripheral base address register

Offset: 0x78, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH4M0ADDR

Channel 4 memory 0 base address register

Offset: 0x7C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0ADDR
rw
Toggle Fields.

M0ADDR

Bits 0-31: Memory 0 base address.

CH4M1ADDR

Channel 4 memory 1 base address register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1ADDR
rw
Toggle Fields.

M1ADDR

Bits 0-31: Memory 1 base address.

CH4FCTL

Channel 4 FIFO control register

Offset: 0x84, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEEIE
rw 		FCNT
rw 		MDMEN
rw 		FCCV
rw
Toggle Fields.

FCCV

Bits 0-1: FIFO counter critical value.

MDMEN

Bit 2: Multi-data mode enable.

FCNT

Bits 3-5: FIFO counter.

FEEIE

Bit 7: Enable bit for FIFO error and exception interrupt.

CH5CTL

Channel 5 control register

Offset: 0x88, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERIEN
rw 		MBURST
rw 		PBURST
rw 		MBS
rw 		SBMEN
rw 		PRIO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAIF
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		TM
rw 		TFCS
rw 		FTFIE
rw 		HTFIE
rw 		TAEIE
rw 		SDEIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

SDEIE

Bit 1: Enable bit for single data mode exception interrupt.

TAEIE

Bit 2: Enable bit for tranfer access error interrupt.

HTFIE

Bit 3: Enable bit for half transfer finish interrupt.

FTFIE

Bit 4: Enable bit for full transfer finish interrupt.

TFCS

Bit 5: Transfer flow controller select.

TM

Bits 6-7: Transfer mode.

CMEN

Bit 8: Circulation mode enable.

PNAGA

Bit 9: Next address generation algorithm of peripheral.

MNAGA

Bit 10: Next address generation algorithm of memory.

PWIDTH

Bits 11-12: Transfer width of peripheral.

MWIDTH

Bits 13-14: Transfer width of memory.

PAIF

Bit 15: Peripheral address increment fixed.

PRIO

Bits 16-17: Priority level.

SBMEN

Bit 18: Switch-buffer mode enable.

MBS

Bit 19: Memory buffer select.

PBURST

Bits 21-22: Transfer burst type of peripheral.

MBURST

Bits 23-24: Transfer burst type of memory.

PERIEN

Bits 25-27: Peripheral enable.

CH5CNT

Channel 5 counter register

Offset: 0x8C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

CH5PADDR

Channel 5 peripheral base address register

Offset: 0x90, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH5M0ADDR

Channel 5 memory 0 base address register

Offset: 0x94, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0ADDR
rw
Toggle Fields.

M0ADDR

Bits 0-31: Memory 0 base address.

CH5M1ADDR

Channel 5 memory 1 base address register

Offset: 0x98, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1ADDR
rw
Toggle Fields.

M1ADDR

Bits 0-31: Memory 1 base address.

CH5FCTL

Channel 5 FIFO control register

Offset: 0x9C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEEIE
rw 		FCNT
rw 		MDMEN
rw 		FCCV
rw
Toggle Fields.

FCCV

Bits 0-1: FIFO counter critical value.

MDMEN

Bit 2: Multi-data mode enable.

FCNT

Bits 3-5: FIFO counter.

FEEIE

Bit 7: Enable bit for FIFO error and exception interrupt.

CH6CTL

Channel 6 control register

Offset: 0xA0, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERIEN
rw 		MBURST
rw 		PBURST
rw 		MBS
rw 		SBMEN
rw 		PRIO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAIF
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		TM
rw 		TFCS
rw 		FTFIE
rw 		HTFIE
rw 		TAEIE
rw 		SDEIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

SDEIE

Bit 1: Enable bit for single data mode exception interrupt.

TAEIE

Bit 2: Enable bit for tranfer access error interrupt.

HTFIE

Bit 3: Enable bit for half transfer finish interrupt.

FTFIE

Bit 4: Enable bit for full transfer finish interrupt.

TFCS

Bit 5: Transfer flow controller select.

TM

Bits 6-7: Transfer mode.

CMEN

Bit 8: Circulation mode enable.

PNAGA

Bit 9: Next address generation algorithm of peripheral.

MNAGA

Bit 10: Next address generation algorithm of memory.

PWIDTH

Bits 11-12: Transfer width of peripheral.

MWIDTH

Bits 13-14: Transfer width of memory.

PAIF

Bit 15: Peripheral address increment fixed.

PRIO

Bits 16-17: Priority level.

SBMEN

Bit 18: Switch-buffer mode enable.

MBS

Bit 19: Memory buffer select.

PBURST

Bits 21-22: Transfer burst type of peripheral.

MBURST

Bits 23-24: Transfer burst type of memory.

PERIEN

Bits 25-27: Peripheral enable.

CH6CNT

Channel 6 counter register

Offset: 0xA4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

CH6PADDR

Channel 6 peripheral base address register

Offset: 0xA8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH6M0ADDR

Channel 6 memory 0 base address register

Offset: 0xAC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0ADDR
rw
Toggle Fields.

M0ADDR

Bits 0-31: Memory 0 base address.

CH6M1ADDR

Channel 6 memory 1 base address register

Offset: 0xB0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1ADDR
rw
Toggle Fields.

M1ADDR

Bits 0-31: Memory 1 base address.

CH6FCTL

Channel 6 FIFO control register

Offset: 0xB4, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEEIE
rw 		FCNT
rw 		MDMEN
rw 		FCCV
rw
Toggle Fields.

FCCV

Bits 0-1: FIFO counter critical value.

MDMEN

Bit 2: Multi-data mode enable.

FCNT

Bits 3-5: FIFO counter.

FEEIE

Bit 7: Enable bit for FIFO error and exception interrupt.

CH7CTL

Channel 7 control register

Offset: 0xB8, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERIEN
rw 		MBURST
rw 		PBURST
rw 		MBS
rw 		SBMEN
rw 		PRIO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAIF
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		TM
rw 		TFCS
rw 		FTFIE
rw 		HTFIE
rw 		TAEIE
rw 		SDEIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

SDEIE

Bit 1: Enable bit for single data mode exception interrupt.

TAEIE

Bit 2: Enable bit for tranfer access error interrupt.

HTFIE

Bit 3: Enable bit for half transfer finish interrupt.

FTFIE

Bit 4: Enable bit for full transfer finish interrupt.

TFCS

Bit 5: Transfer flow controller select.

TM

Bits 6-7: Transfer mode.

CMEN

Bit 8: Circulation mode enable.

PNAGA

Bit 9: Next address generation algorithm of peripheral.

MNAGA

Bit 10: Next address generation algorithm of memory.

PWIDTH

Bits 11-12: Transfer width of peripheral.

MWIDTH

Bits 13-14: Transfer width of memory.

PAIF

Bit 15: Peripheral address increment fixed.

PRIO

Bits 16-17: Priority level.

SBMEN

Bit 18: Switch-buffer mode enable.

MBS

Bit 19: Memory buffer select.

PBURST

Bits 21-22: Transfer burst type of peripheral.

MBURST

Bits 23-24: Transfer burst type of memory.

PERIEN

Bits 25-27: Peripheral enable.

CH7CNT

Channel 7 counter register

Offset: 0xBC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

CH7PADDR

Channel 7 peripheral base address register

Offset: 0xC0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH7M0ADDR

Channel 7 memory 0 base address register

Offset: 0xC4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0ADDR
rw
Toggle Fields.

M0ADDR

Bits 0-31: Memory 0 base address.

CH7M1ADDR

Channel 7 memory 1 base address register

Offset: 0xC8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1ADDR
rw
Toggle Fields.

M1ADDR

Bits 0-31: Memory 1 base address.

CH7FCTL

Channel 7 FIFO control register

Offset: 0xCC, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEEIE
rw 		FCNT
rw 		MDMEN
rw 		FCCV
rw
Toggle Fields.

FCCV

Bits 0-1: FIFO counter critical value.

MDMEN

Bit 2: Multi-data mode enable.

FCNT

Bits 3-5: FIFO counter.

FEEIE

Bit 7: Enable bit for FIFO error and exception interrupt.

DMA1

0x40026400: DMA controller

40/296 fields covered. Toggle Registers.

INTF0

Interrupt flag register 0

Offset: 0x0, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTFIF3
r 		HTFIF3
r 		TAEIF3
r 		SDEIF3
r 		FEEIF3
r 		FTFIF2
r 		HTFIF2
r 		TAEIF2
r 		SDEIF2
r 		FEEIF2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTFIF1
r 		HTFIF1
r 		TAEIF1
r 		SDEIF1
r 		FEEIF1
r 		FTFIF0
r 		HTFIF0
r 		TAEIF0
r 		SDEIF0
r 		FEEIF0
r
Toggle Fields.

FEEIF0

Bit 0: FIFO error and exception of channel 0.

SDEIF0

Bit 2: Single data mode exception of channel 0.

TAEIF0

Bit 3: Transfer access error flag of channel 0.

HTFIF0

Bit 4: Half transfer finish flag of channel 0.

FTFIF0

Bit 5: Full Transfer finish flag of channel 0.

FEEIF1

Bit 6: FIFO error and exception of channel 1.

SDEIF1

Bit 8: Single data mode exception of channel 1.

TAEIF1

Bit 9: Transfer access error flag of channel 1.

HTFIF1

Bit 10: Half transfer finish flag of channel 1.

FTFIF1

Bit 11: Full Transfer finish flag of channel 1.

FEEIF2

Bit 16: FIFO error and exception of channel 2.

SDEIF2

Bit 18: Single data mode exception of channel 2.

TAEIF2

Bit 19: Transfer access error flag of channel 2.

HTFIF2

Bit 20: Half transfer finish flag of channel 2.

FTFIF2

Bit 21: Full Transfer finish flag of channel 2.

FEEIF3

Bit 22: FIFO error and exception of channel 3.

SDEIF3

Bit 24: Single data mode exception of channel 3.

TAEIF3

Bit 25: Transfer access error flag of channel 3.

HTFIF3

Bit 26: Half transfer finish flag of channel 3.

FTFIF3

Bit 27: Full Transfer finish flag of channel 3.

INTF1

Interrupt flag register 1

Offset: 0x4, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTFIF7
r 		HTFIF7
r 		TAEIF7
r 		SDEIF7
r 		FEEIF7
r 		FTFIF6
r 		HTFIF6
r 		TAEIF6
r 		SDEIF6
r 		FEEIF6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTFIF5
r 		HTFIF5
r 		TAEIF5
r 		SDEIF5
r 		FEEIF5
r 		FTFIF4
r 		HTFIF4
r 		TAEIF4
r 		SDEIF4
r 		FEEIF4
r
Toggle Fields.

FEEIF4

Bit 0: FIFO error and exception of channel 4.

SDEIF4

Bit 2: Single data mode exception of channel 4.

TAEIF4

Bit 3: Transfer access error flag of channel 4.

HTFIF4

Bit 4: Half transfer finish flag of channel 4.

FTFIF4

Bit 5: Full Transfer finish flag of channel 4.

FEEIF5

Bit 6: FIFO error and exception of channel 5.

SDEIF5

Bit 8: Single data mode exception of channel 5.

TAEIF5

Bit 9: Transfer access error flag of channel 5.

HTFIF5

Bit 10: Half transfer finish flag of channel 5.

FTFIF5

Bit 11: Full Transfer finish flag of channel 5.

FEEIF6

Bit 16: FIFO error and exception of channel 6.

SDEIF6

Bit 18: Single data mode exception of channel 6.

TAEIF6

Bit 19: Transfer access error flag of channel 6.

HTFIF6

Bit 20: Half transfer finish flag of channel 6.

FTFIF6

Bit 21: Full Transfer finish flag of channel 6.

FEEIF7

Bit 22: FIFO error and exception of channel 7.

SDEIF7

Bit 24: Single data mode exception of channel 7.

TAEIF7

Bit 25: Transfer access error flag of channel 7.

HTFIF7

Bit 26: Half transfer finish flag of channel 7.

FTFIF7

Bit 27: Full Transfer finish flag of channel 7.

INTC0

Interrupt flag clear register 0

Offset: 0x8, reset: 0x00000000, access: write-only

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTFIFC3
w 		HTFIFC3
w 		TAEIFC3
w 		SDEIFC3
w 		FEEIFC3
w 		FTFIFC2
w 		HTFIFC2
w 		TAEIFC2
w 		SDEIFC2
w 		FEEIFC2
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTFIFC1
w 		HTFIFC1
w 		TAEIFC1
w 		SDEIFC1
w 		FEEIFC1
w 		FTFIFC0
w 		HTFIFC0
w 		TAEIFC0
w 		SDEIFC0
w 		FEEIFC0
w
Toggle Fields.

FEEIFC0

Bit 0: Clear bit for FIFO error and exception of channel 0.

SDEIFC0

Bit 2: Clear bit for single data mode exception of channel 0.

TAEIFC0

Bit 3: Clear bit for transfer access error flag of channel 0.

HTFIFC0

Bit 4: Clear bit for half transfer finish flag of channel 0.

FTFIFC0

Bit 5: Clear bit for Full transfer finish flag of channel 0.

FEEIFC1

Bit 6: Clear bit for FIFO error and exception of channel 1.

SDEIFC1

Bit 8: Clear bit for single data mode exception of channel 1.

TAEIFC1

Bit 9: Clear bit for transfer access error flag of channel 1.

HTFIFC1

Bit 10: Clear bit for half transfer finish flag of channel 1.

FTFIFC1

Bit 11: Clear bit for Full transfer finish flag of channel 1.

FEEIFC2

Bit 16: Clear bit for FIFO error and exception of channel 2.

SDEIFC2

Bit 18: Clear bit for single data mode exception of channel 2.

TAEIFC2

Bit 19: Clear bit for transfer access error flag of channel 2.

HTFIFC2

Bit 20: Clear bit for half transfer finish flag of channel 2.

FTFIFC2

Bit 21: Clear bit for Full transfer finish flag of channel 2.

FEEIFC3

Bit 22: Clear bit for FIFO error and exception of channel 3.

SDEIFC3

Bit 24: Clear bit for single data mode exception of channel 3.

TAEIFC3

Bit 25: Clear bit for transfer access error flag of channel 3.

HTFIFC3

Bit 26: Clear bit for half transfer finish flag of channel 3.

FTFIFC3

Bit 27: Clear bit for Full transfer finish flag of channel 3.

INTC1

Interrupt flag clear register 1

Offset: 0xC, reset: 0x00000000, access: write-only

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTFIFC7
w 		HTFIFC7
w 		TAEIFC7
w 		SDEIFC7
w 		FEEIFC7
w 		FTFIFC6
w 		HTFIFC6
w 		TAEIFC6
w 		SDEIFC6
w 		FEEIFC6
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTFIFC5
w 		HTFIFC5
w 		TAEIFC5
w 		SDEIFC5
w 		FEEIFC5
w 		FTFIFC4
w 		HTFIFC4
w 		TAEIFC4
w 		SDEIFC4
w 		FEEIFC4
w
Toggle Fields.

FEEIFC4

Bit 0: Clear bit for FIFO error and exception of channel 4.

SDEIFC4

Bit 2: Clear bit for single data mode exception of channel 4.

TAEIFC4

Bit 3: Clear bit for transfer access error flag of channel 4.

HTFIFC4

Bit 4: Clear bit for half transfer finish flag of channel 4.

FTFIFC4

Bit 5: Clear bit for Full transfer finish flag of channel 4.

FEEIFC5

Bit 6: Clear bit for FIFO error and exception of channel 5.

SDEIFC5

Bit 8: Clear bit for single data mode exception of channel 5.

TAEIFC5

Bit 9: Clear bit for transfer access error flag of channel 5.

HTFIFC5

Bit 10: Clear bit for half transfer finish flag of channel 5.

FTFIFC5

Bit 11: Clear bit for Full transfer finish flag of channel 5.

FEEIFC6

Bit 16: Clear bit for FIFO error and exception of channel 6.

SDEIFC6

Bit 18: Clear bit for single data mode exception of channel 6.

TAEIFC6

Bit 19: Clear bit for transfer access error flag of channel 6.

HTFIFC6

Bit 20: Clear bit for half transfer finish flag of channel 6.

FTFIFC6

Bit 21: Clear bit for Full transfer finish flag of channel 6.

FEEIFC7

Bit 22: Clear bit for FIFO error and exception of channel 7.

SDEIFC7

Bit 24: Clear bit for single data mode exception of channel 7.

TAEIFC7

Bit 25: Clear bit for transfer access error flag of channel 7.

HTFIFC7

Bit 26: Clear bit for half transfer finish flag of channel 7.

FTFIFC7

Bit 27: Clear bit for Full transfer finish flag of channel 7.

CH0CTL

Channel 0 control register

Offset: 0x10, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERIEN
rw 		MBURST
rw 		PBURST
rw 		MBS
rw 		SBMEN
rw 		PRIO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAIF
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		TM
rw 		TFCS
rw 		FTFIE
rw 		HTFIE
rw 		TAEIE
rw 		SDEIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

SDEIE

Bit 1: Enable bit for single data mode exception interrupt.

TAEIE

Bit 2: Enable bit for tranfer access error interrupt.

HTFIE

Bit 3: Enable bit for half transfer finish interrupt.

FTFIE

Bit 4: Enable bit for full transfer finish interrupt.

TFCS

Bit 5: Transfer flow controller select.

TM

Bits 6-7: Transfer mode.

CMEN

Bit 8: Circulation mode enable.

PNAGA

Bit 9: Next address generation algorithm of peripheral.

MNAGA

Bit 10: Next address generation algorithm of memory.

PWIDTH

Bits 11-12: Transfer width of peripheral.

MWIDTH

Bits 13-14: Transfer width of memory.

PAIF

Bit 15: Peripheral address increment fixed.

PRIO

Bits 16-17: Priority level.

SBMEN

Bit 18: Switch-buffer mode enable.

MBS

Bit 19: Memory buffer select.

PBURST

Bits 21-22: Transfer burst type of peripheral.

MBURST

Bits 23-24: Transfer burst type of memory.

PERIEN

Bits 25-27: Peripheral enable.

CH0CNT

Channel 0 counter register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

CH0PADDR

Channel 0 peripheral base address register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH0M0ADDR

Channel 0 memory 0 base address register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0ADDR
rw
Toggle Fields.

M0ADDR

Bits 0-31: Memory 0 base address.

CH0M1ADDR

Channel 0 memory 1 base address register

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1ADDR
rw
Toggle Fields.

M1ADDR

Bits 0-31: Memory 1 base address.

CH0FCTL

Channel 0 FIFO control register

Offset: 0x24, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEEIE
rw 		FCNT
rw 		MDMEN
rw 		FCCV
rw
Toggle Fields.

FCCV

Bits 0-1: FIFO counter critical value.

MDMEN

Bit 2: Multi-data mode enable.

FCNT

Bits 3-5: FIFO counter.

FEEIE

Bit 7: Enable bit for FIFO error and exception interrupt.

CH1CTL

Channel 1 control register

Offset: 0x28, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERIEN
rw 		MBURST
rw 		PBURST
rw 		MBS
rw 		SBMEN
rw 		PRIO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAIF
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		TM
rw 		TFCS
rw 		FTFIE
rw 		HTFIE
rw 		TAEIE
rw 		SDEIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

SDEIE

Bit 1: Enable bit for single data mode exception interrupt.

TAEIE

Bit 2: Enable bit for tranfer access error interrupt.

HTFIE

Bit 3: Enable bit for half transfer finish interrupt.

FTFIE

Bit 4: Enable bit for full transfer finish interrupt.

TFCS

Bit 5: Transfer flow controller select.

TM

Bits 6-7: Transfer mode.

CMEN

Bit 8: Circulation mode enable.

PNAGA

Bit 9: Next address generation algorithm of peripheral.

MNAGA

Bit 10: Next address generation algorithm of memory.

PWIDTH

Bits 11-12: Transfer width of peripheral.

MWIDTH

Bits 13-14: Transfer width of memory.

PAIF

Bit 15: Peripheral address increment fixed.

PRIO

Bits 16-17: Priority level.

SBMEN

Bit 18: Switch-buffer mode enable.

MBS

Bit 19: Memory buffer select.

PBURST

Bits 21-22: Transfer burst type of peripheral.

MBURST

Bits 23-24: Transfer burst type of memory.

PERIEN

Bits 25-27: Peripheral enable.

CH1CNT

Channel 1 counter register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

CH1PADDR

Channel 1 peripheral base address register

Offset: 0x30, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH1M0ADDR

Channel 1 memory 0 base address register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0ADDR
rw
Toggle Fields.

M0ADDR

Bits 0-31: Memory 0 base address.

CH1M1ADDR

Channel 1 memory 1 base address register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1ADDR
rw
Toggle Fields.

M1ADDR

Bits 0-31: Memory 1 base address.

CH1FCTL

Channel 1 FIFO control register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEEIE
rw 		FCNT
rw 		MDMEN
rw 		FCCV
rw
Toggle Fields.

FCCV

Bits 0-1: FIFO counter critical value.

MDMEN

Bit 2: Multi-data mode enable.

FCNT

Bits 3-5: FIFO counter.

FEEIE

Bit 7: Enable bit for FIFO error and exception interrupt.

CH2CTL

Channel 2 control register

Offset: 0x40, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERIEN
rw 		MBURST
rw 		PBURST
rw 		MBS
rw 		SBMEN
rw 		PRIO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAIF
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		TM
rw 		TFCS
rw 		FTFIE
rw 		HTFIE
rw 		TAEIE
rw 		SDEIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

SDEIE

Bit 1: Enable bit for single data mode exception interrupt.

TAEIE

Bit 2: Enable bit for tranfer access error interrupt.

HTFIE

Bit 3: Enable bit for half transfer finish interrupt.

FTFIE

Bit 4: Enable bit for full transfer finish interrupt.

TFCS

Bit 5: Transfer flow controller select.

TM

Bits 6-7: Transfer mode.

CMEN

Bit 8: Circulation mode enable.

PNAGA

Bit 9: Next address generation algorithm of peripheral.

MNAGA

Bit 10: Next address generation algorithm of memory.

PWIDTH

Bits 11-12: Transfer width of peripheral.

MWIDTH

Bits 13-14: Transfer width of memory.

PAIF

Bit 15: Peripheral address increment fixed.

PRIO

Bits 16-17: Priority level.

SBMEN

Bit 18: Switch-buffer mode enable.

MBS

Bit 19: Memory buffer select.

PBURST

Bits 21-22: Transfer burst type of peripheral.

MBURST

Bits 23-24: Transfer burst type of memory.

PERIEN

Bits 25-27: Peripheral enable.

CH2CNT

Channel 2 counter register

Offset: 0x44, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

CH2PADDR

Channel 2 peripheral base address register

Offset: 0x48, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH2M0ADDR

Channel 2 memory 0 base address register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0ADDR
rw
Toggle Fields.

M0ADDR

Bits 0-31: Memory 0 base address.

CH2M1ADDR

Channel 2 memory 1 base address register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1ADDR
rw
Toggle Fields.

M1ADDR

Bits 0-31: Memory 1 base address.

CH2FCTL

Channel 2 FIFO control register

Offset: 0x54, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEEIE
rw 		FCNT
rw 		MDMEN
rw 		FCCV
rw
Toggle Fields.

FCCV

Bits 0-1: FIFO counter critical value.

MDMEN

Bit 2: Multi-data mode enable.

FCNT

Bits 3-5: FIFO counter.

FEEIE

Bit 7: Enable bit for FIFO error and exception interrupt.

CH3CTL

Channel 3 control register

Offset: 0x58, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERIEN
rw 		MBURST
rw 		PBURST
rw 		MBS
rw 		SBMEN
rw 		PRIO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAIF
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		TM
rw 		TFCS
rw 		FTFIE
rw 		HTFIE
rw 		TAEIE
rw 		SDEIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

SDEIE

Bit 1: Enable bit for single data mode exception interrupt.

TAEIE

Bit 2: Enable bit for tranfer access error interrupt.

HTFIE

Bit 3: Enable bit for half transfer finish interrupt.

FTFIE

Bit 4: Enable bit for full transfer finish interrupt.

TFCS

Bit 5: Transfer flow controller select.

TM

Bits 6-7: Transfer mode.

CMEN

Bit 8: Circulation mode enable.

PNAGA

Bit 9: Next address generation algorithm of peripheral.

MNAGA

Bit 10: Next address generation algorithm of memory.

PWIDTH

Bits 11-12: Transfer width of peripheral.

MWIDTH

Bits 13-14: Transfer width of memory.

PAIF

Bit 15: Peripheral address increment fixed.

PRIO

Bits 16-17: Priority level.

SBMEN

Bit 18: Switch-buffer mode enable.

MBS

Bit 19: Memory buffer select.

PBURST

Bits 21-22: Transfer burst type of peripheral.

MBURST

Bits 23-24: Transfer burst type of memory.

PERIEN

Bits 25-27: Peripheral enable.

CH3CNT

Channel 3 counter register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

CH3PADDR

Channel 3 peripheral base address register

Offset: 0x60, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH3M0ADDR

Channel 3 memory 0 base address register

Offset: 0x64, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0ADDR
rw
Toggle Fields.

M0ADDR

Bits 0-31: Memory 0 base address.

CH3M1ADDR

Channel 3 memory 1 base address register

Offset: 0x68, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1ADDR
rw
Toggle Fields.

M1ADDR

Bits 0-31: Memory 1 base address.

CH3FCTL

Channel 3 FIFO control register

Offset: 0x6C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEEIE
rw 		FCNT
rw 		MDMEN
rw 		FCCV
rw
Toggle Fields.

FCCV

Bits 0-1: FIFO counter critical value.

MDMEN

Bit 2: Multi-data mode enable.

FCNT

Bits 3-5: FIFO counter.

FEEIE

Bit 7: Enable bit for FIFO error and exception interrupt.

CH4CTL

Channel 4 control register

Offset: 0x70, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERIEN
rw 		MBURST
rw 		PBURST
rw 		MBS
rw 		SBMEN
rw 		PRIO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAIF
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		TM
rw 		TFCS
rw 		FTFIE
rw 		HTFIE
rw 		TAEIE
rw 		SDEIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

SDEIE

Bit 1: Enable bit for single data mode exception interrupt.

TAEIE

Bit 2: Enable bit for tranfer access error interrupt.

HTFIE

Bit 3: Enable bit for half transfer finish interrupt.

FTFIE

Bit 4: Enable bit for full transfer finish interrupt.

TFCS

Bit 5: Transfer flow controller select.

TM

Bits 6-7: Transfer mode.

CMEN

Bit 8: Circulation mode enable.

PNAGA

Bit 9: Next address generation algorithm of peripheral.

MNAGA

Bit 10: Next address generation algorithm of memory.

PWIDTH

Bits 11-12: Transfer width of peripheral.

MWIDTH

Bits 13-14: Transfer width of memory.

PAIF

Bit 15: Peripheral address increment fixed.

PRIO

Bits 16-17: Priority level.

SBMEN

Bit 18: Switch-buffer mode enable.

MBS

Bit 19: Memory buffer select.

PBURST

Bits 21-22: Transfer burst type of peripheral.

MBURST

Bits 23-24: Transfer burst type of memory.

PERIEN

Bits 25-27: Peripheral enable.

CH4CNT

Channel 4 counter register

Offset: 0x74, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

CH4PADDR

Channel 4 peripheral base address register

Offset: 0x78, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH4M0ADDR

Channel 4 memory 0 base address register

Offset: 0x7C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0ADDR
rw
Toggle Fields.

M0ADDR

Bits 0-31: Memory 0 base address.

CH4M1ADDR

Channel 4 memory 1 base address register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1ADDR
rw
Toggle Fields.

M1ADDR

Bits 0-31: Memory 1 base address.

CH4FCTL

Channel 4 FIFO control register

Offset: 0x84, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEEIE
rw 		FCNT
rw 		MDMEN
rw 		FCCV
rw
Toggle Fields.

FCCV

Bits 0-1: FIFO counter critical value.

MDMEN

Bit 2: Multi-data mode enable.

FCNT

Bits 3-5: FIFO counter.

FEEIE

Bit 7: Enable bit for FIFO error and exception interrupt.

CH5CTL

Channel 5 control register

Offset: 0x88, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERIEN
rw 		MBURST
rw 		PBURST
rw 		MBS
rw 		SBMEN
rw 		PRIO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAIF
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		TM
rw 		TFCS
rw 		FTFIE
rw 		HTFIE
rw 		TAEIE
rw 		SDEIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

SDEIE

Bit 1: Enable bit for single data mode exception interrupt.

TAEIE

Bit 2: Enable bit for tranfer access error interrupt.

HTFIE

Bit 3: Enable bit for half transfer finish interrupt.

FTFIE

Bit 4: Enable bit for full transfer finish interrupt.

TFCS

Bit 5: Transfer flow controller select.

TM

Bits 6-7: Transfer mode.

CMEN

Bit 8: Circulation mode enable.

PNAGA

Bit 9: Next address generation algorithm of peripheral.

MNAGA

Bit 10: Next address generation algorithm of memory.

PWIDTH

Bits 11-12: Transfer width of peripheral.

MWIDTH

Bits 13-14: Transfer width of memory.

PAIF

Bit 15: Peripheral address increment fixed.

PRIO

Bits 16-17: Priority level.

SBMEN

Bit 18: Switch-buffer mode enable.

MBS

Bit 19: Memory buffer select.

PBURST

Bits 21-22: Transfer burst type of peripheral.

MBURST

Bits 23-24: Transfer burst type of memory.

PERIEN

Bits 25-27: Peripheral enable.

CH5CNT

Channel 5 counter register

Offset: 0x8C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

CH5PADDR

Channel 5 peripheral base address register

Offset: 0x90, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH5M0ADDR

Channel 5 memory 0 base address register

Offset: 0x94, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0ADDR
rw
Toggle Fields.

M0ADDR

Bits 0-31: Memory 0 base address.

CH5M1ADDR

Channel 5 memory 1 base address register

Offset: 0x98, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1ADDR
rw
Toggle Fields.

M1ADDR

Bits 0-31: Memory 1 base address.

CH5FCTL

Channel 5 FIFO control register

Offset: 0x9C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEEIE
rw 		FCNT
rw 		MDMEN
rw 		FCCV
rw
Toggle Fields.

FCCV

Bits 0-1: FIFO counter critical value.

MDMEN

Bit 2: Multi-data mode enable.

FCNT

Bits 3-5: FIFO counter.

FEEIE

Bit 7: Enable bit for FIFO error and exception interrupt.

CH6CTL

Channel 6 control register

Offset: 0xA0, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERIEN
rw 		MBURST
rw 		PBURST
rw 		MBS
rw 		SBMEN
rw 		PRIO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAIF
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		TM
rw 		TFCS
rw 		FTFIE
rw 		HTFIE
rw 		TAEIE
rw 		SDEIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

SDEIE

Bit 1: Enable bit for single data mode exception interrupt.

TAEIE

Bit 2: Enable bit for tranfer access error interrupt.

HTFIE

Bit 3: Enable bit for half transfer finish interrupt.

FTFIE

Bit 4: Enable bit for full transfer finish interrupt.

TFCS

Bit 5: Transfer flow controller select.

TM

Bits 6-7: Transfer mode.

CMEN

Bit 8: Circulation mode enable.

PNAGA

Bit 9: Next address generation algorithm of peripheral.

MNAGA

Bit 10: Next address generation algorithm of memory.

PWIDTH

Bits 11-12: Transfer width of peripheral.

MWIDTH

Bits 13-14: Transfer width of memory.

PAIF

Bit 15: Peripheral address increment fixed.

PRIO

Bits 16-17: Priority level.

SBMEN

Bit 18: Switch-buffer mode enable.

MBS

Bit 19: Memory buffer select.

PBURST

Bits 21-22: Transfer burst type of peripheral.

MBURST

Bits 23-24: Transfer burst type of memory.

PERIEN

Bits 25-27: Peripheral enable.

CH6CNT

Channel 6 counter register

Offset: 0xA4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

CH6PADDR

Channel 6 peripheral base address register

Offset: 0xA8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH6M0ADDR

Channel 6 memory 0 base address register

Offset: 0xAC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0ADDR
rw
Toggle Fields.

M0ADDR

Bits 0-31: Memory 0 base address.

CH6M1ADDR

Channel 6 memory 1 base address register

Offset: 0xB0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1ADDR
rw
Toggle Fields.

M1ADDR

Bits 0-31: Memory 1 base address.

CH6FCTL

Channel 6 FIFO control register

Offset: 0xB4, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEEIE
rw 		FCNT
rw 		MDMEN
rw 		FCCV
rw
Toggle Fields.

FCCV

Bits 0-1: FIFO counter critical value.

MDMEN

Bit 2: Multi-data mode enable.

FCNT

Bits 3-5: FIFO counter.

FEEIE

Bit 7: Enable bit for FIFO error and exception interrupt.

CH7CTL

Channel 7 control register

Offset: 0xB8, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERIEN
rw 		MBURST
rw 		PBURST
rw 		MBS
rw 		SBMEN
rw 		PRIO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAIF
rw 		MWIDTH
rw 		PWIDTH
rw 		MNAGA
rw 		PNAGA
rw 		CMEN
rw 		TM
rw 		TFCS
rw 		FTFIE
rw 		HTFIE
rw 		TAEIE
rw 		SDEIE
rw 		CHEN
rw
Toggle Fields.

CHEN

Bit 0: Channel enable.

SDEIE

Bit 1: Enable bit for single data mode exception interrupt.

TAEIE

Bit 2: Enable bit for tranfer access error interrupt.

HTFIE

Bit 3: Enable bit for half transfer finish interrupt.

FTFIE

Bit 4: Enable bit for full transfer finish interrupt.

TFCS

Bit 5: Transfer flow controller select.

TM

Bits 6-7: Transfer mode.

CMEN

Bit 8: Circulation mode enable.

PNAGA

Bit 9: Next address generation algorithm of peripheral.

MNAGA

Bit 10: Next address generation algorithm of memory.

PWIDTH

Bits 11-12: Transfer width of peripheral.

MWIDTH

Bits 13-14: Transfer width of memory.

PAIF

Bit 15: Peripheral address increment fixed.

PRIO

Bits 16-17: Priority level.

SBMEN

Bit 18: Switch-buffer mode enable.

MBS

Bit 19: Memory buffer select.

PBURST

Bits 21-22: Transfer burst type of peripheral.

MBURST

Bits 23-24: Transfer burst type of memory.

PERIEN

Bits 25-27: Peripheral enable.

CH7CNT

Channel 7 counter register

Offset: 0xBC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Transfer counter.

CH7PADDR

Channel 7 peripheral base address register

Offset: 0xC0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PADDR
rw
Toggle Fields.

PADDR

Bits 0-31: Peripheral base address.

CH7M0ADDR

Channel 7 memory 0 base address register

Offset: 0xC4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0ADDR
rw
Toggle Fields.

M0ADDR

Bits 0-31: Memory 0 base address.

CH7M1ADDR

Channel 7 memory 1 base address register

Offset: 0xC8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1ADDR
rw
Toggle Fields.

M1ADDR

Bits 0-31: Memory 1 base address.

CH7FCTL

Channel 7 FIFO control register

Offset: 0xCC, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEEIE
rw 		FCNT
rw 		MDMEN
rw 		FCCV
rw
Toggle Fields.

FCCV

Bits 0-1: FIFO counter critical value.

MDMEN

Bit 2: Multi-data mode enable.

FCNT

Bits 3-5: FIFO counter.

FEEIE

Bit 7: Enable bit for FIFO error and exception interrupt.

ENET_DMA

0x40029000: Ethernet: DMA controller operation

12/71 fields covered. Toggle Registers.

DMA_BCTL

Ethernet DMA bus control register

Offset: 0x0, reset: 0x00020101, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MB
rw 		AA
rw 		FPBL
rw 		UIP
rw 		RXDP
rw 		FB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTPR
rw 		PGBL
rw 		DFM
rw 		DPSL
rw 		DAB
rw 		SWR
rw
Toggle Fields.

SWR

Bit 0: Software reset.

DAB

Bit 1: DMA Arbitration.

DPSL

Bits 2-6: Descriptor skip length.

DFM

Bit 7: Descriptor format mode.

PGBL

Bits 8-13: Programmable burst length.

RTPR

Bits 14-15: RxDMA and TxDMA transfer priority ratio.

FB

Bit 16: Fixed burst.

RXDP

Bits 17-22: Rx DMA PGBL.

UIP

Bit 23: Use independent PGBL.

FPBL

Bit 24: Four times PGBL mode.

AA

Bit 25: Address-aligned .

MB

Bit 26: Mixed burst.

DMA_TPEN

Ethernet DMA transmit poll enable register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TPE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPE
rw
Toggle Fields.

TPE

Bits 0-31: Transmit poll enable.

DMA_RPEN

Ethernet DMA receive poll enable register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPE
rw
Toggle Fields.

RPE

Bits 0-31: Receive poll enable.

DMA_RDTADDR

Ethernet DMA receive descriptor table address register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRT
rw
Toggle Fields.

SRT

Bits 0-31: Start address of receive table.

DMA_TDTADDR

Ethernet DMA transmit descriptor table address register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STT
rw
Toggle Fields.

STT

Bits 0-31: Start address of transmit table.

DMA_STAT

Ethernet DMA status register

Offset: 0x14, reset: 0x00000000, access: Unspecified

6/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TST
r 		WUM
r 		MSC
r 		EB
r 		TP
r 		RP
r 		NI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AI
rw 		ER
rw 		FBE
rw 		ET
rw 		RWT
rw 		RPS
rw 		RBU
rw 		RS
rw 		TU
rw 		RO
rw 		TJT
rw 		TBU
rw 		TPS
rw 		TS
rw
Toggle Fields.

TS

Bit 0: Transmit status.

TPS

Bit 1: Transmit process stopped status.

TBU

Bit 2: Transmit buffer unavailable status.

TJT

Bit 3: Transmit jabber timeout status.

RO

Bit 4: Receive overflow status.

TU

Bit 5: Transmit underflow status.

RS

Bit 6: Receive status.

RBU

Bit 7: Receive buffer unavailable status.

RPS

Bit 8: Receive process stopped status.

RWT

Bit 9: Receive watchdog timeout status.

ET

Bit 10: Early transmit status.

FBE

Bit 13: Fatal bus error status.

ER

Bit 14: Early receive status.

AI

Bit 15: Abnormal interrupt summary.

NI

Bit 16: Normal interrupt summary.

RP

Bits 17-19: Receive process state.

TP

Bits 20-22: Transmit process state.

EB

Bits 23-25: Error bits status.

MSC

Bit 27: MSC status.

WUM

Bit 28: WUM status.

TST

Bit 29: Time stamp trigger status.

DMA_CTL

Ethernet DMA control register

Offset: 0x18, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTCERFD
rw 		RSFD
rw 		DAFRF
rw 		TSFD
rw 		FTF
rw 		TTHC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTHC
rw 		STE
rw 		FERF
rw 		FUF
rw 		RTHC
rw 		OSF
rw 		SRE
rw
Toggle Fields.

SRE

Bit 1: Start/stop receive enable.

OSF

Bit 2: Operate on second frame.

RTHC

Bits 3-4: Receive threshold control.

FUF

Bit 6: Forward undersized good frames.

FERF

Bit 7: Forward error frames.

STE

Bit 13: Start/stop transmission enable.

TTHC

Bits 14-16: Transmit threshold control.

FTF

Bit 20: Flush transmit FIFO.

TSFD

Bit 21: Transmit Store-and-Forward.

DAFRF

Bit 24: Disable flushing of received frames.

RSFD

Bit 25: Receive Store-and-Forward.

DTCERFD

Bit 26: Dropping of TCP/IP checksum error frames disable.

DMA_INTEN

Ethernet DMA interrupt enable register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AIEN
rw 		ERIEN
rw 		FBEIEN
rw 		ETIEN
rw 		RWTIEN
rw 		RPSIEN
rw 		RBUIEN
rw 		RIEN
rw 		TUIEN
rw 		ROIEN
rw 		TJTIEN
rw 		TBUIEN
rw 		TPSIEN
rw 		TIEN
rw
Toggle Fields.

TIEN

Bit 0: Transmit interrupt enable.

TPSIEN

Bit 1: Transmit process stopped interrupt enable.

TBUIEN

Bit 2: Transmit buffer unavailable interrupt enable.

TJTIEN

Bit 3: Transmit jabber timeout interrupt enable.

ROIEN

Bit 4: Receive overflow interrupt enable.

TUIEN

Bit 5: Transmit underflow interrupt enable.

RIEN

Bit 6: Receive interrupt enable.

RBUIEN

Bit 7: Receive buffer unavailable interrupt enable.

RPSIEN

Bit 8: Receive process stopped interrupt enable.

RWTIEN

Bit 9: receive watchdog timeout interrupt enable.

ETIEN

Bit 10: Early transmit interrupt enable.

FBEIEN

Bit 13: Fatal bus error interrupt enable.

ERIEN

Bit 14: Early receive interrupt enable.

AIEN

Bit 15: Abnormal interrupt summary enable.

NIEN

Bit 16: Normal interrupt summary enable.

DMA_MFBOCNT

Ethernet DMA missed frame and buffer overflow counter register

Offset: 0x20, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSFA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSFC
r
Toggle Fields.

MSFC

Bits 0-15: Missed frames by the controller.

MSFA

Bits 17-27: Missed frames by the application.

DMA_RSWDC

Ethernet DMA receive state watchdog counter register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDCFRS
rw
Toggle Fields.

WDCFRS

Bits 0-7: Watchdog counter for receive status (RS).

DMA_CTDADDR

DMA current transmit descriptor address register

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDAP
r
Toggle Fields.

TDAP

Bits 0-31: transmit descriptor address pointer.

DMA_CRDADDR

Ethernet DMA current receive descriptor address register

Offset: 0x4C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDAP
r
Toggle Fields.

RDAP

Bits 0-31: Receive descriptor address pointer.

DMA_CTBADDR

Ethernet DMA current transmit buffer address register

Offset: 0x50, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TBAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBAP
r
Toggle Fields.

TBAP

Bits 0-31: Transmit buffer address pointer.

DMA_CRBADDR

Ethernet DMA current receive buffer address register

Offset: 0x54, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RBAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RBAP
r
Toggle Fields.

RBAP

Bits 0-31: receive buffer address pointer.

ENET_MAC

0x40028000: Ethernet: media access control

17/89 fields covered. Toggle Registers.

MAC_CFG

Ethernet MAC configuration register (MAC_CFG)

Offset: 0x0, reset: 0x00008000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TFCD
rw 		WDD
rw 		JBD
rw 		IGBS
rw 		CSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPD
rw 		ROD
rw 		LBM
rw 		DPM
rw 		IPFCO
rw 		RTD
rw 		APCD
rw 		BOL
rw 		DFC
rw 		TEN
rw 		REN
rw
Toggle Fields.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

DFC

Bit 4: Deferral check.

BOL

Bits 5-6: Back-off limit.

APCD

Bit 7: Automatic pad/CRC drop.

RTD

Bit 9: Retry disable.

IPFCO

Bit 10: IP frame checksum offload.

DPM

Bit 11: Duplex mode.

LBM

Bit 12: Loopback mode.

ROD

Bit 13: Receive own disable.

SPD

Bit 14: Fast Ethernet speed.

CSD

Bit 16: Carrier sense disable.

IGBS

Bits 17-19: Inter frame gap bit selection.

JBD

Bit 22: Jabber disable.

WDD

Bit 23: Watchdog disable.

TFCD

Bit 25: Type Frame CRC Dropping.

MAC_FRMF

Ethernet MAC frame filter register (MAC_FRMF)

Offset: 0x4, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HPFLT
rw 		SAFLT
rw 		SAIFLT
rw 		PCFRM
rw 		BFRMD
rw 		MFD
rw 		DAIFLT
rw 		HMF
rw 		HUF
rw 		PM
rw
Toggle Fields.

PM

Bit 0: Promiscuous mode.

HUF

Bit 1: Hash unicast filter.

HMF

Bit 2: Hash multicast filter.

DAIFLT

Bit 3: Destination address inverse filtering.

MFD

Bit 4: multicast filter disable.

BFRMD

Bit 5: Broadcast frames disable.

PCFRM

Bits 6-7: Pass control frames.

SAIFLT

Bit 8: Source address inverse filtering.

SAFLT

Bit 9: Source address filter.

HPFLT

Bit 10: Hash or perfect filter.

FAR

Bit 31: Frames all receive.

MAC_HLH

Ethernet MAC hash list high register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HLH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HLH
rw
Toggle Fields.

HLH

Bits 0-31: Hash list high.

MAC_HLL

Ethernet MAC hash list low register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HLL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HLL
rw
Toggle Fields.

HLL

Bits 0-31: Hash list low.

MAC_PHY_CTL

Ethernet MAC PHY control register (MAC_PHY_CTL)

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw 		PR
rw 		CLR
rw 		PW
rw 		PB
rw
Toggle Fields.

PB

Bit 0: PHY busy.

PW

Bit 1: PHY write.

CLR

Bits 2-4: Clock range.

PR

Bits 6-10: PHY register.

PA

Bits 11-15: PHY address.

MAC_PHY_DATA

Ethernet MAC MII data register (MAC_PHY_DATA)

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD
rw
Toggle Fields.

PD

Bits 0-15: PHY data.

MAC_FCTL

Ethernet MAC flow control register (MAC_FCTL)

Offset: 0x18, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DZQP
rw 		PLTS
rw 		UPFDT
rw 		RFCEN
rw 		TFCEN
rw 		FLCB_BKPA
rw
Toggle Fields.

FLCB_BKPA

Bit 0: Flow control busy/back pressure activate.

TFCEN

Bit 1: Transmit flow control enable.

RFCEN

Bit 2: Receive flow control enable.

UPFDT

Bit 3: Unicast pause frame detect.

PLTS

Bits 4-5: Pause low threshold.

DZQP

Bit 7: Disable Zero-quanta pause.

PTM

Bits 16-31: Pause time.

MAC_VLT

Ethernet MAC VLAN tag register (MAC_VLT)

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VLTC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VLTI
rw
Toggle Fields.

VLTI

Bits 0-15: VLAN tag identifier (for receive frames).

VLTC

Bit 16: 12-bit VLAN tag comparison.

MAC_RWFF

Ethernet MAC remote wakeup frame filter register (MAC_RWFF)

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

MAC_WUM

Ethernet MAC wakeup management register (MAC_WUM)

Offset: 0x2C, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUFFRPR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GU
rw 		WUFR
rw 		MPKR
rw 		WFEN
rw 		MPEN
rw 		PWD
rw
Toggle Fields.

PWD

Bit 0: Power down.

MPEN

Bit 1: Magic Packet enable.

WFEN

Bit 2: Wakeup frame enable.

MPKR

Bit 5: Magic packet received.

WUFR

Bit 6: Wakeup frame received.

GU

Bit 9: Global unicast.

WUFFRPR

Bit 31: Wakeup frame filter register pointer reset.

MAC_DBG

Ethernet MAC debug register (MAC_DBG)

Offset: 0x34, reset: 0x00000000, access: read-only

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFF
r 		TXFNE
r 		TXFW
r 		TXFRS
r 		PCS
r 		SOMT
r 		MTNI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFS
r 		RXFRS
r 		RXFW
r 		RXAFS
r 		MRNI
r
Toggle Fields.

MRNI

Bit 0: MAC receive state not idle.

RXAFS

Bits 1-2: Rx asynchronous FIFO status.

RXFW

Bit 4: RxFIFO is writing.

RXFRS

Bits 5-6: RxFIFO read operation status.

RXFS

Bits 8-9: RxFIFO state.

MTNI

Bit 16: MAC transmit state not idle.

SOMT

Bits 17-18: Status of MAC transmitter.

PCS

Bit 19: Pause condition status.

TXFRS

Bits 20-21: TxFIFO read operation status.

TXFW

Bit 22: TxFIFO is writing.

TXFNE

Bit 24: TxFIFO not empty flag.

TXFF

Bit 25: TxFIFO Full flag.

MAC_INTF

Ethernet MAC interrupt flag register (MAC_INTF)

Offset: 0x38, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMST
r 		MSCT
r 		MSCR
r 		MSC
r 		WUM
r
Toggle Fields.

WUM

Bit 3: WUM status.

MSC

Bit 4: MSC status.

MSCR

Bit 5: MSC receive status.

MSCT

Bit 6: MSC transmit status.

TMST

Bit 9: Time stamp trigger status.

MAC_INTMSK

Ethernet MAC interrupt mask register (MAC_INTMSK)

Offset: 0x3C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMSTIM
rw 		WUMIM
rw
Toggle Fields.

WUMIM

Bit 3: WUM interrupt mask.

TMSTIM

Bit 9: Time stamp trigger interrupt mask.

MAC_ADDR0H

Ethernet MAC address 0 high register (MAC_ADDR0H)

Offset: 0x40, reset: 0x8000FFFF, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR0H
rw
Toggle Fields.

ADDR0H

Bits 0-15: MAC address0 high.

MO

Bit 31: Always 1.

MAC_ADDR0L

Ethernet MAC address 0 low register

Offset: 0x44, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR0L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR0L
rw
Toggle Fields.

ADDR0L

Bits 0-31: MAC address0 low.

MAC_ADDR1H

Ethernet MAC address 1 high register (MAC_ADDR1H)

Offset: 0x48, reset: 0x0000FFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFE
rw 		SAF
rw 		MB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR1H
rw
Toggle Fields.

ADDR1H

Bits 0-15: MAC address1 high.

MB

Bits 24-29: Mask byte.

SAF

Bit 30: Source address filter.

AFE

Bit 31: Address filter enable.

MAC_ADDR1L

Ethernet MAC address1 low register

Offset: 0x4C, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR1L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR1L
rw
Toggle Fields.

ADDR1L

Bits 0-31: MAC address1 low.

MAC_ADDR2H

Ethernet MAC address 2 high register (MAC_ADDR2H)

Offset: 0x50, reset: 0x0000FFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFE
rw 		SAF
rw 		MB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR2H
rw
Toggle Fields.

ADDR2H

Bits 0-15: Ethernet MAC address 2 high register.

MB

Bits 24-29: Mask byte.

SAF

Bit 30: Source address filter.

AFE

Bit 31: Address filter enable .

MAC_ADDR2L

Ethernet MAC address 2 low register

Offset: 0x54, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR2L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR2L
rw
Toggle Fields.

ADDR2L

Bits 0-31: MAC address2 low.

MAC_ADDR3H

Ethernet MAC address 3 high register (MAC_ADDR3H)

Offset: 0x58, reset: 0x0000FFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFE
rw 		SAF
rw 		MB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR3H
rw
Toggle Fields.

ADDR3H

Bits 0-15: MAC address3 high.

MB

Bits 24-29: Mask byte.

SAF

Bit 30: Source address filter.

AFE

Bit 31: Address filter enable.

MAC_ADDR3L

Ethernet MAC address 3 low register

Offset: 0x5C, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR3L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR3L
rw
Toggle Fields.

ADDR3L

Bits 0-31: MAC address3 low.

ENET_MAC_FCTH

0x40029080: MAC flow control threshold register

0/2 fields covered. Toggle Registers.

MAC_FCTH

Ethernet MAC flow control threshold register

Offset: 0x0, reset: 0x00000015, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFD
rw 		RFA
rw
Toggle Fields.

RFA

Bits 0-2: Threshold of active flow control.

RFD

Bits 4-6: Threshold of deactive flow control.

ENET_MSC

0x40028100: Ethernet: MAC statistics counters

12/24 fields covered. Toggle Registers.

MSC_CTL

Ethernet MSC control register (MSC_CTL)

Offset: 0x0, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFHPM
rw 		PMC
w 		MCFZ
rw 		RTOR
rw 		CTSR
rw 		CTR
rw
Toggle Fields.

CTR

Bit 0: Counter reset.

CTSR

Bit 1: Counter stop rollover.

RTOR

Bit 2: Reset on read.

MCFZ

Bit 3: MSC counter freeze.

PMC

Bit 4: Preset MSC counter.

AFHPM

Bit 5: Almost full or half preset mode.

MSC_RINTF

Ethernet MSC receive interrupt flag register (MSC_RINTF)

Offset: 0x4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RGUF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFAE
r 		RFCE
r
Toggle Fields.

RFCE

Bit 5: Received frames CRC error.

RFAE

Bit 6: Received frames alignment error.

RGUF

Bit 17: Received Good Unicast Frames.

MSC_TINTF

Ethernet MSC transmit interrupt flag register (MSC_TINTF)

Offset: 0x8, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFMSC
r 		TGFSC
r
Toggle Fields.

TGFSC

Bit 14: Transmitted good frames single collision.

TGFMSC

Bit 15: Transmitted good frames more single collision .

TGF

Bit 21: Transmitted good frames.

MSC_RINTMSK

Ethernet MSC receive interrupt mask register (MSC_RINTMSK)

Offset: 0xC, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RGUFIM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFAEIM
rw 		RFCEIM
rw
Toggle Fields.

RFCEIM

Bit 5: Received frame CRC error interrupt mask.

RFAEIM

Bit 6: Received frames alignment error interrupt mask.

RGUFIM

Bit 17: Received good unicast frames interrupt mask.

MSC_TINTMSK

Ethernet MSC transmit interrupt mask register (MSC_TINTMSK)

Offset: 0x10, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGFIM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGFMSCIM
rw 		TGFSCIM
rw
Toggle Fields.

TGFSCIM

Bit 14: Transmitted good frames single collision interrupt mask.

TGFMSCIM

Bit 15: Transmitted good frames more single interrupt collision mask.

TGFIM

Bit 21: Transmitted good frames interrupt mask.

MSC_SCCNT

Ethernet MSC transmitted good frames after a single collision counter

Offset: 0x4C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCC
r
Toggle Fields.

SCC

Bits 0-31: Transmitted good frames after a single collision counter.

MSC_MSCCNT

Ethernet MSC transmitted good frames after more than a single collision

Offset: 0x50, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSCC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSCC
r
Toggle Fields.

MSCC

Bits 0-31: Transmitted good frames after more than a single collision counter.

MSC_TGFCNT

Ethernet MSC transmitted good frames counter register

Offset: 0x68, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TGF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TGF
r
Toggle Fields.

TGF

Bits 0-31: Transmitted good frames counter.

MSC_RFCECNT

Ethernet MSC received frames with CRC error counter register

Offset: 0x94, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RFCER
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFCER
r
Toggle Fields.

RFCER

Bits 0-31: Received frames with CRC error counter.

MSC_RFAECNT

Ethernet MSC received frames with alignment error counter register

Offset: 0x98, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RFAER
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFAER
r
Toggle Fields.

RFAER

Bits 0-31: Received frames with alignment error counter.

MSC_RGUFCNT

MSC received good unicast frames counter register

Offset: 0xC4, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RGUF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGUF
r
Toggle Fields.

RGUF

Bits 0-31: Received good unicast frames counter.

ENET_PTP

0x40028700: Ethernet: Precision time protocol

5/29 fields covered. Toggle Registers.

PTP_TSCTL

Ethernet PTP time stamp control register (PTP_TSCTL)

Offset: 0x0, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAFEN
rw 		CKNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNMSEN
rw 		ETMSEN
rw 		IP4SEN
rw 		IP6SEN
rw 		ESEN
rw 		PFSV
rw 		SCROM
rw 		ARFSEN
rw 		TMSARU
rw 		TMSITEN
rw 		TMSSTU
rw 		TMSSTI
rw 		TMSFCU
rw 		TMSEN
rw
Toggle Fields.

TMSEN

Bit 0: Time stamp enable.

TMSFCU

Bit 1: Time stamp fine or coarse update.

TMSSTI

Bit 2: Time stamp system time initialize.

TMSSTU

Bit 3: Time stamp system time update.

TMSITEN

Bit 4: Time stamp interrupt trigger enable.

TMSARU

Bit 5: Time stamp addend register update.

ARFSEN

Bit 8: All received frames snapshot enable.

SCROM

Bit 9: Subsecond counter rollover mode.

PFSV

Bit 10: PTP frame snooping version.

ESEN

Bit 11: Received Ethernet snapshot enable.

IP6SEN

Bit 12: Received IPv6 snapshot enable.

IP4SEN

Bit 13: Received IPv4 snapshot enable.

ETMSEN

Bit 14: Received event type message snapshot enable.

MNMSEN

Bit 15: Received master node message snapshot enable.

CKNT

Bits 16-17: Clock node type for time stamp.

MAFEN

Bit 18: MAC address filter enable for PTP frame.

PTP_SSINC

Ethernet PTP subsecond increment register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STMSSI
rw
Toggle Fields.

STMSSI

Bits 0-7: System time subsecond increment.

PTP_TSH

Ethernet PTP time stamp high register

Offset: 0x8, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STMS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STMS
r
Toggle Fields.

STMS

Bits 0-31: System time second.

PTP_TSL

Ethernet PTP time stamp low register (PTP_TSL)

Offset: 0xC, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STS
r 		STMSS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STMSS
r
Toggle Fields.

STMSS

Bits 0-30: System time subseconds.

STS

Bit 31: System time sign.

PTP_TSUH

Ethernet PTP time stamp high update register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TMSUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMSUS
rw
Toggle Fields.

TMSUS

Bits 0-31: Time stamp update second.

PTP_TSUL

Ethernet PTP time stamp low update register (PTP_TSUL)

Offset: 0x14, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TMSUPNS
rw 		TMSUSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMSUSS
rw
Toggle Fields.

TMSUSS

Bits 0-30: Time stamp update subseconds.

TMSUPNS

Bit 31: Time stamp update positive or negative sign.

PTP_TSADDEND

Ethernet PTP time stamp addend register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TMSA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMSA
rw
Toggle Fields.

TMSA

Bits 0-31: Time stamp addend.

PTP_ETH

Ethernet PTP expected time high register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETSH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETSH
rw
Toggle Fields.

ETSH

Bits 0-31: Expected time stamp high.

PTP_ETL

Ethernet PTP expected time low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETSL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETSL
rw
Toggle Fields.

ETSL

Bits 0-31: Expected time stamp low.

PTP_TSF

Ethernet PTP time stamp flag register

Offset: 0x28, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTM
r 		TSSCO
r
Toggle Fields.

TSSCO

Bit 0: Timestamp second counter overflow.

TTM

Bit 1: Target time match.

PTP_PPSCTL

Ethernet PTP PPS control register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PPSOFC
rw
Toggle Fields.

PPSOFC

Bits 0-3: PPS output frequency configure.

EXMC

0xA0000000: External memory controller

2/248 fields covered. Toggle Registers.

SNCTL0

SRAM/NOR flash control register 0

Offset: 0x0, reset: 0x000030DA, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCK
rw 		SYNCWR
rw 		CPS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXMODEN
rw 		NRWTEN
rw 		WREN
rw 		NRWTCFG
rw 		WRAPEN
rw 		NRWTPOL
rw 		SBRSTEN
rw 		NREN
rw 		NRW
rw 		NRTP
rw 		NRMUX
rw 		NRBKEN
rw
Toggle Fields.

NRBKEN

Bit 0: NOR bank enable.

NRMUX

Bit 1: NOR bank memory address/data multiplexing.

NRTP

Bits 2-3: NOR bank memory type.

NRW

Bits 4-5: NOR bank memory data bus width.

NREN

Bit 6: NOR Flash access enable.

SBRSTEN

Bit 8: Synchronous burst enable.

NRWTPOL

Bit 9: NWAIT signal polarity.

WRAPEN

Bit 10: Wrapped burst mode enable.

NRWTCFG

Bit 11: NWAIT signal configuration, only work in synchronous mode.

WREN

Bit 12: Write enable.

NRWTEN

Bit 13: NWAIT signal enable.

EXMODEN

Bit 14: Extended mode enable.

ASYNCWAIT

Bit 15: Asynchronous wait.

CPS

Bits 16-18: CRAM page size.

SYNCWR

Bit 19: Synchronous write.

CCK

Bit 20: Consecutive Clock.

SNTCFG0

SRAM/NOR flash timing configuration register 0

Offset: 0x4, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ASYNCMOD
rw 		DLAT
rw 		CKDIV
rw 		BUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSET
rw 		AHLD
rw 		ASET
rw
Toggle Fields.

ASET

Bits 0-3: Address setup time.

AHLD

Bits 4-7: Address hold time.

DSET

Bits 8-15: Data setup time.

BUSLAT

Bits 16-19: Bus latency.

CKDIV

Bits 20-23: Synchronous clock divide ratio.

DLAT

Bits 24-27: Data latency for NOR Flash.

ASYNCMOD

Bits 28-29: Asynchronous access mode.

SNCTL1

SRAM/NOR flash control register 1

Offset: 0x8, reset: 0x000030D2, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCK
rw 		SYNCWR
rw 		CPS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXMODEN
rw 		NRWTEN
rw 		WREN
rw 		NRWTCFG
rw 		WRAPEN
rw 		NRWTPOL
rw 		SBRSTEN
rw 		NREN
rw 		NRW
rw 		NRTP
rw 		NRMUX
rw 		NRBKEN
rw
Toggle Fields.

NRBKEN

Bit 0: NOR bank enable.

NRMUX

Bit 1: NOR bank memory address/data multiplexing.

NRTP

Bits 2-3: NOR bank memory type.

NRW

Bits 4-5: NOR bank memory data bus width.

NREN

Bit 6: NOR Flash access enable.

SBRSTEN

Bit 8: Synchronous burst enable.

NRWTPOL

Bit 9: NWAIT signal polarity.

WRAPEN

Bit 10: Wrapped burst mode enable.

NRWTCFG

Bit 11: NWAIT signal configuration, only work in synchronous mode.

WREN

Bit 12: Write enable.

NRWTEN

Bit 13: NWAIT signal enable.

EXMODEN

Bit 14: Extended mode enable.

ASYNCWAIT

Bit 15: Asynchronous wait.

CPS

Bits 16-18: CRAM page size.

SYNCWR

Bit 19: Synchronous write.

CCK

Bit 20: Consecutive Clock.

SNTCFG1

SRAM/NOR flash timing configuration register 1

Offset: 0xC, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ASYNCMOD
rw 		DLAT
rw 		CKDIV
rw 		BUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSET
rw 		AHLD
rw 		ASET
rw
Toggle Fields.

ASET

Bits 0-3: Address setup time.

AHLD

Bits 4-7: Address hold time.

DSET

Bits 8-15: Data setup time.

BUSLAT

Bits 16-19: Bus latency.

CKDIV

Bits 20-23: Synchronous clock divide ratio.

DLAT

Bits 24-27: Data latency for NOR Flash.

ASYNCMOD

Bits 28-29: Asynchronous access mode.

SNCTL2

SRAM/NOR flash control register 2

Offset: 0x10, reset: 0x000030D2, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCK
rw 		SYNCWR
rw 		CPS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXMODEN
rw 		NRWTEN
rw 		WREN
rw 		NRWTCFG
rw 		WRAPEN
rw 		NRWTPOL
rw 		SBRSTEN
rw 		NREN
rw 		NRW
rw 		NRTP
rw 		NRMUX
rw 		NRBKEN
rw
Toggle Fields.

NRBKEN

Bit 0: NOR bank enable.

NRMUX

Bit 1: NOR bank memory address/data multiplexing.

NRTP

Bits 2-3: NOR bank memory type.

NRW

Bits 4-5: NOR bank memory data bus width.

NREN

Bit 6: NOR Flash access enable.

SBRSTEN

Bit 8: Synchronous burst enable.

NRWTPOL

Bit 9: NWAIT signal polarity.

WRAPEN

Bit 10: Wrapped burst mode enable.

NRWTCFG

Bit 11: NWAIT signal configuration, only work in synchronous mode.

WREN

Bit 12: Write enable.

NRWTEN

Bit 13: NWAIT signal enable.

EXMODEN

Bit 14: Extended mode enable.

ASYNCWAIT

Bit 15: Asynchronous wait.

CPS

Bits 16-18: CRAM page size.

SYNCWR

Bit 19: Synchronous write.

CCK

Bit 20: Consecutive Clock.

SNTCFG2

SRAM/NOR flash timing configuration register 2

Offset: 0x14, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ASYNCMOD
rw 		DLAT
rw 		CKDIV
rw 		BUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSET
rw 		AHLD
rw 		ASET
rw
Toggle Fields.

ASET

Bits 0-3: Address setup time.

AHLD

Bits 4-7: Address hold time.

DSET

Bits 8-15: Data setup time.

BUSLAT

Bits 16-19: Bus latency.

CKDIV

Bits 20-23: Synchronous clock divide ratio.

DLAT

Bits 24-27: Data latency for NOR Flash.

ASYNCMOD

Bits 28-29: Asynchronous access mode.

SNCTL3

SRAM/NOR flash control register 3

Offset: 0x18, reset: 0x000030D2, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCK
rw 		SYNCWR
rw 		CPS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXMODEN
rw 		NRWTEN
rw 		WREN
rw 		NRWTCFG
rw 		WRAPEN
rw 		NRWTPOL
rw 		SBRSTEN
rw 		NREN
rw 		NRW
rw 		NRTP
rw 		NRMUX
rw 		NRBKEN
rw
Toggle Fields.

NRBKEN

Bit 0: NOR bank enable.

NRMUX

Bit 1: NOR bank memory address/data multiplexing.

NRTP

Bits 2-3: NOR bank memory type.

NRW

Bits 4-5: NOR bank memory data bus width.

NREN

Bit 6: NOR Flash access enable.

SBRSTEN

Bit 8: Synchronous burst enable.

NRWTPOL

Bit 9: NWAIT signal polarity.

WRAPEN

Bit 10: Wrapped burst mode enable.

NRWTCFG

Bit 11: NWAIT signal configuration, only work in synchronous mode.

WREN

Bit 12: Write enable.

NRWTEN

Bit 13: NWAIT signal enable.

EXMODEN

Bit 14: Extended mode enable.

ASYNCWAIT

Bit 15: Asynchronous wait.

CPS

Bits 16-18: CRAM page size.

SYNCWR

Bit 19: Synchronous write.

CCK

Bit 20: Consecutive Clock.

SNTCFG3

SRAM/NOR flash timing configuration register 3

Offset: 0x1C, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ASYNCMOD
rw 		DLAT
rw 		CKDIV
rw 		BUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSET
rw 		AHLD
rw 		ASET
rw
Toggle Fields.

ASET

Bits 0-3: Address setup time.

AHLD

Bits 4-7: Address hold time.

DSET

Bits 8-15: Data setup time.

BUSLAT

Bits 16-19: Bus latency.

CKDIV

Bits 20-23: Synchronous clock divide ratio.

DLAT

Bits 24-27: Data latency for NOR Flash.

ASYNCMOD

Bits 28-29: Asynchronous access mode.

NPCTL1

NAND flash/PC card control register 1

Offset: 0x60, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCSZ
rw 		ATR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATR
rw 		CTR
rw 		ECCEN
rw 		NDW
rw 		NDTP
rw 		NDBKEN
rw 		NDWTEN
rw
Toggle Fields.

NDWTEN

Bit 1: Wait feature enable.

NDBKEN

Bit 2: NAND bank enable.

NDTP

Bit 3: NAND bank memory type.

NDW

Bits 4-5: NAND bank memory data bus width.

ECCEN

Bit 6: ECC enable.

CTR

Bits 9-12: CLE to RE delay.

ATR

Bits 13-16: ALE to RE delay.

ECCSZ

Bits 17-19: ECC size.

NPINTEN1

NAND flash/PC card interrupt enable register 1

Offset: 0x64, reset: 0x00000040, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFEPT
rw 		INTFEN
rw 		INTHEN
rw 		INTREN
rw 		INTFS
rw 		INTHS
rw 		INTRS
rw
Toggle Fields.

INTRS

Bit 0: Interrupt rising edge status.

INTHS

Bit 1: Interrupt high-level status.

INTFS

Bit 2: Interrupt falling edge status.

INTREN

Bit 3: Interrupt rising edge detection enable bit.

INTHEN

Bit 4: Interrupt high-level detection enable.

INTFEN

Bit 5: Interrupt falling edge detection enable.

FFEPT

Bit 6: FIFO empty flag.

NPCTCFG1

NAND flash/PC card common space timing configuration register 1

Offset: 0x68, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMHIZ
rw 		COMHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMWAIT
rw 		COMSET
rw
Toggle Fields.

COMSET

Bits 0-7: Common memory setup time.

COMWAIT

Bits 8-15: Common memory wait time.

COMHLD

Bits 16-23: Common memory hold time.

COMHIZ

Bits 24-31: Common memory data bus HiZ time.

NPATCFG1

NAND flash/PC card attribute space timing configuration register 1

Offset: 0x6C, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw 		ATTHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw 		ATTSET
rw
Toggle Fields.

ATTSET

Bits 0-7: Attribute memory setup time.

ATTWAIT

Bits 8-15: Attribute memory wait time.

ATTHLD

Bits 16-23: Attribute memory hold time.

ATTHIZ

Bits 24-31: Attribute memory data bus HiZ time.

NECC1

NAND flash ECC register 1

Offset: 0x74, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC
r
Toggle Fields.

ECC

Bits 0-31: ECC result.

NPCTL2

NAND flash/PC card control register 2

Offset: 0x80, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCSZ
rw 		ATR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATR
rw 		CTR
rw 		ECCEN
rw 		NDW
rw 		NDTP
rw 		NDBKEN
rw 		NDWTEN
rw
Toggle Fields.

NDWTEN

Bit 1: Wait feature enable.

NDBKEN

Bit 2: NAND bank enable.

NDTP

Bit 3: NAND bank memory type.

NDW

Bits 4-5: NAND bank memory data bus width.

ECCEN

Bit 6: ECC enable.

CTR

Bits 9-12: CLE to RE delay.

ATR

Bits 13-16: ALE to RE delay.

ECCSZ

Bits 17-19: ECC size.

NPINTEN2

NAND flash/PC card interrupt enable register 2

Offset: 0x84, reset: 0x00000040, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFEPT
rw 		INTFEN
rw 		INTHEN
rw 		INTREN
rw 		INTFS
rw 		INTHS
rw 		INTRS
rw
Toggle Fields.

INTRS

Bit 0: Interrupt rising edge status.

INTHS

Bit 1: Interrupt high-level status.

INTFS

Bit 2: Interrupt falling edge status.

INTREN

Bit 3: Interrupt rising edge detection enable bit.

INTHEN

Bit 4: Interrupt high-level detection enable.

INTFEN

Bit 5: Interrupt falling edge detection enable.

FFEPT

Bit 6: FIFO empty flag.

NPCTCFG2

NAND flash/PC card common space timing configuration register 2

Offset: 0x88, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMHIZ
rw 		COMHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMWAIT
rw 		COMSET
rw
Toggle Fields.

COMSET

Bits 0-7: Common memory setup time.

COMWAIT

Bits 8-15: Common memory wait time.

COMHLD

Bits 16-23: Common memory hold time.

COMHIZ

Bits 24-31: Common memory data bus HiZ time.

NPATCFG2

NAND flash/PC card attribute space timing configuration register 2

Offset: 0x8C, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw 		ATTHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw 		ATTSET
rw
Toggle Fields.

ATTSET

Bits 0-7: Attribute memory setup time.

ATTWAIT

Bits 8-15: Attribute memory wait time.

ATTHLD

Bits 16-23: Attribute memory hold time.

ATTHIZ

Bits 24-31: Attribute memory data bus HiZ time.

NECC2

NAND flash ECC register 2

Offset: 0x94, reset: 0x00000000, access: Unspecified

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC
r
Toggle Fields.

ECC

Bits 0-31: ECC result.

NPCTL3

NAND flash/PC card control register 3

Offset: 0xA0, reset: 0x00000018, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCSZ
rw 		ATR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATR
rw 		CTR
rw 		ECCEN
rw 		NDW
rw 		NDTP
rw 		NDBKEN
rw 		NDWTEN
rw
Toggle Fields.

NDWTEN

Bit 1: Wait feature enable.

NDBKEN

Bit 2: NAND bank enable.

NDTP

Bit 3: NAND bank memory type.

NDW

Bits 4-5: NAND bank memory data bus width.

ECCEN

Bit 6: ECC enable.

CTR

Bits 9-12: CLE to RE delay.

ATR

Bits 13-16: ALE to RE delay.

ECCSZ

Bits 17-19: ECC size.

NPINTEN3

NAND flash/PC card interrupt enable register 3

Offset: 0xA4, reset: 0x00000040, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFEPT
rw 		INTFEN
rw 		INTHEN
rw 		INTREN
rw 		INTFS
rw 		INTHS
rw 		INTRS
rw
Toggle Fields.

INTRS

Bit 0: Interrupt rising edge status.

INTHS

Bit 1: Interrupt high-level status.

INTFS

Bit 2: Interrupt falling edge status.

INTREN

Bit 3: Interrupt rising edge detection enable bit.

INTHEN

Bit 4: Interrupt high-level detection enable.

INTFEN

Bit 5: Interrupt falling edge detection enable.

FFEPT

Bit 6: FIFO empty flag.

NPCTCFG3

NAND flash/PC card common space timing configuration register 3

Offset: 0xA8, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMHIZ
rw 		COMHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMWAIT
rw 		COMSET
rw
Toggle Fields.

COMSET

Bits 0-7: Common memory setup time.

COMWAIT

Bits 8-15: Common memory wait time.

COMHLD

Bits 16-23: Common memory hold time.

COMHIZ

Bits 24-31: Common memory data bus HiZ time.

NPATCFG3

NAND flash/PC card attribute space timing configuration register 3

Offset: 0xAC, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw 		ATTHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw 		ATTSET
rw
Toggle Fields.

ATTSET

Bits 0-7: Attribute memory setup time.

ATTWAIT

Bits 8-15: Attribute memory wait time.

ATTHLD

Bits 16-23: Attribute memory hold time.

ATTHIZ

Bits 24-31: Attribute memory data bus HiZ time.

PIOTCFG3

PC card I/O space timing configuration register

Offset: 0xB0, reset: 0xFCFCFCFC, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOHIZ
rw 		IOHLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOWAIT
rw 		IOSET
rw
Toggle Fields.

IOSET

Bits 0-7: IO space setup time.

IOWAIT

Bits 8-15: IO space wait time.

IOHLD

Bits 16-23: IO space hold time.

IOHIZ

Bits 24-31: IO space data bus HiZ time.

SNWTCFG0

SRAM/NOR flash write timing configuration register 0

Offset: 0x104, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WASYNCMOD
rw 		WBUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDSET
rw 		WAHLD
rw 		WASET
rw
Toggle Fields.

WASET

Bits 0-3: Address setup time.

WAHLD

Bits 4-7: Address hold time.

WDSET

Bits 8-15: Data setup time.

WBUSLAT

Bits 16-19: Bus latency.

WASYNCMOD

Bits 28-29: Asynchronous access mode.

SNWTCFG1

SRAM/NOR flash write timing configuration register 1

Offset: 0x10C, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WASYNCMOD
rw 		WBUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDSET
rw 		WAHLD
rw 		WASET
rw
Toggle Fields.

WASET

Bits 0-3: Address setup time.

WAHLD

Bits 4-7: Address hold time.

WDSET

Bits 8-15: Data setup time.

WBUSLAT

Bits 16-19: Bus latency.

WASYNCMOD

Bits 28-29: Asynchronous access mode.

SNWTCFG2

SRAM/NOR flash write timing configuration register 2

Offset: 0x114, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WASYNCMOD
rw 		WBUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDSET
rw 		WAHLD
rw 		WASET
rw
Toggle Fields.

WASET

Bits 0-3: Address setup time.

WAHLD

Bits 4-7: Address hold time.

WDSET

Bits 8-15: Data setup time.

WBUSLAT

Bits 16-19: Bus latency.

WASYNCMOD

Bits 28-29: Asynchronous access mode.

SNWTCFG3

SRAM/NOR flash write timing configuration register 3

Offset: 0x11C, reset: 0x0FFFFFFF, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WASYNCMOD
rw 		WBUSLAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDSET
rw 		WAHLD
rw 		WASET
rw
Toggle Fields.

WASET

Bits 0-3: Address setup time.

WAHLD

Bits 4-7: Address hold time.

WDSET

Bits 8-15: Data setup time.

WBUSLAT

Bits 16-19: Bus latency.

WASYNCMOD

Bits 28-29: Asynchronous access mode.

SDCTL0

SDRAM control register 0

Offset: 0x140, reset: 0x000002D0, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIPED
rw 		BRSTRD
rw 		SDCLK
rw 		WPEN
rw 		CL
rw 		NBK
rw 		SDW
rw 		RAW
rw 		CAW
rw
Toggle Fields.

CAW

Bits 0-1: Column address bit width.

RAW

Bits 2-3: Row address bit width.

SDW

Bits 4-5: SDRAM data bus width.

NBK

Bit 6: Number of banks.

CL

Bits 7-8: CAS Latency.

WPEN

Bit 9: Write protection enable.

SDCLK

Bits 10-11: SDRAM clock configuration.

BRSTRD

Bit 12: Burst read.

PIPED

Bits 13-14: Pipeline delay.

SDCTL1

SDRAM control register 1

Offset: 0x144, reset: 0x000002D0, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIPED
rw 		BRSTRD
rw 		SDCLK
rw 		WPEN
rw 		CL
rw 		NBK
rw 		SDW
rw 		RAW
rw 		CAW
rw
Toggle Fields.

CAW

Bits 0-1: Column address bit width.

RAW

Bits 2-3: Row address bit width.

SDW

Bits 4-5: SDRAM data bus width.

NBK

Bit 6: Number of banks.

CL

Bits 7-8: CAS Latency.

WPEN

Bit 9: Write protection enable.

SDCLK

Bits 10-11: SDRAM clock configuration.

BRSTRD

Bit 12: Burst read.

PIPED

Bits 13-14: Pipeline delay.

SDTCFG0

SDRAM timing configuration register 0

Offset: 0x148, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RCD
rw 		RPD
rw 		WRD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARFD
rw 		RASD
rw 		XSRD
rw 		LMRD
rw
Toggle Fields.

LMRD

Bits 0-3: Load Mode Register Delay.

XSRD

Bits 4-7: Exit Self-refresh delay.

RASD

Bits 8-11: Row address select delay.

ARFD

Bits 12-15: Auto refresh delay.

WRD

Bits 16-19: Write recovery delay.

RPD

Bits 20-23: Row precharge delay.

RCD

Bits 24-27: Row to column delay.

SDTCFG1

SDRAM timing configuration register 1

Offset: 0x14C, reset: 0x0FFFFFFF, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RCD
rw 		RPD
rw 		WRD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARFD
rw 		RASD
rw 		XSRD
rw 		LMRD
rw
Toggle Fields.

LMRD

Bits 0-3: Load Mode Register Delay.

XSRD

Bits 4-7: Exit Self-refresh delay.

RASD

Bits 8-11: Row address select delay.

ARFD

Bits 12-15: Auto refresh delay.

WRD

Bits 16-19: Write recovery delay.

RPD

Bits 20-23: Row precharge delay.

RCD

Bits 24-27: Row to column delay.

SDCMD

SDRAM command register

Offset: 0x150, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MRC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MRC
rw 		NARF
rw 		DS0
rw 		DS1
rw 		CMD
rw
Toggle Fields.

CMD

Bits 0-2: Command.

DS1

Bit 3: Device select 1.

DS0

Bit 4: Device select 0.

NARF

Bits 5-8: Number of successive Auto-refresh.

MRC

Bits 9-21: Mode register content.

SDARI

SDRAM auto-refresh interval register

Offset: 0x154, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REIE
rw 		ARINTV
rw 		REC
rw
Toggle Fields.

REC

Bit 0: Refresh error flag clear.

ARINTV

Bits 1-13: Auto-Refresh Interval.

REIE

Bit 14: Refresh error interrupt Enable.

SDSTAT

SDRAM status register

Offset: 0x158, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NRDY
rw 		STA1
rw 		STA0
rw 		REIF
rw
Toggle Fields.

REIF

Bit 0: Refresh error interrupt flag.

STA0

Bits 1-2: Device 0 status.

STA1

Bits 3-4: Device1 status.

NRDY

Bit 5: Not Ready status.

SDRSCTL

SDRAM read sample control register

Offset: 0x180, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDSC
rw 		SSCR
rw 		RSEN
rw
Toggle Fields.

RSEN

Bit 0: Read sample enable.

SSCR

Bit 1: Select sample cycle of read data.

SDSC

Bits 4-7: Select the delayed sample clock of read data.

SINIT

SPI initialization register

Offset: 0x310, reset: 0x18010000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
POL
rw 		IDL
rw 		ADRBIT
rw 		CMDBIT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

CMDBIT

Bits 16-17: Bit number of SPI PSRAM command phase.

ADRBIT

Bits 24-28: Bit number of SPI PSRAM address phase.

IDL

Bits 29-30: SPI PSRAM ID Length.

POL

Bit 31: Read data sample polarity.

SRCMD

SPI read command register

Offset: 0x320, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDID
rw 		RMODE
rw 		RWAITCYCLE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCMD
rw
Toggle Fields.

RCMD

Bits 0-15: SPI Read Command for AHB read transfer.

RWAITCYCLE

Bits 16-19: SPI Read Wait Cycle number after address phase.

RMODE

Bits 20-21: SPI PSRAM Read command mode.

RDID

Bit 31: Send SPI Read ID Command.

SWCMD

SPI write command register

Offset: 0x330, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SC
rw 		WMODE
rw 		WWAITCYCLE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WCMD
rw
Toggle Fields.

WCMD

Bits 0-14: SPI Write Command for AHB write transfer.

WWAITCYCLE

Bits 16-19: SPI Write Wait Cycle number after address phase.

WMODE

Bits 20-21: SPI PSRAM Write command mode.

SC

Bit 31: Send SPI Special Command which does not have address and data phase, command code and mode come from WCMD and WMODE.

SIDL

SPI ID low register

Offset: 0x340, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIDL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIDL
rw
Toggle Fields.

SIDL

Bits 0-31: ID Low Data saved for SPI Read ID Command.

SIDH

SPI ID high register

Offset: 0x350, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIDH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIDH
rw
Toggle Fields.

SIDH

Bits 0-31: ID High Data saved for SPI Read ID Command.

EXTI

0x40013C00: External interrupt/event controller

0/138 fields covered. Toggle Registers.

INTEN

Interrupt enable register (EXTI_INTEN)

Offset: 0x0, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INTEN22
rw 		INTEN21
rw 		INTEN20
rw 		INTEN19
rw 		INTEN18
rw 		INTEN17
rw 		INTEN16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTEN15
rw 		INTEN14
rw 		INTEN13
rw 		INTEN12
rw 		INTEN11
rw 		INTEN10
rw 		INTEN9
rw 		INTEN8
rw 		INTEN7
rw 		INTEN6
rw 		INTEN5
rw 		INTEN4
rw 		INTEN3
rw 		INTEN2
rw 		INTEN1
rw 		INTEN0
rw
Toggle Fields.

INTEN0

Bit 0: Enable Interrupt on line 0.

INTEN1

Bit 1: Enable Interrupt on line 1.

INTEN2

Bit 2: Enable Interrupt on line 2.

INTEN3

Bit 3: Enable Interrupt on line 3.

INTEN4

Bit 4: Enable Interrupt on line 4.

INTEN5

Bit 5: Enable Interrupt on line 5.

INTEN6

Bit 6: Enable Interrupt on line 6.

INTEN7

Bit 7: Enable Interrupt on line 7.

INTEN8

Bit 8: Enable Interrupt on line 8.

INTEN9

Bit 9: Enable Interrupt on line 9.

INTEN10

Bit 10: Enable Interrupt on line 10.

INTEN11

Bit 11: Enable Interrupt on line 11.

INTEN12

Bit 12: Enable Interrupt on line 12.

INTEN13

Bit 13: Enable Interrupt on line 13.

INTEN14

Bit 14: Enable Interrupt on line 14.

INTEN15

Bit 15: Enable Interrupt on line 15.

INTEN16

Bit 16: Enable Interrupt on line 16.

INTEN17

Bit 17: Enable Interrupt on line 17.

INTEN18

Bit 18: Enable Interrupt on line 18.

INTEN19

Bit 19: Enable Interrupt on line 19.

INTEN20

Bit 20: Enable Interrupt on line 20.

INTEN21

Bit 21: Enable Interrupt on line 21.

INTEN22

Bit 22: Enable Interrupt on line 22.

EVEN

Event enable register (EXTI_EVEN)

Offset: 0x4, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EVEN22
rw 		EVEN21
rw 		EVEN20
rw 		EVEN19
rw 		EVEN18
rw 		EVEN17
rw 		EVEN16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EVEN15
rw 		EVEN14
rw 		EVEN13
rw 		EVEN12
rw 		EVEN11
rw 		EVEN10
rw 		EVEN9
rw 		EVEN8
rw 		EVEN7
rw 		EVEN6
rw 		EVEN5
rw 		EVEN4
rw 		EVEN3
rw 		EVEN2
rw 		EVEN1
rw 		EVEN0
rw
Toggle Fields.

EVEN0

Bit 0: Enable Event on line 0.

EVEN1

Bit 1: Enable Event on line 1.

EVEN2

Bit 2: Enable Event on line 2.

EVEN3

Bit 3: Enable Event on line 3.

EVEN4

Bit 4: Enable Event on line 4.

EVEN5

Bit 5: Enable Event on line 5.

EVEN6

Bit 6: Enable Event on line 6.

EVEN7

Bit 7: Enable Event on line 7.

EVEN8

Bit 8: Enable Event on line 8.

EVEN9

Bit 9: Enable Event on line 9.

EVEN10

Bit 10: Enable Event on line 10.

EVEN11

Bit 11: Enable Event on line 11.

EVEN12

Bit 12: Enable Event on line 12.

EVEN13

Bit 13: Enable Event on line 13.

EVEN14

Bit 14: Enable Event on line 14.

EVEN15

Bit 15: Enable Event on line 15.

EVEN16

Bit 16: Enable Event on line 16.

EVEN17

Bit 17: Enable Event on line 17.

EVEN18

Bit 18: Enable Event on line 18.

EVEN19

Bit 19: Enable Event on line 19.

EVEN20

Bit 20: Enable Event on line 20.

EVEN21

Bit 21: Enable Event on line 21.

EVEN22

Bit 22: Enable Event on line 22.

RTEN

Rising Edge Trigger Enable register (EXTI_RTEN)

Offset: 0x8, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RTEN22
rw 		RTEN21
rw 		RTEN20
rw 		RTEN19
rw 		RTEN18
rw 		RTEN17
rw 		RTEN16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTEN15
rw 		RTEN14
rw 		RTEN13
rw 		RTEN12
rw 		RTEN11
rw 		RTEN10
rw 		RTEN9
rw 		RTEN8
rw 		RTEN7
rw 		RTEN6
rw 		RTEN5
rw 		RTEN4
rw 		RTEN3
rw 		RTEN2
rw 		RTEN1
rw 		RTEN0
rw
Toggle Fields.

RTEN0

Bit 0: Rising edge trigger enable of line 0.

RTEN1

Bit 1: Rising edge trigger enable of line 1.

RTEN2

Bit 2: Rising edge trigger enable of line 2.

RTEN3

Bit 3: Rising edge trigger enable of line 3.

RTEN4

Bit 4: Rising edge trigger enable of line 4.

RTEN5

Bit 5: Rising edge trigger enable of line 5.

RTEN6

Bit 6: Rising edge trigger enable of line 6.

RTEN7

Bit 7: Rising edge trigger enable of line 7.

RTEN8

Bit 8: Rising edge trigger enable of line 8.

RTEN9

Bit 9: Rising edge trigger enable of line 9.

RTEN10

Bit 10: Rising edge trigger enable of line 10.

RTEN11

Bit 11: Rising edge trigger enable of line 11.

RTEN12

Bit 12: Rising edge trigger enable of line 12.

RTEN13

Bit 13: Rising edge trigger enable of line 13.

RTEN14

Bit 14: Rising edge trigger enable of line 14.

RTEN15

Bit 15: Rising edge trigger enable of line 15.

RTEN16

Bit 16: Rising edge trigger enable of line 16.

RTEN17

Bit 17: Rising edge trigger enable of line 17.

RTEN18

Bit 18: Rising edge trigger enable of line 18.

RTEN19

Bit 19: Rising edge trigger enable of line 19.

RTEN20

Bit 20: Rising edge trigger enable of line 20.

RTEN21

Bit 21: Rising edge trigger enable of line 21.

RTEN22

Bit 22: Rising edge trigger enable of line 22.

FTEN

Falling Egde Trigger Enable register (EXTI_FTEN)

Offset: 0xC, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTEN22
rw 		FTEN21
rw 		FTEN20
rw 		FTEN19
rw 		FTEN18
rw 		FTEN17
rw 		FTEN16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTEN15
rw 		FTEN14
rw 		FTEN13
rw 		FTEN12
rw 		FTEN11
rw 		FTEN10
rw 		FTEN9
rw 		FTEN8
rw 		FTEN7
rw 		FTEN6
rw 		FTEN5
rw 		FTEN4
rw 		FTEN3
rw 		FTEN2
rw 		FTEN1
rw 		FTEN0
rw
Toggle Fields.

FTEN0

Bit 0: Falling edge trigger enable of line 0.

FTEN1

Bit 1: Falling edge trigger enable of line 1.

FTEN2

Bit 2: Falling edge trigger enable of line 2.

FTEN3

Bit 3: Falling edge trigger enable of line 3.

FTEN4

Bit 4: Falling edge trigger enable of line 4.

FTEN5

Bit 5: Falling edge trigger enable of line 5.

FTEN6

Bit 6: Falling edge trigger enable of line 6.

FTEN7

Bit 7: Falling edge trigger enable of line 7.

FTEN8

Bit 8: Falling edge trigger enable of line 8.

FTEN9

Bit 9: Falling edge trigger enable of line 9.

FTEN10

Bit 10: Falling edge trigger enable of line 10.

FTEN11

Bit 11: Falling edge trigger enable of line 11.

FTEN12

Bit 12: Falling edge trigger enable of line 12.

FTEN13

Bit 13: Falling edge trigger enable of line 13.

FTEN14

Bit 14: Falling edge trigger enable of line 14.

FTEN15

Bit 15: Falling edge trigger enable of line 15.

FTEN16

Bit 16: Falling edge trigger enable of line 16.

FTEN17

Bit 17: Falling edge trigger enable of line 17.

FTEN18

Bit 18: Falling edge trigger enable of line 18.

FTEN19

Bit 19: Falling edge trigger enable of line 19.

FTEN20

Bit 20: Falling edge trigger enable of line 20.

FTEN21

Bit 21: Falling edge trigger enable of line 21.

FTEN22

Bit 22: Falling edge trigger enable of line 22.

SWIEV

Software interrupt event register (EXTI_SWIEV)

Offset: 0x10, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWIEV22
rw 		SWIEV21
rw 		SWIEV20
rw 		SWIEV19
rw 		SWIEV18
rw 		SWIEV17
rw 		SWIEV16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWIEV15
rw 		SWIEV14
rw 		SWIEV13
rw 		SWIEV12
rw 		SWIEV11
rw 		SWIEV10
rw 		SWIEV9
rw 		SWIEV8
rw 		SWIEV7
rw 		SWIEV6
rw 		SWIEV5
rw 		SWIEV4
rw 		SWIEV3
rw 		SWIEV2
rw 		SWIEV1
rw 		SWIEV0
rw
Toggle Fields.

SWIEV0

Bit 0: Interrupt/Event software trigger on line 0.

SWIEV1

Bit 1: Interrupt/Event software trigger on line 1.

SWIEV2

Bit 2: Interrupt/Event software trigger on line 2.

SWIEV3

Bit 3: Interrupt/Event software trigger on line 3.

SWIEV4

Bit 4: Interrupt/Event software trigger on line 4.

SWIEV5

Bit 5: Interrupt/Event software trigger on line 5.

SWIEV6

Bit 6: Interrupt/Event software trigger on line 6.

SWIEV7

Bit 7: Interrupt/Event software trigger on line 7.

SWIEV8

Bit 8: Interrupt/Event software trigger on line 8.

SWIEV9

Bit 9: Interrupt/Event software trigger on line 9.

SWIEV10

Bit 10: Interrupt/Event software trigger on line 10.

SWIEV11

Bit 11: Interrupt/Event software trigger on line 11.

SWIEV12

Bit 12: Interrupt/Event software trigger on line 12.

SWIEV13

Bit 13: Interrupt/Event software trigger on line 13.

SWIEV14

Bit 14: Interrupt/Event software trigger on line 14.

SWIEV15

Bit 15: Interrupt/Event software trigger on line 15.

SWIEV16

Bit 16: Interrupt/Event software trigger on line 16.

SWIEV17

Bit 17: Interrupt/Event software trigger on line 17.

SWIEV18

Bit 18: Interrupt/Event software trigger on line 18.

SWIEV19

Bit 19: Interrupt/Event software trigger on line 19.

SWIEV20

Bit 20: Interrupt/Event software trigger on line 20.

SWIEV21

Bit 21: Interrupt/Event software trigger on line 21.

SWIEV22

Bit 22: Interrupt/Event software trigger on line 22.

PD

Pending register (EXTI_PD)

Offset: 0x14, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PD22
rw 		PD21
rw 		PD20
rw 		PD19
rw 		PD18
rw 		PD17
rw 		PD16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw 		PD14
rw 		PD13
rw 		PD12
rw 		PD11
rw 		PD10
rw 		PD9
rw 		PD8
rw 		PD7
rw 		PD6
rw 		PD5
rw 		PD4
rw 		PD3
rw 		PD2
rw 		PD1
rw 		PD0
rw
Toggle Fields.

PD0

Bit 0: Interrupt pending status of line 0.

PD1

Bit 1: Interrupt pending status of line 1.

PD2

Bit 2: Interrupt pending status of line 2.

PD3

Bit 3: Interrupt pending status of line 3.

PD4

Bit 4: Interrupt pending status of line 4.

PD5

Bit 5: Interrupt pending status of line 5.

PD6

Bit 6: Interrupt pending status of line 6.

PD7

Bit 7: Interrupt pending status of line 7.

PD8

Bit 8: Interrupt pending status of line 8.

PD9

Bit 9: Interrupt pending status of line 9.

PD10

Bit 10: Interrupt pending status of line 10.

PD11

Bit 11: Interrupt pending status of line 11.

PD12

Bit 12: Interrupt pending status of line 12.

PD13

Bit 13: Interrupt pending status of line 13.

PD14

Bit 14: Interrupt pending status of line 14.

PD15

Bit 15: Interrupt pending status of line 15.

PD16

Bit 16: Interrupt pending status of line 16.

PD17

Bit 17: Interrupt pending status of line 17.

PD18

Bit 18: Interrupt pending status of line 18.

PD19

Bit 19: Interrupt pending status of line 19.

PD20

Bit 20: Interrupt pending status of line 20.

PD21

Bit 21: Interrupt pending status of line 21.

PD22

Bit 22: Interrupt pending status of line 22.

FMC

0x40023C00: FMC

3/34 fields covered. Toggle Registers.

WS

wait state counter register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WSCNT
rw
Toggle Fields.

WSCNT

Bits 0-3: wait state counter register.

KEY

Unlock key register

Offset: 0x4, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-31: FMC_CTL unlock register.

OBKEY

Option byte unlock key register

Offset: 0x8, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OBKEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OBKEY
w
Toggle Fields.

OBKEY

Bits 0-31: FMC_ OBCTL0 option byte operation unlock register.

STAT

Status register

Offset: 0xC, reset: 0x00000000, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDDERR
rw 		PGSERR
rw 		PGMERR
rw 		WPERR
rw 		OPERR
rw 		END
rw
Toggle Fields.

END

Bit 0: End of operation flag bit.

OPERR

Bit 1: Flash operation error flag bit.

WPERR

Bit 4: Erase/Program protection error flag bit.

PGMERR

Bit 6: Program size not match error flag bit.

PGSERR

Bit 7: Program sequence error flag bit.

RDDERR

Bit 8: Read D-bus protection error flag bit.

BUSY

Bit 16: The flash is busy bit.

CTL

Control register

Offset: 0x10, reset: 0x00000080, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LK
rw 		ERRIE
rw 		ENDIE
rw 		START
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MER1
rw 		PSZ
rw 		SN
rw 		MER0
rw 		SER
rw 		PG
rw
Toggle Fields.

PG

Bit 0: main flash program command bit.

SER

Bit 1: main flash sector erase command bit.

MER0

Bit 2: main flash mass erase for bank0 command bit.

SN

Bits 3-7: Select which sector number to be erased..

PSZ

Bits 8-9: Program size bit.

MER1

Bit 15: main flash mass erase for bank1command bit.

START

Bit 16: send erase command to FMC bit.

ENDIE

Bit 24: End of operation interrupt enable bit.

ERRIE

Bit 25: Error interrupt enable bit.

LK

Bit 31: FMC_CTL lock bit.

OBCTL0

Option byte control register 0

Offset: 0x14, reset: 0x2FFFAAED, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DRP
rw 		DBS
rw 		WP0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPC
rw 		nRST_STDBY
rw 		nRST_DPSLP
rw 		nWDG_HW
rw 		BB
rw 		BOR_TH
rw 		OB_START
rw 		OB_LK
rw
Toggle Fields.

OB_LK

Bit 0: FMC_OBCTL0 lock bit.

OB_START

Bit 1: send option byte change command to FMC bit.

BOR_TH

Bits 2-3: option byte BOR threshold value.

BB

Bit 4: option byte boot bank value.

nWDG_HW

Bit 5: option byte watchdog value.

nRST_DPSLP

Bit 6: option byte deepsleep reset value.

nRST_STDBY

Bit 7: option byte standby reset value.

SPC

Bits 8-15: option byte Security Protection code.

WP0

Bits 16-27: Erase/program protection of each sector when DRP is 0.

DBS

Bit 30: Double banks or single bank selection when flash size is 1M.

DRP

Bit 31: D-bus read protection bit.

OBCTL1

Option byte control register 1

Offset: 0x18, reset: 0x0FFF0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WP1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

WP1

Bits 16-27: Erase/program protection of each sector when DRP is 0.

WSEN

Wait state enable register

Offset: 0xFC, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WSEN
r
Toggle Fields.

WSEN

Bit 0: FMC wait state enable register.

PID

Product ID register

Offset: 0x100, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PID
r
Toggle Fields.

PID

Bits 0-31: Product reserved ID code register.

FS_DEVICE

0x50000800: USB on the go full speed device

35/200 fields covered. Toggle Registers.

DCFG

device configuration register (DCFG)

Offset: 0x0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPFT
rw 		DAR
rw 		NZLSOH
rw 		DS
rw
Toggle Fields.

DS

Bits 0-1: Device speed.

NZLSOH

Bit 2: Non-zero-length status OUT handshake.

DAR

Bits 4-10: Device address.

EOPFT

Bits 11-12: end of periodic frame time.

DCTL

device control register (DCTL)

Offset: 0x4, reset: 0x00000000, access: Unspecified

2/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POIF
rw 		CGONAK
w 		SGONAK
w 		CGINAK
w 		SGINAK
w 		GONS
r 		GINS
r 		SD
rw 		RWKUP
rw
Toggle Fields.

RWKUP

Bit 0: Remote wakeup.

SD

Bit 1: Soft disconnect.

GINS

Bit 2: Global IN NAK status.

GONS

Bit 3: Global OUT NAK status.

SGINAK

Bit 7: Set global IN NAK.

CGINAK

Bit 8: Clear global IN NAK.

SGONAK

Bit 9: Set global OUT NAK.

CGONAK

Bit 10: Clear global OUT NAK.

POIF

Bit 11: Power-on initialization flag.

DSTAT

device status register (DSTAT)

Offset: 0x8, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FNRSOF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNRSOF
r 		ES
r 		SPST
r
Toggle Fields.

SPST

Bit 0: Suspend status.

ES

Bits 1-2: Enumerated speed.

FNRSOF

Bits 8-21: Frame number of the received SOF.

DIEPINTEN

device IN endpoint common interrupt mask register (DIEPINTEN)

Offset: 0x10, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFEEN
rw 		IEPNEEN
rw 		EPTXFUDEN
rw 		CITOEN
rw 		EPDISEN
rw 		TFEN
rw
Toggle Fields.

TFEN

Bit 0: Transfer finished interrupt enable.

EPDISEN

Bit 1: Endpoint disabled interrupt enable.

CITOEN

Bit 3: Control IN timeout condition interrupt enable (Non-isochronous endpoints).

EPTXFUDEN

Bit 4: Endpoint Tx FIFO underrun interrupt enable bit.

IEPNEEN

Bit 6: IN endpoint NAK effective interrupt enable.

TXFEEN

Bit 7: Trabsmit FIFO empty interrupt enable.

DOEPINTEN

device OUT endpoint common interrupt enable register (DOEPINTEN)

Offset: 0x14, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTBSTPEN
rw 		EPRXFOVREN
rw 		STPFEN
rw 		EPDISEN
rw 		TFEN
rw
Toggle Fields.

TFEN

Bit 0: Transfer finished interrupt enable.

EPDISEN

Bit 1: Endpoint disabled interrupt enable.

STPFEN

Bit 3: SETUP phase finished interrupt enable.

EPRXFOVREN

Bit 4: Endpoint Rx FIFO overrun interrupt enable.

BTBSTPEN

Bit 6: Back-to-back SETUP packets interrupt enable.

DAEPINT

device all endpoints interrupt register (DAEPINT)

Offset: 0x18, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPITB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPITB
r
Toggle Fields.

IEPITB

Bits 0-3: Device all IN endpoint interrupt bits.

OEPITB

Bits 16-19: Device all OUT endpoint interrupt bits.

DAEPINTEN

Device all endpoints interrupt enable register (DAEPINTEN)

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPIE
rw
Toggle Fields.

IEPIE

Bits 0-3: IN EP interrupt interrupt enable bits.

OEPIE

Bits 16-19: OUT endpoint interrupt enable bits.

DVBUSDT

device VBUS discharge time register

Offset: 0x28, reset: 0x000017D7, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DVBUSDT
rw
Toggle Fields.

DVBUSDT

Bits 0-15: Device VBUS discharge time.

DVBUSPT

device VBUS pulsing time register

Offset: 0x2C, reset: 0x000005B8, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DVBUSPT
rw
Toggle Fields.

DVBUSPT

Bits 0-11: Device VBUS pulsing time.

DIEPFEINTEN

device IN endpoint FIFO empty interrupt enable register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTXFEIE
rw
Toggle Fields.

IEPTXFEIE

Bits 0-3: IN EP Tx FIFO empty interrupt enable bits.

DIEP0CTL

device IN endpoint 0 control register (DIEP0CTL)

Offset: 0x100, reset: 0x00008000, access: Unspecified

3/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYPE
r 		NAKS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
r 		MPL
rw
Toggle Fields.

MPL

Bits 0-1: Maximum packet length.

EPACT

Bit 15: endpoint active.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DIEP0INTF

device endpoint-0 interrupt register

Offset: 0x108, reset: 0x00000080, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r 		IEPNE
rw 		EPTXFUD
rw 		CITO
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint finished.

CITO

Bit 3: Control in timeout interrupt.

EPTXFUD

Bit 4: Endpoint Tx FIFO underrun.

IEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

DIEP0LEN

device IN endpoint-0 transfer length register

Offset: 0x110, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-6: Transfer length.

PCNT

Bits 19-20: Packet count.

DIEP0TFSTAT

device IN endpoint 0 transmit FIFO status register

Offset: 0x118, reset: 0x00000200, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTFS
r
Toggle Fields.

IEPTFS

Bits 0-15: IN endpoint TxFIFO space remaining.

DIEP1CTL

device in endpoint-1 control register

Offset: 0x120, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: Tx FIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVNFRM.

SD1PID_SODDFRM

Bit 29: Set DATA1 PID/Set odd frame.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DIEP1INTF

device endpoint-1 interrupt register

Offset: 0x128, reset: 0x00000080, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r 		IEPNE
rw 		EPTXFUD
rw 		CITO
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint finished.

CITO

Bit 3: Control in timeout interrupt.

EPTXFUD

Bit 4: Endpoint Tx FIFO underrun.

IEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

DIEP1LEN

device IN endpoint-1 transfer length register

Offset: 0x130, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DIEP1TFSTAT

device IN endpoint 1 transmit FIFO status register

Offset: 0x138, reset: 0x00000200, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTFS
r
Toggle Fields.

IEPTFS

Bits 0-15: IN endpoint TxFIFO space remaining.

DIEP2CTL

device endpoint-2 control register

Offset: 0x140, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: Tx FIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVNFRM.

SD1PID_SODDFRM

Bit 29: Set DATA1 PID/Set odd frame.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DIEP2INTF

device endpoint-2 interrupt register

Offset: 0x148, reset: 0x00000080, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r 		IEPNE
rw 		EPTXFUD
rw 		CITO
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint finished.

CITO

Bit 3: Control in timeout interrupt.

EPTXFUD

Bit 4: Endpoint Tx FIFO underrun.

IEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

DIEP2LEN

device IN endpoint-2 transfer length register

Offset: 0x150, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DIEP2TFSTAT

device IN endpoint 2 transmit FIFO status register

Offset: 0x158, reset: 0x00000200, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTFS
r
Toggle Fields.

IEPTFS

Bits 0-15: IN endpoint TxFIFO space remaining.

DIEP3CTL

device endpoint-3 control register

Offset: 0x160, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: Tx FIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVNFRM.

SD1PID_SODDFRM

Bit 29: Set DATA1 PID/Set odd frame.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DIEP3INTF

device endpoint-3 interrupt register

Offset: 0x168, reset: 0x00000080, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFE
r 		IEPNE
rw 		EPTXFUD
rw 		CITO
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint finished.

CITO

Bit 3: Control in timeout interrupt.

EPTXFUD

Bit 4: Endpoint Tx FIFO underrun.

IEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

DIEP3LEN

device IN endpoint-3 transfer length register

Offset: 0x170, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DIEP3TFSTAT

device IN endpoint 3 transmit FIFO status register

Offset: 0x178, reset: 0x00000200, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTFS
r
Toggle Fields.

IEPTFS

Bits 0-15: IN endpoint TxFIFO space remaining.

DOEP0CTL

device endpoint-0 control register

Offset: 0x300, reset: 0x00008000, access: Unspecified

5/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
w 		EPD
r 		SNAK
w 		CNAK
w 		STALL
rw 		SNOOP
rw 		EPTYPE
r 		NAKS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
r 		MPL
r
Toggle Fields.

MPL

Bits 0-1: Maximum packet length.

EPACT

Bit 15: Endpoint active.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

SNOOP

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DOEP0INTF

device out endpoint-0 interrupt flag register

Offset: 0x308, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTBSTP
rw 		EPRXFOVR
rw 		STPF
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint disabled.

STPF

Bit 3: Setup phase finished.

EPRXFOVR

Bit 4: Endpoint Rx FIFO overrun.

BTBSTP

Bit 6: Back-to-back SETUP packets.

DOEP0LEN

device OUT endpoint-0 transfer length register

Offset: 0x310, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STPCNT
rw 		PCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-6: Transfer length.

PCNT

Bit 19: Packet count.

STPCNT

Bits 29-30: SETUP packet count.

DOEP1CTL

device endpoint-1 control register

Offset: 0x320, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNOOP
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

SNOOP

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVENFRM.

SD1PID_SODDFRM

Bit 29: SD1PID/SODDFRM.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DOEP1INTF

device out endpoint-1 interrupt flag register

Offset: 0x328, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTBSTP
rw 		EPRXFOVR
rw 		STPF
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint disabled.

STPF

Bit 3: Setup phase finished.

EPRXFOVR

Bit 4: Endpoint Rx FIFO overrun.

BTBSTP

Bit 6: Back-to-back SETUP packets.

DOEP1LEN

device OUT endpoint-1 transfer length register

Offset: 0x330, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STPCNT_RXDPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

STPCNT_RXDPID

Bits 29-30: SETUP packet count/Received data PID.

DOEP2CTL

device endpoint-2 control register

Offset: 0x340, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNOOP
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

SNOOP

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVENFRM.

SD1PID_SODDFRM

Bit 29: SD1PID/SODDFRM.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DOEP2INTF

device out endpoint-2 interrupt flag register

Offset: 0x348, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTBSTP
rw 		EPRXFOVR
rw 		STPF
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint disabled.

STPF

Bit 3: Setup phase finished.

EPRXFOVR

Bit 4: Endpoint Rx FIFO overrun.

BTBSTP

Bit 6: Back-to-back SETUP packets.

DOEP2LEN

device OUT endpoint-2 transfer length register

Offset: 0x350, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STPCNT_RXDPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

STPCNT_RXDPID

Bits 29-30: SETUP packet count/Received data PID.

DOEP3CTL

device endpoint-3 control register

Offset: 0x360, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNOOP
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

SNOOP

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVENFRM.

SD1PID_SODDFRM

Bit 29: SD1PID/SODDFRM.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DOEP3INTF

device out endpoint-3 interrupt flag register

Offset: 0x368, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTBSTP
rw 		EPRXFOVR
rw 		STPF
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint disabled.

STPF

Bit 3: Setup phase finished.

EPRXFOVR

Bit 4: Endpoint Rx FIFO overrun.

BTBSTP

Bit 6: Back-to-back SETUP packets.

DOEP3LEN

device OUT endpoint-3 transfer length register

Offset: 0x370, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STPCNT_RXDPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

STPCNT_RXDPID

Bits 29-30: SETUP packet count/Received data PID.

FS_GLOBAL

0x50000000: USB full speed global registers

37/118 fields covered. Toggle Registers.

GOTGCS

Global OTG control and status register (USBFS_GOTGCS)

Offset: 0x0, reset: 0x00000800, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSV
r 		ASV
r 		DI
r 		IDPS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DHNPEN
rw 		HHNPEN
rw 		HNPREQ
rw 		HNPS
r 		SRPREQ
rw 		SRPS
r
Toggle Fields.

SRPS

Bit 0: SRP success.

SRPREQ

Bit 1: SRP request.

HNPS

Bit 8: Host success.

HNPREQ

Bit 9: HNP request.

HHNPEN

Bit 10: Host HNP enable.

DHNPEN

Bit 11: Device HNP enabled.

IDPS

Bit 16: ID pin status.

DI

Bit 17: Debounce interval.

ASV

Bit 18: A-session valid.

BSV

Bit 19: B-session valid.

GOTGINTF

Global OTG interrupt flag register (OTG_FS_GOTGINTF)

Offset: 0x4, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DF
rw 		ADTO
rw 		HNPDET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HNPEND
rw 		SRPEND
rw 		SESEND
rw
Toggle Fields.

SESEND

Bit 2: Session end .

SRPEND

Bit 8: Session request success status change.

HNPEND

Bit 9: HNP end.

HNPDET

Bit 17: Host negotiation request detected.

ADTO

Bit 18: A-device timeout.

DF

Bit 19: Debounce finish.

GAHBCS

Global AHB control and status register (USBFS_GAHBCS)

Offset: 0x8, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFTH
rw 		TXFTH
rw 		GINTEN
rw
Toggle Fields.

GINTEN

Bit 0: Global interrupt enable.

TXFTH

Bit 7: Tx FIFO threshold.

PTXFTH

Bit 8: Periodic Tx FIFO threshold.

GUSBCS

Global USB control and status register (OTG_FS_GUSBCSR)

Offset: 0xC, reset: 0x00000A80, access: Unspecified

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDM
rw 		FHM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UTT
rw 		HNPCEN
rw 		SRPCEN
rw 		TOC
rw
Toggle Fields.

TOC

Bits 0-2: Timeout calibration.

SRPCEN

Bit 8: SRP capability enable.

HNPCEN

Bit 9: HNP capability enable.

UTT

Bits 10-13: USB turnaround time.

FHM

Bit 29: Force host mode.

FDM

Bit 30: Force device mode.

GRSTCTL

Global reset control register (USBFS_GRSTCTL)

Offset: 0x10, reset: 0x80000000, access: Unspecified

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFNUM
rw 		TXFF
rw 		RXFF
rw 		HFCRST
rw 		HCSRST
rw 		CSRST
rw
Toggle Fields.

CSRST

Bit 0: Core soft reset.

HCSRST

Bit 1: HCLK soft reset.

HFCRST

Bit 2: Host frame counter reset.

RXFF

Bit 4: RxFIFO flush.

TXFF

Bit 5: TxFIFO flush.

TXFNUM

Bits 6-10: TxFIFO number.

GINTF

Global interrupt flag register (USBFS_GINTF)

Offset: 0x14, reset: 0x04000021, access: Unspecified

11/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPIF
rw 		SESIF
rw 		DISCIF
rw 		IDPSC
rw 		PTXFEIF
r 		HCIF
r 		HPIF
r 		PXNCIF_ISOONCIF
rw 		ISOINCIF
rw 		OEPIF
r 		IEPIF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPFIF
rw 		ISOOPDIF
rw 		ENUMF
rw 		RST
rw 		SP
rw 		ESP
rw 		GONAK
r 		GNPINAK
r 		NPTXFEIF
r 		RXFNEIF
r 		SOF
rw 		OTGIF
r 		MFIF
rw 		COPM
r
Toggle Fields.

COPM

Bit 0: Current operation mode.

MFIF

Bit 1: Mode fault interrupt flag.

OTGIF

Bit 2: OTG interrupt flag.

SOF

Bit 3: Start of frame.

RXFNEIF

Bit 4: RxFIFO non-empty interrupt flag.

NPTXFEIF

Bit 5: Non-periodic TxFIFO empty interrupt flag.

GNPINAK

Bit 6: Global Non-Periodic IN NAK effective.

GONAK

Bit 7: Global OUT NAK effective.

ESP

Bit 10: Early suspend.

SP

Bit 11: USB suspend.

RST

Bit 12: USB reset.

ENUMF

Bit 13: Enumeration finished.

ISOOPDIF

Bit 14: Isochronous OUT packet dropped interrupt.

EOPFIF

Bit 15: End of periodic frame interrupt flag.

IEPIF

Bit 18: IN endpoint interrupt flag.

OEPIF

Bit 19: OUT endpoint interrupt flag.

ISOINCIF

Bit 20: Isochronous IN transfer Not Complete Interrupt Flag.

PXNCIF_ISOONCIF

Bit 21: periodic transfer not complete interrupt flag(Host mode)/isochronous OUT transfer not complete interrupt flag(Device mode).

HPIF

Bit 24: Host port interrupt flag.

HCIF

Bit 25: Host channels interrupt flag.

PTXFEIF

Bit 26: Periodic TxFIFO empty interrupt flag.

IDPSC

Bit 28: ID pin status change.

DISCIF

Bit 29: Disconnect interrupt flag.

SESIF

Bit 30: Session interrupt flag.

WKUPIF

Bit 31: Wakeup interrupt flag.

GINTEN

Global interrupt enable register (USBFS_GINTEN)

Offset: 0x18, reset: 0x00000000, access: Unspecified

1/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPIE
rw 		SESIE
rw 		DISCIE
rw 		IDPSCIE
rw 		PTXFEIE
rw 		HCIE
rw 		HPIE
r 		PXNCIE_ISOONCIE
rw 		ISOINCIE
rw 		OEPIE
rw 		IEPIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPFIE
rw 		ISOOPDIE
rw 		ENUMFIE
rw 		RSTIE
rw 		SPIE
rw 		ESPIE
rw 		GONAKIE
rw 		GNPINAKIE
rw 		NPTXFEIE
rw 		RXFNEIE
rw 		SOFIE
rw 		OTGIE
rw 		MFIE
rw
Toggle Fields.

MFIE

Bit 1: Mode fault interrupt enable.

OTGIE

Bit 2: OTG interrupt enable .

SOFIE

Bit 3: Start of frame interrupt enable.

RXFNEIE

Bit 4: Receive FIFO non-empty interrupt enable.

NPTXFEIE

Bit 5: Non-periodic TxFIFO empty interrupt enable.

GNPINAKIE

Bit 6: Global non-periodic IN NAK effective interrupt enable.

GONAKIE

Bit 7: Global OUT NAK effective interrupt enable.

ESPIE

Bit 10: Early suspend interrupt enable.

SPIE

Bit 11: USB suspend interrupt enable.

RSTIE

Bit 12: USB reset interrupt enable.

ENUMFIE

Bit 13: Enumeration finish interrupt enable.

ISOOPDIE

Bit 14: Isochronous OUT packet dropped interrupt enable.

EOPFIE

Bit 15: End of periodic frame interrupt enable.

IEPIE

Bit 18: IN endpoints interrupt enable.

OEPIE

Bit 19: OUT endpoints interrupt enable.

ISOINCIE

Bit 20: isochronous IN transfer not complete interrupt enable.

PXNCIE_ISOONCIE

Bit 21: periodic transfer not compelete Interrupt enable(Host mode)/isochronous OUT transfer not complete interrupt enable(Device mode).

HPIE

Bit 24: Host port interrupt enable.

HCIE

Bit 25: Host channels interrupt enable.

PTXFEIE

Bit 26: Periodic TxFIFO empty interrupt enable.

IDPSCIE

Bit 28: ID pin status change interrupt enable.

DISCIE

Bit 29: Disconnect interrupt enable.

SESIE

Bit 30: Session interrupt enable.

WKUPIE

Bit 31: Wakeup interrupt enable.

GRSTATR_Host

Global Receive status read(Host mode)

Offset: 0x1C, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPCKST
r 		DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r 		BCOUNT
r 		CNUM
r
Toggle Fields.

CNUM

Bits 0-3: Channel number.

BCOUNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

RPCKST

Bits 17-20: Reivece packet status.

GRSTATP_Host

Global Receive status pop(Host mode)

Offset: 0x20, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPCKST
r 		DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r 		BCOUNT
r 		CNUM
r
Toggle Fields.

CNUM

Bits 0-3: Channel number.

BCOUNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

RPCKST

Bits 17-20: Reivece packet status.

GRFLEN

Global Receive FIFO size register (USBFS_GRFLEN)

Offset: 0x24, reset: 0x00000200, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFD
rw
Toggle Fields.

RXFD

Bits 0-15: Rx FIFO depth.

DIEP0TFLEN

Device IN endpoint 0 transmit FIFO length (Device mode)

Offset: 0x28, reset: 0x02000200, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEP0TXRSAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEP0TXFD
rw
Toggle Fields.

IEP0TXFD

Bits 0-15: in endpoint 0 Tx FIFO depth.

IEP0TXRSAR

Bits 16-31: in endpoint 0 Tx RAM start address.

HNPTFQSTAT

Host non-periodic transmit FIFO/queue status register (HNPTFQSTAT)

Offset: 0x2C, reset: 0x00080200, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPTXRQTOP
r 		NPTXRQS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPTXFS
r
Toggle Fields.

NPTXFS

Bits 0-15: Non-periodic TxFIFO space.

NPTXRQS

Bits 16-23: Non-periodic transmit request queue space .

NPTXRQTOP

Bits 24-30: Top of the non-periodic transmit request queue.

GCCFG

Global core configuration register (USBFS_GCCFG)

Offset: 0x38, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VBUSIG
rw 		SOFOEN
rw 		VBUSBCEN
rw 		VBUSACEN
rw 		PWRON
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PWRON

Bit 16: Power on.

VBUSACEN

Bit 18: The VBUS A-device Comparer enable.

VBUSBCEN

Bit 19: The VBUS B-device Comparer enable.

SOFOEN

Bit 20: SOF output enable.

VBUSIG

Bit 21: VBUS ignored.

CID

core ID register

Offset: 0x3C, reset: 0x00001000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CID
rw
Toggle Fields.

CID

Bits 0-31: Core ID.

HPTFLEN

Host periodic transmit FIFO length register (HPTFLEN)

Offset: 0x100, reset: 0x02000600, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HPTXFSAR
rw
Toggle Fields.

HPTXFSAR

Bits 0-15: Host periodic TxFIFO start address.

HPTXFD

Bits 16-31: Host periodic TxFIFO depth.

DIEP1TFLEN

device IN endpoint transmit FIFO size register (DIEP1TFLEN)

Offset: 0x104, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTXRSAR
rw
Toggle Fields.

IEPTXRSAR

Bits 0-15: IN endpoint FIFO transmit RAM start address.

IEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEP2TFLEN

device IN endpoint transmit FIFO size register (DIEP2TFLEN)

Offset: 0x108, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTXRSAR
rw
Toggle Fields.

IEPTXRSAR

Bits 0-15: IN endpoint FIFO transmit RAM start address.

IEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEP3TFLEN

device IN endpoint transmit FIFO size register (FS_DIEP3TXFLEN)

Offset: 0x10C, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTXRSAR
rw
Toggle Fields.

IEPTXRSAR

Bits 0-15: IN endpoint FIFO4 transmit RAM start address.

IEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

FS_HOST

0x50000400: USB on the go full speed host

9/259 fields covered. Toggle Registers.

HCTL

host configuration register (HCTL)

Offset: 0x0, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKSEL
rw
Toggle Fields.

CLKSEL

Bits 0-1: clock select for USB clock.

HFT

Host frame interval register

Offset: 0x4, reset: 0x0000BB80, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRI
rw
Toggle Fields.

FRI

Bits 0-15: Frame interval.

HFINFR

OTG_FS host frame number/frame time remaining register (HFINFR)

Offset: 0x8, reset: 0xBB800000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRNUM
r
Toggle Fields.

FRNUM

Bits 0-15: Frame number.

FRT

Bits 16-31: Frame remaining time.

HPTFQSTAT

Host periodic transmit FIFO/queue status register (HPTFQSTAT)

Offset: 0x10, reset: 0x00080200, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTXREQT
r 		PTXREQS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFS
r
Toggle Fields.

PTXFS

Bits 0-15: Periodic transmit data FIFO space available.

PTXREQS

Bits 16-23: Periodic transmit request queue space available.

PTXREQT

Bits 24-31: Top of the periodic transmit request queue.

HACHINT

Host all channels interrupt register

Offset: 0x14, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HACHINT
r
Toggle Fields.

HACHINT

Bits 0-7: Host all channel interrupts.

HACHINTEN

host all channels interrupt mask register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CINTEN
rw
Toggle Fields.

CINTEN

Bits 0-7: Channel interrupt enable.

HPCS

Host port control and status register (USBFS_HPCS)

Offset: 0x40, reset: 0x00000000, access: Unspecified

3/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PP
rw 		PLST
r 		PRST
rw 		PSP
rw 		PREM
rw 		PEDC
rw 		PE
rw 		PCD
rw 		PCST
r
Toggle Fields.

PCST

Bit 0: Port connect status.

PCD

Bit 1: Port connect detected.

PE

Bit 2: Port enable.

PEDC

Bit 3: Port enable/disable change.

PREM

Bit 6: Port resume.

PSP

Bit 7: Port suspend.

PRST

Bit 8: Port reset.

PLST

Bits 10-11: Port line status.

PP

Bit 12: Port power.

PS

Bits 17-18: Port speed.

HCH0CTL

host channel-0 characteristics register (HCH0CTL)

Offset: 0x100, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH0INTF

host channel-0 interrupt register (USBFS_HCHxINTF)

Offset: 0x108, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

CH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH0INTEN

host channel-0 interrupt enable register (HCH0INTEN)

Offset: 0x10C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer completed interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH0LEN

host channel-0 transfer length register

Offset: 0x110, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

HCH1CTL

host channel-1 characteristics register (HCH1CTL)

Offset: 0x120, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH1INTF

host channel-1 interrupt register (HCH1INTF)

Offset: 0x128, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

CH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH1INTEN

host channel-1 interrupt enable register (HCH1INTEN)

Offset: 0x12C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer completed interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH1LEN

host channel-1 transfer length register

Offset: 0x130, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

HCH2CTL

host channel-2 characteristics register (HCH2CTL)

Offset: 0x140, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH2INTF

host channel-2 interrupt register (HCH2INTF)

Offset: 0x148, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

CH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH2INTEN

host channel-2 interrupt enable register (HCH2INTEN)

Offset: 0x14C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer completed interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH2LEN

host channel-2 transfer length register

Offset: 0x150, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

HCH3CTL

host channel-3 characteristics register (HCH3CTL)

Offset: 0x160, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH3INTF

host channel-3 interrupt register (HCH3INTF)

Offset: 0x168, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

CH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH3INTEN

host channel-3 interrupt enable register (HCH3INTEN)

Offset: 0x16C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer completed interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH3LEN

host channel-3 transfer length register

Offset: 0x170, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

HCH4CTL

host channel-4 characteristics register (HCH4CTL)

Offset: 0x180, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH4INTF

host channel-4 interrupt register (HCH4INTF)

Offset: 0x188, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

CH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH4INTEN

host channel-4 interrupt enable register (HCH4INTEN)

Offset: 0x18C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer completed interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH4LEN

host channel-4 transfer length register

Offset: 0x190, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

HCH5CTL

host channel-5 characteristics register (HCH5CTL)

Offset: 0x1A0, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH5INTF

host channel-5 interrupt register (HCH5INTF)

Offset: 0x1A8, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

CH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH5INTEN

host channel-5 interrupt enable register (HCH5INTEN)

Offset: 0x1AC, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer completed interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH5LEN

host channel-5 transfer length register

Offset: 0x1B0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

HCH6CTL

host channel-6 characteristics register (HCH6CTL)

Offset: 0x1C0, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH6INTF

host channel-6 interrupt register (HCH6INTF)

Offset: 0x1C8, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

CH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH6INTEN

host channel-6 interrupt enable register (HCH6INTEN)

Offset: 0x1CC, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer completed interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH6LEN

host channel-6 transfer length register

Offset: 0x1D0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

HCH7CTL

host channel-7 characteristics register (HCH7CTL)

Offset: 0x1E0, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH7INTF

host channel-7 interrupt register (HCH7INTF)

Offset: 0x1E8, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		ACK
rw 		NAK
rw 		STALL
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

CH

Bit 1: Channel halted.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH7INTEN

host channel-7 interrupt enable register (HCH7INTEN)

Offset: 0x1EC, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer completed interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH7LEN

host channel-7 transfer length register

Offset: 0x1F0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

FS_PWRCLK

0x50000E00: USB on the go full speed

0/2 fields covered. Toggle Registers.

PWRCLKCTL

power and clock gating control register (PWRCLKCTL)

Offset: 0x0, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHCLK
rw 		SUCLK
rw
Toggle Fields.

SUCLK

Bit 0: Stop the USB clock.

SHCLK

Bit 1: Stop HCLK.

FWDGT

0x40003000: free watchdog timer

2/5 fields covered. Toggle Registers.

CTL

Control register

Offset: 0x0, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMD
w
Toggle Fields.

CMD

Bits 0-15: Key value.

PSC

Prescaler register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-2: Prescaler divider.

RLD

Reload register

Offset: 0x8, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RLD
rw
Toggle Fields.

RLD

Bits 0-11: Free watchdog timer counter reload value.

STAT

Status register

Offset: 0xC, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RUD
r 		PUD
r
Toggle Fields.

PUD

Bit 0: Free watchdog timer prescaler value update.

RUD

Bit 1: Free watchdog timer counter reload value update.

GPIOA

0x40020000: General-purpose I/Os

16/193 fields covered. Toggle Registers.

CTL

GPIO port control register

Offset: 0x0, reset: 0xA8000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		CTL14
rw 		CTL13
rw 		CTL12
rw 		CTL11
rw 		CTL10
rw 		CTL9
rw 		CTL8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL7
rw 		CTL6
rw 		CTL5
rw 		CTL4
rw 		CTL3
rw 		CTL2
rw 		CTL1
rw 		CTL0
rw
Toggle Fields.

CTL0

Bits 0-1: Port x configuration bits (x = 0).

CTL1

Bits 2-3: Port x configuration bits (x = 1).

CTL2

Bits 4-5: Port x configuration bits (x = 2).

CTL3

Bits 6-7: Port x configuration bits (x = 3).

CTL4

Bits 8-9: Port x configuration bits (x = 4 ).

CTL5

Bits 10-11: Port x configuration bits (x = 5).

CTL6

Bits 12-13: Port x configuration bits (x = 6 ).

CTL7

Bits 14-15: Port x configuration bits (x = 7).

CTL8

Bits 16-17: Port x configuration bits (x = 8).

CTL9

Bits 18-19: Port x configuration bits (x = 9).

CTL10

Bits 20-21: Port x configuration bits (x = 10).

CTL11

Bits 22-23: Port x configuration bits (x = 11).

CTL12

Bits 24-25: Port x configuration bits (x = 12).

CTL13

Bits 26-27: Port x configuration bits (x = 13).

CTL14

Bits 28-29: Port x configuration bits (x = 14).

CTL15

Bits 30-31: Port x configuration bits (x = 15).

OMODE

GPIO port output mode register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OM15
rw 		OM14
rw 		OM13
rw 		OM12
rw 		OM11
rw 		OM10
rw 		OM9
rw 		OM8
rw 		OM7
rw 		OM6
rw 		OM5
rw 		OM4
rw 		OM3
rw 		OM2
rw 		OM1
rw 		OM0
rw
Toggle Fields.

OM0

Bit 0: Port 0 output mode bit.

OM1

Bit 1: Port 1 output mode bit.

OM2

Bit 2: Port 2 output mode bit.

OM3

Bit 3: Port 3 output mode bit.

OM4

Bit 4: Port 4 output mode bit.

OM5

Bit 5: Port 5 output mode bit.

OM6

Bit 6: Port 6 output mode bit.

OM7

Bit 7: Port 7 output mode bit.

OM8

Bit 8: Port 8 output mode bit.

OM9

Bit 9: Port 9 output mode bit.

OM10

Bit 10: Port 10 output mode bit.

OM11

Bit 11: Port 11 output mode bit.

OM12

Bit 12: Port 12 output mode bit.

OM13

Bit 13: Port 13 output mode bit.

OM14

Bit 14: Port 14 output mode bit.

OM15

Bit 15: Port 15 output mode bit.

OSPD

GPIO port output speed register

Offset: 0x8, reset: 0x0C000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPD15
rw 		OSPD14
rw 		OSPD13
rw 		OSPD12
rw 		OSPD11
rw 		OSPD10
rw 		OSPD9
rw 		OSPD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPD7
rw 		OSPD6
rw 		OSPD5
rw 		OSPD4
rw 		OSPD3
rw 		OSPD2
rw 		OSPD1
rw 		OSPD0
rw
Toggle Fields.

OSPD0

Bits 0-1: Port 0 output max speed bits.

OSPD1

Bits 2-3: Port 1 output max speed bits.

OSPD2

Bits 4-5: Port 2 output max speed bits.

OSPD3

Bits 6-7: Port 3 output max speed bits.

OSPD4

Bits 8-9: Port 4 output max speed bits.

OSPD5

Bits 10-11: Port 5 output max speed bits.

OSPD6

Bits 12-13: Port 6 output max speed bits.

OSPD7

Bits 14-15: Port 7 output max speed bits.

OSPD8

Bits 16-17: Port 8 output max speed bits.

OSPD9

Bits 18-19: Port 9 output max speed bits.

OSPD10

Bits 20-21: Port 10 output max speed bits.

OSPD11

Bits 22-23: Port 11 output max speed bits.

OSPD12

Bits 24-25: Port 12 output max speed bits.

OSPD13

Bits 26-27: Port 13 output max speed bits.

OSPD14

Bits 28-29: Port 14 output max speed bits.

OSPD15

Bits 30-31: Port 15 output max speed bits.

PUD

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x64000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUD15
rw 		PUD14
rw 		PUD13
rw 		PUD12
rw 		PUD11
rw 		PUD10
rw 		PUD9
rw 		PUD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUD7
rw 		PUD6
rw 		PUD5
rw 		PUD4
rw 		PUD3
rw 		PUD2
rw 		PUD1
rw 		PUD0
rw
Toggle Fields.

PUD0

Bits 0-1: Port 0 pull-up or pull-down bits.

PUD1

Bits 2-3: Port 1 pull-up or pull-down bits.

PUD2

Bits 4-5: Port 2 pull-up or pull-down bits.

PUD3

Bits 6-7: Port 3 pull-up or pull-down bits.

PUD4

Bits 8-9: Port 4 pull-up or pull-down bits.

PUD5

Bits 10-11: Port 5 pull-up or pull-down bits.

PUD6

Bits 12-13: Port 6 pull-up or pull-down bits.

PUD7

Bits 14-15: Port 7 pull-up or pull-down bits.

PUD8

Bits 16-17: Port 8 pull-up or pull-down bits.

PUD9

Bits 18-19: Port 9 pull-up or pull-down bits.

PUD10

Bits 20-21: Port 10 pull-up or pull-down bits.

PUD11

Bits 22-23: Port 11 pull-up or pull-down bits.

PUD12

Bits 24-25: Port 12 pull-up or pull-down bits.

PUD13

Bits 26-27: Port 13 pull-up or pull-down bits.

PUD14

Bits 28-29: Port 14 pull-up or pull-down bits.

PUD15

Bits 30-31: Port 15 pull-up or pull-down bits.

ISTAT

GPIO port input status register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status (y = 0).

ISTAT1

Bit 1: Port input status (y = 1).

ISTAT2

Bit 2: Port input status (y = 2).

ISTAT3

Bit 3: Port input status (y = 3).

ISTAT4

Bit 4: Port input status (y = 4).

ISTAT5

Bit 5: Port input status (y = 5).

ISTAT6

Bit 6: Port input status (y = 6).

ISTAT7

Bit 7: Port input status (y = 7).

ISTAT8

Bit 8: Port input status (y = 8).

ISTAT9

Bit 9: Port input status (y = 9).

ISTAT10

Bit 10: Port input status (y = 10).

ISTAT11

Bit 11: Port input status (y = 11).

ISTAT12

Bit 12: Port input status (y = 12).

ISTAT13

Bit 13: Port input status (y = 13).

ISTAT14

Bit 14: Port input status (y = 14).

ISTAT15

Bit 15: Port input status (y = 15).

OCTL

GPIO port output control register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control (y = 0).

OCTL1

Bit 1: Port output control (y = 1).

OCTL2

Bit 2: Port output control (y = 2).

OCTL3

Bit 3: Port output control (y = 3).

OCTL4

Bit 4: Port output control (y = 4).

OCTL5

Bit 5: Port output control (y = 5).

OCTL6

Bit 6: Port output control (y = 6).

OCTL7

Bit 7: Port output control (y = 7).

OCTL8

Bit 8: Port output control (y = 8).

OCTL9

Bit 9: Port output control (y = 9).

OCTL10

Bit 10: Port output control (y = 10).

OCTL11

Bit 11: Port output control (y = 11).

OCTL12

Bit 12: Port output control (y = 12).

OCTL13

Bit 13: Port output control (y = 13).

OCTL14

Bit 14: Port output control (y = 14).

OCTL15

Bit 15: Port output control (y = 15).

BOP

GPIO port bit operate register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port Set bit 0.

BOP1

Bit 1: Port Set bit 1.

BOP2

Bit 2: Port Set bit 2.

BOP3

Bit 3: Port Set bit 3.

BOP4

Bit 4: Port Set bit 4.

BOP5

Bit 5: Port Set bit 5.

BOP6

Bit 6: Port Set bit 6.

BOP7

Bit 7: Port Set bit 7.

BOP8

Bit 8: Port Set bit 8.

BOP9

Bit 9: Port Set bit 9.

BOP10

Bit 10: Port Set bit 10.

BOP11

Bit 11: Port Set bit 11.

BOP12

Bit 12: Port Set bit 12.

BOP13

Bit 13: Port Set bit 13.

BOP14

Bit 14: Port Set bit 14.

BOP15

Bit 15: Port Set bit 15.

CR0

Bit 16: Port Clear bit 0.

CR1

Bit 17: Port Clear bit 1.

CR2

Bit 18: Port Clear bit 2.

CR3

Bit 19: Port Clear bit 3.

CR4

Bit 20: Port Clear bit 4.

CR5

Bit 21: Port Clear bit 5.

CR6

Bit 22: Port Clear bit 6.

CR7

Bit 23: Port Clear bit 7.

CR8

Bit 24: Port Clear bit 8.

CR9

Bit 25: Port Clear bit 9.

CR10

Bit 26: Port Clear bit 10.

CR11

Bit 27: Port Clear bit 11.

CR12

Bit 28: Port Clear bit 12.

CR13

Bit 29: Port Clear bit 13.

CR14

Bit 30: Port Clear bit 14.

CR15

Bit 31: Port Clear bit 15.

LOCK

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

LK1

Bit 1: Port Lock bit 1.

LK2

Bit 2: Port Lock bit 2.

LK3

Bit 3: Port Lock bit 3.

LK4

Bit 4: Port Lock bit 4.

LK5

Bit 5: Port Lock bit 5.

LK6

Bit 6: Port Lock bit 6.

LK7

Bit 7: Port Lock bit 7.

LK8

Bit 8: Port Lock bit 8.

LK9

Bit 9: Port Lock bit 9.

LK10

Bit 10: Port Lock bit 10.

LK11

Bit 11: Port Lock bit 11.

LK12

Bit 12: Port Lock bit 12.

LK13

Bit 13: Port Lock bit 13.

LK14

Bit 14: Port Lock bit 14.

LK15

Bit 15: Port Lock bit 15.

LKK

Bit 16: Lock sequence key .

AFSEL0

GPIO alternate function selected register 0

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL7
rw 		SEL6
rw 		SEL5
rw 		SEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL3
rw 		SEL2
rw 		SEL1
rw 		SEL0
rw
Toggle Fields.

SEL0

Bits 0-3: Port 0 alternate function selected.

SEL1

Bits 4-7: Port 1 alternate function selected.

SEL2

Bits 8-11: Port 2 alternate function selected.

SEL3

Bits 12-15: Port 3 alternate function selected.

SEL4

Bits 16-19: Port 4 alternate function selected.

SEL5

Bits 20-23: Port 5 alternate function selected.

SEL6

Bits 24-27: Port 6 alternate function selected.

SEL7

Bits 28-31: Port 7 alternate function selected.

AFSEL1

GPIO alternate function selected register 1

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL15
rw 		SEL14
rw 		SEL13
rw 		SEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL11
rw 		SEL10
rw 		SEL9
rw 		SEL8
rw
Toggle Fields.

SEL8

Bits 0-3: Port 8 alternate function selected.

SEL9

Bits 4-7: Port 9 alternate function selected.

SEL10

Bits 8-11: Port 10 alternate function selected.

SEL11

Bits 12-15: Port 11 alternate function selected.

SEL12

Bits 16-19: Port 12 alternate function selected.

SEL13

Bits 20-23: Port 13 alternate function selected.

SEL14

Bits 24-27: Port 14 alternate function selected.

SEL15

Bits 28-31: Port 15 alternate function selected.

BC

Bit clear register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port cleat bit.

CR1

Bit 1: Port cleat bit.

CR2

Bit 2: Port cleat bit.

CR3

Bit 3: Port cleat bit.

CR4

Bit 4: Port cleat bit.

CR5

Bit 5: Port cleat bit.

CR6

Bit 6: Port cleat bit.

CR7

Bit 7: Port cleat bit.

CR8

Bit 8: Port cleat bit.

CR9

Bit 9: Port cleat bit.

CR10

Bit 10: Port cleat bit.

CR11

Bit 11: Port cleat bit.

CR12

Bit 12: Port cleat bit.

CR13

Bit 13: Port cleat bit.

CR14

Bit 14: Port cleat bit.

CR15

Bit 15: Port cleat bit.

TG

Port bit toggle register

Offset: 0x2C, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG15
w 		TG14
w 		TG13
w 		TG12
w 		TG11
w 		TG10
w 		TG9
w 		TG8
w 		TG7
w 		TG6
w 		TG5
w 		TG4
w 		TG3
w 		TG2
w 		TG1
w 		TG0
w
Toggle Fields.

TG0

Bit 0: Port toggle bit .

TG1

Bit 1: Port toggle bit.

TG2

Bit 2: Port toggle bit.

TG3

Bit 3: Port toggle bit.

TG4

Bit 4: Port toggle bit.

TG5

Bit 5: Port toggle bit.

TG6

Bit 6: Port toggle bit.

TG7

Bit 7: Port toggle bit.

TG8

Bit 8: Port toggle bit.

TG9

Bit 9: Port toggle bit.

TG10

Bit 10: Port toggle bit.

TG11

Bit 11: Port toggle bit.

TG12

Bit 12: Port toggle bit.

TG13

Bit 13: Port toggle bit.

TG14

Bit 14: Port toggle bit.

TG15

Bit 15: Port toggle bit.

GPIOB

0x40020400: General-purpose I/Os

16/193 fields covered. Toggle Registers.

CTL

GPIO port control register

Offset: 0x0, reset: 0x00000280, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		CTL14
rw 		CTL13
rw 		CTL12
rw 		CTL11
rw 		CTL10
rw 		CTL9
rw 		CTL8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL7
rw 		CTL6
rw 		CTL5
rw 		CTL4
rw 		CTL3
rw 		CTL2
rw 		CTL1
rw 		CTL0
rw
Toggle Fields.

CTL0

Bits 0-1: Port x configuration bits (x = 0).

CTL1

Bits 2-3: Port x configuration bits (x = 1).

CTL2

Bits 4-5: Port x configuration bits (x = 2).

CTL3

Bits 6-7: Port x configuration bits (x = 3).

CTL4

Bits 8-9: Port x configuration bits (x = 4 ).

CTL5

Bits 10-11: Port x configuration bits (x = 5).

CTL6

Bits 12-13: Port x configuration bits (x = 6 ).

CTL7

Bits 14-15: Port x configuration bits (x = 7).

CTL8

Bits 16-17: Port x configuration bits (x = 8).

CTL9

Bits 18-19: Port x configuration bits (x = 9).

CTL10

Bits 20-21: Port x configuration bits (x = 10).

CTL11

Bits 22-23: Port x configuration bits (x = 11).

CTL12

Bits 24-25: Port x configuration bits (x = 12).

CTL13

Bits 26-27: Port x configuration bits (x = 13).

CTL14

Bits 28-29: Port x configuration bits (x = 14).

CTL15

Bits 30-31: Port x configuration bits (x = 15).

OMODE

GPIO port output mode register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OM15
rw 		OM14
rw 		OM13
rw 		OM12
rw 		OM11
rw 		OM10
rw 		OM9
rw 		OM8
rw 		OM7
rw 		OM6
rw 		OM5
rw 		OM4
rw 		OM3
rw 		OM2
rw 		OM1
rw 		OM0
rw
Toggle Fields.

OM0

Bit 0: Port 0 output mode bit.

OM1

Bit 1: Port 1 output mode bit.

OM2

Bit 2: Port 2 output mode bit.

OM3

Bit 3: Port 3 output mode bit.

OM4

Bit 4: Port 4 output mode bit.

OM5

Bit 5: Port 5 output mode bit.

OM6

Bit 6: Port 6 output mode bit.

OM7

Bit 7: Port 7 output mode bit.

OM8

Bit 8: Port 8 output mode bit.

OM9

Bit 9: Port 9 output mode bit.

OM10

Bit 10: Port 10 output mode bit.

OM11

Bit 11: Port 11 output mode bit.

OM12

Bit 12: Port 12 output mode bit.

OM13

Bit 13: Port 13 output mode bit.

OM14

Bit 14: Port 14 output mode bit.

OM15

Bit 15: Port 15 output mode bit.

OSPD

GPIO port output speed register

Offset: 0x8, reset: 0x000000C0, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPD15
rw 		OSPD14
rw 		OSPD13
rw 		OSPD12
rw 		OSPD11
rw 		OSPD10
rw 		OSPD9
rw 		OSPD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPD7
rw 		OSPD6
rw 		OSPD5
rw 		OSPD4
rw 		OSPD3
rw 		OSPD2
rw 		OSPD1
rw 		OSPD0
rw
Toggle Fields.

OSPD0

Bits 0-1: Port 0 output max speed bits.

OSPD1

Bits 2-3: Port 1 output max speed bits.

OSPD2

Bits 4-5: Port 2 output max speed bits.

OSPD3

Bits 6-7: Port 3 output max speed bits.

OSPD4

Bits 8-9: Port 4 output max speed bits.

OSPD5

Bits 10-11: Port 5 output max speed bits.

OSPD6

Bits 12-13: Port 6 output max speed bits.

OSPD7

Bits 14-15: Port 7 output max speed bits.

OSPD8

Bits 16-17: Port 8 output max speed bits.

OSPD9

Bits 18-19: Port 9 output max speed bits.

OSPD10

Bits 20-21: Port 10 output max speed bits.

OSPD11

Bits 22-23: Port 11 output max speed bits.

OSPD12

Bits 24-25: Port 12 output max speed bits.

OSPD13

Bits 26-27: Port 13 output max speed bits.

OSPD14

Bits 28-29: Port 14 output max speed bits.

OSPD15

Bits 30-31: Port 15 output max speed bits.

PUD

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000100, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUD15
rw 		PUD14
rw 		PUD13
rw 		PUD12
rw 		PUD11
rw 		PUD10
rw 		PUD9
rw 		PUD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUD7
rw 		PUD6
rw 		PUD5
rw 		PUD4
rw 		PUD3
rw 		PUD2
rw 		PUD1
rw 		PUD0
rw
Toggle Fields.

PUD0

Bits 0-1: Port 0 pull-up or pull-down bits.

PUD1

Bits 2-3: Port 1 pull-up or pull-down bits.

PUD2

Bits 4-5: Port 2 pull-up or pull-down bits.

PUD3

Bits 6-7: Port 3 pull-up or pull-down bits.

PUD4

Bits 8-9: Port 4 pull-up or pull-down bits.

PUD5

Bits 10-11: Port 5 pull-up or pull-down bits.

PUD6

Bits 12-13: Port 6 pull-up or pull-down bits.

PUD7

Bits 14-15: Port 7 pull-up or pull-down bits.

PUD8

Bits 16-17: Port 8 pull-up or pull-down bits.

PUD9

Bits 18-19: Port 9 pull-up or pull-down bits.

PUD10

Bits 20-21: Port 10 pull-up or pull-down bits.

PUD11

Bits 22-23: Port 11 pull-up or pull-down bits.

PUD12

Bits 24-25: Port 12 pull-up or pull-down bits.

PUD13

Bits 26-27: Port 13 pull-up or pull-down bits.

PUD14

Bits 28-29: Port 14 pull-up or pull-down bits.

PUD15

Bits 30-31: Port 15 pull-up or pull-down bits.

ISTAT

GPIO port input status register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status (y = 0).

ISTAT1

Bit 1: Port input status (y = 1).

ISTAT2

Bit 2: Port input status (y = 2).

ISTAT3

Bit 3: Port input status (y = 3).

ISTAT4

Bit 4: Port input status (y = 4).

ISTAT5

Bit 5: Port input status (y = 5).

ISTAT6

Bit 6: Port input status (y = 6).

ISTAT7

Bit 7: Port input status (y = 7).

ISTAT8

Bit 8: Port input status (y = 8).

ISTAT9

Bit 9: Port input status (y = 9).

ISTAT10

Bit 10: Port input status (y = 10).

ISTAT11

Bit 11: Port input status (y = 11).

ISTAT12

Bit 12: Port input status (y = 12).

ISTAT13

Bit 13: Port input status (y = 13).

ISTAT14

Bit 14: Port input status (y = 14).

ISTAT15

Bit 15: Port input status (y = 15).

OCTL

GPIO port output control register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control (y = 0).

OCTL1

Bit 1: Port output control (y = 1).

OCTL2

Bit 2: Port output control (y = 2).

OCTL3

Bit 3: Port output control (y = 3).

OCTL4

Bit 4: Port output control (y = 4).

OCTL5

Bit 5: Port output control (y = 5).

OCTL6

Bit 6: Port output control (y = 6).

OCTL7

Bit 7: Port output control (y = 7).

OCTL8

Bit 8: Port output control (y = 8).

OCTL9

Bit 9: Port output control (y = 9).

OCTL10

Bit 10: Port output control (y = 10).

OCTL11

Bit 11: Port output control (y = 11).

OCTL12

Bit 12: Port output control (y = 12).

OCTL13

Bit 13: Port output control (y = 13).

OCTL14

Bit 14: Port output control (y = 14).

OCTL15

Bit 15: Port output control (y = 15).

BOP

GPIO port bit operate register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port Set bit 0.

BOP1

Bit 1: Port Set bit 1.

BOP2

Bit 2: Port Set bit 2.

BOP3

Bit 3: Port Set bit 3.

BOP4

Bit 4: Port Set bit 4.

BOP5

Bit 5: Port Set bit 5.

BOP6

Bit 6: Port Set bit 6.

BOP7

Bit 7: Port Set bit 7.

BOP8

Bit 8: Port Set bit 8.

BOP9

Bit 9: Port Set bit 9.

BOP10

Bit 10: Port Set bit 10.

BOP11

Bit 11: Port Set bit 11.

BOP12

Bit 12: Port Set bit 12.

BOP13

Bit 13: Port Set bit 13.

BOP14

Bit 14: Port Set bit 14.

BOP15

Bit 15: Port Set bit 15.

CR0

Bit 16: Port Clear bit 0.

CR1

Bit 17: Port Clear bit 1.

CR2

Bit 18: Port Clear bit 2.

CR3

Bit 19: Port Clear bit 3.

CR4

Bit 20: Port Clear bit 4.

CR5

Bit 21: Port Clear bit 5.

CR6

Bit 22: Port Clear bit 6.

CR7

Bit 23: Port Clear bit 7.

CR8

Bit 24: Port Clear bit 8.

CR9

Bit 25: Port Clear bit 9.

CR10

Bit 26: Port Clear bit 10.

CR11

Bit 27: Port Clear bit 11.

CR12

Bit 28: Port Clear bit 12.

CR13

Bit 29: Port Clear bit 13.

CR14

Bit 30: Port Clear bit 14.

CR15

Bit 31: Port Clear bit 15.

LOCK

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

LK1

Bit 1: Port Lock bit 1.

LK2

Bit 2: Port Lock bit 2.

LK3

Bit 3: Port Lock bit 3.

LK4

Bit 4: Port Lock bit 4.

LK5

Bit 5: Port Lock bit 5.

LK6

Bit 6: Port Lock bit 6.

LK7

Bit 7: Port Lock bit 7.

LK8

Bit 8: Port Lock bit 8.

LK9

Bit 9: Port Lock bit 9.

LK10

Bit 10: Port Lock bit 10.

LK11

Bit 11: Port Lock bit 11.

LK12

Bit 12: Port Lock bit 12.

LK13

Bit 13: Port Lock bit 13.

LK14

Bit 14: Port Lock bit 14.

LK15

Bit 15: Port Lock bit 15.

LKK

Bit 16: Lock sequence key .

AFSEL0

GPIO alternate function selected register 0

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL7
rw 		SEL6
rw 		SEL5
rw 		SEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL3
rw 		SEL2
rw 		SEL1
rw 		SEL0
rw
Toggle Fields.

SEL0

Bits 0-3: Port 0 alternate function selected.

SEL1

Bits 4-7: Port 1 alternate function selected.

SEL2

Bits 8-11: Port 2 alternate function selected.

SEL3

Bits 12-15: Port 3 alternate function selected.

SEL4

Bits 16-19: Port 4 alternate function selected.

SEL5

Bits 20-23: Port 5 alternate function selected.

SEL6

Bits 24-27: Port 6 alternate function selected.

SEL7

Bits 28-31: Port 7 alternate function selected.

AFSEL1

GPIO alternate function selected register 1

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL15
rw 		SEL14
rw 		SEL13
rw 		SEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL11
rw 		SEL10
rw 		SEL9
rw 		SEL8
rw
Toggle Fields.

SEL8

Bits 0-3: Port 8 alternate function selected.

SEL9

Bits 4-7: Port 9 alternate function selected.

SEL10

Bits 8-11: Port 10 alternate function selected.

SEL11

Bits 12-15: Port 11 alternate function selected.

SEL12

Bits 16-19: Port 12 alternate function selected.

SEL13

Bits 20-23: Port 13 alternate function selected.

SEL14

Bits 24-27: Port 14 alternate function selected.

SEL15

Bits 28-31: Port 15 alternate function selected.

BC

Bit clear register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port cleat bit.

CR1

Bit 1: Port cleat bit.

CR2

Bit 2: Port cleat bit.

CR3

Bit 3: Port cleat bit.

CR4

Bit 4: Port cleat bit.

CR5

Bit 5: Port cleat bit.

CR6

Bit 6: Port cleat bit.

CR7

Bit 7: Port cleat bit.

CR8

Bit 8: Port cleat bit.

CR9

Bit 9: Port cleat bit.

CR10

Bit 10: Port cleat bit.

CR11

Bit 11: Port cleat bit.

CR12

Bit 12: Port cleat bit.

CR13

Bit 13: Port cleat bit.

CR14

Bit 14: Port cleat bit.

CR15

Bit 15: Port cleat bit.

TG

Port bit toggle register

Offset: 0x2C, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG15
w 		TG14
w 		TG13
w 		TG12
w 		TG11
w 		TG10
w 		TG9
w 		TG8
w 		TG7
w 		TG6
w 		TG5
w 		TG4
w 		TG3
w 		TG2
w 		TG1
w 		TG0
w
Toggle Fields.

TG0

Bit 0: Port toggle bit .

TG1

Bit 1: Port toggle bit.

TG2

Bit 2: Port toggle bit.

TG3

Bit 3: Port toggle bit.

TG4

Bit 4: Port toggle bit.

TG5

Bit 5: Port toggle bit.

TG6

Bit 6: Port toggle bit.

TG7

Bit 7: Port toggle bit.

TG8

Bit 8: Port toggle bit.

TG9

Bit 9: Port toggle bit.

TG10

Bit 10: Port toggle bit.

TG11

Bit 11: Port toggle bit.

TG12

Bit 12: Port toggle bit.

TG13

Bit 13: Port toggle bit.

TG14

Bit 14: Port toggle bit.

TG15

Bit 15: Port toggle bit.

GPIOC

0x40020800: General-purpose I/Os

16/193 fields covered. Toggle Registers.

CTL

GPIO port control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		CTL14
rw 		CTL13
rw 		CTL12
rw 		CTL11
rw 		CTL10
rw 		CTL9
rw 		CTL8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL7
rw 		CTL6
rw 		CTL5
rw 		CTL4
rw 		CTL3
rw 		CTL2
rw 		CTL1
rw 		CTL0
rw
Toggle Fields.

CTL0

Bits 0-1: Port x configuration bits (x = 0).

CTL1

Bits 2-3: Port x configuration bits (x = 1).

CTL2

Bits 4-5: Port x configuration bits (x = 2).

CTL3

Bits 6-7: Port x configuration bits (x = 3).

CTL4

Bits 8-9: Port x configuration bits (x = 4 ).

CTL5

Bits 10-11: Port x configuration bits (x = 5).

CTL6

Bits 12-13: Port x configuration bits (x = 6 ).

CTL7

Bits 14-15: Port x configuration bits (x = 7).

CTL8

Bits 16-17: Port x configuration bits (x = 8).

CTL9

Bits 18-19: Port x configuration bits (x = 9).

CTL10

Bits 20-21: Port x configuration bits (x = 10).

CTL11

Bits 22-23: Port x configuration bits (x = 11).

CTL12

Bits 24-25: Port x configuration bits (x = 12).

CTL13

Bits 26-27: Port x configuration bits (x = 13).

CTL14

Bits 28-29: Port x configuration bits (x = 14).

CTL15

Bits 30-31: Port x configuration bits (x = 15).

OMODE

GPIO port output mode register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OM15
rw 		OM14
rw 		OM13
rw 		OM12
rw 		OM11
rw 		OM10
rw 		OM9
rw 		OM8
rw 		OM7
rw 		OM6
rw 		OM5
rw 		OM4
rw 		OM3
rw 		OM2
rw 		OM1
rw 		OM0
rw
Toggle Fields.

OM0

Bit 0: Port 0 output mode bit.

OM1

Bit 1: Port 1 output mode bit.

OM2

Bit 2: Port 2 output mode bit.

OM3

Bit 3: Port 3 output mode bit.

OM4

Bit 4: Port 4 output mode bit.

OM5

Bit 5: Port 5 output mode bit.

OM6

Bit 6: Port 6 output mode bit.

OM7

Bit 7: Port 7 output mode bit.

OM8

Bit 8: Port 8 output mode bit.

OM9

Bit 9: Port 9 output mode bit.

OM10

Bit 10: Port 10 output mode bit.

OM11

Bit 11: Port 11 output mode bit.

OM12

Bit 12: Port 12 output mode bit.

OM13

Bit 13: Port 13 output mode bit.

OM14

Bit 14: Port 14 output mode bit.

OM15

Bit 15: Port 15 output mode bit.

OSPD

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPD15
rw 		OSPD14
rw 		OSPD13
rw 		OSPD12
rw 		OSPD11
rw 		OSPD10
rw 		OSPD9
rw 		OSPD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPD7
rw 		OSPD6
rw 		OSPD5
rw 		OSPD4
rw 		OSPD3
rw 		OSPD2
rw 		OSPD1
rw 		OSPD0
rw
Toggle Fields.

OSPD0

Bits 0-1: Port 0 output max speed bits.

OSPD1

Bits 2-3: Port 1 output max speed bits.

OSPD2

Bits 4-5: Port 2 output max speed bits.

OSPD3

Bits 6-7: Port 3 output max speed bits.

OSPD4

Bits 8-9: Port 4 output max speed bits.

OSPD5

Bits 10-11: Port 5 output max speed bits.

OSPD6

Bits 12-13: Port 6 output max speed bits.

OSPD7

Bits 14-15: Port 7 output max speed bits.

OSPD8

Bits 16-17: Port 8 output max speed bits.

OSPD9

Bits 18-19: Port 9 output max speed bits.

OSPD10

Bits 20-21: Port 10 output max speed bits.

OSPD11

Bits 22-23: Port 11 output max speed bits.

OSPD12

Bits 24-25: Port 12 output max speed bits.

OSPD13

Bits 26-27: Port 13 output max speed bits.

OSPD14

Bits 28-29: Port 14 output max speed bits.

OSPD15

Bits 30-31: Port 15 output max speed bits.

PUD

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUD15
rw 		PUD14
rw 		PUD13
rw 		PUD12
rw 		PUD11
rw 		PUD10
rw 		PUD9
rw 		PUD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUD7
rw 		PUD6
rw 		PUD5
rw 		PUD4
rw 		PUD3
rw 		PUD2
rw 		PUD1
rw 		PUD0
rw
Toggle Fields.

PUD0

Bits 0-1: Port 0 pull-up or pull-down bits.

PUD1

Bits 2-3: Port 1 pull-up or pull-down bits.

PUD2

Bits 4-5: Port 2 pull-up or pull-down bits.

PUD3

Bits 6-7: Port 3 pull-up or pull-down bits.

PUD4

Bits 8-9: Port 4 pull-up or pull-down bits.

PUD5

Bits 10-11: Port 5 pull-up or pull-down bits.

PUD6

Bits 12-13: Port 6 pull-up or pull-down bits.

PUD7

Bits 14-15: Port 7 pull-up or pull-down bits.

PUD8

Bits 16-17: Port 8 pull-up or pull-down bits.

PUD9

Bits 18-19: Port 9 pull-up or pull-down bits.

PUD10

Bits 20-21: Port 10 pull-up or pull-down bits.

PUD11

Bits 22-23: Port 11 pull-up or pull-down bits.

PUD12

Bits 24-25: Port 12 pull-up or pull-down bits.

PUD13

Bits 26-27: Port 13 pull-up or pull-down bits.

PUD14

Bits 28-29: Port 14 pull-up or pull-down bits.

PUD15

Bits 30-31: Port 15 pull-up or pull-down bits.

ISTAT

GPIO port input status register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status (y = 0).

ISTAT1

Bit 1: Port input status (y = 1).

ISTAT2

Bit 2: Port input status (y = 2).

ISTAT3

Bit 3: Port input status (y = 3).

ISTAT4

Bit 4: Port input status (y = 4).

ISTAT5

Bit 5: Port input status (y = 5).

ISTAT6

Bit 6: Port input status (y = 6).

ISTAT7

Bit 7: Port input status (y = 7).

ISTAT8

Bit 8: Port input status (y = 8).

ISTAT9

Bit 9: Port input status (y = 9).

ISTAT10

Bit 10: Port input status (y = 10).

ISTAT11

Bit 11: Port input status (y = 11).

ISTAT12

Bit 12: Port input status (y = 12).

ISTAT13

Bit 13: Port input status (y = 13).

ISTAT14

Bit 14: Port input status (y = 14).

ISTAT15

Bit 15: Port input status (y = 15).

OCTL

GPIO port output control register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control (y = 0).

OCTL1

Bit 1: Port output control (y = 1).

OCTL2

Bit 2: Port output control (y = 2).

OCTL3

Bit 3: Port output control (y = 3).

OCTL4

Bit 4: Port output control (y = 4).

OCTL5

Bit 5: Port output control (y = 5).

OCTL6

Bit 6: Port output control (y = 6).

OCTL7

Bit 7: Port output control (y = 7).

OCTL8

Bit 8: Port output control (y = 8).

OCTL9

Bit 9: Port output control (y = 9).

OCTL10

Bit 10: Port output control (y = 10).

OCTL11

Bit 11: Port output control (y = 11).

OCTL12

Bit 12: Port output control (y = 12).

OCTL13

Bit 13: Port output control (y = 13).

OCTL14

Bit 14: Port output control (y = 14).

OCTL15

Bit 15: Port output control (y = 15).

BOP

GPIO port bit operate register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port Set bit 0.

BOP1

Bit 1: Port Set bit 1.

BOP2

Bit 2: Port Set bit 2.

BOP3

Bit 3: Port Set bit 3.

BOP4

Bit 4: Port Set bit 4.

BOP5

Bit 5: Port Set bit 5.

BOP6

Bit 6: Port Set bit 6.

BOP7

Bit 7: Port Set bit 7.

BOP8

Bit 8: Port Set bit 8.

BOP9

Bit 9: Port Set bit 9.

BOP10

Bit 10: Port Set bit 10.

BOP11

Bit 11: Port Set bit 11.

BOP12

Bit 12: Port Set bit 12.

BOP13

Bit 13: Port Set bit 13.

BOP14

Bit 14: Port Set bit 14.

BOP15

Bit 15: Port Set bit 15.

CR0

Bit 16: Port Clear bit 0.

CR1

Bit 17: Port Clear bit 1.

CR2

Bit 18: Port Clear bit 2.

CR3

Bit 19: Port Clear bit 3.

CR4

Bit 20: Port Clear bit 4.

CR5

Bit 21: Port Clear bit 5.

CR6

Bit 22: Port Clear bit 6.

CR7

Bit 23: Port Clear bit 7.

CR8

Bit 24: Port Clear bit 8.

CR9

Bit 25: Port Clear bit 9.

CR10

Bit 26: Port Clear bit 10.

CR11

Bit 27: Port Clear bit 11.

CR12

Bit 28: Port Clear bit 12.

CR13

Bit 29: Port Clear bit 13.

CR14

Bit 30: Port Clear bit 14.

CR15

Bit 31: Port Clear bit 15.

LOCK

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

LK1

Bit 1: Port Lock bit 1.

LK2

Bit 2: Port Lock bit 2.

LK3

Bit 3: Port Lock bit 3.

LK4

Bit 4: Port Lock bit 4.

LK5

Bit 5: Port Lock bit 5.

LK6

Bit 6: Port Lock bit 6.

LK7

Bit 7: Port Lock bit 7.

LK8

Bit 8: Port Lock bit 8.

LK9

Bit 9: Port Lock bit 9.

LK10

Bit 10: Port Lock bit 10.

LK11

Bit 11: Port Lock bit 11.

LK12

Bit 12: Port Lock bit 12.

LK13

Bit 13: Port Lock bit 13.

LK14

Bit 14: Port Lock bit 14.

LK15

Bit 15: Port Lock bit 15.

LKK

Bit 16: Lock sequence key .

AFSEL0

GPIO alternate function selected register 0

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL7
rw 		SEL6
rw 		SEL5
rw 		SEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL3
rw 		SEL2
rw 		SEL1
rw 		SEL0
rw
Toggle Fields.

SEL0

Bits 0-3: Port 0 alternate function selected.

SEL1

Bits 4-7: Port 1 alternate function selected.

SEL2

Bits 8-11: Port 2 alternate function selected.

SEL3

Bits 12-15: Port 3 alternate function selected.

SEL4

Bits 16-19: Port 4 alternate function selected.

SEL5

Bits 20-23: Port 5 alternate function selected.

SEL6

Bits 24-27: Port 6 alternate function selected.

SEL7

Bits 28-31: Port 7 alternate function selected.

AFSEL1

GPIO alternate function selected register 1

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL15
rw 		SEL14
rw 		SEL13
rw 		SEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL11
rw 		SEL10
rw 		SEL9
rw 		SEL8
rw
Toggle Fields.

SEL8

Bits 0-3: Port 8 alternate function selected.

SEL9

Bits 4-7: Port 9 alternate function selected.

SEL10

Bits 8-11: Port 10 alternate function selected.

SEL11

Bits 12-15: Port 11 alternate function selected.

SEL12

Bits 16-19: Port 12 alternate function selected.

SEL13

Bits 20-23: Port 13 alternate function selected.

SEL14

Bits 24-27: Port 14 alternate function selected.

SEL15

Bits 28-31: Port 15 alternate function selected.

BC

Bit clear register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port cleat bit.

CR1

Bit 1: Port cleat bit.

CR2

Bit 2: Port cleat bit.

CR3

Bit 3: Port cleat bit.

CR4

Bit 4: Port cleat bit.

CR5

Bit 5: Port cleat bit.

CR6

Bit 6: Port cleat bit.

CR7

Bit 7: Port cleat bit.

CR8

Bit 8: Port cleat bit.

CR9

Bit 9: Port cleat bit.

CR10

Bit 10: Port cleat bit.

CR11

Bit 11: Port cleat bit.

CR12

Bit 12: Port cleat bit.

CR13

Bit 13: Port cleat bit.

CR14

Bit 14: Port cleat bit.

CR15

Bit 15: Port cleat bit.

TG

Port bit toggle register

Offset: 0x2C, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG15
w 		TG14
w 		TG13
w 		TG12
w 		TG11
w 		TG10
w 		TG9
w 		TG8
w 		TG7
w 		TG6
w 		TG5
w 		TG4
w 		TG3
w 		TG2
w 		TG1
w 		TG0
w
Toggle Fields.

TG0

Bit 0: Port toggle bit .

TG1

Bit 1: Port toggle bit.

TG2

Bit 2: Port toggle bit.

TG3

Bit 3: Port toggle bit.

TG4

Bit 4: Port toggle bit.

TG5

Bit 5: Port toggle bit.

TG6

Bit 6: Port toggle bit.

TG7

Bit 7: Port toggle bit.

TG8

Bit 8: Port toggle bit.

TG9

Bit 9: Port toggle bit.

TG10

Bit 10: Port toggle bit.

TG11

Bit 11: Port toggle bit.

TG12

Bit 12: Port toggle bit.

TG13

Bit 13: Port toggle bit.

TG14

Bit 14: Port toggle bit.

TG15

Bit 15: Port toggle bit.

GPIOD

0x40020C00: General-purpose I/Os

16/193 fields covered. Toggle Registers.

CTL

GPIO port control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		CTL14
rw 		CTL13
rw 		CTL12
rw 		CTL11
rw 		CTL10
rw 		CTL9
rw 		CTL8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL7
rw 		CTL6
rw 		CTL5
rw 		CTL4
rw 		CTL3
rw 		CTL2
rw 		CTL1
rw 		CTL0
rw
Toggle Fields.

CTL0

Bits 0-1: Port x configuration bits (x = 0).

CTL1

Bits 2-3: Port x configuration bits (x = 1).

CTL2

Bits 4-5: Port x configuration bits (x = 2).

CTL3

Bits 6-7: Port x configuration bits (x = 3).

CTL4

Bits 8-9: Port x configuration bits (x = 4 ).

CTL5

Bits 10-11: Port x configuration bits (x = 5).

CTL6

Bits 12-13: Port x configuration bits (x = 6 ).

CTL7

Bits 14-15: Port x configuration bits (x = 7).

CTL8

Bits 16-17: Port x configuration bits (x = 8).

CTL9

Bits 18-19: Port x configuration bits (x = 9).

CTL10

Bits 20-21: Port x configuration bits (x = 10).

CTL11

Bits 22-23: Port x configuration bits (x = 11).

CTL12

Bits 24-25: Port x configuration bits (x = 12).

CTL13

Bits 26-27: Port x configuration bits (x = 13).

CTL14

Bits 28-29: Port x configuration bits (x = 14).

CTL15

Bits 30-31: Port x configuration bits (x = 15).

OMODE

GPIO port output mode register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OM15
rw 		OM14
rw 		OM13
rw 		OM12
rw 		OM11
rw 		OM10
rw 		OM9
rw 		OM8
rw 		OM7
rw 		OM6
rw 		OM5
rw 		OM4
rw 		OM3
rw 		OM2
rw 		OM1
rw 		OM0
rw
Toggle Fields.

OM0

Bit 0: Port 0 output mode bit.

OM1

Bit 1: Port 1 output mode bit.

OM2

Bit 2: Port 2 output mode bit.

OM3

Bit 3: Port 3 output mode bit.

OM4

Bit 4: Port 4 output mode bit.

OM5

Bit 5: Port 5 output mode bit.

OM6

Bit 6: Port 6 output mode bit.

OM7

Bit 7: Port 7 output mode bit.

OM8

Bit 8: Port 8 output mode bit.

OM9

Bit 9: Port 9 output mode bit.

OM10

Bit 10: Port 10 output mode bit.

OM11

Bit 11: Port 11 output mode bit.

OM12

Bit 12: Port 12 output mode bit.

OM13

Bit 13: Port 13 output mode bit.

OM14

Bit 14: Port 14 output mode bit.

OM15

Bit 15: Port 15 output mode bit.

OSPD

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPD15
rw 		OSPD14
rw 		OSPD13
rw 		OSPD12
rw 		OSPD11
rw 		OSPD10
rw 		OSPD9
rw 		OSPD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPD7
rw 		OSPD6
rw 		OSPD5
rw 		OSPD4
rw 		OSPD3
rw 		OSPD2
rw 		OSPD1
rw 		OSPD0
rw
Toggle Fields.

OSPD0

Bits 0-1: Port 0 output max speed bits.

OSPD1

Bits 2-3: Port 1 output max speed bits.

OSPD2

Bits 4-5: Port 2 output max speed bits.

OSPD3

Bits 6-7: Port 3 output max speed bits.

OSPD4

Bits 8-9: Port 4 output max speed bits.

OSPD5

Bits 10-11: Port 5 output max speed bits.

OSPD6

Bits 12-13: Port 6 output max speed bits.

OSPD7

Bits 14-15: Port 7 output max speed bits.

OSPD8

Bits 16-17: Port 8 output max speed bits.

OSPD9

Bits 18-19: Port 9 output max speed bits.

OSPD10

Bits 20-21: Port 10 output max speed bits.

OSPD11

Bits 22-23: Port 11 output max speed bits.

OSPD12

Bits 24-25: Port 12 output max speed bits.

OSPD13

Bits 26-27: Port 13 output max speed bits.

OSPD14

Bits 28-29: Port 14 output max speed bits.

OSPD15

Bits 30-31: Port 15 output max speed bits.

PUD

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUD15
rw 		PUD14
rw 		PUD13
rw 		PUD12
rw 		PUD11
rw 		PUD10
rw 		PUD9
rw 		PUD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUD7
rw 		PUD6
rw 		PUD5
rw 		PUD4
rw 		PUD3
rw 		PUD2
rw 		PUD1
rw 		PUD0
rw
Toggle Fields.

PUD0

Bits 0-1: Port 0 pull-up or pull-down bits.

PUD1

Bits 2-3: Port 1 pull-up or pull-down bits.

PUD2

Bits 4-5: Port 2 pull-up or pull-down bits.

PUD3

Bits 6-7: Port 3 pull-up or pull-down bits.

PUD4

Bits 8-9: Port 4 pull-up or pull-down bits.

PUD5

Bits 10-11: Port 5 pull-up or pull-down bits.

PUD6

Bits 12-13: Port 6 pull-up or pull-down bits.

PUD7

Bits 14-15: Port 7 pull-up or pull-down bits.

PUD8

Bits 16-17: Port 8 pull-up or pull-down bits.

PUD9

Bits 18-19: Port 9 pull-up or pull-down bits.

PUD10

Bits 20-21: Port 10 pull-up or pull-down bits.

PUD11

Bits 22-23: Port 11 pull-up or pull-down bits.

PUD12

Bits 24-25: Port 12 pull-up or pull-down bits.

PUD13

Bits 26-27: Port 13 pull-up or pull-down bits.

PUD14

Bits 28-29: Port 14 pull-up or pull-down bits.

PUD15

Bits 30-31: Port 15 pull-up or pull-down bits.

ISTAT

GPIO port input status register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status (y = 0).

ISTAT1

Bit 1: Port input status (y = 1).

ISTAT2

Bit 2: Port input status (y = 2).

ISTAT3

Bit 3: Port input status (y = 3).

ISTAT4

Bit 4: Port input status (y = 4).

ISTAT5

Bit 5: Port input status (y = 5).

ISTAT6

Bit 6: Port input status (y = 6).

ISTAT7

Bit 7: Port input status (y = 7).

ISTAT8

Bit 8: Port input status (y = 8).

ISTAT9

Bit 9: Port input status (y = 9).

ISTAT10

Bit 10: Port input status (y = 10).

ISTAT11

Bit 11: Port input status (y = 11).

ISTAT12

Bit 12: Port input status (y = 12).

ISTAT13

Bit 13: Port input status (y = 13).

ISTAT14

Bit 14: Port input status (y = 14).

ISTAT15

Bit 15: Port input status (y = 15).

OCTL

GPIO port output control register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control (y = 0).

OCTL1

Bit 1: Port output control (y = 1).

OCTL2

Bit 2: Port output control (y = 2).

OCTL3

Bit 3: Port output control (y = 3).

OCTL4

Bit 4: Port output control (y = 4).

OCTL5

Bit 5: Port output control (y = 5).

OCTL6

Bit 6: Port output control (y = 6).

OCTL7

Bit 7: Port output control (y = 7).

OCTL8

Bit 8: Port output control (y = 8).

OCTL9

Bit 9: Port output control (y = 9).

OCTL10

Bit 10: Port output control (y = 10).

OCTL11

Bit 11: Port output control (y = 11).

OCTL12

Bit 12: Port output control (y = 12).

OCTL13

Bit 13: Port output control (y = 13).

OCTL14

Bit 14: Port output control (y = 14).

OCTL15

Bit 15: Port output control (y = 15).

BOP

GPIO port bit operate register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port Set bit 0.

BOP1

Bit 1: Port Set bit 1.

BOP2

Bit 2: Port Set bit 2.

BOP3

Bit 3: Port Set bit 3.

BOP4

Bit 4: Port Set bit 4.

BOP5

Bit 5: Port Set bit 5.

BOP6

Bit 6: Port Set bit 6.

BOP7

Bit 7: Port Set bit 7.

BOP8

Bit 8: Port Set bit 8.

BOP9

Bit 9: Port Set bit 9.

BOP10

Bit 10: Port Set bit 10.

BOP11

Bit 11: Port Set bit 11.

BOP12

Bit 12: Port Set bit 12.

BOP13

Bit 13: Port Set bit 13.

BOP14

Bit 14: Port Set bit 14.

BOP15

Bit 15: Port Set bit 15.

CR0

Bit 16: Port Clear bit 0.

CR1

Bit 17: Port Clear bit 1.

CR2

Bit 18: Port Clear bit 2.

CR3

Bit 19: Port Clear bit 3.

CR4

Bit 20: Port Clear bit 4.

CR5

Bit 21: Port Clear bit 5.

CR6

Bit 22: Port Clear bit 6.

CR7

Bit 23: Port Clear bit 7.

CR8

Bit 24: Port Clear bit 8.

CR9

Bit 25: Port Clear bit 9.

CR10

Bit 26: Port Clear bit 10.

CR11

Bit 27: Port Clear bit 11.

CR12

Bit 28: Port Clear bit 12.

CR13

Bit 29: Port Clear bit 13.

CR14

Bit 30: Port Clear bit 14.

CR15

Bit 31: Port Clear bit 15.

LOCK

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

LK1

Bit 1: Port Lock bit 1.

LK2

Bit 2: Port Lock bit 2.

LK3

Bit 3: Port Lock bit 3.

LK4

Bit 4: Port Lock bit 4.

LK5

Bit 5: Port Lock bit 5.

LK6

Bit 6: Port Lock bit 6.

LK7

Bit 7: Port Lock bit 7.

LK8

Bit 8: Port Lock bit 8.

LK9

Bit 9: Port Lock bit 9.

LK10

Bit 10: Port Lock bit 10.

LK11

Bit 11: Port Lock bit 11.

LK12

Bit 12: Port Lock bit 12.

LK13

Bit 13: Port Lock bit 13.

LK14

Bit 14: Port Lock bit 14.

LK15

Bit 15: Port Lock bit 15.

LKK

Bit 16: Lock sequence key .

AFSEL0

GPIO alternate function selected register 0

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL7
rw 		SEL6
rw 		SEL5
rw 		SEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL3
rw 		SEL2
rw 		SEL1
rw 		SEL0
rw
Toggle Fields.

SEL0

Bits 0-3: Port 0 alternate function selected.

SEL1

Bits 4-7: Port 1 alternate function selected.

SEL2

Bits 8-11: Port 2 alternate function selected.

SEL3

Bits 12-15: Port 3 alternate function selected.

SEL4

Bits 16-19: Port 4 alternate function selected.

SEL5

Bits 20-23: Port 5 alternate function selected.

SEL6

Bits 24-27: Port 6 alternate function selected.

SEL7

Bits 28-31: Port 7 alternate function selected.

AFSEL1

GPIO alternate function selected register 1

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL15
rw 		SEL14
rw 		SEL13
rw 		SEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL11
rw 		SEL10
rw 		SEL9
rw 		SEL8
rw
Toggle Fields.

SEL8

Bits 0-3: Port 8 alternate function selected.

SEL9

Bits 4-7: Port 9 alternate function selected.

SEL10

Bits 8-11: Port 10 alternate function selected.

SEL11

Bits 12-15: Port 11 alternate function selected.

SEL12

Bits 16-19: Port 12 alternate function selected.

SEL13

Bits 20-23: Port 13 alternate function selected.

SEL14

Bits 24-27: Port 14 alternate function selected.

SEL15

Bits 28-31: Port 15 alternate function selected.

BC

Bit clear register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port cleat bit.

CR1

Bit 1: Port cleat bit.

CR2

Bit 2: Port cleat bit.

CR3

Bit 3: Port cleat bit.

CR4

Bit 4: Port cleat bit.

CR5

Bit 5: Port cleat bit.

CR6

Bit 6: Port cleat bit.

CR7

Bit 7: Port cleat bit.

CR8

Bit 8: Port cleat bit.

CR9

Bit 9: Port cleat bit.

CR10

Bit 10: Port cleat bit.

CR11

Bit 11: Port cleat bit.

CR12

Bit 12: Port cleat bit.

CR13

Bit 13: Port cleat bit.

CR14

Bit 14: Port cleat bit.

CR15

Bit 15: Port cleat bit.

TG

Port bit toggle register

Offset: 0x2C, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG15
w 		TG14
w 		TG13
w 		TG12
w 		TG11
w 		TG10
w 		TG9
w 		TG8
w 		TG7
w 		TG6
w 		TG5
w 		TG4
w 		TG3
w 		TG2
w 		TG1
w 		TG0
w
Toggle Fields.

TG0

Bit 0: Port toggle bit .

TG1

Bit 1: Port toggle bit.

TG2

Bit 2: Port toggle bit.

TG3

Bit 3: Port toggle bit.

TG4

Bit 4: Port toggle bit.

TG5

Bit 5: Port toggle bit.

TG6

Bit 6: Port toggle bit.

TG7

Bit 7: Port toggle bit.

TG8

Bit 8: Port toggle bit.

TG9

Bit 9: Port toggle bit.

TG10

Bit 10: Port toggle bit.

TG11

Bit 11: Port toggle bit.

TG12

Bit 12: Port toggle bit.

TG13

Bit 13: Port toggle bit.

TG14

Bit 14: Port toggle bit.

TG15

Bit 15: Port toggle bit.

GPIOE

0x40021000: General-purpose I/Os

16/193 fields covered. Toggle Registers.

CTL

GPIO port control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		CTL14
rw 		CTL13
rw 		CTL12
rw 		CTL11
rw 		CTL10
rw 		CTL9
rw 		CTL8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL7
rw 		CTL6
rw 		CTL5
rw 		CTL4
rw 		CTL3
rw 		CTL2
rw 		CTL1
rw 		CTL0
rw
Toggle Fields.

CTL0

Bits 0-1: Port x configuration bits (x = 0).

CTL1

Bits 2-3: Port x configuration bits (x = 1).

CTL2

Bits 4-5: Port x configuration bits (x = 2).

CTL3

Bits 6-7: Port x configuration bits (x = 3).

CTL4

Bits 8-9: Port x configuration bits (x = 4 ).

CTL5

Bits 10-11: Port x configuration bits (x = 5).

CTL6

Bits 12-13: Port x configuration bits (x = 6 ).

CTL7

Bits 14-15: Port x configuration bits (x = 7).

CTL8

Bits 16-17: Port x configuration bits (x = 8).

CTL9

Bits 18-19: Port x configuration bits (x = 9).

CTL10

Bits 20-21: Port x configuration bits (x = 10).

CTL11

Bits 22-23: Port x configuration bits (x = 11).

CTL12

Bits 24-25: Port x configuration bits (x = 12).

CTL13

Bits 26-27: Port x configuration bits (x = 13).

CTL14

Bits 28-29: Port x configuration bits (x = 14).

CTL15

Bits 30-31: Port x configuration bits (x = 15).

OMODE

GPIO port output mode register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OM15
rw 		OM14
rw 		OM13
rw 		OM12
rw 		OM11
rw 		OM10
rw 		OM9
rw 		OM8
rw 		OM7
rw 		OM6
rw 		OM5
rw 		OM4
rw 		OM3
rw 		OM2
rw 		OM1
rw 		OM0
rw
Toggle Fields.

OM0

Bit 0: Port 0 output mode bit.

OM1

Bit 1: Port 1 output mode bit.

OM2

Bit 2: Port 2 output mode bit.

OM3

Bit 3: Port 3 output mode bit.

OM4

Bit 4: Port 4 output mode bit.

OM5

Bit 5: Port 5 output mode bit.

OM6

Bit 6: Port 6 output mode bit.

OM7

Bit 7: Port 7 output mode bit.

OM8

Bit 8: Port 8 output mode bit.

OM9

Bit 9: Port 9 output mode bit.

OM10

Bit 10: Port 10 output mode bit.

OM11

Bit 11: Port 11 output mode bit.

OM12

Bit 12: Port 12 output mode bit.

OM13

Bit 13: Port 13 output mode bit.

OM14

Bit 14: Port 14 output mode bit.

OM15

Bit 15: Port 15 output mode bit.

OSPD

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPD15
rw 		OSPD14
rw 		OSPD13
rw 		OSPD12
rw 		OSPD11
rw 		OSPD10
rw 		OSPD9
rw 		OSPD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPD7
rw 		OSPD6
rw 		OSPD5
rw 		OSPD4
rw 		OSPD3
rw 		OSPD2
rw 		OSPD1
rw 		OSPD0
rw
Toggle Fields.

OSPD0

Bits 0-1: Port 0 output max speed bits.

OSPD1

Bits 2-3: Port 1 output max speed bits.

OSPD2

Bits 4-5: Port 2 output max speed bits.

OSPD3

Bits 6-7: Port 3 output max speed bits.

OSPD4

Bits 8-9: Port 4 output max speed bits.

OSPD5

Bits 10-11: Port 5 output max speed bits.

OSPD6

Bits 12-13: Port 6 output max speed bits.

OSPD7

Bits 14-15: Port 7 output max speed bits.

OSPD8

Bits 16-17: Port 8 output max speed bits.

OSPD9

Bits 18-19: Port 9 output max speed bits.

OSPD10

Bits 20-21: Port 10 output max speed bits.

OSPD11

Bits 22-23: Port 11 output max speed bits.

OSPD12

Bits 24-25: Port 12 output max speed bits.

OSPD13

Bits 26-27: Port 13 output max speed bits.

OSPD14

Bits 28-29: Port 14 output max speed bits.

OSPD15

Bits 30-31: Port 15 output max speed bits.

PUD

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUD15
rw 		PUD14
rw 		PUD13
rw 		PUD12
rw 		PUD11
rw 		PUD10
rw 		PUD9
rw 		PUD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUD7
rw 		PUD6
rw 		PUD5
rw 		PUD4
rw 		PUD3
rw 		PUD2
rw 		PUD1
rw 		PUD0
rw
Toggle Fields.

PUD0

Bits 0-1: Port 0 pull-up or pull-down bits.

PUD1

Bits 2-3: Port 1 pull-up or pull-down bits.

PUD2

Bits 4-5: Port 2 pull-up or pull-down bits.

PUD3

Bits 6-7: Port 3 pull-up or pull-down bits.

PUD4

Bits 8-9: Port 4 pull-up or pull-down bits.

PUD5

Bits 10-11: Port 5 pull-up or pull-down bits.

PUD6

Bits 12-13: Port 6 pull-up or pull-down bits.

PUD7

Bits 14-15: Port 7 pull-up or pull-down bits.

PUD8

Bits 16-17: Port 8 pull-up or pull-down bits.

PUD9

Bits 18-19: Port 9 pull-up or pull-down bits.

PUD10

Bits 20-21: Port 10 pull-up or pull-down bits.

PUD11

Bits 22-23: Port 11 pull-up or pull-down bits.

PUD12

Bits 24-25: Port 12 pull-up or pull-down bits.

PUD13

Bits 26-27: Port 13 pull-up or pull-down bits.

PUD14

Bits 28-29: Port 14 pull-up or pull-down bits.

PUD15

Bits 30-31: Port 15 pull-up or pull-down bits.

ISTAT

GPIO port input status register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status (y = 0).

ISTAT1

Bit 1: Port input status (y = 1).

ISTAT2

Bit 2: Port input status (y = 2).

ISTAT3

Bit 3: Port input status (y = 3).

ISTAT4

Bit 4: Port input status (y = 4).

ISTAT5

Bit 5: Port input status (y = 5).

ISTAT6

Bit 6: Port input status (y = 6).

ISTAT7

Bit 7: Port input status (y = 7).

ISTAT8

Bit 8: Port input status (y = 8).

ISTAT9

Bit 9: Port input status (y = 9).

ISTAT10

Bit 10: Port input status (y = 10).

ISTAT11

Bit 11: Port input status (y = 11).

ISTAT12

Bit 12: Port input status (y = 12).

ISTAT13

Bit 13: Port input status (y = 13).

ISTAT14

Bit 14: Port input status (y = 14).

ISTAT15

Bit 15: Port input status (y = 15).

OCTL

GPIO port output control register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control (y = 0).

OCTL1

Bit 1: Port output control (y = 1).

OCTL2

Bit 2: Port output control (y = 2).

OCTL3

Bit 3: Port output control (y = 3).

OCTL4

Bit 4: Port output control (y = 4).

OCTL5

Bit 5: Port output control (y = 5).

OCTL6

Bit 6: Port output control (y = 6).

OCTL7

Bit 7: Port output control (y = 7).

OCTL8

Bit 8: Port output control (y = 8).

OCTL9

Bit 9: Port output control (y = 9).

OCTL10

Bit 10: Port output control (y = 10).

OCTL11

Bit 11: Port output control (y = 11).

OCTL12

Bit 12: Port output control (y = 12).

OCTL13

Bit 13: Port output control (y = 13).

OCTL14

Bit 14: Port output control (y = 14).

OCTL15

Bit 15: Port output control (y = 15).

BOP

GPIO port bit operate register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port Set bit 0.

BOP1

Bit 1: Port Set bit 1.

BOP2

Bit 2: Port Set bit 2.

BOP3

Bit 3: Port Set bit 3.

BOP4

Bit 4: Port Set bit 4.

BOP5

Bit 5: Port Set bit 5.

BOP6

Bit 6: Port Set bit 6.

BOP7

Bit 7: Port Set bit 7.

BOP8

Bit 8: Port Set bit 8.

BOP9

Bit 9: Port Set bit 9.

BOP10

Bit 10: Port Set bit 10.

BOP11

Bit 11: Port Set bit 11.

BOP12

Bit 12: Port Set bit 12.

BOP13

Bit 13: Port Set bit 13.

BOP14

Bit 14: Port Set bit 14.

BOP15

Bit 15: Port Set bit 15.

CR0

Bit 16: Port Clear bit 0.

CR1

Bit 17: Port Clear bit 1.

CR2

Bit 18: Port Clear bit 2.

CR3

Bit 19: Port Clear bit 3.

CR4

Bit 20: Port Clear bit 4.

CR5

Bit 21: Port Clear bit 5.

CR6

Bit 22: Port Clear bit 6.

CR7

Bit 23: Port Clear bit 7.

CR8

Bit 24: Port Clear bit 8.

CR9

Bit 25: Port Clear bit 9.

CR10

Bit 26: Port Clear bit 10.

CR11

Bit 27: Port Clear bit 11.

CR12

Bit 28: Port Clear bit 12.

CR13

Bit 29: Port Clear bit 13.

CR14

Bit 30: Port Clear bit 14.

CR15

Bit 31: Port Clear bit 15.

LOCK

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

LK1

Bit 1: Port Lock bit 1.

LK2

Bit 2: Port Lock bit 2.

LK3

Bit 3: Port Lock bit 3.

LK4

Bit 4: Port Lock bit 4.

LK5

Bit 5: Port Lock bit 5.

LK6

Bit 6: Port Lock bit 6.

LK7

Bit 7: Port Lock bit 7.

LK8

Bit 8: Port Lock bit 8.

LK9

Bit 9: Port Lock bit 9.

LK10

Bit 10: Port Lock bit 10.

LK11

Bit 11: Port Lock bit 11.

LK12

Bit 12: Port Lock bit 12.

LK13

Bit 13: Port Lock bit 13.

LK14

Bit 14: Port Lock bit 14.

LK15

Bit 15: Port Lock bit 15.

LKK

Bit 16: Lock sequence key .

AFSEL0

GPIO alternate function selected register 0

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL7
rw 		SEL6
rw 		SEL5
rw 		SEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL3
rw 		SEL2
rw 		SEL1
rw 		SEL0
rw
Toggle Fields.

SEL0

Bits 0-3: Port 0 alternate function selected.

SEL1

Bits 4-7: Port 1 alternate function selected.

SEL2

Bits 8-11: Port 2 alternate function selected.

SEL3

Bits 12-15: Port 3 alternate function selected.

SEL4

Bits 16-19: Port 4 alternate function selected.

SEL5

Bits 20-23: Port 5 alternate function selected.

SEL6

Bits 24-27: Port 6 alternate function selected.

SEL7

Bits 28-31: Port 7 alternate function selected.

AFSEL1

GPIO alternate function selected register 1

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL15
rw 		SEL14
rw 		SEL13
rw 		SEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL11
rw 		SEL10
rw 		SEL9
rw 		SEL8
rw
Toggle Fields.

SEL8

Bits 0-3: Port 8 alternate function selected.

SEL9

Bits 4-7: Port 9 alternate function selected.

SEL10

Bits 8-11: Port 10 alternate function selected.

SEL11

Bits 12-15: Port 11 alternate function selected.

SEL12

Bits 16-19: Port 12 alternate function selected.

SEL13

Bits 20-23: Port 13 alternate function selected.

SEL14

Bits 24-27: Port 14 alternate function selected.

SEL15

Bits 28-31: Port 15 alternate function selected.

BC

Bit clear register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port cleat bit.

CR1

Bit 1: Port cleat bit.

CR2

Bit 2: Port cleat bit.

CR3

Bit 3: Port cleat bit.

CR4

Bit 4: Port cleat bit.

CR5

Bit 5: Port cleat bit.

CR6

Bit 6: Port cleat bit.

CR7

Bit 7: Port cleat bit.

CR8

Bit 8: Port cleat bit.

CR9

Bit 9: Port cleat bit.

CR10

Bit 10: Port cleat bit.

CR11

Bit 11: Port cleat bit.

CR12

Bit 12: Port cleat bit.

CR13

Bit 13: Port cleat bit.

CR14

Bit 14: Port cleat bit.

CR15

Bit 15: Port cleat bit.

TG

Port bit toggle register

Offset: 0x2C, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG15
w 		TG14
w 		TG13
w 		TG12
w 		TG11
w 		TG10
w 		TG9
w 		TG8
w 		TG7
w 		TG6
w 		TG5
w 		TG4
w 		TG3
w 		TG2
w 		TG1
w 		TG0
w
Toggle Fields.

TG0

Bit 0: Port toggle bit .

TG1

Bit 1: Port toggle bit.

TG2

Bit 2: Port toggle bit.

TG3

Bit 3: Port toggle bit.

TG4

Bit 4: Port toggle bit.

TG5

Bit 5: Port toggle bit.

TG6

Bit 6: Port toggle bit.

TG7

Bit 7: Port toggle bit.

TG8

Bit 8: Port toggle bit.

TG9

Bit 9: Port toggle bit.

TG10

Bit 10: Port toggle bit.

TG11

Bit 11: Port toggle bit.

TG12

Bit 12: Port toggle bit.

TG13

Bit 13: Port toggle bit.

TG14

Bit 14: Port toggle bit.

TG15

Bit 15: Port toggle bit.

GPIOF

0x40021400: General-purpose I/Os

16/193 fields covered. Toggle Registers.

CTL

GPIO port control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		CTL14
rw 		CTL13
rw 		CTL12
rw 		CTL11
rw 		CTL10
rw 		CTL9
rw 		CTL8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL7
rw 		CTL6
rw 		CTL5
rw 		CTL4
rw 		CTL3
rw 		CTL2
rw 		CTL1
rw 		CTL0
rw
Toggle Fields.

CTL0

Bits 0-1: Port x configuration bits (x = 0).

CTL1

Bits 2-3: Port x configuration bits (x = 1).

CTL2

Bits 4-5: Port x configuration bits (x = 2).

CTL3

Bits 6-7: Port x configuration bits (x = 3).

CTL4

Bits 8-9: Port x configuration bits (x = 4 ).

CTL5

Bits 10-11: Port x configuration bits (x = 5).

CTL6

Bits 12-13: Port x configuration bits (x = 6 ).

CTL7

Bits 14-15: Port x configuration bits (x = 7).

CTL8

Bits 16-17: Port x configuration bits (x = 8).

CTL9

Bits 18-19: Port x configuration bits (x = 9).

CTL10

Bits 20-21: Port x configuration bits (x = 10).

CTL11

Bits 22-23: Port x configuration bits (x = 11).

CTL12

Bits 24-25: Port x configuration bits (x = 12).

CTL13

Bits 26-27: Port x configuration bits (x = 13).

CTL14

Bits 28-29: Port x configuration bits (x = 14).

CTL15

Bits 30-31: Port x configuration bits (x = 15).

OMODE

GPIO port output mode register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OM15
rw 		OM14
rw 		OM13
rw 		OM12
rw 		OM11
rw 		OM10
rw 		OM9
rw 		OM8
rw 		OM7
rw 		OM6
rw 		OM5
rw 		OM4
rw 		OM3
rw 		OM2
rw 		OM1
rw 		OM0
rw
Toggle Fields.

OM0

Bit 0: Port 0 output mode bit.

OM1

Bit 1: Port 1 output mode bit.

OM2

Bit 2: Port 2 output mode bit.

OM3

Bit 3: Port 3 output mode bit.

OM4

Bit 4: Port 4 output mode bit.

OM5

Bit 5: Port 5 output mode bit.

OM6

Bit 6: Port 6 output mode bit.

OM7

Bit 7: Port 7 output mode bit.

OM8

Bit 8: Port 8 output mode bit.

OM9

Bit 9: Port 9 output mode bit.

OM10

Bit 10: Port 10 output mode bit.

OM11

Bit 11: Port 11 output mode bit.

OM12

Bit 12: Port 12 output mode bit.

OM13

Bit 13: Port 13 output mode bit.

OM14

Bit 14: Port 14 output mode bit.

OM15

Bit 15: Port 15 output mode bit.

OSPD

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPD15
rw 		OSPD14
rw 		OSPD13
rw 		OSPD12
rw 		OSPD11
rw 		OSPD10
rw 		OSPD9
rw 		OSPD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPD7
rw 		OSPD6
rw 		OSPD5
rw 		OSPD4
rw 		OSPD3
rw 		OSPD2
rw 		OSPD1
rw 		OSPD0
rw
Toggle Fields.

OSPD0

Bits 0-1: Port 0 output max speed bits.

OSPD1

Bits 2-3: Port 1 output max speed bits.

OSPD2

Bits 4-5: Port 2 output max speed bits.

OSPD3

Bits 6-7: Port 3 output max speed bits.

OSPD4

Bits 8-9: Port 4 output max speed bits.

OSPD5

Bits 10-11: Port 5 output max speed bits.

OSPD6

Bits 12-13: Port 6 output max speed bits.

OSPD7

Bits 14-15: Port 7 output max speed bits.

OSPD8

Bits 16-17: Port 8 output max speed bits.

OSPD9

Bits 18-19: Port 9 output max speed bits.

OSPD10

Bits 20-21: Port 10 output max speed bits.

OSPD11

Bits 22-23: Port 11 output max speed bits.

OSPD12

Bits 24-25: Port 12 output max speed bits.

OSPD13

Bits 26-27: Port 13 output max speed bits.

OSPD14

Bits 28-29: Port 14 output max speed bits.

OSPD15

Bits 30-31: Port 15 output max speed bits.

PUD

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUD15
rw 		PUD14
rw 		PUD13
rw 		PUD12
rw 		PUD11
rw 		PUD10
rw 		PUD9
rw 		PUD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUD7
rw 		PUD6
rw 		PUD5
rw 		PUD4
rw 		PUD3
rw 		PUD2
rw 		PUD1
rw 		PUD0
rw
Toggle Fields.

PUD0

Bits 0-1: Port 0 pull-up or pull-down bits.

PUD1

Bits 2-3: Port 1 pull-up or pull-down bits.

PUD2

Bits 4-5: Port 2 pull-up or pull-down bits.

PUD3

Bits 6-7: Port 3 pull-up or pull-down bits.

PUD4

Bits 8-9: Port 4 pull-up or pull-down bits.

PUD5

Bits 10-11: Port 5 pull-up or pull-down bits.

PUD6

Bits 12-13: Port 6 pull-up or pull-down bits.

PUD7

Bits 14-15: Port 7 pull-up or pull-down bits.

PUD8

Bits 16-17: Port 8 pull-up or pull-down bits.

PUD9

Bits 18-19: Port 9 pull-up or pull-down bits.

PUD10

Bits 20-21: Port 10 pull-up or pull-down bits.

PUD11

Bits 22-23: Port 11 pull-up or pull-down bits.

PUD12

Bits 24-25: Port 12 pull-up or pull-down bits.

PUD13

Bits 26-27: Port 13 pull-up or pull-down bits.

PUD14

Bits 28-29: Port 14 pull-up or pull-down bits.

PUD15

Bits 30-31: Port 15 pull-up or pull-down bits.

ISTAT

GPIO port input status register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status (y = 0).

ISTAT1

Bit 1: Port input status (y = 1).

ISTAT2

Bit 2: Port input status (y = 2).

ISTAT3

Bit 3: Port input status (y = 3).

ISTAT4

Bit 4: Port input status (y = 4).

ISTAT5

Bit 5: Port input status (y = 5).

ISTAT6

Bit 6: Port input status (y = 6).

ISTAT7

Bit 7: Port input status (y = 7).

ISTAT8

Bit 8: Port input status (y = 8).

ISTAT9

Bit 9: Port input status (y = 9).

ISTAT10

Bit 10: Port input status (y = 10).

ISTAT11

Bit 11: Port input status (y = 11).

ISTAT12

Bit 12: Port input status (y = 12).

ISTAT13

Bit 13: Port input status (y = 13).

ISTAT14

Bit 14: Port input status (y = 14).

ISTAT15

Bit 15: Port input status (y = 15).

OCTL

GPIO port output control register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control (y = 0).

OCTL1

Bit 1: Port output control (y = 1).

OCTL2

Bit 2: Port output control (y = 2).

OCTL3

Bit 3: Port output control (y = 3).

OCTL4

Bit 4: Port output control (y = 4).

OCTL5

Bit 5: Port output control (y = 5).

OCTL6

Bit 6: Port output control (y = 6).

OCTL7

Bit 7: Port output control (y = 7).

OCTL8

Bit 8: Port output control (y = 8).

OCTL9

Bit 9: Port output control (y = 9).

OCTL10

Bit 10: Port output control (y = 10).

OCTL11

Bit 11: Port output control (y = 11).

OCTL12

Bit 12: Port output control (y = 12).

OCTL13

Bit 13: Port output control (y = 13).

OCTL14

Bit 14: Port output control (y = 14).

OCTL15

Bit 15: Port output control (y = 15).

BOP

GPIO port bit operate register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port Set bit 0.

BOP1

Bit 1: Port Set bit 1.

BOP2

Bit 2: Port Set bit 2.

BOP3

Bit 3: Port Set bit 3.

BOP4

Bit 4: Port Set bit 4.

BOP5

Bit 5: Port Set bit 5.

BOP6

Bit 6: Port Set bit 6.

BOP7

Bit 7: Port Set bit 7.

BOP8

Bit 8: Port Set bit 8.

BOP9

Bit 9: Port Set bit 9.

BOP10

Bit 10: Port Set bit 10.

BOP11

Bit 11: Port Set bit 11.

BOP12

Bit 12: Port Set bit 12.

BOP13

Bit 13: Port Set bit 13.

BOP14

Bit 14: Port Set bit 14.

BOP15

Bit 15: Port Set bit 15.

CR0

Bit 16: Port Clear bit 0.

CR1

Bit 17: Port Clear bit 1.

CR2

Bit 18: Port Clear bit 2.

CR3

Bit 19: Port Clear bit 3.

CR4

Bit 20: Port Clear bit 4.

CR5

Bit 21: Port Clear bit 5.

CR6

Bit 22: Port Clear bit 6.

CR7

Bit 23: Port Clear bit 7.

CR8

Bit 24: Port Clear bit 8.

CR9

Bit 25: Port Clear bit 9.

CR10

Bit 26: Port Clear bit 10.

CR11

Bit 27: Port Clear bit 11.

CR12

Bit 28: Port Clear bit 12.

CR13

Bit 29: Port Clear bit 13.

CR14

Bit 30: Port Clear bit 14.

CR15

Bit 31: Port Clear bit 15.

LOCK

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

LK1

Bit 1: Port Lock bit 1.

LK2

Bit 2: Port Lock bit 2.

LK3

Bit 3: Port Lock bit 3.

LK4

Bit 4: Port Lock bit 4.

LK5

Bit 5: Port Lock bit 5.

LK6

Bit 6: Port Lock bit 6.

LK7

Bit 7: Port Lock bit 7.

LK8

Bit 8: Port Lock bit 8.

LK9

Bit 9: Port Lock bit 9.

LK10

Bit 10: Port Lock bit 10.

LK11

Bit 11: Port Lock bit 11.

LK12

Bit 12: Port Lock bit 12.

LK13

Bit 13: Port Lock bit 13.

LK14

Bit 14: Port Lock bit 14.

LK15

Bit 15: Port Lock bit 15.

LKK

Bit 16: Lock sequence key .

AFSEL0

GPIO alternate function selected register 0

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL7
rw 		SEL6
rw 		SEL5
rw 		SEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL3
rw 		SEL2
rw 		SEL1
rw 		SEL0
rw
Toggle Fields.

SEL0

Bits 0-3: Port 0 alternate function selected.

SEL1

Bits 4-7: Port 1 alternate function selected.

SEL2

Bits 8-11: Port 2 alternate function selected.

SEL3

Bits 12-15: Port 3 alternate function selected.

SEL4

Bits 16-19: Port 4 alternate function selected.

SEL5

Bits 20-23: Port 5 alternate function selected.

SEL6

Bits 24-27: Port 6 alternate function selected.

SEL7

Bits 28-31: Port 7 alternate function selected.

AFSEL1

GPIO alternate function selected register 1

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL15
rw 		SEL14
rw 		SEL13
rw 		SEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL11
rw 		SEL10
rw 		SEL9
rw 		SEL8
rw
Toggle Fields.

SEL8

Bits 0-3: Port 8 alternate function selected.

SEL9

Bits 4-7: Port 9 alternate function selected.

SEL10

Bits 8-11: Port 10 alternate function selected.

SEL11

Bits 12-15: Port 11 alternate function selected.

SEL12

Bits 16-19: Port 12 alternate function selected.

SEL13

Bits 20-23: Port 13 alternate function selected.

SEL14

Bits 24-27: Port 14 alternate function selected.

SEL15

Bits 28-31: Port 15 alternate function selected.

BC

Bit clear register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port cleat bit.

CR1

Bit 1: Port cleat bit.

CR2

Bit 2: Port cleat bit.

CR3

Bit 3: Port cleat bit.

CR4

Bit 4: Port cleat bit.

CR5

Bit 5: Port cleat bit.

CR6

Bit 6: Port cleat bit.

CR7

Bit 7: Port cleat bit.

CR8

Bit 8: Port cleat bit.

CR9

Bit 9: Port cleat bit.

CR10

Bit 10: Port cleat bit.

CR11

Bit 11: Port cleat bit.

CR12

Bit 12: Port cleat bit.

CR13

Bit 13: Port cleat bit.

CR14

Bit 14: Port cleat bit.

CR15

Bit 15: Port cleat bit.

TG

Port bit toggle register

Offset: 0x2C, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG15
w 		TG14
w 		TG13
w 		TG12
w 		TG11
w 		TG10
w 		TG9
w 		TG8
w 		TG7
w 		TG6
w 		TG5
w 		TG4
w 		TG3
w 		TG2
w 		TG1
w 		TG0
w
Toggle Fields.

TG0

Bit 0: Port toggle bit .

TG1

Bit 1: Port toggle bit.

TG2

Bit 2: Port toggle bit.

TG3

Bit 3: Port toggle bit.

TG4

Bit 4: Port toggle bit.

TG5

Bit 5: Port toggle bit.

TG6

Bit 6: Port toggle bit.

TG7

Bit 7: Port toggle bit.

TG8

Bit 8: Port toggle bit.

TG9

Bit 9: Port toggle bit.

TG10

Bit 10: Port toggle bit.

TG11

Bit 11: Port toggle bit.

TG12

Bit 12: Port toggle bit.

TG13

Bit 13: Port toggle bit.

TG14

Bit 14: Port toggle bit.

TG15

Bit 15: Port toggle bit.

GPIOG

0x40021800: General-purpose I/Os

16/193 fields covered. Toggle Registers.

CTL

GPIO port control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		CTL14
rw 		CTL13
rw 		CTL12
rw 		CTL11
rw 		CTL10
rw 		CTL9
rw 		CTL8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL7
rw 		CTL6
rw 		CTL5
rw 		CTL4
rw 		CTL3
rw 		CTL2
rw 		CTL1
rw 		CTL0
rw
Toggle Fields.

CTL0

Bits 0-1: Port x configuration bits (x = 0).

CTL1

Bits 2-3: Port x configuration bits (x = 1).

CTL2

Bits 4-5: Port x configuration bits (x = 2).

CTL3

Bits 6-7: Port x configuration bits (x = 3).

CTL4

Bits 8-9: Port x configuration bits (x = 4 ).

CTL5

Bits 10-11: Port x configuration bits (x = 5).

CTL6

Bits 12-13: Port x configuration bits (x = 6 ).

CTL7

Bits 14-15: Port x configuration bits (x = 7).

CTL8

Bits 16-17: Port x configuration bits (x = 8).

CTL9

Bits 18-19: Port x configuration bits (x = 9).

CTL10

Bits 20-21: Port x configuration bits (x = 10).

CTL11

Bits 22-23: Port x configuration bits (x = 11).

CTL12

Bits 24-25: Port x configuration bits (x = 12).

CTL13

Bits 26-27: Port x configuration bits (x = 13).

CTL14

Bits 28-29: Port x configuration bits (x = 14).

CTL15

Bits 30-31: Port x configuration bits (x = 15).

OMODE

GPIO port output mode register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OM15
rw 		OM14
rw 		OM13
rw 		OM12
rw 		OM11
rw 		OM10
rw 		OM9
rw 		OM8
rw 		OM7
rw 		OM6
rw 		OM5
rw 		OM4
rw 		OM3
rw 		OM2
rw 		OM1
rw 		OM0
rw
Toggle Fields.

OM0

Bit 0: Port 0 output mode bit.

OM1

Bit 1: Port 1 output mode bit.

OM2

Bit 2: Port 2 output mode bit.

OM3

Bit 3: Port 3 output mode bit.

OM4

Bit 4: Port 4 output mode bit.

OM5

Bit 5: Port 5 output mode bit.

OM6

Bit 6: Port 6 output mode bit.

OM7

Bit 7: Port 7 output mode bit.

OM8

Bit 8: Port 8 output mode bit.

OM9

Bit 9: Port 9 output mode bit.

OM10

Bit 10: Port 10 output mode bit.

OM11

Bit 11: Port 11 output mode bit.

OM12

Bit 12: Port 12 output mode bit.

OM13

Bit 13: Port 13 output mode bit.

OM14

Bit 14: Port 14 output mode bit.

OM15

Bit 15: Port 15 output mode bit.

OSPD

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPD15
rw 		OSPD14
rw 		OSPD13
rw 		OSPD12
rw 		OSPD11
rw 		OSPD10
rw 		OSPD9
rw 		OSPD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPD7
rw 		OSPD6
rw 		OSPD5
rw 		OSPD4
rw 		OSPD3
rw 		OSPD2
rw 		OSPD1
rw 		OSPD0
rw
Toggle Fields.

OSPD0

Bits 0-1: Port 0 output max speed bits.

OSPD1

Bits 2-3: Port 1 output max speed bits.

OSPD2

Bits 4-5: Port 2 output max speed bits.

OSPD3

Bits 6-7: Port 3 output max speed bits.

OSPD4

Bits 8-9: Port 4 output max speed bits.

OSPD5

Bits 10-11: Port 5 output max speed bits.

OSPD6

Bits 12-13: Port 6 output max speed bits.

OSPD7

Bits 14-15: Port 7 output max speed bits.

OSPD8

Bits 16-17: Port 8 output max speed bits.

OSPD9

Bits 18-19: Port 9 output max speed bits.

OSPD10

Bits 20-21: Port 10 output max speed bits.

OSPD11

Bits 22-23: Port 11 output max speed bits.

OSPD12

Bits 24-25: Port 12 output max speed bits.

OSPD13

Bits 26-27: Port 13 output max speed bits.

OSPD14

Bits 28-29: Port 14 output max speed bits.

OSPD15

Bits 30-31: Port 15 output max speed bits.

PUD

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUD15
rw 		PUD14
rw 		PUD13
rw 		PUD12
rw 		PUD11
rw 		PUD10
rw 		PUD9
rw 		PUD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUD7
rw 		PUD6
rw 		PUD5
rw 		PUD4
rw 		PUD3
rw 		PUD2
rw 		PUD1
rw 		PUD0
rw
Toggle Fields.

PUD0

Bits 0-1: Port 0 pull-up or pull-down bits.

PUD1

Bits 2-3: Port 1 pull-up or pull-down bits.

PUD2

Bits 4-5: Port 2 pull-up or pull-down bits.

PUD3

Bits 6-7: Port 3 pull-up or pull-down bits.

PUD4

Bits 8-9: Port 4 pull-up or pull-down bits.

PUD5

Bits 10-11: Port 5 pull-up or pull-down bits.

PUD6

Bits 12-13: Port 6 pull-up or pull-down bits.

PUD7

Bits 14-15: Port 7 pull-up or pull-down bits.

PUD8

Bits 16-17: Port 8 pull-up or pull-down bits.

PUD9

Bits 18-19: Port 9 pull-up or pull-down bits.

PUD10

Bits 20-21: Port 10 pull-up or pull-down bits.

PUD11

Bits 22-23: Port 11 pull-up or pull-down bits.

PUD12

Bits 24-25: Port 12 pull-up or pull-down bits.

PUD13

Bits 26-27: Port 13 pull-up or pull-down bits.

PUD14

Bits 28-29: Port 14 pull-up or pull-down bits.

PUD15

Bits 30-31: Port 15 pull-up or pull-down bits.

ISTAT

GPIO port input status register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status (y = 0).

ISTAT1

Bit 1: Port input status (y = 1).

ISTAT2

Bit 2: Port input status (y = 2).

ISTAT3

Bit 3: Port input status (y = 3).

ISTAT4

Bit 4: Port input status (y = 4).

ISTAT5

Bit 5: Port input status (y = 5).

ISTAT6

Bit 6: Port input status (y = 6).

ISTAT7

Bit 7: Port input status (y = 7).

ISTAT8

Bit 8: Port input status (y = 8).

ISTAT9

Bit 9: Port input status (y = 9).

ISTAT10

Bit 10: Port input status (y = 10).

ISTAT11

Bit 11: Port input status (y = 11).

ISTAT12

Bit 12: Port input status (y = 12).

ISTAT13

Bit 13: Port input status (y = 13).

ISTAT14

Bit 14: Port input status (y = 14).

ISTAT15

Bit 15: Port input status (y = 15).

OCTL

GPIO port output control register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control (y = 0).

OCTL1

Bit 1: Port output control (y = 1).

OCTL2

Bit 2: Port output control (y = 2).

OCTL3

Bit 3: Port output control (y = 3).

OCTL4

Bit 4: Port output control (y = 4).

OCTL5

Bit 5: Port output control (y = 5).

OCTL6

Bit 6: Port output control (y = 6).

OCTL7

Bit 7: Port output control (y = 7).

OCTL8

Bit 8: Port output control (y = 8).

OCTL9

Bit 9: Port output control (y = 9).

OCTL10

Bit 10: Port output control (y = 10).

OCTL11

Bit 11: Port output control (y = 11).

OCTL12

Bit 12: Port output control (y = 12).

OCTL13

Bit 13: Port output control (y = 13).

OCTL14

Bit 14: Port output control (y = 14).

OCTL15

Bit 15: Port output control (y = 15).

BOP

GPIO port bit operate register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port Set bit 0.

BOP1

Bit 1: Port Set bit 1.

BOP2

Bit 2: Port Set bit 2.

BOP3

Bit 3: Port Set bit 3.

BOP4

Bit 4: Port Set bit 4.

BOP5

Bit 5: Port Set bit 5.

BOP6

Bit 6: Port Set bit 6.

BOP7

Bit 7: Port Set bit 7.

BOP8

Bit 8: Port Set bit 8.

BOP9

Bit 9: Port Set bit 9.

BOP10

Bit 10: Port Set bit 10.

BOP11

Bit 11: Port Set bit 11.

BOP12

Bit 12: Port Set bit 12.

BOP13

Bit 13: Port Set bit 13.

BOP14

Bit 14: Port Set bit 14.

BOP15

Bit 15: Port Set bit 15.

CR0

Bit 16: Port Clear bit 0.

CR1

Bit 17: Port Clear bit 1.

CR2

Bit 18: Port Clear bit 2.

CR3

Bit 19: Port Clear bit 3.

CR4

Bit 20: Port Clear bit 4.

CR5

Bit 21: Port Clear bit 5.

CR6

Bit 22: Port Clear bit 6.

CR7

Bit 23: Port Clear bit 7.

CR8

Bit 24: Port Clear bit 8.

CR9

Bit 25: Port Clear bit 9.

CR10

Bit 26: Port Clear bit 10.

CR11

Bit 27: Port Clear bit 11.

CR12

Bit 28: Port Clear bit 12.

CR13

Bit 29: Port Clear bit 13.

CR14

Bit 30: Port Clear bit 14.

CR15

Bit 31: Port Clear bit 15.

LOCK

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

LK1

Bit 1: Port Lock bit 1.

LK2

Bit 2: Port Lock bit 2.

LK3

Bit 3: Port Lock bit 3.

LK4

Bit 4: Port Lock bit 4.

LK5

Bit 5: Port Lock bit 5.

LK6

Bit 6: Port Lock bit 6.

LK7

Bit 7: Port Lock bit 7.

LK8

Bit 8: Port Lock bit 8.

LK9

Bit 9: Port Lock bit 9.

LK10

Bit 10: Port Lock bit 10.

LK11

Bit 11: Port Lock bit 11.

LK12

Bit 12: Port Lock bit 12.

LK13

Bit 13: Port Lock bit 13.

LK14

Bit 14: Port Lock bit 14.

LK15

Bit 15: Port Lock bit 15.

LKK

Bit 16: Lock sequence key .

AFSEL0

GPIO alternate function selected register 0

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL7
rw 		SEL6
rw 		SEL5
rw 		SEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL3
rw 		SEL2
rw 		SEL1
rw 		SEL0
rw
Toggle Fields.

SEL0

Bits 0-3: Port 0 alternate function selected.

SEL1

Bits 4-7: Port 1 alternate function selected.

SEL2

Bits 8-11: Port 2 alternate function selected.

SEL3

Bits 12-15: Port 3 alternate function selected.

SEL4

Bits 16-19: Port 4 alternate function selected.

SEL5

Bits 20-23: Port 5 alternate function selected.

SEL6

Bits 24-27: Port 6 alternate function selected.

SEL7

Bits 28-31: Port 7 alternate function selected.

AFSEL1

GPIO alternate function selected register 1

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL15
rw 		SEL14
rw 		SEL13
rw 		SEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL11
rw 		SEL10
rw 		SEL9
rw 		SEL8
rw
Toggle Fields.

SEL8

Bits 0-3: Port 8 alternate function selected.

SEL9

Bits 4-7: Port 9 alternate function selected.

SEL10

Bits 8-11: Port 10 alternate function selected.

SEL11

Bits 12-15: Port 11 alternate function selected.

SEL12

Bits 16-19: Port 12 alternate function selected.

SEL13

Bits 20-23: Port 13 alternate function selected.

SEL14

Bits 24-27: Port 14 alternate function selected.

SEL15

Bits 28-31: Port 15 alternate function selected.

BC

Bit clear register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port cleat bit.

CR1

Bit 1: Port cleat bit.

CR2

Bit 2: Port cleat bit.

CR3

Bit 3: Port cleat bit.

CR4

Bit 4: Port cleat bit.

CR5

Bit 5: Port cleat bit.

CR6

Bit 6: Port cleat bit.

CR7

Bit 7: Port cleat bit.

CR8

Bit 8: Port cleat bit.

CR9

Bit 9: Port cleat bit.

CR10

Bit 10: Port cleat bit.

CR11

Bit 11: Port cleat bit.

CR12

Bit 12: Port cleat bit.

CR13

Bit 13: Port cleat bit.

CR14

Bit 14: Port cleat bit.

CR15

Bit 15: Port cleat bit.

TG

Port bit toggle register

Offset: 0x2C, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG15
w 		TG14
w 		TG13
w 		TG12
w 		TG11
w 		TG10
w 		TG9
w 		TG8
w 		TG7
w 		TG6
w 		TG5
w 		TG4
w 		TG3
w 		TG2
w 		TG1
w 		TG0
w
Toggle Fields.

TG0

Bit 0: Port toggle bit .

TG1

Bit 1: Port toggle bit.

TG2

Bit 2: Port toggle bit.

TG3

Bit 3: Port toggle bit.

TG4

Bit 4: Port toggle bit.

TG5

Bit 5: Port toggle bit.

TG6

Bit 6: Port toggle bit.

TG7

Bit 7: Port toggle bit.

TG8

Bit 8: Port toggle bit.

TG9

Bit 9: Port toggle bit.

TG10

Bit 10: Port toggle bit.

TG11

Bit 11: Port toggle bit.

TG12

Bit 12: Port toggle bit.

TG13

Bit 13: Port toggle bit.

TG14

Bit 14: Port toggle bit.

TG15

Bit 15: Port toggle bit.

GPIOH

0x40021C00: General-purpose I/Os

16/193 fields covered. Toggle Registers.

CTL

GPIO port control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		CTL14
rw 		CTL13
rw 		CTL12
rw 		CTL11
rw 		CTL10
rw 		CTL9
rw 		CTL8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL7
rw 		CTL6
rw 		CTL5
rw 		CTL4
rw 		CTL3
rw 		CTL2
rw 		CTL1
rw 		CTL0
rw
Toggle Fields.

CTL0

Bits 0-1: Port x configuration bits (x = 0).

CTL1

Bits 2-3: Port x configuration bits (x = 1).

CTL2

Bits 4-5: Port x configuration bits (x = 2).

CTL3

Bits 6-7: Port x configuration bits (x = 3).

CTL4

Bits 8-9: Port x configuration bits (x = 4 ).

CTL5

Bits 10-11: Port x configuration bits (x = 5).

CTL6

Bits 12-13: Port x configuration bits (x = 6 ).

CTL7

Bits 14-15: Port x configuration bits (x = 7).

CTL8

Bits 16-17: Port x configuration bits (x = 8).

CTL9

Bits 18-19: Port x configuration bits (x = 9).

CTL10

Bits 20-21: Port x configuration bits (x = 10).

CTL11

Bits 22-23: Port x configuration bits (x = 11).

CTL12

Bits 24-25: Port x configuration bits (x = 12).

CTL13

Bits 26-27: Port x configuration bits (x = 13).

CTL14

Bits 28-29: Port x configuration bits (x = 14).

CTL15

Bits 30-31: Port x configuration bits (x = 15).

OMODE

GPIO port output mode register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OM15
rw 		OM14
rw 		OM13
rw 		OM12
rw 		OM11
rw 		OM10
rw 		OM9
rw 		OM8
rw 		OM7
rw 		OM6
rw 		OM5
rw 		OM4
rw 		OM3
rw 		OM2
rw 		OM1
rw 		OM0
rw
Toggle Fields.

OM0

Bit 0: Port 0 output mode bit.

OM1

Bit 1: Port 1 output mode bit.

OM2

Bit 2: Port 2 output mode bit.

OM3

Bit 3: Port 3 output mode bit.

OM4

Bit 4: Port 4 output mode bit.

OM5

Bit 5: Port 5 output mode bit.

OM6

Bit 6: Port 6 output mode bit.

OM7

Bit 7: Port 7 output mode bit.

OM8

Bit 8: Port 8 output mode bit.

OM9

Bit 9: Port 9 output mode bit.

OM10

Bit 10: Port 10 output mode bit.

OM11

Bit 11: Port 11 output mode bit.

OM12

Bit 12: Port 12 output mode bit.

OM13

Bit 13: Port 13 output mode bit.

OM14

Bit 14: Port 14 output mode bit.

OM15

Bit 15: Port 15 output mode bit.

OSPD

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPD15
rw 		OSPD14
rw 		OSPD13
rw 		OSPD12
rw 		OSPD11
rw 		OSPD10
rw 		OSPD9
rw 		OSPD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPD7
rw 		OSPD6
rw 		OSPD5
rw 		OSPD4
rw 		OSPD3
rw 		OSPD2
rw 		OSPD1
rw 		OSPD0
rw
Toggle Fields.

OSPD0

Bits 0-1: Port 0 output max speed bits.

OSPD1

Bits 2-3: Port 1 output max speed bits.

OSPD2

Bits 4-5: Port 2 output max speed bits.

OSPD3

Bits 6-7: Port 3 output max speed bits.

OSPD4

Bits 8-9: Port 4 output max speed bits.

OSPD5

Bits 10-11: Port 5 output max speed bits.

OSPD6

Bits 12-13: Port 6 output max speed bits.

OSPD7

Bits 14-15: Port 7 output max speed bits.

OSPD8

Bits 16-17: Port 8 output max speed bits.

OSPD9

Bits 18-19: Port 9 output max speed bits.

OSPD10

Bits 20-21: Port 10 output max speed bits.

OSPD11

Bits 22-23: Port 11 output max speed bits.

OSPD12

Bits 24-25: Port 12 output max speed bits.

OSPD13

Bits 26-27: Port 13 output max speed bits.

OSPD14

Bits 28-29: Port 14 output max speed bits.

OSPD15

Bits 30-31: Port 15 output max speed bits.

PUD

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUD15
rw 		PUD14
rw 		PUD13
rw 		PUD12
rw 		PUD11
rw 		PUD10
rw 		PUD9
rw 		PUD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUD7
rw 		PUD6
rw 		PUD5
rw 		PUD4
rw 		PUD3
rw 		PUD2
rw 		PUD1
rw 		PUD0
rw
Toggle Fields.

PUD0

Bits 0-1: Port 0 pull-up or pull-down bits.

PUD1

Bits 2-3: Port 1 pull-up or pull-down bits.

PUD2

Bits 4-5: Port 2 pull-up or pull-down bits.

PUD3

Bits 6-7: Port 3 pull-up or pull-down bits.

PUD4

Bits 8-9: Port 4 pull-up or pull-down bits.

PUD5

Bits 10-11: Port 5 pull-up or pull-down bits.

PUD6

Bits 12-13: Port 6 pull-up or pull-down bits.

PUD7

Bits 14-15: Port 7 pull-up or pull-down bits.

PUD8

Bits 16-17: Port 8 pull-up or pull-down bits.

PUD9

Bits 18-19: Port 9 pull-up or pull-down bits.

PUD10

Bits 20-21: Port 10 pull-up or pull-down bits.

PUD11

Bits 22-23: Port 11 pull-up or pull-down bits.

PUD12

Bits 24-25: Port 12 pull-up or pull-down bits.

PUD13

Bits 26-27: Port 13 pull-up or pull-down bits.

PUD14

Bits 28-29: Port 14 pull-up or pull-down bits.

PUD15

Bits 30-31: Port 15 pull-up or pull-down bits.

ISTAT

GPIO port input status register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status (y = 0).

ISTAT1

Bit 1: Port input status (y = 1).

ISTAT2

Bit 2: Port input status (y = 2).

ISTAT3

Bit 3: Port input status (y = 3).

ISTAT4

Bit 4: Port input status (y = 4).

ISTAT5

Bit 5: Port input status (y = 5).

ISTAT6

Bit 6: Port input status (y = 6).

ISTAT7

Bit 7: Port input status (y = 7).

ISTAT8

Bit 8: Port input status (y = 8).

ISTAT9

Bit 9: Port input status (y = 9).

ISTAT10

Bit 10: Port input status (y = 10).

ISTAT11

Bit 11: Port input status (y = 11).

ISTAT12

Bit 12: Port input status (y = 12).

ISTAT13

Bit 13: Port input status (y = 13).

ISTAT14

Bit 14: Port input status (y = 14).

ISTAT15

Bit 15: Port input status (y = 15).

OCTL

GPIO port output control register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control (y = 0).

OCTL1

Bit 1: Port output control (y = 1).

OCTL2

Bit 2: Port output control (y = 2).

OCTL3

Bit 3: Port output control (y = 3).

OCTL4

Bit 4: Port output control (y = 4).

OCTL5

Bit 5: Port output control (y = 5).

OCTL6

Bit 6: Port output control (y = 6).

OCTL7

Bit 7: Port output control (y = 7).

OCTL8

Bit 8: Port output control (y = 8).

OCTL9

Bit 9: Port output control (y = 9).

OCTL10

Bit 10: Port output control (y = 10).

OCTL11

Bit 11: Port output control (y = 11).

OCTL12

Bit 12: Port output control (y = 12).

OCTL13

Bit 13: Port output control (y = 13).

OCTL14

Bit 14: Port output control (y = 14).

OCTL15

Bit 15: Port output control (y = 15).

BOP

GPIO port bit operate register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port Set bit 0.

BOP1

Bit 1: Port Set bit 1.

BOP2

Bit 2: Port Set bit 2.

BOP3

Bit 3: Port Set bit 3.

BOP4

Bit 4: Port Set bit 4.

BOP5

Bit 5: Port Set bit 5.

BOP6

Bit 6: Port Set bit 6.

BOP7

Bit 7: Port Set bit 7.

BOP8

Bit 8: Port Set bit 8.

BOP9

Bit 9: Port Set bit 9.

BOP10

Bit 10: Port Set bit 10.

BOP11

Bit 11: Port Set bit 11.

BOP12

Bit 12: Port Set bit 12.

BOP13

Bit 13: Port Set bit 13.

BOP14

Bit 14: Port Set bit 14.

BOP15

Bit 15: Port Set bit 15.

CR0

Bit 16: Port Clear bit 0.

CR1

Bit 17: Port Clear bit 1.

CR2

Bit 18: Port Clear bit 2.

CR3

Bit 19: Port Clear bit 3.

CR4

Bit 20: Port Clear bit 4.

CR5

Bit 21: Port Clear bit 5.

CR6

Bit 22: Port Clear bit 6.

CR7

Bit 23: Port Clear bit 7.

CR8

Bit 24: Port Clear bit 8.

CR9

Bit 25: Port Clear bit 9.

CR10

Bit 26: Port Clear bit 10.

CR11

Bit 27: Port Clear bit 11.

CR12

Bit 28: Port Clear bit 12.

CR13

Bit 29: Port Clear bit 13.

CR14

Bit 30: Port Clear bit 14.

CR15

Bit 31: Port Clear bit 15.

LOCK

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

LK1

Bit 1: Port Lock bit 1.

LK2

Bit 2: Port Lock bit 2.

LK3

Bit 3: Port Lock bit 3.

LK4

Bit 4: Port Lock bit 4.

LK5

Bit 5: Port Lock bit 5.

LK6

Bit 6: Port Lock bit 6.

LK7

Bit 7: Port Lock bit 7.

LK8

Bit 8: Port Lock bit 8.

LK9

Bit 9: Port Lock bit 9.

LK10

Bit 10: Port Lock bit 10.

LK11

Bit 11: Port Lock bit 11.

LK12

Bit 12: Port Lock bit 12.

LK13

Bit 13: Port Lock bit 13.

LK14

Bit 14: Port Lock bit 14.

LK15

Bit 15: Port Lock bit 15.

LKK

Bit 16: Lock sequence key .

AFSEL0

GPIO alternate function selected register 0

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL7
rw 		SEL6
rw 		SEL5
rw 		SEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL3
rw 		SEL2
rw 		SEL1
rw 		SEL0
rw
Toggle Fields.

SEL0

Bits 0-3: Port 0 alternate function selected.

SEL1

Bits 4-7: Port 1 alternate function selected.

SEL2

Bits 8-11: Port 2 alternate function selected.

SEL3

Bits 12-15: Port 3 alternate function selected.

SEL4

Bits 16-19: Port 4 alternate function selected.

SEL5

Bits 20-23: Port 5 alternate function selected.

SEL6

Bits 24-27: Port 6 alternate function selected.

SEL7

Bits 28-31: Port 7 alternate function selected.

AFSEL1

GPIO alternate function selected register 1

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL15
rw 		SEL14
rw 		SEL13
rw 		SEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL11
rw 		SEL10
rw 		SEL9
rw 		SEL8
rw
Toggle Fields.

SEL8

Bits 0-3: Port 8 alternate function selected.

SEL9

Bits 4-7: Port 9 alternate function selected.

SEL10

Bits 8-11: Port 10 alternate function selected.

SEL11

Bits 12-15: Port 11 alternate function selected.

SEL12

Bits 16-19: Port 12 alternate function selected.

SEL13

Bits 20-23: Port 13 alternate function selected.

SEL14

Bits 24-27: Port 14 alternate function selected.

SEL15

Bits 28-31: Port 15 alternate function selected.

BC

Bit clear register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port cleat bit.

CR1

Bit 1: Port cleat bit.

CR2

Bit 2: Port cleat bit.

CR3

Bit 3: Port cleat bit.

CR4

Bit 4: Port cleat bit.

CR5

Bit 5: Port cleat bit.

CR6

Bit 6: Port cleat bit.

CR7

Bit 7: Port cleat bit.

CR8

Bit 8: Port cleat bit.

CR9

Bit 9: Port cleat bit.

CR10

Bit 10: Port cleat bit.

CR11

Bit 11: Port cleat bit.

CR12

Bit 12: Port cleat bit.

CR13

Bit 13: Port cleat bit.

CR14

Bit 14: Port cleat bit.

CR15

Bit 15: Port cleat bit.

TG

Port bit toggle register

Offset: 0x2C, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG15
w 		TG14
w 		TG13
w 		TG12
w 		TG11
w 		TG10
w 		TG9
w 		TG8
w 		TG7
w 		TG6
w 		TG5
w 		TG4
w 		TG3
w 		TG2
w 		TG1
w 		TG0
w
Toggle Fields.

TG0

Bit 0: Port toggle bit .

TG1

Bit 1: Port toggle bit.

TG2

Bit 2: Port toggle bit.

TG3

Bit 3: Port toggle bit.

TG4

Bit 4: Port toggle bit.

TG5

Bit 5: Port toggle bit.

TG6

Bit 6: Port toggle bit.

TG7

Bit 7: Port toggle bit.

TG8

Bit 8: Port toggle bit.

TG9

Bit 9: Port toggle bit.

TG10

Bit 10: Port toggle bit.

TG11

Bit 11: Port toggle bit.

TG12

Bit 12: Port toggle bit.

TG13

Bit 13: Port toggle bit.

TG14

Bit 14: Port toggle bit.

TG15

Bit 15: Port toggle bit.

GPIOI

0x40022000: General-purpose I/Os

16/193 fields covered. Toggle Registers.

CTL

GPIO port control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTL15
rw 		CTL14
rw 		CTL13
rw 		CTL12
rw 		CTL11
rw 		CTL10
rw 		CTL9
rw 		CTL8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTL7
rw 		CTL6
rw 		CTL5
rw 		CTL4
rw 		CTL3
rw 		CTL2
rw 		CTL1
rw 		CTL0
rw
Toggle Fields.

CTL0

Bits 0-1: Port x configuration bits (x = 0).

CTL1

Bits 2-3: Port x configuration bits (x = 1).

CTL2

Bits 4-5: Port x configuration bits (x = 2).

CTL3

Bits 6-7: Port x configuration bits (x = 3).

CTL4

Bits 8-9: Port x configuration bits (x = 4 ).

CTL5

Bits 10-11: Port x configuration bits (x = 5).

CTL6

Bits 12-13: Port x configuration bits (x = 6 ).

CTL7

Bits 14-15: Port x configuration bits (x = 7).

CTL8

Bits 16-17: Port x configuration bits (x = 8).

CTL9

Bits 18-19: Port x configuration bits (x = 9).

CTL10

Bits 20-21: Port x configuration bits (x = 10).

CTL11

Bits 22-23: Port x configuration bits (x = 11).

CTL12

Bits 24-25: Port x configuration bits (x = 12).

CTL13

Bits 26-27: Port x configuration bits (x = 13).

CTL14

Bits 28-29: Port x configuration bits (x = 14).

CTL15

Bits 30-31: Port x configuration bits (x = 15).

OMODE

GPIO port output mode register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OM15
rw 		OM14
rw 		OM13
rw 		OM12
rw 		OM11
rw 		OM10
rw 		OM9
rw 		OM8
rw 		OM7
rw 		OM6
rw 		OM5
rw 		OM4
rw 		OM3
rw 		OM2
rw 		OM1
rw 		OM0
rw
Toggle Fields.

OM0

Bit 0: Port 0 output mode bit.

OM1

Bit 1: Port 1 output mode bit.

OM2

Bit 2: Port 2 output mode bit.

OM3

Bit 3: Port 3 output mode bit.

OM4

Bit 4: Port 4 output mode bit.

OM5

Bit 5: Port 5 output mode bit.

OM6

Bit 6: Port 6 output mode bit.

OM7

Bit 7: Port 7 output mode bit.

OM8

Bit 8: Port 8 output mode bit.

OM9

Bit 9: Port 9 output mode bit.

OM10

Bit 10: Port 10 output mode bit.

OM11

Bit 11: Port 11 output mode bit.

OM12

Bit 12: Port 12 output mode bit.

OM13

Bit 13: Port 13 output mode bit.

OM14

Bit 14: Port 14 output mode bit.

OM15

Bit 15: Port 15 output mode bit.

OSPD

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPD15
rw 		OSPD14
rw 		OSPD13
rw 		OSPD12
rw 		OSPD11
rw 		OSPD10
rw 		OSPD9
rw 		OSPD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPD7
rw 		OSPD6
rw 		OSPD5
rw 		OSPD4
rw 		OSPD3
rw 		OSPD2
rw 		OSPD1
rw 		OSPD0
rw
Toggle Fields.

OSPD0

Bits 0-1: Port 0 output max speed bits.

OSPD1

Bits 2-3: Port 1 output max speed bits.

OSPD2

Bits 4-5: Port 2 output max speed bits.

OSPD3

Bits 6-7: Port 3 output max speed bits.

OSPD4

Bits 8-9: Port 4 output max speed bits.

OSPD5

Bits 10-11: Port 5 output max speed bits.

OSPD6

Bits 12-13: Port 6 output max speed bits.

OSPD7

Bits 14-15: Port 7 output max speed bits.

OSPD8

Bits 16-17: Port 8 output max speed bits.

OSPD9

Bits 18-19: Port 9 output max speed bits.

OSPD10

Bits 20-21: Port 10 output max speed bits.

OSPD11

Bits 22-23: Port 11 output max speed bits.

OSPD12

Bits 24-25: Port 12 output max speed bits.

OSPD13

Bits 26-27: Port 13 output max speed bits.

OSPD14

Bits 28-29: Port 14 output max speed bits.

OSPD15

Bits 30-31: Port 15 output max speed bits.

PUD

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUD15
rw 		PUD14
rw 		PUD13
rw 		PUD12
rw 		PUD11
rw 		PUD10
rw 		PUD9
rw 		PUD8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUD7
rw 		PUD6
rw 		PUD5
rw 		PUD4
rw 		PUD3
rw 		PUD2
rw 		PUD1
rw 		PUD0
rw
Toggle Fields.

PUD0

Bits 0-1: Port 0 pull-up or pull-down bits.

PUD1

Bits 2-3: Port 1 pull-up or pull-down bits.

PUD2

Bits 4-5: Port 2 pull-up or pull-down bits.

PUD3

Bits 6-7: Port 3 pull-up or pull-down bits.

PUD4

Bits 8-9: Port 4 pull-up or pull-down bits.

PUD5

Bits 10-11: Port 5 pull-up or pull-down bits.

PUD6

Bits 12-13: Port 6 pull-up or pull-down bits.

PUD7

Bits 14-15: Port 7 pull-up or pull-down bits.

PUD8

Bits 16-17: Port 8 pull-up or pull-down bits.

PUD9

Bits 18-19: Port 9 pull-up or pull-down bits.

PUD10

Bits 20-21: Port 10 pull-up or pull-down bits.

PUD11

Bits 22-23: Port 11 pull-up or pull-down bits.

PUD12

Bits 24-25: Port 12 pull-up or pull-down bits.

PUD13

Bits 26-27: Port 13 pull-up or pull-down bits.

PUD14

Bits 28-29: Port 14 pull-up or pull-down bits.

PUD15

Bits 30-31: Port 15 pull-up or pull-down bits.

ISTAT

GPIO port input status register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT15
r 		ISTAT14
r 		ISTAT13
r 		ISTAT12
r 		ISTAT11
r 		ISTAT10
r 		ISTAT9
r 		ISTAT8
r 		ISTAT7
r 		ISTAT6
r 		ISTAT5
r 		ISTAT4
r 		ISTAT3
r 		ISTAT2
r 		ISTAT1
r 		ISTAT0
r
Toggle Fields.

ISTAT0

Bit 0: Port input status (y = 0).

ISTAT1

Bit 1: Port input status (y = 1).

ISTAT2

Bit 2: Port input status (y = 2).

ISTAT3

Bit 3: Port input status (y = 3).

ISTAT4

Bit 4: Port input status (y = 4).

ISTAT5

Bit 5: Port input status (y = 5).

ISTAT6

Bit 6: Port input status (y = 6).

ISTAT7

Bit 7: Port input status (y = 7).

ISTAT8

Bit 8: Port input status (y = 8).

ISTAT9

Bit 9: Port input status (y = 9).

ISTAT10

Bit 10: Port input status (y = 10).

ISTAT11

Bit 11: Port input status (y = 11).

ISTAT12

Bit 12: Port input status (y = 12).

ISTAT13

Bit 13: Port input status (y = 13).

ISTAT14

Bit 14: Port input status (y = 14).

ISTAT15

Bit 15: Port input status (y = 15).

OCTL

GPIO port output control register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTL15
rw 		OCTL14
rw 		OCTL13
rw 		OCTL12
rw 		OCTL11
rw 		OCTL10
rw 		OCTL9
rw 		OCTL8
rw 		OCTL7
rw 		OCTL6
rw 		OCTL5
rw 		OCTL4
rw 		OCTL3
rw 		OCTL2
rw 		OCTL1
rw 		OCTL0
rw
Toggle Fields.

OCTL0

Bit 0: Port output control (y = 0).

OCTL1

Bit 1: Port output control (y = 1).

OCTL2

Bit 2: Port output control (y = 2).

OCTL3

Bit 3: Port output control (y = 3).

OCTL4

Bit 4: Port output control (y = 4).

OCTL5

Bit 5: Port output control (y = 5).

OCTL6

Bit 6: Port output control (y = 6).

OCTL7

Bit 7: Port output control (y = 7).

OCTL8

Bit 8: Port output control (y = 8).

OCTL9

Bit 9: Port output control (y = 9).

OCTL10

Bit 10: Port output control (y = 10).

OCTL11

Bit 11: Port output control (y = 11).

OCTL12

Bit 12: Port output control (y = 12).

OCTL13

Bit 13: Port output control (y = 13).

OCTL14

Bit 14: Port output control (y = 14).

OCTL15

Bit 15: Port output control (y = 15).

BOP

GPIO port bit operate register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOP15
w 		BOP14
w 		BOP13
w 		BOP12
w 		BOP11
w 		BOP10
w 		BOP9
w 		BOP8
w 		BOP7
w 		BOP6
w 		BOP5
w 		BOP4
w 		BOP3
w 		BOP2
w 		BOP1
w 		BOP0
w
Toggle Fields.

BOP0

Bit 0: Port Set bit 0.

BOP1

Bit 1: Port Set bit 1.

BOP2

Bit 2: Port Set bit 2.

BOP3

Bit 3: Port Set bit 3.

BOP4

Bit 4: Port Set bit 4.

BOP5

Bit 5: Port Set bit 5.

BOP6

Bit 6: Port Set bit 6.

BOP7

Bit 7: Port Set bit 7.

BOP8

Bit 8: Port Set bit 8.

BOP9

Bit 9: Port Set bit 9.

BOP10

Bit 10: Port Set bit 10.

BOP11

Bit 11: Port Set bit 11.

BOP12

Bit 12: Port Set bit 12.

BOP13

Bit 13: Port Set bit 13.

BOP14

Bit 14: Port Set bit 14.

BOP15

Bit 15: Port Set bit 15.

CR0

Bit 16: Port Clear bit 0.

CR1

Bit 17: Port Clear bit 1.

CR2

Bit 18: Port Clear bit 2.

CR3

Bit 19: Port Clear bit 3.

CR4

Bit 20: Port Clear bit 4.

CR5

Bit 21: Port Clear bit 5.

CR6

Bit 22: Port Clear bit 6.

CR7

Bit 23: Port Clear bit 7.

CR8

Bit 24: Port Clear bit 8.

CR9

Bit 25: Port Clear bit 9.

CR10

Bit 26: Port Clear bit 10.

CR11

Bit 27: Port Clear bit 11.

CR12

Bit 28: Port Clear bit 12.

CR13

Bit 29: Port Clear bit 13.

CR14

Bit 30: Port Clear bit 14.

CR15

Bit 31: Port Clear bit 15.

LOCK

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LK15
rw 		LK14
rw 		LK13
rw 		LK12
rw 		LK11
rw 		LK10
rw 		LK9
rw 		LK8
rw 		LK7
rw 		LK6
rw 		LK5
rw 		LK4
rw 		LK3
rw 		LK2
rw 		LK1
rw 		LK0
rw
Toggle Fields.

LK0

Bit 0: Port Lock bit 0.

LK1

Bit 1: Port Lock bit 1.

LK2

Bit 2: Port Lock bit 2.

LK3

Bit 3: Port Lock bit 3.

LK4

Bit 4: Port Lock bit 4.

LK5

Bit 5: Port Lock bit 5.

LK6

Bit 6: Port Lock bit 6.

LK7

Bit 7: Port Lock bit 7.

LK8

Bit 8: Port Lock bit 8.

LK9

Bit 9: Port Lock bit 9.

LK10

Bit 10: Port Lock bit 10.

LK11

Bit 11: Port Lock bit 11.

LK12

Bit 12: Port Lock bit 12.

LK13

Bit 13: Port Lock bit 13.

LK14

Bit 14: Port Lock bit 14.

LK15

Bit 15: Port Lock bit 15.

LKK

Bit 16: Lock sequence key .

AFSEL0

GPIO alternate function selected register 0

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL7
rw 		SEL6
rw 		SEL5
rw 		SEL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL3
rw 		SEL2
rw 		SEL1
rw 		SEL0
rw
Toggle Fields.

SEL0

Bits 0-3: Port 0 alternate function selected.

SEL1

Bits 4-7: Port 1 alternate function selected.

SEL2

Bits 8-11: Port 2 alternate function selected.

SEL3

Bits 12-15: Port 3 alternate function selected.

SEL4

Bits 16-19: Port 4 alternate function selected.

SEL5

Bits 20-23: Port 5 alternate function selected.

SEL6

Bits 24-27: Port 6 alternate function selected.

SEL7

Bits 28-31: Port 7 alternate function selected.

AFSEL1

GPIO alternate function selected register 1

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL15
rw 		SEL14
rw 		SEL13
rw 		SEL12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEL11
rw 		SEL10
rw 		SEL9
rw 		SEL8
rw
Toggle Fields.

SEL8

Bits 0-3: Port 8 alternate function selected.

SEL9

Bits 4-7: Port 9 alternate function selected.

SEL10

Bits 8-11: Port 10 alternate function selected.

SEL11

Bits 12-15: Port 11 alternate function selected.

SEL12

Bits 16-19: Port 12 alternate function selected.

SEL13

Bits 20-23: Port 13 alternate function selected.

SEL14

Bits 24-27: Port 14 alternate function selected.

SEL15

Bits 28-31: Port 15 alternate function selected.

BC

Bit clear register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR15
w 		CR14
w 		CR13
w 		CR12
w 		CR11
w 		CR10
w 		CR9
w 		CR8
w 		CR7
w 		CR6
w 		CR5
w 		CR4
w 		CR3
w 		CR2
w 		CR1
w 		CR0
w
Toggle Fields.

CR0

Bit 0: Port cleat bit.

CR1

Bit 1: Port cleat bit.

CR2

Bit 2: Port cleat bit.

CR3

Bit 3: Port cleat bit.

CR4

Bit 4: Port cleat bit.

CR5

Bit 5: Port cleat bit.

CR6

Bit 6: Port cleat bit.

CR7

Bit 7: Port cleat bit.

CR8

Bit 8: Port cleat bit.

CR9

Bit 9: Port cleat bit.

CR10

Bit 10: Port cleat bit.

CR11

Bit 11: Port cleat bit.

CR12

Bit 12: Port cleat bit.

CR13

Bit 13: Port cleat bit.

CR14

Bit 14: Port cleat bit.

CR15

Bit 15: Port cleat bit.

TG

Port bit toggle register

Offset: 0x2C, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG15
w 		TG14
w 		TG13
w 		TG12
w 		TG11
w 		TG10
w 		TG9
w 		TG8
w 		TG7
w 		TG6
w 		TG5
w 		TG4
w 		TG3
w 		TG2
w 		TG1
w 		TG0
w
Toggle Fields.

TG0

Bit 0: Port toggle bit .

TG1

Bit 1: Port toggle bit.

TG2

Bit 2: Port toggle bit.

TG3

Bit 3: Port toggle bit.

TG4

Bit 4: Port toggle bit.

TG5

Bit 5: Port toggle bit.

TG6

Bit 6: Port toggle bit.

TG7

Bit 7: Port toggle bit.

TG8

Bit 8: Port toggle bit.

TG9

Bit 9: Port toggle bit.

TG10

Bit 10: Port toggle bit.

TG11

Bit 11: Port toggle bit.

TG12

Bit 12: Port toggle bit.

TG13

Bit 13: Port toggle bit.

TG14

Bit 14: Port toggle bit.

TG15

Bit 15: Port toggle bit.

HS_DEVICE

0x40040800: USB on the go high speed device

49/333 fields covered. Toggle Registers.

DCFG

device configuration register (DCFG)

Offset: 0x0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPFT
rw 		DAR
rw 		NZLSOH
rw 		DS
rw
Toggle Fields.

DS

Bits 0-1: Device speed.

NZLSOH

Bit 2: Non-zero-length status OUT handshake.

DAR

Bits 4-10: Device address.

EOPFT

Bits 11-12: end of periodic frame time.

DCTL

device control register (DCTL)

Offset: 0x4, reset: 0x00000000, access: Unspecified

2/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POIF
rw 		CGONAK
rw 		SGONAK
rw 		CGINAK
rw 		SGINAK
rw 		GONS
r 		GINS
r 		SD
rw 		RWKUP
rw
Toggle Fields.

RWKUP

Bit 0: Remote wakeup signaling.

SD

Bit 1: Soft disconnect.

GINS

Bit 2: Global IN NAK status.

GONS

Bit 3: Global OUT NAK status.

SGINAK

Bit 7: Set global IN NAK.

CGINAK

Bit 8: Clear global IN NAK.

SGONAK

Bit 9: Set global OUT NAK.

CGONAK

Bit 10: Clear global OUT NAK.

POIF

Bit 11: Power-on initialization finished.

DSTAT

device status register (DSTAT)

Offset: 0x8, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FNRSOF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNRSOF
r 		ES
r 		SPST
r
Toggle Fields.

SPST

Bit 0: Suspend status.

ES

Bits 1-2: Enumerated speed.

FNRSOF

Bits 8-21: Frame number of the received SOF.

DIEPINTEN

device IN endpoint common interrupt mask register (DIEPINTEN)

Offset: 0x10, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAKEN
rw 		TXFEEN
rw 		IEPNEEN
rw 		EPTXFUDEN
rw 		CITOEN
rw 		EPDISEN
rw 		TFEN
rw
Toggle Fields.

TFEN

Bit 0: Transfer completed interrupt enable.

EPDISEN

Bit 1: Endpoint disabled interrupt enable.

CITOEN

Bit 3: Control IN timeout condition interrupt enable (Non-isochronous endpoints).

EPTXFUDEN

Bit 4: Endpoint Tx FIFO underrun interrupt enable bit.

IEPNEEN

Bit 6: IN endpoint NAK effective interrupt enable.

TXFEEN

Bit 7: Trabsmit FIFO empty interrupt enable.

NAKEN

Bit 13: NAK handshake sent by USBHS interrupt enable bit.

DOEPINTEN

device OUT endpoint common interrupt enable register (DOEPINTEN)

Offset: 0x14, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYETEN
rw 		BTBSTPEN
rw 		EPRXFOVREN
rw 		STPFEN
rw 		EPDISEN
rw 		TFEN
rw
Toggle Fields.

TFEN

Bit 0: Transfer completed interrupt enable.

EPDISEN

Bit 1: Endpoint disabled interrupt enable.

STPFEN

Bit 3: SETUP phase done interrupt enable.

EPRXFOVREN

Bit 4: Endpoint Rx FIFO overrun interrupt enable.

BTBSTPEN

Bit 6: Back-to-back SETUP packets ( Only for control OUT endpoint) interrupt enable bit.

NYETEN

Bit 14: NYET handshake is sent interrupt enable.

DAEPINT

device all endpoints interrupt register (DAEPINT)

Offset: 0x18, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPITB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPITB
r
Toggle Fields.

IEPITB

Bits 0-5: Device all IN endpoint interrupt bits.

OEPITB

Bits 16-21: Device all OUT endpoint interrupt bits.

DAEPINTEN

Device all endpoints interrupt enable register (DAEPINTEN)

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPIE
rw
Toggle Fields.

IEPIE

Bits 0-5: IN endpoint interrupt enable bits.

OEPIE

Bits 16-21: OUT endpoint interrupt enable bits.

DVBUSDT

device VBUS discharge time register

Offset: 0x28, reset: 0x000017D7, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DVBUSDT
rw
Toggle Fields.

DVBUSDT

Bits 0-15: Device VBUS discharge time.

DVBUSPT

device VBUS pulsing time register

Offset: 0x2C, reset: 0x000005B8, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DVBUSPT
rw
Toggle Fields.

DVBUSPT

Bits 0-11: Device VBUS pulsing time.

DIEPFEINTEN

device IN endpoint FIFO empty interrupt enable register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTXFEIE
rw
Toggle Fields.

IEPTXFEIE

Bits 0-5: IN EP Tx FIFO empty interrupt enable bits.

DEP1INT

device endpoint 1 interrupt register

Offset: 0x38, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEP1INT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEP1INT
rw
Toggle Fields.

IEP1INT

Bit 1: IN endpoint 1 interrupt bits.

OEP1INT

Bit 17: OUT endpoint 1 interrupt bits.

DEP1INTEN

device endpoint 1 interrupt enable register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEP1INTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEP1INTEN
rw
Toggle Fields.

IEP1INTEN

Bit 1: IN endpoint 1 interrupt enable bits.

OEP1INTEN

Bit 17: OUT endpoint 1 interrupt enable bits.

DIEP1INTEN

device IN endpoint 1 interrupt mask register (DIEP1INTEN)

Offset: 0x44, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAKEN
rw 		IEPNEEN
rw 		EPTXFUDEN
rw 		CITOEN
rw 		EPDISEN
rw 		TFEN
rw
Toggle Fields.

TFEN

Bit 0: Transfer finished interrupt enable.

EPDISEN

Bit 1: Endpoint disabled interrupt enable.

CITOEN

Bit 3: Control IN timeout condition interrupt enable (Non-isochronous endpoints).

EPTXFUDEN

Bit 4: Endpoint Tx FIFO underrun interrupt enable bit.

IEPNEEN

Bit 6: IN endpoint NAK effective interrupt enable.

NAKEN

Bit 13: NAK handshake sent by USBHS interrupt enable bit.

DOEP1INTEN

device OUT endpoint common interrupt enable register (DOEP1INTEN)

Offset: 0x84, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYETEN
rw 		BTBSTPEN
rw 		EPRXFOVREN
rw 		STPFEN
rw 		EPDISEN
rw 		TFEN
rw
Toggle Fields.

TFEN

Bit 0: Transfer completed interrupt enable.

EPDISEN

Bit 1: Endpoint disabled interrupt enable.

STPFEN

Bit 3: SETUP phase done interrupt enable.

EPRXFOVREN

Bit 4: Endpoint Rx FIFO overrun interrupt enable.

BTBSTPEN

Bit 6: Back-to-back SETUP packets ( Only for control OUT endpoint) interrupt enable bit.

NYETEN

Bit 14: NYET handshake is sent interrupt enable bit.

DIEP0CTL

Device IN endpoint 0 control register (USBHS_DIEP0CTL)

Offset: 0x100, reset: 0x00008000, access: Unspecified

5/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
r 		EPD
r 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYPE
r 		NAKS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
r 		MPL
rw
Toggle Fields.

MPL

Bits 0-1: Maximum packet length.

EPACT

Bit 15: endpoint active.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: TxFIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DIEP0INTF

Device IN endpoint-0 interrupt register

Offset: 0x108, reset: 0x00000080, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		TXFE
r 		IEPNE
rw 		EPTXFUD
rw 		CITO
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint finished.

CITO

Bit 3: Control in timeout interrupt.

EPTXFUD

Bit 4: Endpoint Tx FIFO underrun.

IEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

NAK

Bit 13: NAK handshake sent by USBHS.

DIEP0LEN

device IN endpoint-0 transfer length register

Offset: 0x110, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-6: Transfer length.

PCNT

Bits 19-20: Packet count.

DIEP0DMAADDR

device IN endpoint 0 DMA address register

Offset: 0x114, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

DIEP0TFSTAT

device IN endpoint 0 transmit FIFO status register

Offset: 0x118, reset: 0x00000200, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTFS
r
Toggle Fields.

IEPTFS

Bits 0-15: IN endpoint TxFIFO space available.

DIEP1CTL

Device IN endpoint-x control register

Offset: 0x120, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: Tx FIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVNFRM.

SD1PID_SODDFRM

Bit 29: Set DATA1 PID/Set odd frame.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DIEP1INTF

Device IN endpoint-1 interrupt register

Offset: 0x128, reset: 0x00000080, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		TXFE
r 		IEPNE
rw 		EPTXFUD
rw 		CITO
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint finished.

CITO

Bit 3: Control in timeout interrupt.

EPTXFUD

Bit 4: Endpoint Tx FIFO underrun.

IEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

NAK

Bit 13: NAK handshake sent by USBHS.

DIEP1LEN

device IN endpoint-1 transfer length register

Offset: 0x130, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DIEP1DMAADDR

device IN endpoint 1 DMA address register

Offset: 0x134, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

DIEP1TFSTAT

device IN endpoint 1 transmit FIFO status register

Offset: 0x138, reset: 0x00000200, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTFS
r
Toggle Fields.

IEPTFS

Bits 0-15: IN endpoint TxFIFO space available.

DIEP2CTL

device endpoint-2 control register

Offset: 0x140, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: Tx FIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVNFRM.

SD1PID_SODDFRM

Bit 29: Set DATA1 PID/Set odd frame.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DIEP2INTF

Device IN endpoint-2 interrupt register

Offset: 0x148, reset: 0x00000080, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		TXFE
r 		IEPNE
rw 		EPTXFUD
rw 		CITO
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint finished.

CITO

Bit 3: Control in timeout interrupt.

EPTXFUD

Bit 4: Endpoint Tx FIFO underrun.

IEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

NAK

Bit 13: NAK handshake sent by USBHS.

DIEP2LEN

device IN endpoint-2 transfer length register

Offset: 0x150, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DIEP2DMAADDR

device IN endpoint 2 DMA address register

Offset: 0x154, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

DIEP2TFSTAT

device IN endpoint 2 transmit FIFO status register

Offset: 0x158, reset: 0x00000200, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTFS
r
Toggle Fields.

IEPTFS

Bits 0-15: IN endpoint TxFIFO space available.

DIEP3CTL

device endpoint-3 control register

Offset: 0x160, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: Tx FIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVNFRM.

SD1PID_SODDFRM

Bit 29: Set DATA1 PID/Set odd frame.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DIEP3INTF

Device IN endpoint-3 interrupt register

Offset: 0x168, reset: 0x00000080, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		TXFE
r 		IEPNE
rw 		EPTXFUD
rw 		CITO
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint finished.

CITO

Bit 3: Control in timeout interrupt.

EPTXFUD

Bit 4: Endpoint Tx FIFO underrun.

IEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

NAK

Bit 13: NAK handshake sent by USBHS.

DIEP3LEN

device IN endpoint-3 transfer length register

Offset: 0x170, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DIEP3DMAADDR

device IN endpoint 3 DMA address register

Offset: 0x174, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

DIEP3TFSTAT

device IN endpoint 3 transmit FIFO status register

Offset: 0x178, reset: 0x00000200, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTFS
r
Toggle Fields.

IEPTFS

Bits 0-15: IN endpoint TxFIFO space available.

DIEP4CTL

device endpoint-4 control register

Offset: 0x180, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: Tx FIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVNFRM.

SD1PID_SODDFRM

Bit 29: Set DATA1 PID/Set odd frame.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DIEP4INTF

Device IN endpoint-4 interrupt register

Offset: 0x188, reset: 0x00000080, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		TXFE
r 		IEPNE
rw 		EPTXFUD
rw 		CITO
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint finished.

CITO

Bit 3: Control in timeout interrupt.

EPTXFUD

Bit 4: Endpoint Tx FIFO underrun.

IEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

NAK

Bit 13: NAK handshake sent by USBHS.

DIEP4LEN

device IN endpoint-4 transfer length register

Offset: 0x190, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DIEP4DMAADDR

device IN endpoint 4 DMA address register

Offset: 0x194, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

DIEP4TFSTAT

device IN endpoint 4 transmit FIFO status register

Offset: 0x198, reset: 0x00000200, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTFS
r
Toggle Fields.

IEPTFS

Bits 0-15: IN endpoint TxFIFO space available.

DIEP5CTL

device endpoint-5 control register

Offset: 0x1A0, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

STALL

Bit 21: STALL handshake.

TXFNUM

Bits 22-25: Tx FIFO number.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVNFRM.

SD1PID_SODDFRM

Bit 29: Set DATA1 PID/Set odd frame.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DIEP5INTF

Device IN endpoint-5 interrupt register

Offset: 0x1A8, reset: 0x00000080, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		TXFE
r 		IEPNE
rw 		EPTXFUD
rw 		CITO
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint finished.

CITO

Bit 3: Control in timeout interrupt.

EPTXFUD

Bit 4: Endpoint Tx FIFO underrun.

IEPNE

Bit 6: IN endpoint NAK effective.

TXFE

Bit 7: Transmit FIFO empty.

NAK

Bit 13: NAK handshake sent by USBHS.

DIEP5LEN

device IN endpoint-5 transfer length register

Offset: 0x1B0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

MCNT

Bits 29-30: Multi count.

DIEP5DMAADDR

device IN endpoint 5 DMA address register

Offset: 0x1B4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

DIEP5TFSTAT

device IN endpoint 5 transmit FIFO status register

Offset: 0x1B8, reset: 0x00000200, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTFS
r
Toggle Fields.

IEPTFS

Bits 0-15: IN endpoint TxFIFO space available.

DOEP0CTL

Device OUT endpoint-0 control register

Offset: 0x300, reset: 0x00008000, access: Unspecified

5/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
w 		EPD
r 		SNAK
w 		CNAK
w 		STALL
rw 		SNOOP
rw 		EPTYPE
r 		NAKS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
r 		MPL
r
Toggle Fields.

MPL

Bits 0-1: Maximum packet length.

EPACT

Bit 15: Endpoint active.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

SNOOP

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DOEP0INTF

device out endpoint-0 interrupt register

Offset: 0x308, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw 		BTBSTP
rw 		EPRXFOVR
rw 		STPF
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint disabled.

STPF

Bit 3: Setup phase finished.

EPRXFOVR

Bit 4: Endpoint Rx FIFO overrun.

BTBSTP

Bit 6: Back-to-back SETUP packets.

NYET

Bit 14: NYET handshake is sent.

DOEP0LEN

device OUT endpoint-0 transfer length register

Offset: 0x310, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STPCNT
rw 		PCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-6: Transfer length.

PCNT

Bit 19: Packet count.

STPCNT

Bits 29-30: SETUP packet count.

DOEP0DMAADDR

device OUT endpoint 0 DMA address register

Offset: 0x314, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

DOEP1CTL

Device OUT endpoint-1 control register

Offset: 0x320, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNOOP
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

SNOOP

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVENFRM.

SD1PID_SODDFRM

Bit 29: SD1PID/SODDFRM.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DOEP1INTF

device out endpoint-1 interrupt register

Offset: 0x328, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw 		BTBSTP
rw 		EPRXFOVR
rw 		STPF
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint disabled.

STPF

Bit 3: Setup phase finished.

EPRXFOVR

Bit 4: Endpoint Rx FIFO overrun.

BTBSTP

Bit 6: Back-to-back SETUP packets.

NYET

Bit 14: NYET handshake is sent.

DOEP1LEN

device OUT endpoint-1 transfer length register

Offset: 0x330, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STPCNT_RXDPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

STPCNT_RXDPID

Bits 29-30: SETUP packet count/Received data PID.

DOEP1DMAADDR

device OUT endpoint 1 DMA address register

Offset: 0x334, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

DOEP2CTL

Device OUT endpoint-2 control register

Offset: 0x340, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNOOP
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

SNOOP

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVENFRM.

SD1PID_SODDFRM

Bit 29: SD1PID/SODDFRM.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DOEP2INTF

device out endpoint-2 interrupt register

Offset: 0x348, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw 		BTBSTP
rw 		EPRXFOVR
rw 		STPF
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint disabled.

STPF

Bit 3: Setup phase finished.

EPRXFOVR

Bit 4: Endpoint Rx FIFO overrun.

BTBSTP

Bit 6: Back-to-back SETUP packets.

NYET

Bit 14: NYET handshake is sent.

DOEP2LEN

device OUT endpoint-2 transfer length register

Offset: 0x350, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STPCNT_RXDPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

STPCNT_RXDPID

Bits 29-30: SETUP packet count/Received data PID.

DOEP2DMAADDR

device OUT endpoint 2 DMA address register

Offset: 0x354, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

DOEP3CTL

Device OUT endpoint-3 control register

Offset: 0x360, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNOOP
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

SNOOP

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVENFRM.

SD1PID_SODDFRM

Bit 29: SD1PID/SODDFRM.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DOEP3INTF

device out endpoint-3 interrupt register

Offset: 0x368, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw 		BTBSTP
rw 		EPRXFOVR
rw 		STPF
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint disabled.

STPF

Bit 3: Setup phase finished.

EPRXFOVR

Bit 4: Endpoint Rx FIFO overrun.

BTBSTP

Bit 6: Back-to-back SETUP packets.

NYET

Bit 14: NYET handshake is sent.

DOEP3LEN

device OUT endpoint-3 transfer length register

Offset: 0x370, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STPCNT_RXDPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

STPCNT_RXDPID

Bits 29-30: SETUP packet count/Received data PID.

DOEP3DMAADDR

device OUT endpoint 3 DMA address register

Offset: 0x374, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

DOEP4CTL

Device OUT endpoint-4 control register

Offset: 0x380, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNOOP
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

SNOOP

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVENFRM.

SD1PID_SODDFRM

Bit 29: SD1PID/SODDFRM.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DOEP4INTF

device out endpoint-4 interrupt register

Offset: 0x388, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw 		BTBSTP
rw 		EPRXFOVR
rw 		STPF
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint disabled.

STPF

Bit 3: Setup phase finished.

EPRXFOVR

Bit 4: Endpoint Rx FIFO overrun.

BTBSTP

Bit 6: Back-to-back SETUP packets.

NYET

Bit 14: NYET handshake is sent.

DOEP4LEN

device OUT endpoint-4 transfer length register

Offset: 0x390, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STPCNT_RXDPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

STPCNT_RXDPID

Bits 29-30: SETUP packet count/Received data PID.

DOEP4DMAADDR

device OUT endpoint 4 DMA address register

Offset: 0x394, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

DOEP5CTL

Device OUT endpoint-5 control register

Offset: 0x3A0, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPEN
rw 		EPD
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVENFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNOOP
rw 		EPTYPE
rw 		NAKS
r 		EOFRM_DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPACT
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: maximum packet length.

EPACT

Bit 15: Endpoint active.

EOFRM_DPID

Bit 16: EOFRM/DPID.

NAKS

Bit 17: NAK status.

EPTYPE

Bits 18-19: Endpoint type.

SNOOP

Bit 20: Snoop mode.

STALL

Bit 21: STALL handshake.

CNAK

Bit 26: Clear NAK.

SNAK

Bit 27: Set NAK.

SD0PID_SEVENFRM

Bit 28: SD0PID/SEVENFRM.

SD1PID_SODDFRM

Bit 29: SD1PID/SODDFRM.

EPD

Bit 30: Endpoint disable.

EPEN

Bit 31: Endpoint enable.

DOEP5INTF

device out endpoint-5 interrupt register

Offset: 0x3A8, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYET
rw 		BTBSTP
rw 		EPRXFOVR
rw 		STPF
rw 		EPDIS
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer finished.

EPDIS

Bit 1: Endpoint disabled.

STPF

Bit 3: Setup phase finished.

EPRXFOVR

Bit 4: Endpoint Rx FIFO overrun.

BTBSTP

Bit 6: Back-to-back SETUP packets.

NYET

Bit 14: NYET handshake is sent.

DOEP5LEN

device OUT endpoint-5 transfer length register

Offset: 0x3B0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STPCNT_RXDPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

STPCNT_RXDPID

Bits 29-30: SETUP packet count/Received data PID.

DOEP5DMAADDR

device OUT endpoint 5 DMA address register

Offset: 0x3B4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

HS_GLOBAL

0x40040000: USB high speed global registers

39/129 fields covered. Toggle Registers.

GOTGCS

control and status register (GOTGCS)

Offset: 0x0, reset: 0x00000800, access: Unspecified

6/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSV
r 		ASV
r 		DI
r 		CIDPS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DHNPEN
rw 		HHNPEN
rw 		HNPREQ
rw 		HNPS
r 		SRPREQ
rw 		SRPS
r
Toggle Fields.

SRPS

Bit 0: Session request success.

SRPREQ

Bit 1: SRP request.

HNPS

Bit 8: Host negotiation success.

HNPREQ

Bit 9: HNP request.

HHNPEN

Bit 10: Host HNP enable.

DHNPEN

Bit 11: Device HNP enabled.

CIDPS

Bit 16: ID pin status.

DI

Bit 17: Debounce interval of a detected connection.

ASV

Bit 18: A-session valid.

BSV

Bit 19: B-session valid.

GOTGINTF

Global OTG interrupt register (GOTGINTF)

Offset: 0x4, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DF
rw 		ADTO
rw 		HNPDET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HNPEND
rw 		SRPEND
rw 		SESEND
rw
Toggle Fields.

SESEND

Bit 2: Session end .

SRPEND

Bit 8: SRPEND.

HNPEND

Bit 9: HNP end.

HNPDET

Bit 17: Host negotiation detected.

ADTO

Bit 18: A-device timeout.

DF

Bit 19: Debounce finish.

GAHBCS

Global AHB configuration register (GAHBCS)

Offset: 0x8, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFTH
rw 		TXFTH
rw 		DMAEN
rw 		BURST
rw 		GINTEN
rw
Toggle Fields.

GINTEN

Bit 0: Global interrupt enable.

BURST

Bits 1-4: AHB burst type used by DMA.

DMAEN

Bit 5: DMA function enalbed.

TXFTH

Bit 7: TxFIFO threshold.

PTXFTH

Bit 8: Periodic TxFIFO empty level.

GUSBCS

USB configuration register (GUSBCS)

Offset: 0xC, reset: 0x00000A00, access: Unspecified

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDM
rw 		FHM
rw 		ULPIEOI
rw 		ULPIEVD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UTT
rw 		HNPCEN
rw 		SRPCEN
rw 		EMBPHY
rw 		TOC
rw
Toggle Fields.

TOC

Bits 0-2: timeout calibration.

EMBPHY

Bit 6: Embedded PHY selected.

SRPCEN

Bit 8: SRP capability enable.

HNPCEN

Bit 9: HNP capability enable.

UTT

Bits 10-13: USB turnaround time.

ULPIEVD

Bit 20: ULPI external VBUS driver.

ULPIEOI

Bit 21: ULPI external over current indicator.

FHM

Bit 29: Force host mode.

FDM

Bit 30: Force device mode.

GRSTCTL

Global reset register (GRSTCTL)

Offset: 0x10, reset: 0x80000000, access: Unspecified

2/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAIDL
r 		DMABSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFNUM
rw 		TXFF
rw 		RXFF
rw 		HFCRST
rw 		HCSRST
rw 		CSRST
rw
Toggle Fields.

CSRST

Bit 0: Core soft reset.

HCSRST

Bit 1: HCLK soft reset.

HFCRST

Bit 2: Host frame counter reset.

RXFF

Bit 4: RxFIFO flush.

TXFF

Bit 5: TxFIFO flush.

TXFNUM

Bits 6-10: TxFIFO number.

DMABSY

Bit 30: DMA Busy.

DMAIDL

Bit 31: DMA idle state.

GINTF

Global interrupt flag register (GINTF)

Offset: 0x14, reset: 0x04000021, access: Unspecified

11/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPIF
rw 		SESIF
rw 		DISCIF
rw 		IDPSC
rw 		PTXFEIF
r 		HCIF
r 		HPIF
r 		PXNCIF_ISOONCIF
rw 		ISOINCIF
rw 		OEPIF
r 		IEPIF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPFIF
rw 		ISOOPDIF
rw 		ENUMF
rw 		RST
rw 		SP
rw 		ESP
rw 		GONAK
r 		GNPINAK
r 		NPTXFEIF
r 		RXFNEIF
r 		SOF
rw 		OTGIF
r 		MFIF
rw 		COPM
r
Toggle Fields.

COPM

Bit 0: Current mode of operation.

MFIF

Bit 1: Mode fault interrupt flag.

OTGIF

Bit 2: OTG interrupt.

SOF

Bit 3: Start of frame.

RXFNEIF

Bit 4: RxFIFO non-empty.

NPTXFEIF

Bit 5: Non-periodic TxFIFO empty interrupt flag.

GNPINAK

Bit 6: Global IN non-periodic NAK effective.

GONAK

Bit 7: Global OUT NAK effective.

ESP

Bit 10: Early suspend.

SP

Bit 11: USB suspend.

RST

Bit 12: USB reset.

ENUMF

Bit 13: Enumeration finished.

ISOOPDIF

Bit 14: Isochronous OUT packet dropped interrupt flag.

EOPFIF

Bit 15: End of periodic frame interrupt flag.

IEPIF

Bit 18: IN endpoint interrupt flag.

OEPIF

Bit 19: OUT endpoint interrupt flag.

ISOINCIF

Bit 20: Isochronous IN transfer Not Complete Interrupt Flag.

PXNCIF_ISOONCIF

Bit 21: periodic transfer not complete interrupt flag(Host mode)/isochronous OUT transfer not complete interrupt flag(Device mode).

HPIF

Bit 24: Host port interrupt flag.

HCIF

Bit 25: Host channels interrupt flag.

PTXFEIF

Bit 26: Periodic TxFIFO empty interrupt flag.

IDPSC

Bit 28: ID pin status change.

DISCIF

Bit 29: Disconnect interrupt flag.

SESIF

Bit 30: Session interrupt flag.

WKUPIF

Bit 31: wakeup interrupt flag.

GINTEN

Global interrupt enable register (GINTEN)

Offset: 0x18, reset: 0x00000000, access: Unspecified

1/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPIE
rw 		SESIE
rw 		DISCIE
rw 		IDPSCIE
rw 		PTXFEIE
rw 		HCIE
rw 		HPIE
r 		PXNCIE_ISOONCIE
rw 		ISOINCIE
rw 		OEPIE
rw 		IEPIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPFIE
rw 		ISOOPDIE
rw 		ENUMFIE
rw 		RSTIE
rw 		SPIE
rw 		ESPIE
rw 		GONAKIE
rw 		GNPINAKIE
rw 		NPTXFEIE
rw 		RXFNEIE
rw 		SOFIE
rw 		OTGIE
rw 		MFIE
rw
Toggle Fields.

MFIE

Bit 1: Mode fault interrupt enable.

OTGIE

Bit 2: OTG interrupt enable .

SOFIE

Bit 3: Start of frame interrupt enable.

RXFNEIE

Bit 4: Receive FIFO non-empty interrupt enable.

NPTXFEIE

Bit 5: Non-periodic TxFIFO empty interrupt enable.

GNPINAKIE

Bit 6: Global non-periodic IN NAK interrupt enable.

GONAKIE

Bit 7: Global OUT NAK effective interrupt enable.

ESPIE

Bit 10: Early suspend interrupt enable.

SPIE

Bit 11: USB suspend interrupt enable.

RSTIE

Bit 12: USB reset interrupt enable.

ENUMFIE

Bit 13: Enumeration finish enable.

ISOOPDIE

Bit 14: Isochronous OUT packet dropped interrupt enable.

EOPFIE

Bit 15: End of periodic frame interrupt enable.

IEPIE

Bit 18: IN endpoints interrupt enable.

OEPIE

Bit 19: OUT endpoints interrupt enable.

ISOINCIE

Bit 20: isochronous IN transfer not complete interrupt enable.

PXNCIE_ISOONCIE

Bit 21: periodic transfer not compelete Interrupt enable(Host mode)/isochronous OUT transfer not complete interrupt enable(Device mode).

HPIE

Bit 24: Host port interrupt enable.

HCIE

Bit 25: Host channels interrupt enable.

PTXFEIE

Bit 26: Periodic TxFIFO empty interrupt enable.

IDPSCIE

Bit 28: ID pin status change interrupt enable.

DISCIE

Bit 29: Disconnect interrupt enable.

SESIE

Bit 30: Session interrupt enable.

WKUPIE

Bit 31: Wakeup interrupt enable.

GRSTATR_Host

Global Receive status debug read(Host mode)

Offset: 0x1C, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPCKST
r 		DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r 		BCOUNT
r 		CNUM
r
Toggle Fields.

CNUM

Bits 0-3: Channel number.

BCOUNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

RPCKST

Bits 17-20: Reivece packet status.

GRSTATP_Host

Global Receive status debug pop(Host mode)

Offset: 0x20, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPCKST
r 		DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r 		BCOUNT
r 		CNUM
r
Toggle Fields.

CNUM

Bits 0-3: Channel number.

BCOUNT

Bits 4-14: Byte count.

DPID

Bits 15-16: Data PID.

RPCKST

Bits 17-20: Reivece packet status.

GRFLEN

Global Receive FIFO size register (OTG_FS_GRFLEN)

Offset: 0x24, reset: 0x00000200, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFD
rw
Toggle Fields.

RXFD

Bits 0-15: Rx FIFO depth.

DIEP0TFLEN

Device IN endpoint 0 transmit FIFO length (Device mode)

Offset: 0x28, reset: 0x02000200, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEP0TXRSAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEP0TXFD
rw
Toggle Fields.

IEP0TXFD

Bits 0-15: in endpoint 0 Tx FIFO depth.

IEP0TXRSAR

Bits 16-31: in endpoint 0 Tx RAM start address.

HNPTFQSTAT

Host non-periodic transmit FIFO/queue status register (HNPTFQSTAT)

Offset: 0x2C, reset: 0x00080200, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPTXRQTOP
r 		NPTXRQS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPTXFS
r
Toggle Fields.

NPTXFS

Bits 0-15: Non-periodic TxFIFO space available.

NPTXRQS

Bits 16-23: Non-periodic transmit request queue space.

NPTXRQTOP

Bits 24-30: Top entry of the non-periodic Tx request queue.

GCCFG

Global core configuration register (GCCFG)

Offset: 0x38, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VBUSIG
rw 		SOFOEN
rw 		VBUSBCEN
rw 		VBUSACEN
rw 		PWRON
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PWRON

Bit 16: Power on.

VBUSACEN

Bit 18: The VBUS A-device Comparer enable.

VBUSBCEN

Bit 19: The VBUS B-device Comparer enable.

SOFOEN

Bit 20: SOF output enable.

VBUSIG

Bit 21: VBUS ignored.

CID

core ID register

Offset: 0x3C, reset: 0x00001000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CID
rw
Toggle Fields.

CID

Bits 0-31: Core ID.

HPTFLEN

Host periodic transmit FIFO size register (HPTFLEN)

Offset: 0x100, reset: 0x02000600, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HPTXFSAR
rw
Toggle Fields.

HPTXFSAR

Bits 0-15: Host periodic TxFIFO start address.

HPTXFD

Bits 16-31: Host periodic TxFIFO depth.

DIEP1TFLEN

device IN endpoint transmit FIFO size register (DIEP1TFLEN)

Offset: 0x104, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTXRSAR
rw
Toggle Fields.

IEPTXRSAR

Bits 0-15: IN endpoint FIFO transmit RAM start address.

IEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEP2TFLEN

device IN endpoint transmit FIFO size register (DIEP2TFLEN)

Offset: 0x108, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTXRSAR
rw
Toggle Fields.

IEPTXRSAR

Bits 0-15: IN endpoint FIFO transmit RAM start address.

IEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEP3TFLEN

device IN endpoint transmit FIFO size register (DIEP3TXFLEN)

Offset: 0x10C, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTXRSAR
rw
Toggle Fields.

IEPTXRSAR

Bits 0-15: IN endpoint FIFO transmit RAM start address.

IEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEP4TFLEN

device IN endpoint transmit FIFO size register (DIEP4TXFLEN)

Offset: 0x110, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTXRSAR
rw
Toggle Fields.

IEPTXRSAR

Bits 0-15: IN endpoint FIFO transmit RAM start address.

IEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

DIEP5TFLEN

device IN endpoint transmit FIFO size register (DIEP5TXFLEN)

Offset: 0x114, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPTXRSAR
rw
Toggle Fields.

IEPTXRSAR

Bits 0-15: IN endpoint FIFO4 transmit RAM start address.

IEPTXFD

Bits 16-31: IN endpoint TxFIFO depth.

HS_HOST

0x40040400: USB on the go full speed host

9/523 fields covered. Toggle Registers.

HCTL

host control register (HCTL)

Offset: 0x0, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPDFSLS
rw
Toggle Fields.

SPDFSLS

Bit 2: Speed limited to FS and LS.

HFT

Host frame interval register

Offset: 0x4, reset: 0x0000BB80, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRI
rw
Toggle Fields.

FRI

Bits 0-15: Frame interval.

HFINFR

host frame number/frame time remaining register (HFINFR)

Offset: 0x8, reset: 0xBB800000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRNUM
r
Toggle Fields.

FRNUM

Bits 0-15: Frame number.

FRT

Bits 16-31: Frame remaining time.

HPTFQSTAT

Host periodic transmit FIFO/queue status register (HPTFQSTAT)

Offset: 0x10, reset: 0x00080200, access: Unspecified

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTXREQT
r 		PTXREQS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFS
r
Toggle Fields.

PTXFS

Bits 0-15: Periodic transmit data FIFO space available.

PTXREQS

Bits 16-23: Periodic Tx request queue space.

PTXREQT

Bits 24-31: Top of the periodic transmit request queue.

HACHINT

Host all channels interrupt register

Offset: 0x14, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HACHINT
r
Toggle Fields.

HACHINT

Bits 0-11: Host all channel interrupts.

HACHINTEN

host all channels interrupt mask register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CINTEN
rw
Toggle Fields.

CINTEN

Bits 0-11: Channel interrupt enable.

HPCS

host port control and status register (HPCS)

Offset: 0x40, reset: 0x00000000, access: Unspecified

3/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PP
rw 		PLST
r 		PRST
rw 		PSP
rw 		PREM
rw 		PEDC
rw 		PE
rw 		PCD
rw 		PCST
r
Toggle Fields.

PCST

Bit 0: Port connect status.

PCD

Bit 1: Port connect detected.

PE

Bit 2: Port enable.

PEDC

Bit 3: Port enable/disable change.

PREM

Bit 6: Port resume.

PSP

Bit 7: Port suspend.

PRST

Bit 8: Port reset.

PLST

Bits 10-11: Port line status.

PP

Bit 12: Port power.

PS

Bits 17-18: Port speed.

HCH0CTL

host channel-0 control register (HCH0CTL)

Offset: 0x100, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		MPC
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

MPC

Bits 20-21: Multiple packet count.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH0STCTL

host channel-0 split transaction control register (HCH0STCTL)

Offset: 0x104, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLEN
rw 		CSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISOPCE
rw 		HADDR
rw 		PADDR
rw
Toggle Fields.

PADDR

Bits 0-6: Port address.

HADDR

Bits 7-13: HUB address.

ISOPCE

Bits 14-15: Isochronous OUT payload continuation encoding.

CSPLT

Bit 16: Complete split enable.

SPLEN

Bit 31: Enable high speed split transaction.

HCH0INTF

host channel-0 interrupt flag register (HCH0INTF)

Offset: 0x108, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		DMAER
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer completed.

CH

Bit 1: Channel halted.

DMAER

Bit 2: DMA Error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: NYET.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH0INTEN

host channel-0 interrupt enable register (HCH0INTEN)

Offset: 0x10C, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		NYETIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		DMAERIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer finished interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

DMAERIE

Bit 2: DMA error interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

NYETIE

Bit 6: NYET interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH0LEN

host channel-0 transfer length register

Offset: 0x110, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PING
rw 		DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

PING

Bit 31: Ping token request.

HCH0DMAADDR

host channel-0 DMA address register

Offset: 0x114, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

HCH1CTL

host channel-1 control register (HCH1CTL)

Offset: 0x120, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		MPC
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

MPC

Bits 20-21: Multiple packet count.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH1STCTL

host channel-1 split transaction control register (HCH1STCTL)

Offset: 0x124, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLEN
rw 		CSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISOPCE
rw 		HADDR
rw 		PADDR
rw
Toggle Fields.

PADDR

Bits 0-6: Port address.

HADDR

Bits 7-13: HUB address.

ISOPCE

Bits 14-15: Isochronous OUT payload continuation encoding.

CSPLT

Bit 16: Complete split enable.

SPLEN

Bit 31: Enable high speed split transaction.

HCH1INTF

host channel-1 interrupt flag register (HCH1INTF)

Offset: 0x128, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		DMAER
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer completed.

CH

Bit 1: Channel halted.

DMAER

Bit 2: DMA Error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: NYET.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH1INTEN

host channel-1 interrupt enable register (HCH1INTEN)

Offset: 0x12C, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		NYETIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		DMAERIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer finished interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

DMAERIE

Bit 2: DMA error interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

NYETIE

Bit 6: NYET interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH1LEN

host channel-1 transfer length register

Offset: 0x130, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PING
rw 		DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

PING

Bit 31: Ping token request.

HCH1DMAADDR

host channel-1 DMA address register

Offset: 0x134, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

HCH2CTL

host channel-2 control register (HCH2CTL)

Offset: 0x140, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		MPC
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

MPC

Bits 20-21: Multiple packet count.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH2STCTL

host channel-2 split transaction control register (HCH2STCTL)

Offset: 0x144, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLEN
rw 		CSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISOPCE
rw 		HADDR
rw 		PADDR
rw
Toggle Fields.

PADDR

Bits 0-6: Port address.

HADDR

Bits 7-13: HUB address.

ISOPCE

Bits 14-15: Isochronous OUT payload continuation encoding.

CSPLT

Bit 16: Complete split enable.

SPLEN

Bit 31: Enable high speed split transaction.

HCH2INTF

host channel-2 interrupt flag register (HCH2INTF)

Offset: 0x148, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		DMAER
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer completed.

CH

Bit 1: Channel halted.

DMAER

Bit 2: DMA Error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: NYET.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH2INTEN

host channel-2 interrupt enable register (HCH2INTEN)

Offset: 0x14C, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		NYETIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		DMAERIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer finished interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

DMAERIE

Bit 2: DMA error interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

NYETIE

Bit 6: NYET interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH2LEN

host channel-2 transfer length register

Offset: 0x150, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PING
rw 		DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

PING

Bit 31: Ping token request.

HCH2DMAADDR

host channel-2 DMA address register

Offset: 0x154, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

HCH3CTL

host channel-3 control register (HCH3CTL)

Offset: 0x160, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		MPC
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

MPC

Bits 20-21: Multiple packet count.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH3STCTL

host channel-3 split transaction control register (HCH3STCTL)

Offset: 0x164, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLEN
rw 		CSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISOPCE
rw 		HADDR
rw 		PADDR
rw
Toggle Fields.

PADDR

Bits 0-6: Port address.

HADDR

Bits 7-13: HUB address.

ISOPCE

Bits 14-15: Isochronous OUT payload continuation encoding.

CSPLT

Bit 16: Complete split enable.

SPLEN

Bit 31: Enable high speed split transaction.

HCH3INTF

host channel-3 interrupt flag register (HCH3INTF)

Offset: 0x168, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		DMAER
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer completed.

CH

Bit 1: Channel halted.

DMAER

Bit 2: DMA Error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: NYET.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH3INTEN

host channel-3 interrupt enable register (HCH3INTEN)

Offset: 0x16C, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		NYETIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		DMAERIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer finished interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

DMAERIE

Bit 2: DMA error interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

NYETIE

Bit 6: NYET interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH3LEN

host channel-3 transfer length register

Offset: 0x170, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PING
rw 		DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

PING

Bit 31: Ping token request.

HCH3DMAADDR

host channel-3 DMA address register

Offset: 0x174, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

HCH4CTL

host channel-4 control register (HCH4CTL)

Offset: 0x180, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		MPC
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

MPC

Bits 20-21: Multiple packet count.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH4STCTL

host channel-4 split transaction control register (HCH4STCTL)

Offset: 0x184, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLEN
rw 		CSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISOPCE
rw 		HADDR
rw 		PADDR
rw
Toggle Fields.

PADDR

Bits 0-6: Port address.

HADDR

Bits 7-13: HUB address.

ISOPCE

Bits 14-15: Isochronous OUT payload continuation encoding.

CSPLT

Bit 16: Complete split enable.

SPLEN

Bit 31: Enable high speed split transaction.

HCH4INTF

host channel-4 interrupt flag register (HCH4INTF)

Offset: 0x188, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		DMAER
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer completed.

CH

Bit 1: Channel halted.

DMAER

Bit 2: DMA Error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: NYET.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH4INTEN

host channel-4 interrupt enable register (HCH4INTEN)

Offset: 0x18C, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		NYETIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		DMAERIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer finished interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

DMAERIE

Bit 2: DMA error interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

NYETIE

Bit 6: NYET interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH4LEN

host channel-4 transfer length register

Offset: 0x190, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PING
rw 		DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

PING

Bit 31: Ping token request.

HCH4DMAADDR

host channel-4 DMA address register

Offset: 0x194, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

HCH5CTL

host channel-5 control register (HCH5CTL)

Offset: 0x1A0, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		MPC
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

MPC

Bits 20-21: Multiple packet count.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH5STCTL

host channel-5 split transaction control register (HCH5STCTL)

Offset: 0x1A4, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLEN
rw 		CSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISOPCE
rw 		HADDR
rw 		PADDR
rw
Toggle Fields.

PADDR

Bits 0-6: Port address.

HADDR

Bits 7-13: HUB address.

ISOPCE

Bits 14-15: Isochronous OUT payload continuation encoding.

CSPLT

Bit 16: Complete split enable.

SPLEN

Bit 31: Enable high speed split transaction.

HCH5INTF

host channel-5 interrupt flag register (HCH5INTF)

Offset: 0x1A8, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		DMAER
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer completed.

CH

Bit 1: Channel halted.

DMAER

Bit 2: DMA Error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: NYET.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH5INTEN

host channel-5 interrupt enable register (HCH5INTEN)

Offset: 0x1AC, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		NYETIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		DMAERIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer finished interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

DMAERIE

Bit 2: DMA error interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

NYETIE

Bit 6: NYET interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH5LEN

host channel-5 transfer length register

Offset: 0x1B0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PING
rw 		DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

PING

Bit 31: Ping token request.

HCH5DMAADDR

host channel-5 DMA address register

Offset: 0x1B4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

HCH6CTL

host channel-6 control register (HCH6CTL)

Offset: 0x1C0, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		MPC
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

MPC

Bits 20-21: Multiple packet count.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH6STCTL

host channel-6 split transaction control register (HCH6STCTL)

Offset: 0x1C4, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLEN
rw 		CSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISOPCE
rw 		HADDR
rw 		PADDR
rw
Toggle Fields.

PADDR

Bits 0-6: Port address.

HADDR

Bits 7-13: HUB address.

ISOPCE

Bits 14-15: Isochronous OUT payload continuation encoding.

CSPLT

Bit 16: Complete split enable.

SPLEN

Bit 31: Enable high speed split transaction.

HCH6INTF

host channel-6 interrupt flag register (HCH6INTF)

Offset: 0x1C8, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		DMAER
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer completed.

CH

Bit 1: Channel halted.

DMAER

Bit 2: DMA Error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: NYET.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH6INTEN

host channel-6 interrupt enable register (HCH6INTEN)

Offset: 0x1CC, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		NYETIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		DMAERIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer finished interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

DMAERIE

Bit 2: DMA error interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

NYETIE

Bit 6: NYET interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH6LEN

host channel-6 transfer length register

Offset: 0x1D0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PING
rw 		DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

PING

Bit 31: Ping token request.

HCH6DMAADDR

host channel-6 DMA address register

Offset: 0x1D4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

HCH7CTL

host channel-7 control register (HCH7CTL)

Offset: 0x1E0, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		MPC
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

MPC

Bits 20-21: Multiple packet count.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH7STCTL

host channel-7 split transaction control register (HCH7STCTL)

Offset: 0x1E4, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLEN
rw 		CSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISOPCE
rw 		HADDR
rw 		PADDR
rw
Toggle Fields.

PADDR

Bits 0-6: Port address.

HADDR

Bits 7-13: HUB address.

ISOPCE

Bits 14-15: Isochronous OUT payload continuation encoding.

CSPLT

Bit 16: Complete split enable.

SPLEN

Bit 31: Enable high speed split transaction.

HCH7INTF

host channel-7 interrupt flag register (HCH7INTF)

Offset: 0x1E8, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		DMAER
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer completed.

CH

Bit 1: Channel halted.

DMAER

Bit 2: DMA Error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: NYET.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH7INTEN

host channel-7 interrupt enable register (HCH7INTEN)

Offset: 0x1EC, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		NYETIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		DMAERIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer finished interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

DMAERIE

Bit 2: DMA error interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

NYETIE

Bit 6: NYET interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH7LEN

host channel-7 transfer length register

Offset: 0x1F0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PING
rw 		DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

PING

Bit 31: Ping token request.

HCH7DMAADDR

host channel-7 DMA address register

Offset: 0x1F4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

HCH8CTL

host channel-8 control register (HCH8CTL)

Offset: 0x200, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		MPC
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

MPC

Bits 20-21: Multiple packet count.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH8STCTL

host channel-8 split transaction control register (HCH8STCTL)

Offset: 0x204, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLEN
rw 		CSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISOPCE
rw 		HADDR
rw 		PADDR
rw
Toggle Fields.

PADDR

Bits 0-6: Port address.

HADDR

Bits 7-13: HUB address.

ISOPCE

Bits 14-15: Isochronous OUT payload continuation encoding.

CSPLT

Bit 16: Complete split enable.

SPLEN

Bit 31: Enable high speed split transaction.

HCH8INTF

host channel-8 interrupt flag register (HCH8INTF)

Offset: 0x208, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		DMAER
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer completed.

CH

Bit 1: Channel halted.

DMAER

Bit 2: DMA Error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: NYET.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH8INTEN

host channel-8 interrupt enable register (HCH8INTEN)

Offset: 0x20C, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		NYETIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		DMAERIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer finished interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

DMAERIE

Bit 2: DMA error interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

NYETIE

Bit 6: NYET interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH8LEN

host channel-8 transfer length register

Offset: 0x210, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PING
rw 		DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

PING

Bit 31: Ping token request.

HCH8DMAADDR

host channel-8 DMA address register

Offset: 0x214, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

HCH9CTL

host channel-9 control register (HCH9CTL)

Offset: 0x220, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		MPC
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

MPC

Bits 20-21: Multiple packet count.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH9STCTL

host channel-9 split transaction control register (HCH9STCTL)

Offset: 0x224, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLEN
rw 		CSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISOPCE
rw 		HADDR
rw 		PADDR
rw
Toggle Fields.

PADDR

Bits 0-6: Port address.

HADDR

Bits 7-13: HUB address.

ISOPCE

Bits 14-15: Isochronous OUT payload continuation encoding.

CSPLT

Bit 16: Complete split enable.

SPLEN

Bit 31: Enable high speed split transaction.

HCH9INTF

host channel-9 interrupt flag register (HCH9INTF)

Offset: 0x228, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		DMAER
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer completed.

CH

Bit 1: Channel halted.

DMAER

Bit 2: DMA Error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: NYET.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH9INTEN

host channel-9 interrupt enable register (HCH9INTEN)

Offset: 0x22C, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		NYETIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		DMAERIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer finished interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

DMAERIE

Bit 2: DMA error interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

NYETIE

Bit 6: NYET interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH9LEN

host channel-9 transfer length register

Offset: 0x230, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PING
rw 		DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

PING

Bit 31: Ping token request.

HCH9DMAADDR

host channel-9 DMA address register

Offset: 0x234, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

HCH10CTL

host channel-10 control register (HCH10CTL)

Offset: 0x240, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		MPC
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

MPC

Bits 20-21: Multiple packet count.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH10STCTL

host channel-10 split transaction control register (HCH10STCTL)

Offset: 0x244, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLEN
rw 		CSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISOPCE
rw 		HADDR
rw 		PADDR
rw
Toggle Fields.

PADDR

Bits 0-6: Port address.

HADDR

Bits 7-13: HUB address.

ISOPCE

Bits 14-15: Isochronous OUT payload continuation encoding.

CSPLT

Bit 16: Complete split enable.

SPLEN

Bit 31: Enable high speed split transaction.

HCH10INTF

host channel-10 interrupt flag register (HCH10INTF)

Offset: 0x248, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		DMAER
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer completed.

CH

Bit 1: Channel halted.

DMAER

Bit 2: DMA Error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: NYET.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH10INTEN

host channel-10 interrupt enable register (HCH10INTEN)

Offset: 0x24C, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		NYETIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		DMAERIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer finished interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

DMAERIE

Bit 2: DMA error interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

NYETIE

Bit 6: NYET interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH10LEN

host channel-10 transfer length register

Offset: 0x250, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PING
rw 		DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

PING

Bit 31: Ping token request.

HCH10DMAADDR

host channel-10 DMA address register

Offset: 0x254, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

HCH11CTL

host channel-11 control register (HCH11CTL)

Offset: 0x260, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN
rw 		CDIS
rw 		ODDFRM
rw 		DAR
rw 		MPC
rw 		EPTYPE
rw 		LSD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPL
rw
Toggle Fields.

MPL

Bits 0-10: Maximum packet size.

EPNUM

Bits 11-14: Endpoint number.

EPDIR

Bit 15: Endpoint direction.

LSD

Bit 17: Low-speed device.

EPTYPE

Bits 18-19: Endpoint type.

MPC

Bits 20-21: Multiple packet count.

DAR

Bits 22-28: Device address.

ODDFRM

Bit 29: Odd frame.

CDIS

Bit 30: Channel disable.

CEN

Bit 31: Channel enable.

HCH11STCTL

host channel-11 split transaction control register (HCH11STCTL)

Offset: 0x264, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLEN
rw 		CSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISOPCE
rw 		HADDR
rw 		PADDR
rw
Toggle Fields.

PADDR

Bits 0-6: Port address.

HADDR

Bits 7-13: HUB address.

ISOPCE

Bits 14-15: Isochronous OUT payload continuation encoding.

CSPLT

Bit 16: Complete split enable.

SPLEN

Bit 31: Enable high speed split transaction.

HCH11INTF

host channel-11 interrupt flag register (HCH11INTF)

Offset: 0x268, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTER
rw 		REQOVR
rw 		BBER
rw 		USBER
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		DMAER
rw 		CH
rw 		TF
rw
Toggle Fields.

TF

Bit 0: Transfer completed.

CH

Bit 1: Channel halted.

DMAER

Bit 2: DMA Error.

STALL

Bit 3: STALL response received interrupt.

NAK

Bit 4: NAK response received interrupt.

ACK

Bit 5: ACK response received/transmitted interrupt.

NYET

Bit 6: NYET.

USBER

Bit 7: USB bus error.

BBER

Bit 8: Babble error.

REQOVR

Bit 9: Request queue overrun.

DTER

Bit 10: Data toggle error.

HCH11INTEN

host channel-11 interrupt enable register (HCH11INTEN)

Offset: 0x26C, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTERIE
rw 		REQOVRIE
rw 		BBERIE
rw 		USBERIE
rw 		NYETIE
rw 		ACKIE
rw 		NAKIE
rw 		STALLIE
rw 		DMAERIE
rw 		CHIE
rw 		TFIE
rw
Toggle Fields.

TFIE

Bit 0: Transfer finished interrupt enable.

CHIE

Bit 1: Channel halted interrupt enable.

DMAERIE

Bit 2: DMA error interrupt enable.

STALLIE

Bit 3: STALL interrupt enable.

NAKIE

Bit 4: NAK interrupt enable.

ACKIE

Bit 5: ACK interrupt enable.

NYETIE

Bit 6: NYET interrupt enable.

USBERIE

Bit 7: USB bus error interrupt enable.

BBERIE

Bit 8: Babble error interrupt enable.

REQOVRIE

Bit 9: request queue overrun interrupt enable.

DTERIE

Bit 10: Data toggle error interrupt enable.

HCH11LEN

host channel-11 transfer length register

Offset: 0x270, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PING
rw 		DPID
rw 		PCNT
rw 		TLEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TLEN
rw
Toggle Fields.

TLEN

Bits 0-18: Transfer length.

PCNT

Bits 19-28: Packet count.

DPID

Bits 29-30: Data PID.

PING

Bit 31: Ping token request.

HCH11DMAADDR

host channel-11 DMA address register

Offset: 0x274, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle Fields.

DMAADDR

Bits 0-31: DMA address.

HS_PWRCLK

0x40040E00: USB on the go high speed power and clock

0/2 fields covered. Toggle Registers.

PWRCLKCTL

power and clock gating control register (PWRCLKCTL)

Offset: 0x0, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHCLK
rw 		SUCLK
rw
Toggle Fields.

SUCLK

Bit 0: Stop the USB clock.

SHCLK

Bit 1: Stop HCLK.

I2C0

0x40005400: Inter integrated circuit

17/67 fields covered. Toggle Registers.

CTL0

Control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRESET
rw 		SALT
rw 		PECTRANS
rw 		POAP
rw 		ACKEN
rw 		STOP
rw 		START
rw 		DISSTRC
rw 		GCEN
rw 		PECEN
rw 		ARPEN
rw 		SMBSEL
rw 		SMBEN
rw 		I2CEN
rw
Toggle Fields.

I2CEN

Bit 0: I2C peripheral enable.

SMBEN

Bit 1: SMBus/I2C mode switch.

SMBSEL

Bit 3: SMBusType Selection.

ARPEN

Bit 4: ARP protocol in SMBus switch.

PECEN

Bit 5: PEC Calculation Switch.

GCEN

Bit 6: Whether or not to response to a General Call (0x00).

DISSTRC

Bit 7: Whether to stretch SCL low when data is not ready in slave mode.

START

Bit 8: Generate a START condition on I2C bus.

STOP

Bit 9: Generate a STOP condition on I2C bus.

ACKEN

Bit 10: Whether or not to send an ACK.

POAP

Bit 11: Position of ACK and PEC when receiving.

PECTRANS

Bit 12: PEC Transfer.

SALT

Bit 13: SMBus alert.

SRESET

Bit 15: Software reset.

CTL1

Control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMALST
rw 		DMAON
rw 		BUFIE
rw 		EVIE
rw 		ERRIE
rw 		I2CCLK
rw
Toggle Fields.

I2CCLK

Bits 0-5: I2C Peripheral clock frequency.

ERRIE

Bit 8: Error interrupt enable.

EVIE

Bit 9: Event interrupt enable.

BUFIE

Bit 10: Buffer interrupt enable.

DMAON

Bit 11: DMA mode switch.

DMALST

Bit 12: Flag indicating DMA last transfer.

SADDR0

Slave address register 0

Offset: 0x8, reset: 0x0000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDFORMAT
rw 		ADDRESS9_8
rw 		ADDRESS7_1
rw 		ADDRESS0
rw
Toggle Fields.

ADDRESS0

Bit 0: Bit 0 of a 10-bit address.

ADDRESS7_1

Bits 1-7: 7-bit address or bits 7:1 of a 10-bit address.

ADDRESS9_8

Bits 8-9: Highest two bits of a 10-bit address.

ADDFORMAT

Bit 15: Address mode for the I2C slave.

SADDR1

Slave address register 1

Offset: 0xC, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS2
rw 		DUADEN
rw
Toggle Fields.

DUADEN

Bit 0: Dual-Address mode switch.

ADDRESS2

Bits 1-7: Second I2C address for the slave in Dual-Address mode.

DATA

Transfer buffer register

Offset: 0x10, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRB
rw
Toggle Fields.

TRB

Bits 0-7: Transmission or reception data buffer register.

STAT0

Transfer status register 0

Offset: 0x14, reset: 0x0000, access: Unspecified

7/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALT
rw 		SMBTO
rw 		PECERR
rw 		OUERR
rw 		AERR
rw 		LOSTARB
rw 		BERR
rw 		TBE
r 		RBNE
r 		STPDET
r 		ADD10SEND
r 		BTC
r 		ADDSEND
r 		SBSEND
r
Toggle Fields.

SBSEND

Bit 0: START condition sent out in master mode.

ADDSEND

Bit 1: Address is sent in master mode or received and matches in slave mode.

BTC

Bit 2: Byte transmission completed.

ADD10SEND

Bit 3: Header of 10-bit address is sent in master mode.

STPDET

Bit 4: STOP condition detected in slave mode.

RBNE

Bit 6: I2C_DATA is not Empty during receiving.

TBE

Bit 7: I2C_DATA is Empty during transmitting.

BERR

Bit 8: A bus error occurs indication a unexpected START or STOP condition on I2C bus.

LOSTARB

Bit 9: Arbitration Lost in master mode.

AERR

Bit 10: Acknowledge error.

OUERR

Bit 11: Over-run or under-run situation occurs in slave mode.

PECERR

Bit 12: PEC error when receiving data.

SMBTO

Bit 14: Timeout signal in SMBus mode.

SMBALT

Bit 15: SMBus Alert status.

STAT1

Transfer status register 1

Offset: 0x18, reset: 0x0000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECV
r 		DUMODF
r 		HSTSMB
r 		DEFSMB
r 		RXGC
r 		TRS
r 		I2CBSY
r 		MASTER
r
Toggle Fields.

MASTER

Bit 0: A flag indicating whether I2C block is in master or slave mode.

I2CBSY

Bit 1: Busy flag.

TRS

Bit 2: Whether the I2C is a transmitter or a receiver.

RXGC

Bit 4: General call address (00h) received.

DEFSMB

Bit 5: Default address of SMBusDevice.

HSTSMB

Bit 6: SMBus Host Header detected in slave mode.

DUMODF

Bit 7: Dual Flag in slave mode.

ECV

Bits 8-15: Packet Error Checking Value that calculated by hardware when PEC is enabled.

CKCFG

Clock configure register

Offset: 0x1C, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAST
rw 		DTCY
rw 		CLKC
rw
Toggle Fields.

CLKC

Bits 0-11: I2C Clock control in master mode.

DTCY

Bit 14: Duty cycle in fast mode.

FAST

Bit 15: I2C speed selection in master mode.

RT

Rise time register

Offset: 0x20, reset: 0x0002, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RISETIME
rw
Toggle Fields.

RISETIME

Bits 0-5: Maximum rise time in master mode.

FCTL

Filter control register

Offset: 0x24, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFD
rw 		DF
rw
Toggle Fields.

DF

Bits 0-3: Digital noise filter.

AFD

Bit 4: Analog noise filter disable.

SAMCS

SAM control and status register

Offset: 0x80, reset: 0x0000, access: Unspecified

2/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFR
rw 		RFF
rw 		TFR
rw 		TFF
rw 		RXF
r 		TXF
r 		RFRIE
rw 		RFFIE
rw 		TFRIE
rw 		TFFIE
rw 		STOEN
rw 		SAMEN
rw
Toggle Fields.

SAMEN

Bit 0: SAM_V interface enable.

STOEN

Bit 1: SAM_V interface timeout detect enable.

TFFIE

Bit 4: Txframe fall interrupt enable.

TFRIE

Bit 5: Txframe rise interrupt enable.

RFFIE

Bit 6: Rxframe fall interrupt enable.

RFRIE

Bit 7: Rxframe rise interrupt enable.

TXF

Bit 8: Level of Txframe signal.

RXF

Bit 9: Level of Rxframe signal.

TFF

Bit 12: Txframe fall flag.

TFR

Bit 13: Txframe rise flag.

RFF

Bit 14: Rxframe fall flag.

RFR

Bit 15: Rxframe rise flag.

I2C1

0x40005800: Inter integrated circuit

17/67 fields covered. Toggle Registers.

CTL0

Control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRESET
rw 		SALT
rw 		PECTRANS
rw 		POAP
rw 		ACKEN
rw 		STOP
rw 		START
rw 		DISSTRC
rw 		GCEN
rw 		PECEN
rw 		ARPEN
rw 		SMBSEL
rw 		SMBEN
rw 		I2CEN
rw
Toggle Fields.

I2CEN

Bit 0: I2C peripheral enable.

SMBEN

Bit 1: SMBus/I2C mode switch.

SMBSEL

Bit 3: SMBusType Selection.

ARPEN

Bit 4: ARP protocol in SMBus switch.

PECEN

Bit 5: PEC Calculation Switch.

GCEN

Bit 6: Whether or not to response to a General Call (0x00).

DISSTRC

Bit 7: Whether to stretch SCL low when data is not ready in slave mode.

START

Bit 8: Generate a START condition on I2C bus.

STOP

Bit 9: Generate a STOP condition on I2C bus.

ACKEN

Bit 10: Whether or not to send an ACK.

POAP

Bit 11: Position of ACK and PEC when receiving.

PECTRANS

Bit 12: PEC Transfer.

SALT

Bit 13: SMBus alert.

SRESET

Bit 15: Software reset.

CTL1

Control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMALST
rw 		DMAON
rw 		BUFIE
rw 		EVIE
rw 		ERRIE
rw 		I2CCLK
rw
Toggle Fields.

I2CCLK

Bits 0-5: I2C Peripheral clock frequency.

ERRIE

Bit 8: Error interrupt enable.

EVIE

Bit 9: Event interrupt enable.

BUFIE

Bit 10: Buffer interrupt enable.

DMAON

Bit 11: DMA mode switch.

DMALST

Bit 12: Flag indicating DMA last transfer.

SADDR0

Slave address register 0

Offset: 0x8, reset: 0x0000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDFORMAT
rw 		ADDRESS9_8
rw 		ADDRESS7_1
rw 		ADDRESS0
rw
Toggle Fields.

ADDRESS0

Bit 0: Bit 0 of a 10-bit address.

ADDRESS7_1

Bits 1-7: 7-bit address or bits 7:1 of a 10-bit address.

ADDRESS9_8

Bits 8-9: Highest two bits of a 10-bit address.

ADDFORMAT

Bit 15: Address mode for the I2C slave.

SADDR1

Slave address register 1

Offset: 0xC, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS2
rw 		DUADEN
rw
Toggle Fields.

DUADEN

Bit 0: Dual-Address mode switch.

ADDRESS2

Bits 1-7: Second I2C address for the slave in Dual-Address mode.

DATA

Transfer buffer register

Offset: 0x10, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRB
rw
Toggle Fields.

TRB

Bits 0-7: Transmission or reception data buffer register.

STAT0

Transfer status register 0

Offset: 0x14, reset: 0x0000, access: Unspecified

7/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALT
rw 		SMBTO
rw 		PECERR
rw 		OUERR
rw 		AERR
rw 		LOSTARB
rw 		BERR
rw 		TBE
r 		RBNE
r 		STPDET
r 		ADD10SEND
r 		BTC
r 		ADDSEND
r 		SBSEND
r
Toggle Fields.

SBSEND

Bit 0: START condition sent out in master mode.

ADDSEND

Bit 1: Address is sent in master mode or received and matches in slave mode.

BTC

Bit 2: Byte transmission completed.

ADD10SEND

Bit 3: Header of 10-bit address is sent in master mode.

STPDET

Bit 4: STOP condition detected in slave mode.

RBNE

Bit 6: I2C_DATA is not Empty during receiving.

TBE

Bit 7: I2C_DATA is Empty during transmitting.

BERR

Bit 8: A bus error occurs indication a unexpected START or STOP condition on I2C bus.

LOSTARB

Bit 9: Arbitration Lost in master mode.

AERR

Bit 10: Acknowledge error.

OUERR

Bit 11: Over-run or under-run situation occurs in slave mode.

PECERR

Bit 12: PEC error when receiving data.

SMBTO

Bit 14: Timeout signal in SMBus mode.

SMBALT

Bit 15: SMBus Alert status.

STAT1

Transfer status register 1

Offset: 0x18, reset: 0x0000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECV
r 		DUMODF
r 		HSTSMB
r 		DEFSMB
r 		RXGC
r 		TRS
r 		I2CBSY
r 		MASTER
r
Toggle Fields.

MASTER

Bit 0: A flag indicating whether I2C block is in master or slave mode.

I2CBSY

Bit 1: Busy flag.

TRS

Bit 2: Whether the I2C is a transmitter or a receiver.

RXGC

Bit 4: General call address (00h) received.

DEFSMB

Bit 5: Default address of SMBusDevice.

HSTSMB

Bit 6: SMBus Host Header detected in slave mode.

DUMODF

Bit 7: Dual Flag in slave mode.

ECV

Bits 8-15: Packet Error Checking Value that calculated by hardware when PEC is enabled.

CKCFG

Clock configure register

Offset: 0x1C, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAST
rw 		DTCY
rw 		CLKC
rw
Toggle Fields.

CLKC

Bits 0-11: I2C Clock control in master mode.

DTCY

Bit 14: Duty cycle in fast mode.

FAST

Bit 15: I2C speed selection in master mode.

RT

Rise time register

Offset: 0x20, reset: 0x0002, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RISETIME
rw
Toggle Fields.

RISETIME

Bits 0-5: Maximum rise time in master mode.

FCTL

Filter control register

Offset: 0x24, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFD
rw 		DF
rw
Toggle Fields.

DF

Bits 0-3: Digital noise filter.

AFD

Bit 4: Analog noise filter disable.

SAMCS

SAM control and status register

Offset: 0x80, reset: 0x0000, access: Unspecified

2/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFR
rw 		RFF
rw 		TFR
rw 		TFF
rw 		RXF
r 		TXF
r 		RFRIE
rw 		RFFIE
rw 		TFRIE
rw 		TFFIE
rw 		STOEN
rw 		SAMEN
rw
Toggle Fields.

SAMEN

Bit 0: SAM_V interface enable.

STOEN

Bit 1: SAM_V interface timeout detect enable.

TFFIE

Bit 4: Txframe fall interrupt enable.

TFRIE

Bit 5: Txframe rise interrupt enable.

RFFIE

Bit 6: Rxframe fall interrupt enable.

RFRIE

Bit 7: Rxframe rise interrupt enable.

TXF

Bit 8: Level of Txframe signal.

RXF

Bit 9: Level of Rxframe signal.

TFF

Bit 12: Txframe fall flag.

TFR

Bit 13: Txframe rise flag.

RFF

Bit 14: Rxframe fall flag.

RFR

Bit 15: Rxframe rise flag.

I2C2

0x40005C00: Inter integrated circuit

17/67 fields covered. Toggle Registers.

CTL0

Control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRESET
rw 		SALT
rw 		PECTRANS
rw 		POAP
rw 		ACKEN
rw 		STOP
rw 		START
rw 		DISSTRC
rw 		GCEN
rw 		PECEN
rw 		ARPEN
rw 		SMBSEL
rw 		SMBEN
rw 		I2CEN
rw
Toggle Fields.

I2CEN

Bit 0: I2C peripheral enable.

SMBEN

Bit 1: SMBus/I2C mode switch.

SMBSEL

Bit 3: SMBusType Selection.

ARPEN

Bit 4: ARP protocol in SMBus switch.

PECEN

Bit 5: PEC Calculation Switch.

GCEN

Bit 6: Whether or not to response to a General Call (0x00).

DISSTRC

Bit 7: Whether to stretch SCL low when data is not ready in slave mode.

START

Bit 8: Generate a START condition on I2C bus.

STOP

Bit 9: Generate a STOP condition on I2C bus.

ACKEN

Bit 10: Whether or not to send an ACK.

POAP

Bit 11: Position of ACK and PEC when receiving.

PECTRANS

Bit 12: PEC Transfer.

SALT

Bit 13: SMBus alert.

SRESET

Bit 15: Software reset.

CTL1

Control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMALST
rw 		DMAON
rw 		BUFIE
rw 		EVIE
rw 		ERRIE
rw 		I2CCLK
rw
Toggle Fields.

I2CCLK

Bits 0-5: I2C Peripheral clock frequency.

ERRIE

Bit 8: Error interrupt enable.

EVIE

Bit 9: Event interrupt enable.

BUFIE

Bit 10: Buffer interrupt enable.

DMAON

Bit 11: DMA mode switch.

DMALST

Bit 12: Flag indicating DMA last transfer.

SADDR0

Slave address register 0

Offset: 0x8, reset: 0x0000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDFORMAT
rw 		ADDRESS9_8
rw 		ADDRESS7_1
rw 		ADDRESS0
rw
Toggle Fields.

ADDRESS0

Bit 0: Bit 0 of a 10-bit address.

ADDRESS7_1

Bits 1-7: 7-bit address or bits 7:1 of a 10-bit address.

ADDRESS9_8

Bits 8-9: Highest two bits of a 10-bit address.

ADDFORMAT

Bit 15: Address mode for the I2C slave.

SADDR1

Slave address register 1

Offset: 0xC, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS2
rw 		DUADEN
rw
Toggle Fields.

DUADEN

Bit 0: Dual-Address mode switch.

ADDRESS2

Bits 1-7: Second I2C address for the slave in Dual-Address mode.

DATA

Transfer buffer register

Offset: 0x10, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRB
rw
Toggle Fields.

TRB

Bits 0-7: Transmission or reception data buffer register.

STAT0

Transfer status register 0

Offset: 0x14, reset: 0x0000, access: Unspecified

7/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMBALT
rw 		SMBTO
rw 		PECERR
rw 		OUERR
rw 		AERR
rw 		LOSTARB
rw 		BERR
rw 		TBE
r 		RBNE
r 		STPDET
r 		ADD10SEND
r 		BTC
r 		ADDSEND
r 		SBSEND
r
Toggle Fields.

SBSEND

Bit 0: START condition sent out in master mode.

ADDSEND

Bit 1: Address is sent in master mode or received and matches in slave mode.

BTC

Bit 2: Byte transmission completed.

ADD10SEND

Bit 3: Header of 10-bit address is sent in master mode.

STPDET

Bit 4: STOP condition detected in slave mode.

RBNE

Bit 6: I2C_DATA is not Empty during receiving.

TBE

Bit 7: I2C_DATA is Empty during transmitting.

BERR

Bit 8: A bus error occurs indication a unexpected START or STOP condition on I2C bus.

LOSTARB

Bit 9: Arbitration Lost in master mode.

AERR

Bit 10: Acknowledge error.

OUERR

Bit 11: Over-run or under-run situation occurs in slave mode.

PECERR

Bit 12: PEC error when receiving data.

SMBTO

Bit 14: Timeout signal in SMBus mode.

SMBALT

Bit 15: SMBus Alert status.

STAT1

Transfer status register 1

Offset: 0x18, reset: 0x0000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECV
r 		DUMODF
r 		HSTSMB
r 		DEFSMB
r 		RXGC
r 		TRS
r 		I2CBSY
r 		MASTER
r
Toggle Fields.

MASTER

Bit 0: A flag indicating whether I2C block is in master or slave mode.

I2CBSY

Bit 1: Busy flag.

TRS

Bit 2: Whether the I2C is a transmitter or a receiver.

RXGC

Bit 4: General call address (00h) received.

DEFSMB

Bit 5: Default address of SMBusDevice.

HSTSMB

Bit 6: SMBus Host Header detected in slave mode.

DUMODF

Bit 7: Dual Flag in slave mode.

ECV

Bits 8-15: Packet Error Checking Value that calculated by hardware when PEC is enabled.

CKCFG

Clock configure register

Offset: 0x1C, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FAST
rw 		DTCY
rw 		CLKC
rw
Toggle Fields.

CLKC

Bits 0-11: I2C Clock control in master mode.

DTCY

Bit 14: Duty cycle in fast mode.

FAST

Bit 15: I2C speed selection in master mode.

RT

Rise time register

Offset: 0x20, reset: 0x0002, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RISETIME
rw
Toggle Fields.

RISETIME

Bits 0-5: Maximum rise time in master mode.

FCTL

Filter control register

Offset: 0x24, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFD
rw 		DF
rw
Toggle Fields.

DF

Bits 0-3: Digital noise filter.

AFD

Bit 4: Analog noise filter disable.

SAMCS

SAM control and status register

Offset: 0x80, reset: 0x0000, access: Unspecified

2/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFR
rw 		RFF
rw 		TFR
rw 		TFF
rw 		RXF
r 		TXF
r 		RFRIE
rw 		RFFIE
rw 		TFRIE
rw 		TFFIE
rw 		STOEN
rw 		SAMEN
rw
Toggle Fields.

SAMEN

Bit 0: SAM_V interface enable.

STOEN

Bit 1: SAM_V interface timeout detect enable.

TFFIE

Bit 4: Txframe fall interrupt enable.

TFRIE

Bit 5: Txframe rise interrupt enable.

RFFIE

Bit 6: Rxframe fall interrupt enable.

RFRIE

Bit 7: Rxframe rise interrupt enable.

TXF

Bit 8: Level of Txframe signal.

RXF

Bit 9: Level of Rxframe signal.

TFF

Bit 12: Txframe fall flag.

TFR

Bit 13: Txframe rise flag.

RFF

Bit 14: Rxframe fall flag.

RFR

Bit 15: Rxframe rise flag.

I2S1_add

0x40003400: Serial peripheral interface

9/45 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDEN
rw 		BDOEN
rw 		CRCEN
rw 		CRCNT
rw 		FF16
rw 		RO
rw 		SWNSSEN
rw 		SWNSS
rw 		LF
rw 		SPIEN
rw 		PSC
rw 		MSTMOD
rw 		CKPL
rw 		CKPH
rw
Toggle Fields.

CKPH

Bit 0: Clock Phase Selection.

CKPL

Bit 1: Clock polarity Selection.

MSTMOD

Bit 2: Master Mode Enable.

PSC

Bits 3-5: Master Clock Prescaler Selection.

SPIEN

Bit 6: SPI enable.

LF

Bit 7: LSB First Mode.

SWNSS

Bit 8: NSS Pin Selection In NSS Software Mode.

SWNSSEN

Bit 9: NSS Software Mode Selection.

RO

Bit 10: Receive only.

FF16

Bit 11: Data frame format.

CRCNT

Bit 12: CRC Next Transfer.

CRCEN

Bit 13: CRC Calculation Enable.

BDOEN

Bit 14: Bidirectional Transmit output enable .

BDEN

Bit 15: Bidirectional enable.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBEIE
rw 		RBNEIE
rw 		ERRIE
rw 		TMOD
rw 		NSSDRV
rw 		DMATEN
rw 		DMAREN
rw
Toggle Fields.

DMAREN

Bit 0: Rx buffer DMA enable.

DMATEN

Bit 1: Transmit Buffer DMA Enable.

NSSDRV

Bit 2: Drive NSS Output.

TMOD

Bit 4: SPI TI Mode Enable.

ERRIE

Bit 5: Error interrupt enable.

RBNEIE

Bit 6: RX buffer not empty interrupt enable.

TBEIE

Bit 7: Tx buffer empty interrupt enable.

STAT

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

7/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FERR
rw 		TRANS
r 		RXORERR
r 		CONFERR
r 		CRCERR
rw 		TXURERR
r 		I2SCH
r 		TBE
r 		RBNE
r
Toggle Fields.

RBNE

Bit 0: Receive Buffer Not Empty.

TBE

Bit 1: Transmit Buffer Empty.

I2SCH

Bit 2: I2S channel side.

TXURERR

Bit 3: Transmission underrun error bit.

CRCERR

Bit 4: SPI CRC Error Bit.

CONFERR

Bit 5: SPI Configuration error.

RXORERR

Bit 6: Reception Overrun Error Bit.

TRANS

Bit 7: Transmitting On-going Bit.

FERR

Bit 8: Format Error.

DATA

data register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI_DATA
rw
Toggle Fields.

SPI_DATA

Bits 0-15: Data transfer register.

CPCPOLY

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPR
rw
Toggle Fields.

CPR

Bits 0-15: CRC polynomial register.

RCRC

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCR
r
Toggle Fields.

RCR

Bits 0-15: RX CRC register.

TCRC

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCR
r
Toggle Fields.

TCR

Bits 0-15: Tx CRC register.

I2SCTL

I2S control register

Offset: 0x1C, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SSEL
rw 		I2SEN
rw 		I2SOPMOD
rw 		PCMSMOD
rw 		I2SSTD
rw 		CKPL
rw 		DTLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

DTLEN

Bits 1-2: Data length.

CKPL

Bit 3: Idle state clock polarity.

I2SSTD

Bits 4-5: I2S standard selection.

PCMSMOD

Bit 7: PCM frame synchronization mode.

I2SOPMOD

Bits 8-9: I2S operation mode.

I2SEN

Bit 10: I2S Enable.

I2SSEL

Bit 11: I2S mode selection.

I2SPSC

I2S prescaler register

Offset: 0x20, reset: 0x0002, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOEN
rw 		OF
rw 		DIV
rw
Toggle Fields.

DIV

Bits 0-7: Dividing factor for the prescaler.

OF

Bit 8: Odd factor for the prescaler.

MCKOEN

Bit 9: I2S_MCK output enable.

I2S2_add

0x40004000: Serial peripheral interface

9/45 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDEN
rw 		BDOEN
rw 		CRCEN
rw 		CRCNT
rw 		FF16
rw 		RO
rw 		SWNSSEN
rw 		SWNSS
rw 		LF
rw 		SPIEN
rw 		PSC
rw 		MSTMOD
rw 		CKPL
rw 		CKPH
rw
Toggle Fields.

CKPH

Bit 0: Clock Phase Selection.

CKPL

Bit 1: Clock polarity Selection.

MSTMOD

Bit 2: Master Mode Enable.

PSC

Bits 3-5: Master Clock Prescaler Selection.

SPIEN

Bit 6: SPI enable.

LF

Bit 7: LSB First Mode.

SWNSS

Bit 8: NSS Pin Selection In NSS Software Mode.

SWNSSEN

Bit 9: NSS Software Mode Selection.

RO

Bit 10: Receive only.

FF16

Bit 11: Data frame format.

CRCNT

Bit 12: CRC Next Transfer.

CRCEN

Bit 13: CRC Calculation Enable.

BDOEN

Bit 14: Bidirectional Transmit output enable .

BDEN

Bit 15: Bidirectional enable.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBEIE
rw 		RBNEIE
rw 		ERRIE
rw 		TMOD
rw 		NSSDRV
rw 		DMATEN
rw 		DMAREN
rw
Toggle Fields.

DMAREN

Bit 0: Rx buffer DMA enable.

DMATEN

Bit 1: Transmit Buffer DMA Enable.

NSSDRV

Bit 2: Drive NSS Output.

TMOD

Bit 4: SPI TI Mode Enable.

ERRIE

Bit 5: Error interrupt enable.

RBNEIE

Bit 6: RX buffer not empty interrupt enable.

TBEIE

Bit 7: Tx buffer empty interrupt enable.

STAT

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

7/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FERR
rw 		TRANS
r 		RXORERR
r 		CONFERR
r 		CRCERR
rw 		TXURERR
r 		I2SCH
r 		TBE
r 		RBNE
r
Toggle Fields.

RBNE

Bit 0: Receive Buffer Not Empty.

TBE

Bit 1: Transmit Buffer Empty.

I2SCH

Bit 2: I2S channel side.

TXURERR

Bit 3: Transmission underrun error bit.

CRCERR

Bit 4: SPI CRC Error Bit.

CONFERR

Bit 5: SPI Configuration error.

RXORERR

Bit 6: Reception Overrun Error Bit.

TRANS

Bit 7: Transmitting On-going Bit.

FERR

Bit 8: Format Error.

DATA

data register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI_DATA
rw
Toggle Fields.

SPI_DATA

Bits 0-15: Data transfer register.

CPCPOLY

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPR
rw
Toggle Fields.

CPR

Bits 0-15: CRC polynomial register.

RCRC

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCR
r
Toggle Fields.

RCR

Bits 0-15: RX CRC register.

TCRC

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCR
r
Toggle Fields.

TCR

Bits 0-15: Tx CRC register.

I2SCTL

I2S control register

Offset: 0x1C, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SSEL
rw 		I2SEN
rw 		I2SOPMOD
rw 		PCMSMOD
rw 		I2SSTD
rw 		CKPL
rw 		DTLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

DTLEN

Bits 1-2: Data length.

CKPL

Bit 3: Idle state clock polarity.

I2SSTD

Bits 4-5: I2S standard selection.

PCMSMOD

Bit 7: PCM frame synchronization mode.

I2SOPMOD

Bits 8-9: I2S operation mode.

I2SEN

Bit 10: I2S Enable.

I2SSEL

Bit 11: I2S mode selection.

I2SPSC

I2S prescaler register

Offset: 0x20, reset: 0x0002, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOEN
rw 		OF
rw 		DIV
rw
Toggle Fields.

DIV

Bits 0-7: Dividing factor for the prescaler.

OF

Bit 8: Odd factor for the prescaler.

MCKOEN

Bit 9: I2S_MCK output enable.

IPA

0x4002B000: Image processing accelerator

6/72 fields covered. Toggle Registers.

IPA_CTL

Control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PFCM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WCFIE
rw 		LLFIE
rw 		LACIE
rw 		TLMIE
rw 		FTFIE
rw 		TAEIE
rw 		TST
rw 		THU
rw 		TEN
rw
Toggle Fields.

TEN

Bit 0: Transfer enable.

THU

Bit 1: Transfer hang up.

TST

Bit 2: Transfer stop.

TAEIE

Bit 8: Enable bit for transfer access error interrupt.

FTFIE

Bit 9: Enable bit for full transfer finish interrupt.

TLMIE

Bit 10: Enable bit for transfer line mark interrupt.

LACIE

Bit 11: Enable bit for LUT access conflict interrupt.

LLFIE

Bit 12: Enable bit for LUT loading finish interrupt.

WCFIE

Bit 13: Enable bit for wrong configuration interrupt.

PFCM

Bits 16-17: Pixel format convert mode.

IPA_INTF

Interrupt flag register

Offset: 0x4, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WCFIF
r 		LLFIF
r 		LACIF
r 		TLMIF
r 		FTFIF
r 		TAEIF
r
Toggle Fields.

TAEIF

Bit 0: Transfer access error interrupt flag.

FTFIF

Bit 1: Full transfer finish interrupt flag.

TLMIF

Bit 2: Transfer line mark interrupt flag.

LACIF

Bit 3: LUT access conflict interrupt flag.

LLFIF

Bit 4: LUT loading finish interrupt flag.

WCFIF

Bit 5: Wrong configuration interrupt flag.

IPA_INTC

Interrupt flag clear register

Offset: 0x8, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CWCFIF
rw 		LLFIFC
rw 		LACIFC
rw 		TLMIF
rw 		TFIFC
rw 		TAEIFC
rw
Toggle Fields.

TAEIFC

Bit 0: Clear bit for transfer access error interrupt flag.

TFIFC

Bit 1: Clear bit for full transfer finish interrupt flag.

TLMIF

Bit 2: Clear bit for transfer line mark interrupt flag.

LACIFC

Bit 3: Clear bit for LUT access conflict interrupt flag.

LLFIFC

Bit 4: Clear bit for LUT loading finish interrupt flag.

CWCFIF

Bit 5: Clear bit for wrong configuration interrupt flag.

IPA_FMADDR

Foreground memory base address register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FMADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMADDR
rw
Toggle Fields.

FMADDR

Bits 0-31: Foreground memory base address.

IPA_FLOFF

Foreground line offset register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLOFF
rw
Toggle Fields.

FLOFF

Bits 0-13: Foreground line offset.

IPA_BMADDR

Background memory base address register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BMADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BMADDR
rw
Toggle Fields.

BMADDR

Bits 0-31: Background memory base address.

IPA_BLOFF

Background line offset register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BLOFF
rw
Toggle Fields.

BLOFF

Bits 0-13: Background line offset.

IPA_FPCTL

Foreground pixel control register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FPDAV
rw 		FAVCA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FCNP
rw 		FLLEN
rw 		FLPF
rw 		FPF
rw
Toggle Fields.

FPF

Bits 0-3: Foreground pixel format.

FLPF

Bit 4: Foreground LUT pixel format.

FLLEN

Bit 5: Foreground LUT loading enable.

FCNP

Bits 8-15: Foreground LUT number of pixel.

FAVCA

Bits 16-17: Foreground alpha value calculation algorithm.

FPDAV

Bits 24-31: Foreground pre- defined alpha value.

IPA_FPV

Foreground pixel value register

Offset: 0x20, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FPDRV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPDGV
rw 		FPDBV
rw
Toggle Fields.

FPDBV

Bits 0-7: Foreground pre-defined blue value.

FPDGV

Bits 8-15: Foreground pre-defined green value.

FPDRV

Bits 16-23: Foreground pre-defined red value.

IPA_BPCTL

Background pixel control register

Offset: 0x24, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BPDAV
rw 		BAVCA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCNP
rw 		BLLEN
rw 		BLPF
rw 		BPF
rw
Toggle Fields.

BPF

Bits 0-3: Background pixel format.

BLPF

Bit 4: Background LUT pixel format.

BLLEN

Bit 5: Background LUT loading enable.

BCNP

Bits 8-15: Background LUT number of pixel.

BAVCA

Bits 16-17: Background alpha value calculation algorithm.

BPDAV

Bits 24-31: Background pre- defined alpha value.

IPA_BPV

Background pixel value register

Offset: 0x28, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BPDRV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BPDGV
rw 		BPDBV
rw
Toggle Fields.

BPDBV

Bits 0-7: Background pre-defined blue value.

BPDGV

Bits 8-15: Background pre-defined green value.

BPDRV

Bits 16-23: Background pre-defined red value.

IPA_FLMADDR

Foreground LUT memory base address register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLMBADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLMBADDR
rw
Toggle Fields.

FLMBADDR

Bits 0-31: Foreground LUT memory base address.

IPA_BLMADDR

Background LUT memory base address register

Offset: 0x30, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLMADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BLMADDR
rw
Toggle Fields.

BLMADDR

Bits 0-31: Background LUT memory base address.

IPA_DPCTL

Destination pixel control register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPF
rw
Toggle Fields.

DPF

Bits 0-2: Destination pixel format.

IPA_DPV_ARGB4444

Destination pixel value register(When the destination pixel format is ARGB4444,)

Offset: 0x38, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPDAV
rw 		DPDRV
rw 		DPDGV
rw 		DPDBV
rw
Toggle Fields.

DPDBV

Bits 0-3: Destination pre-defined blue value.

DPDGV

Bits 4-7: Destination pre-defined green value.

DPDRV

Bits 8-11: Destination pre-defined red value.

DPDAV

Bits 12-15: Destination pre-defined alpha value.

IPA_DMADDR

Destination memory base address register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMADDR
rw
Toggle Fields.

DMADDR

Bits 0-31: Destination memory base address.

IPA_DLOFF

Destination line offset register

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLOFF
rw
Toggle Fields.

DLOFF

Bits 0-13: Destination line offset.

IPA_IMS

Image size register

Offset: 0x44, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WIDTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HEIGHT
rw
Toggle Fields.

HEIGHT

Bits 0-15: Height of the image to be processed.

WIDTH

Bits 16-29: Width of the image to be processed.

IPA_LM

Line mark register

Offset: 0x48, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LM
rw
Toggle Fields.

LM

Bits 0-15: line mark.

IPA_ITCTL

Inter-timer control register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCCI
rw 		ITEN
rw
Toggle Fields.

ITEN

Bit 0: Inter-timer enable.

NCCI

Bits 8-15: Number of clock cycles interval.

IREF

0x4000C400: Programmable current reference

0/5 fields covered. Toggle Registers.

CTL

control register

Offset: 0x300, reset: 0x00000F00, access: Unspecified

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CREN
rw 		SSEL
rw 		CPT
rw 		SCMOD
rw 		CSDT
rw
Toggle Fields.

CSDT

Bits 0-5: Current step data.

SCMOD

Bit 7: Sink current mode.

CPT

Bits 8-12: Current precision trim.

SSEL

Bit 14: Step selection.

CREN

Bit 15: Current reference enable.

NVIC

0xE000E100: Nested Vectored Interrupt Controller

0/80 fields covered. Toggle Registers.

ISER

Interrupt Set Enable Register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ICER

Interrupt Clear Enable Register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ISPR

Interrupt Set-Pending Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ICPR

Interrupt Clear-Pending Register

Offset: 0x180, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

IABR

Interrupt Active bit Register

Offset: 0x200, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IABR
rw
Toggle Fields.

IABR

Bits 0-31: IABR.

IPR0

Interrupt Priority Register 0

Offset: 0x300, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_00
rw
Toggle Fields.

PRI_00

Bits 0-7: PRI_00.

IPR1

Interrupt Priority Register 1

Offset: 0x301, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_01
rw
Toggle Fields.

PRI_01

Bits 0-7: PRI_01.

IPR2

Interrupt Priority Register 2

Offset: 0x302, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_02
rw
Toggle Fields.

PRI_02

Bits 0-7: PRI_02.

IPR3

Interrupt Priority Register 3

Offset: 0x303, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_03
rw
Toggle Fields.

PRI_03

Bits 0-7: PRI_03.

IPR4

Interrupt Priority Register 4

Offset: 0x304, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_04
rw
Toggle Fields.

PRI_04

Bits 0-7: PRI_04.

IPR5

Interrupt Priority Register 5

Offset: 0x305, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_05
rw
Toggle Fields.

PRI_05

Bits 0-7: PRI_05.

IPR6

Interrupt Priority Register 6

Offset: 0x306, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_06
rw
Toggle Fields.

PRI_06

Bits 0-7: PRI_06.

IPR7

Interrupt Priority Register 7

Offset: 0x307, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_07
rw
Toggle Fields.

PRI_07

Bits 0-7: PRI_07.

IPR8

Interrupt Priority Register 8

Offset: 0x308, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_08
rw
Toggle Fields.

PRI_08

Bits 0-7: PRI_08.

IPR9

Interrupt Priority Register 9

Offset: 0x309, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_09
rw
Toggle Fields.

PRI_09

Bits 0-7: PRI_09.

IPR10

Interrupt Priority Register 10

Offset: 0x30A, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_10
rw
Toggle Fields.

PRI_10

Bits 0-7: PRI_10.

IPR11

Interrupt Priority Register 11

Offset: 0x30B, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_11
rw
Toggle Fields.

PRI_11

Bits 0-7: PRI_11.

IPR12

Interrupt Priority Register 12

Offset: 0x30C, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_12
rw
Toggle Fields.

PRI_12

Bits 0-7: PRI_12.

IPR13

Interrupt Priority Register 13

Offset: 0x30D, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_13
rw
Toggle Fields.

PRI_13

Bits 0-7: PRI_13.

IPR14

Interrupt Priority Register 14

Offset: 0x30E, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_14
rw
Toggle Fields.

PRI_14

Bits 0-7: PRI_14.

IPR15

Interrupt Priority Register 15

Offset: 0x30F, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_15
rw
Toggle Fields.

PRI_15

Bits 0-7: PRI_15.

IPR16

Interrupt Priority Register 16

Offset: 0x310, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_16
rw
Toggle Fields.

PRI_16

Bits 0-7: PRI_16.

IPR17

Interrupt Priority Register 17

Offset: 0x311, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_17
rw
Toggle Fields.

PRI_17

Bits 0-7: PRI_17.

IPR18

Interrupt Priority Register 18

Offset: 0x312, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_18
rw
Toggle Fields.

PRI_18

Bits 0-7: PRI_18.

IPR19

Interrupt Priority Register 19

Offset: 0x313, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_19
rw
Toggle Fields.

PRI_19

Bits 0-7: PRI_19.

IPR20

Interrupt Priority Register 20

Offset: 0x314, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_20
rw
Toggle Fields.

PRI_20

Bits 0-7: PRI_20.

IPR21

Interrupt Priority Register 21

Offset: 0x315, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_21
rw
Toggle Fields.

PRI_21

Bits 0-7: PRI_21.

IPR22

Interrupt Priority Register 22

Offset: 0x316, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_22
rw
Toggle Fields.

PRI_22

Bits 0-7: PRI_22.

IPR23

Interrupt Priority Register 23

Offset: 0x317, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_23
rw
Toggle Fields.

PRI_23

Bits 0-7: PRI_23.

IPR24

Interrupt Priority Register 24

Offset: 0x318, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_24
rw
Toggle Fields.

PRI_24

Bits 0-7: PRI_24.

IPR25

Interrupt Priority Register 25

Offset: 0x319, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_25
rw
Toggle Fields.

PRI_25

Bits 0-7: PRI_25.

IPR26

Interrupt Priority Register 26

Offset: 0x31A, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_26
rw
Toggle Fields.

PRI_26

Bits 0-7: PRI_26.

IPR27

Interrupt Priority Register 27

Offset: 0x31B, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_27
rw
Toggle Fields.

PRI_27

Bits 0-7: PRI_27.

IPR28

Interrupt Priority Register 28

Offset: 0x31C, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_28
rw
Toggle Fields.

PRI_28

Bits 0-7: PRI_28.

IPR29

Interrupt Priority Register 29

Offset: 0x31D, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_29
rw
Toggle Fields.

PRI_29

Bits 0-7: PRI_29.

IPR30

Interrupt Priority Register 30

Offset: 0x31E, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_30
rw
Toggle Fields.

PRI_30

Bits 0-7: PRI_30.

IPR31

Interrupt Priority Register 31

Offset: 0x31F, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_31
rw
Toggle Fields.

PRI_31

Bits 0-7: PRI_31.

IPR32

Interrupt Priority Register 32

Offset: 0x320, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_32
rw
Toggle Fields.

PRI_32

Bits 0-7: PRI_32.

IPR33

Interrupt Priority Register 33

Offset: 0x321, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_33
rw
Toggle Fields.

PRI_33

Bits 0-7: PRI_33.

IPR34

Interrupt Priority Register 34

Offset: 0x322, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_34
rw
Toggle Fields.

PRI_34

Bits 0-7: PRI_34.

IPR35

Interrupt Priority Register 35

Offset: 0x323, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_35
rw
Toggle Fields.

PRI_35

Bits 0-7: PRI_35.

IPR36

Interrupt Priority Register 36

Offset: 0x324, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_36
rw
Toggle Fields.

PRI_36

Bits 0-7: PRI_36.

IPR37

Interrupt Priority Register 37

Offset: 0x325, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_37
rw
Toggle Fields.

PRI_37

Bits 0-7: PRI_37.

IPR38

Interrupt Priority Register 38

Offset: 0x326, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_38
rw
Toggle Fields.

PRI_38

Bits 0-7: PRI_38.

IPR39

Interrupt Priority Register 39

Offset: 0x327, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_39
rw
Toggle Fields.

PRI_39

Bits 0-7: PRI_39.

IPR40

Interrupt Priority Register 40

Offset: 0x328, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_40
rw
Toggle Fields.

PRI_40

Bits 0-7: PRI_40.

IPR41

Interrupt Priority Register 41

Offset: 0x329, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_41
rw
Toggle Fields.

PRI_41

Bits 0-7: PRI_41.

IPR42

Interrupt Priority Register 42

Offset: 0x32A, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_42
rw
Toggle Fields.

PRI_42

Bits 0-7: PRI_42.

IPR43

Interrupt Priority Register 43

Offset: 0x32B, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_43
rw
Toggle Fields.

PRI_43

Bits 0-7: PRI_43.

IPR44

Interrupt Priority Register 44

Offset: 0x32C, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_44
rw
Toggle Fields.

PRI_44

Bits 0-7: PRI_44.

IPR45

Interrupt Priority Register 45

Offset: 0x32D, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_45
rw
Toggle Fields.

PRI_45

Bits 0-7: PRI_45.

IPR46

Interrupt Priority Register 46

Offset: 0x32E, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_46
rw
Toggle Fields.

PRI_46

Bits 0-7: PRI_46.

IPR47

Interrupt Priority Register 47

Offset: 0x32F, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_47
rw
Toggle Fields.

PRI_47

Bits 0-7: PRI_47.

IPR48

Interrupt Priority Register 48

Offset: 0x330, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_48
rw
Toggle Fields.

PRI_48

Bits 0-7: PRI_48.

IPR49

Interrupt Priority Register 49

Offset: 0x331, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_49
rw
Toggle Fields.

PRI_49

Bits 0-7: PRI_49.

IPR50

Interrupt Priority Register 50

Offset: 0x332, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_50
rw
Toggle Fields.

PRI_50

Bits 0-7: PRI_50.

IPR51

Interrupt Priority Register 51

Offset: 0x333, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_51
rw
Toggle Fields.

PRI_51

Bits 0-7: PRI_51.

IPR52

Interrupt Priority Register 52

Offset: 0x334, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_52
rw
Toggle Fields.

PRI_52

Bits 0-7: PRI_52.

IPR53

Interrupt Priority Register 53

Offset: 0x335, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_53
rw
Toggle Fields.

PRI_53

Bits 0-7: PRI_53.

IPR54

Interrupt Priority Register 54

Offset: 0x336, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_54
rw
Toggle Fields.

PRI_54

Bits 0-7: PRI_54.

IPR55

Interrupt Priority Register 55

Offset: 0x337, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_55
rw
Toggle Fields.

PRI_55

Bits 0-7: PRI_55.

IPR56

Interrupt Priority Register 56

Offset: 0x338, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_56
rw
Toggle Fields.

PRI_56

Bits 0-7: PRI_56.

IPR57

Interrupt Priority Register 57

Offset: 0x339, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_57
rw
Toggle Fields.

PRI_57

Bits 0-7: PRI_57.

IPR58

Interrupt Priority Register 58

Offset: 0x33A, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_58
rw
Toggle Fields.

PRI_58

Bits 0-7: PRI_58.

IPR59

Interrupt Priority Register 59

Offset: 0x33B, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_59
rw
Toggle Fields.

PRI_59

Bits 0-7: PRI_59.

IPR60

Interrupt Priority Register 60

Offset: 0x33C, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_60
rw
Toggle Fields.

PRI_60

Bits 0-7: PRI_60.

IPR61

Interrupt Priority Register 61

Offset: 0x33D, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_61
rw
Toggle Fields.

PRI_61

Bits 0-7: PRI_61.

IPR62

Interrupt Priority Register 62

Offset: 0x33E, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_62
rw
Toggle Fields.

PRI_62

Bits 0-7: PRI_62.

IPR63

Interrupt Priority Register 63

Offset: 0x33F, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_63
rw
Toggle Fields.

PRI_63

Bits 0-7: PRI_63.

IPR64

Interrupt Priority Register 64

Offset: 0x340, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_64
rw
Toggle Fields.

PRI_64

Bits 0-7: PRI_64.

IPR65

Interrupt Priority Register 65

Offset: 0x341, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_65
rw
Toggle Fields.

PRI_65

Bits 0-7: PRI_65.

IPR66

Interrupt Priority Register 66

Offset: 0x342, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_66
rw
Toggle Fields.

PRI_66

Bits 0-7: PRI_66.

IPR67

Interrupt Priority Register 67

Offset: 0x343, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_67
rw
Toggle Fields.

PRI_67

Bits 0-7: PRI_67.

IPR68

Interrupt Priority Register 68

Offset: 0x344, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_68
rw
Toggle Fields.

PRI_68

Bits 0-7: PRI_68.

IPR69

Interrupt Priority Register 69

Offset: 0x345, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_69
rw
Toggle Fields.

PRI_69

Bits 0-7: PRI_69.

IPR70

Interrupt Priority Register 70

Offset: 0x346, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_70
rw
Toggle Fields.

PRI_70

Bits 0-7: PRI_70.

IPR71

Interrupt Priority Register 71

Offset: 0x347, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_71
rw
Toggle Fields.

PRI_71

Bits 0-7: PRI_71.

IPR72

Interrupt Priority Register 72

Offset: 0x348, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_72
rw
Toggle Fields.

PRI_72

Bits 0-7: PRI_72.

IPR73

Interrupt Priority Register 73

Offset: 0x349, reset: 0x00, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_73
rw
Toggle Fields.

PRI_73

Bits 0-7: PRI_73.

STIR

Software Trigger Interrupt Register

Offset: 0xE00, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STIR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STIR
w
Toggle Fields.

STIR

Bits 0-31: STIR.

PMU

0x40007000: Power management unit

7/23 fields covered. Toggle Registers.

CTL

power control register

Offset: 0x0, reset: 0x0000C000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LDEN
rw 		HDS
rw 		HDEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDOVS
rw 		LDNP
rw 		LDLP
rw 		BKPWEN
rw 		LVDT
rw 		LVDEN
rw 		STBRST
rw 		WURST
rw 		STBMOD
rw 		LDOLP
rw
Toggle Fields.

LDOLP

Bit 0: LDO Low Power Mode.

STBMOD

Bit 1: Standby Mode.

WURST

Bit 2: Wakeup Flag Reset.

STBRST

Bit 3: Standby Flag Reset.

LVDEN

Bit 4: Low Voltage Detector Enable.

LVDT

Bits 5-7: Low Voltage Detector Threshold.

BKPWEN

Bit 8: Backup Domain Write Enable.

LDLP

Bit 10: Low-driver mode when use low power LDO..

LDNP

Bit 11: Low-driver mode when use normal power LDO.

LDOVS

Bits 14-15: LDO output voltage select.

HDEN

Bit 16: High-driver mode enable.

HDS

Bit 17: High-driver mode switch.

LDEN

Bits 18-19: Low-driver mode enable in Deep-sleep mode.

CS

power control/status register

Offset: 0x4, reset: 0x00000000, access: Unspecified

7/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LDRF
rw 		HDSRF
r 		HDRF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDOVSRF
r 		BLDOON
rw 		WUPEN
rw 		BLDORF
r 		LVDF
r 		STBF
r 		WUF
r
Toggle Fields.

WUF

Bit 0: Wakeup flag.

STBF

Bit 1: Standby flag.

LVDF

Bit 2: Low Voltage Detector Status Flag.

BLDORF

Bit 3: Backup SRAM LDO ready flag.

WUPEN

Bit 8: Enable WKUP pin.

BLDOON

Bit 9: Backup SRAM LDO on.

LDOVSRF

Bit 14: LDO voltage select ready flag.

HDRF

Bit 16: High-driver ready flag.

HDSRF

Bit 17: High-driver switch ready flag.

LDRF

Bits 18-19: Low-driver mode ready flag.

RCU

0x40023800: Reset and clock unit

27/296 fields covered. Toggle Registers.

CTL0

Control register

Offset: 0x0, reset: 0x00000083, access: Unspecified

6/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAISTB
r 		PLLSAIEN
rw 		PLLI2SSTB
r 		PLLI2SEN
rw 		PLLSTB
r 		PLLEN
rw 		CKMEN
rw 		HXTALBPS
rw 		HXTALSTB
r 		HXTALEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRC16MCALIB
r 		IRC16MADJ
rw 		IRC16MSTB
r 		IRC16MEN
rw
Toggle Fields.

IRC16MEN

Bit 0: Internal 16MHz RC oscillator Enable.

IRC16MSTB

Bit 1: IRC16M Internal 16MHz RC Oscillator stabilization Flag.

IRC16MADJ

Bits 3-7: Internal 16MHz RC Oscillator clock trim adjust value.

IRC16MCALIB

Bits 8-15: Internal 16MHz RC Oscillator calibration value register.

HXTALEN

Bit 16: External High Speed oscillator Enable.

HXTALSTB

Bit 17: External crystal oscillator (HXTAL) clock stabilization flag.

HXTALBPS

Bit 18: External crystal oscillator (HXTAL) clock bypass mode enable.

CKMEN

Bit 19: HXTAL Clock Monitor Enable.

PLLEN

Bit 24: PLL enable.

PLLSTB

Bit 25: PLL Clock Stabilization Flag.

PLLI2SEN

Bit 26: PLLI2S enable.

PLLI2SSTB

Bit 27: PLLI2S Clock Stabilization Flag.

PLLSAIEN

Bit 28: PLLSAI enable.

PLLSAISTB

Bit 29: PLLSAI Clock Stabilization Flag.

PLL

PLL register (RCU_PLL)

Offset: 0x4, reset: 0x24003010, access: Unspecified

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLQ
rw 		PLLSEL
rw 		PLLP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLN
rw 		PLLPSC
rw
Toggle Fields.

PLLPSC

Bits 0-5: The PLL VCO source clock prescaler.

PLLN

Bits 6-14: The PLL VCO clock multi factor.

PLLP

Bits 16-17: The PLLP output frequency division factor from PLL VCO clock.

PLLSEL

Bit 22: PLL Clock Source Selection.

PLLQ

Bits 24-27: The PLL Q output frequency division factor from PLL VCO clock.

CFG0

Clock configuration register 0 (RCU_CFG0)

Offset: 0x8, reset: 0x00000000, access: Unspecified

1/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKOUT1SEL
rw 		CKOUT1DIV
rw 		CKOUT0DIV
rw 		I2SSEL
rw 		CKOUT0SEL
rw 		RTCDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
APB2PSC
rw 		APB1PSC
rw 		AHBPSC
rw 		SCSS
r 		SCS
rw
Toggle Fields.

SCS

Bits 0-1: System clock switch.

SCSS

Bits 2-3: System clock switch status.

AHBPSC

Bits 4-7: AHB prescaler selection.

APB1PSC

Bits 10-12: APB1 prescaler selection.

APB2PSC

Bits 13-15: APB2 prescaler selection.

RTCDIV

Bits 16-20: RTC clock divider factor.

CKOUT0SEL

Bits 21-22: CKOUT0 Clock Source Selection.

I2SSEL

Bit 23: I2S Clock Source Selection.

CKOUT0DIV

Bits 24-26: The CK_OUT0 divider which the CK_OUT0 frequency can be reduced.

CKOUT1DIV

Bits 27-29: The CK_OUT1 divider which the CK_OUT1 frequency can be reduced.

CKOUT1SEL

Bits 30-31: CKOUT1 Clock Source Selection.

INT

Clock interrupt register (RCU_INT)

Offset: 0xC, reset: 0x00000000, access: Unspecified

8/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKMIC
w 		PLLSAISTBIC
w 		PLLI2SSTBIC
w 		PLLSTBIC
w 		HXTALSTBIC
w 		IRC16MSTBIC
w 		LXTALSTBIC
w 		IRC32KSTBIC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLSAISTBIE
rw 		PLLI2SSTBIE
rw 		PLLSTBIE
rw 		HXTALSTBIE
rw 		IRC16MSTBIE
rw 		LXTALSTBIE
rw 		IRC32KSTBIE
rw 		CKMIF
r 		PLLSAISTBIF
r 		PLLI2SSTBIF
r 		PLLSTBIF
r 		HXTALSTBIF
r 		IRC16MSTBIF
r 		LXTALSTBIF
r 		IRC32KSTBIF
r
Toggle Fields.

IRC32KSTBIF

Bit 0: IRC32K stabilization interrupt flag.

LXTALSTBIF

Bit 1: LXTAL stabilization interrupt flag.

IRC16MSTBIF

Bit 2: IRC16M stabilization interrupt flag.

HXTALSTBIF

Bit 3: HXTAL stabilization interrupt flag.

PLLSTBIF

Bit 4: PLL stabilization interrupt flag.

PLLI2SSTBIF

Bit 5: PLLI2S stabilization interrupt flag.

PLLSAISTBIF

Bit 6: PLLSAI stabilization interrupt flag.

CKMIF

Bit 7: HXTAL Clock Stuck Interrupt Flag.

IRC32KSTBIE

Bit 8: IRC32K Stabilization interrupt enable.

LXTALSTBIE

Bit 9: LXTAL Stabilization Interrupt Enable.

IRC16MSTBIE

Bit 10: IRC16M Stabilization Interrupt Enable.

HXTALSTBIE

Bit 11: HXTAL Stabilization Interrupt Enable.

PLLSTBIE

Bit 12: PLL Stabilization Interrupt Enable.

PLLI2SSTBIE

Bit 13: PLLI2S Stabilization Interrupt Enable.

PLLSAISTBIE

Bit 14: PLLSAI Stabilization Interrupt Enable.

IRC32KSTBIC

Bit 16: IRC32K Stabilization Interrupt Clear.

LXTALSTBIC

Bit 17: LXTAL Stabilization Interrupt Clear.

IRC16MSTBIC

Bit 18: IRC16M Stabilization Interrupt Clear.

HXTALSTBIC

Bit 19: HXTAL Stabilization Interrupt Clear.

PLLSTBIC

Bit 20: PLL stabilization Interrupt Clear.

PLLI2SSTBIC

Bit 21: PLLI2S stabilization Interrupt Clear.

PLLSAISTBIC

Bit 22: PLLSAI stabilization Interrupt Clear.

CKMIC

Bit 23: HXTAL Clock Stuck Interrupt Clear.

AHB1RST

AHB1 reset register

Offset: 0x10, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USBHSRST
rw 		ENETRST
rw 		IPARST
rw 		DMA1RST
rw 		DMA0RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCRST
rw 		PIRST
rw 		PHRST
rw 		PGRST
rw 		PFRST
rw 		PERST
rw 		PDRST
rw 		PCRST
rw 		PBRST
rw 		PARST
rw
Toggle Fields.

PARST

Bit 0: GPIO port A reset.

PBRST

Bit 1: GPIO port B reset.

PCRST

Bit 2: GPIO port C reset.

PDRST

Bit 3: GPIO port D reset.

PERST

Bit 4: GPIO port E reset.

PFRST

Bit 5: GPIO port F reset.

PGRST

Bit 6: GPIO port G reset.

PHRST

Bit 7: GPIO port H reset.

PIRST

Bit 8: GPIO port I reset.

CRCRST

Bit 12: CRC reset.

DMA0RST

Bit 21: DMA0 reset.

DMA1RST

Bit 22: DMA1 reset.

IPARST

Bit 23: IPA reset.

ENETRST

Bit 25: Ethernet reset.

USBHSRST

Bit 29: USBHS reset.

AHB2RST

AHB2 reset register

Offset: 0x14, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBFSRST
rw 		TRNGRST
rw 		DCIRST
rw
Toggle Fields.

DCIRST

Bit 0: DCI reset.

TRNGRST

Bit 6: TRNG reset.

USBFSRST

Bit 7: USBFS reset.

AHB3RST

AHB3 reset register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMCRST
rw
Toggle Fields.

EXMCRST

Bit 0: EXMC reset.

APB1RST

APB1 reset register (RCU_APB1RST)

Offset: 0x20, reset: 0x00000000, access: read-write

0/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UART7RST
rw 		UART6RST
rw 		DACRST
rw 		PMURST
rw 		CAN1RST
rw 		CAN0RST
rw 		I2C2RST
rw 		I2C1RST
rw 		I2C0RST
rw 		UART4RST
rw 		UART3RST
rw 		USART2RST
rw 		USART1RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2RST
rw 		SPI1RST
rw 		WWDGTRST
rw 		TIMER13RST
rw 		TIMER12RST
rw 		TIMER11RST
rw 		TIMER6RST
rw 		TIMER5RST
rw 		TIMER4RST
rw 		TIMER3RST
rw 		TIMER2RST
rw 		TIMER1RST
rw
Toggle Fields.

TIMER1RST

Bit 0: TIMER1 timer reset.

TIMER2RST

Bit 1: TIMER2 timer reset.

TIMER3RST

Bit 2: TIMER3 timer reset.

TIMER4RST

Bit 3: TIMER4 timer reset.

TIMER5RST

Bit 4: TIMER5 timer reset.

TIMER6RST

Bit 5: TIMER6 timer reset.

TIMER11RST

Bit 6: TIMER11 timer reset.

TIMER12RST

Bit 7: TIMER12 timer reset.

TIMER13RST

Bit 8: TIMER13 timer reset.

WWDGTRST

Bit 11: Window watchdog timer reset.

SPI1RST

Bit 14: SPI1 reset.

SPI2RST

Bit 15: SPI2 reset.

USART1RST

Bit 17: USART1 reset.

USART2RST

Bit 18: USART2 reset.

UART3RST

Bit 19: UART3 reset.

UART4RST

Bit 20: UART4 reset.

I2C0RST

Bit 21: I2C0 reset.

I2C1RST

Bit 22: I2C1 reset.

I2C2RST

Bit 23: I2C2 reset.

CAN0RST

Bit 25: CAN0 reset.

CAN1RST

Bit 26: CAN1 reset.

PMURST

Bit 28: Power control reset.

DACRST

Bit 29: DAC reset.

UART6RST

Bit 30: UART6 reset.

UART7RST

Bit 31: UART7 reset.

APB2RST

APB2 reset register (RCU_APB2RST)

Offset: 0x24, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TLIRST
rw 		SPI5RST
rw 		SPI4RST
rw 		TIMER10RST
rw 		TIMER9RST
rw 		TIMER8RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSCFGRST
rw 		SPI3RST
rw 		SPI0RST
rw 		SDIORST
rw 		ADCRST
rw 		USART5RST
rw 		USART0RST
rw 		TIMER7RST
rw 		TIMER0RST
rw
Toggle Fields.

TIMER0RST

Bit 0: TIMER0 reset.

TIMER7RST

Bit 1: TIMER7 reset.

USART0RST

Bit 4: USART0 reset.

USART5RST

Bit 5: USART5 reset.

ADCRST

Bit 8: ADC reset.

SDIORST

Bit 11: SDIO reset.

SPI0RST

Bit 12: SPI0 Reset.

SPI3RST

Bit 13: SPI3 Reset.

SYSCFGRST

Bit 14: SYSCFG Reset.

TIMER8RST

Bit 16: TIMER8 reset.

TIMER9RST

Bit 17: TIMER9 reset.

TIMER10RST

Bit 18: TIMER10 reset.

SPI4RST

Bit 20: SPI4 Reset.

SPI5RST

Bit 21: SPI5 Reset.

TLIRST

Bit 26: TLI Reset.

AHB1EN

AHB1 enable register

Offset: 0x30, reset: 0x00100000, access: read-write

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USBHSULPIEN
rw 		USBHSEN
rw 		ENETPTPEN
rw 		ENETRXEN
rw 		ENETTXEN
rw 		ENETEN
rw 		IPAEN
rw 		DMA1EN
rw 		DMA0EN
rw 		TCMSRAMEN
rw 		BKPSRAMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCEN
rw 		PIEN
rw 		PHEN
rw 		PGEN
rw 		PFEN
rw 		PEEN
rw 		PDEN
rw 		PCEN
rw 		PBEN
rw 		PAEN
rw
Toggle Fields.

PAEN

Bit 0: GPIO port A clock enable.

PBEN

Bit 1: GPIO port B clock enable.

PCEN

Bit 2: GPIO port C clock enable.

PDEN

Bit 3: GPIO port D clock enable.

PEEN

Bit 4: GPIO port E clock enable.

PFEN

Bit 5: GPIO port F clock enable.

PGEN

Bit 6: GPIO port G clock enable.

PHEN

Bit 7: GPIO port H clock enable.

PIEN

Bit 8: GPIO port I clock enable.

CRCEN

Bit 12: CRC clock enable.

BKPSRAMEN

Bit 18: BKPSRAM clock enable.

TCMSRAMEN

Bit 20: TCMSRAM clock enable.

DMA0EN

Bit 21: DMA0 clock enable.

DMA1EN

Bit 22: DMA1 clock enable.

IPAEN

Bit 23: IPA clock enable.

ENETEN

Bit 25: Ethernet clock enable.

ENETTXEN

Bit 26: Ethernet TX clock enable.

ENETRXEN

Bit 27: Ethernet RX clock enable.

ENETPTPEN

Bit 28: Ethernet PTP clock enable.

USBHSEN

Bit 29: USBHS clock enable.

USBHSULPIEN

Bit 30: USBHS ULPI clock enable.

AHB2EN

AHB2 enable register

Offset: 0x34, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBFSEN
rw 		TRNGEN
rw 		DCIEN
rw
Toggle Fields.

DCIEN

Bit 0: DCI clock enable.

TRNGEN

Bit 6: TRNG clock enable.

USBFSEN

Bit 7: USBFS clock enable.

AHB3EN

AHB3 clock enable register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMCEN
rw
Toggle Fields.

EXMCEN

Bit 0: EXMC clock enable.

APB1EN

APB1 clock enable register (RCU_APB1EN)

Offset: 0x40, reset: 0x00000000, access: read-write

0/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UART7EN
rw 		UART6EN
rw 		DACEN
rw 		PMUEN
rw 		CAN1EN
rw 		CAN0EN
rw 		I2C2EN
rw 		I2C1EN
rw 		I2C0EN
rw 		UART4EN
rw 		UART3EN
rw 		USART2EN
rw 		USART1EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2EN
rw 		SPI1EN
rw 		WWDGTEN
rw 		TIMER13EN
rw 		TIMER12EN
rw 		TIMER11EN
rw 		TIMER6EN
rw 		TIMER5EN
rw 		TIMER4EN
rw 		TIMER3EN
rw 		TIMER2EN
rw 		TIMER1EN
rw
Toggle Fields.

TIMER1EN

Bit 0: TIMER1 timer clock enable.

TIMER2EN

Bit 1: TIMER2 timer clock enable.

TIMER3EN

Bit 2: TIMER3 timer clock enable.

TIMER4EN

Bit 3: TIMER4 timer clock enable.

TIMER5EN

Bit 4: TIMER5 timer clock enable.

TIMER6EN

Bit 5: TIMER6 timer clock enable.

TIMER11EN

Bit 6: TIMER11 timer clock enable.

TIMER12EN

Bit 7: TIMER12 timer clock enable.

TIMER13EN

Bit 8: TIMER13 timer clock enable.

WWDGTEN

Bit 11: Window watchdog timer clock enable.

SPI1EN

Bit 14: SPI1 clock enable.

SPI2EN

Bit 15: SPI2 clock enable.

USART1EN

Bit 17: USART1 clock enable.

USART2EN

Bit 18: USART2 clock enable.

UART3EN

Bit 19: UART3 clock enable.

UART4EN

Bit 20: UART4 clock enable.

I2C0EN

Bit 21: I2C0 clock enable.

I2C1EN

Bit 22: I2C1 clock enable.

I2C2EN

Bit 23: I2C2 clock enable.

CAN0EN

Bit 25: CAN0 clock enable.

CAN1EN

Bit 26: CAN1 clock enable .

PMUEN

Bit 28: Power control clock enable .

DACEN

Bit 29: DAC clock enable.

UART6EN

Bit 30: UART6 clock enable.

UART7EN

Bit 31: UART7 clock enable .

APB2EN

APB2 clock enable register (RCU_APB2EN)

Offset: 0x44, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TLIEN
rw 		SPI5EN
rw 		SPI4EN
rw 		TIMER10EN
rw 		TIMER9EN
rw 		TIMER8EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSCFGEN
rw 		SPI3EN
rw 		SPI0EN
rw 		SDIOEN
rw 		ADC2EN
rw 		ADC1EN
rw 		ADC0EN
rw 		USART5EN
rw 		USART0EN
rw 		TIMER7EN
rw 		TIMER0EN
rw
Toggle Fields.

TIMER0EN

Bit 0: TIMER0 clock enable .

TIMER7EN

Bit 1: TIMER7 clock enable.

USART0EN

Bit 4: USART0 clock enable.

USART5EN

Bit 5: USART5 clock enable.

ADC0EN

Bit 8: ADC0 clock enable .

ADC1EN

Bit 9: ADC1 clock enable .

ADC2EN

Bit 10: ADC2 clock enable .

SDIOEN

Bit 11: SDIO clock enable.

SPI0EN

Bit 12: SPI0 clock enable.

SPI3EN

Bit 13: SPI3 clock enable.

SYSCFGEN

Bit 14: SYSCFG clock enable .

TIMER8EN

Bit 16: TIMER8 clock enable.

TIMER9EN

Bit 17: TIMER9 clock enable.

TIMER10EN

Bit 18: TIMER10 clock enable .

SPI4EN

Bit 20: SPI4 clock enable.

SPI5EN

Bit 21: SPI5 clock enable .

TLIEN

Bit 26: TLI clock enable .

AHB1SPEN

AHB1 sleep mode enable register

Offset: 0x50, reset: 0x7EEF97FF, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USBHSULPISPEN
rw 		USBHSSPEN
rw 		ENETPTPSPEN
rw 		ENETRXSPEN
rw 		ENETTXSPEN
rw 		ENETSPEN
rw 		IPASPEN
rw 		DMA1SPEN
rw 		DMA0SPEN
rw 		SRAM2SPEN
rw 		BKPSRAMSPEN
rw 		SRAM1SPEN
rw 		SRAM0SPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMCSPEN
rw 		CRCSPEN
rw 		PISPEN
rw 		PHSPEN
rw 		PGSPEN
rw 		PFSPEN
rw 		PESPEN
rw 		PDSPEN
rw 		PCSPEN
rw 		PBSPEN
rw 		PASPEN
rw
Toggle Fields.

PASPEN

Bit 0: GPIO port A clock enable when sleep mode.

PBSPEN

Bit 1: GPIO port B clock enable when sleep mode.

PCSPEN

Bit 2: GPIO port C clock enable when sleep mode.

PDSPEN

Bit 3: GPIO port D clock enable when sleep mode.

PESPEN

Bit 4: GPIO port E clock enable when sleep mode.

PFSPEN

Bit 5: GPIO port F clock enable when sleep mode.

PGSPEN

Bit 6: GPIO port G clock enable when sleep mode.

PHSPEN

Bit 7: GPIO port H clock enable when sleep mode.

PISPEN

Bit 8: GPIO port I clock enable when sleep mode.

CRCSPEN

Bit 12: CRC clock enable when sleep mode.

FMCSPEN

Bit 15: FMC clock enable when sleep mode.

SRAM0SPEN

Bit 16: SRAM0 clock enable when sleep mode.

SRAM1SPEN

Bit 17: SRAM1 clock enable when sleep mode.

BKPSRAMSPEN

Bit 18: BKPSRAM clock enable when sleep mode.

SRAM2SPEN

Bit 19: SRAM2 clock enable when sleep mode.

DMA0SPEN

Bit 21: DMA0 clock enable when sleep mode.

DMA1SPEN

Bit 22: DMA1 clock enable when sleep mode.

IPASPEN

Bit 23: IPA clock enable when sleep mode.

ENETSPEN

Bit 25: Ethernet clock enable when sleep mode.

ENETTXSPEN

Bit 26: Ethernet TX clock enable when sleep mode.

ENETRXSPEN

Bit 27: Ethernet RX clock enable when sleep mode.

ENETPTPSPEN

Bit 28: Ethernet PTP clock enable when sleep mode.

USBHSSPEN

Bit 29: USBHS clock enable when sleep mode.

USBHSULPISPEN

Bit 30: USBHS ULPI clock enable when sleep mode.

AHB2SPEN

AHB2 sleep mode enable register

Offset: 0x54, reset: 0x000000C1, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBFSSPEN
rw 		TRNGSPEN
rw 		DCISPEN
rw
Toggle Fields.

DCISPEN

Bit 0: DCI clock enable when sleep mode.

TRNGSPEN

Bit 6: TRNG clock enable when sleep mode.

USBFSSPEN

Bit 7: USBFS clock enable when sleep mode.

AHB3SPEN

AHB3 Sleep mode enable register

Offset: 0x58, reset: 0x00000001, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMCSPEN
rw
Toggle Fields.

EXMCSPEN

Bit 0: EXMC clock enable when sleep mode.

APB1SPEN

APB1 sleep mode clock enable register (RCU_APB1EN)

Offset: 0x60, reset: 0xF6FEC9FF, access: read-write

0/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UART7SPEN
rw 		UART6SPEN
rw 		DACSPEN
rw 		PMUSPEN
rw 		CAN1SPEN
rw 		CAN0SPEN
rw 		I2C2SPEN
rw 		I2C1SPEN
rw 		I2C0SPEN
rw 		UART4SPEN
rw 		UART3SPEN
rw 		USART2SPEN
rw 		USART1SPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2SPEN
rw 		SPI1SPEN
rw 		WWDGTSPEN
rw 		TIMER13SPEN
rw 		TIMER12SPEN
rw 		TIMER11SPEN
rw 		TIMER6SPEN
rw 		TIMER5SPEN
rw 		TIMER4SPEN
rw 		TIMER3SPEN
rw 		TIMER2SPEN
rw 		TIMER1SPEN
rw
Toggle Fields.

TIMER1SPEN

Bit 0: TIMER1 timer clock enable when sleep mode.

TIMER2SPEN

Bit 1: TIMER2 timer clock enable when sleep mode.

TIMER3SPEN

Bit 2: TIMER3 timer clock enable when sleep mode.

TIMER4SPEN

Bit 3: TIMER4 timer clock enable when sleep mode.

TIMER5SPEN

Bit 4: TIMER5 timer clock enable when sleep mode.

TIMER6SPEN

Bit 5: TIMER6 timer clock enable when sleep mode.

TIMER11SPEN

Bit 6: TIMER11 timer clock enable when sleep mode.

TIMER12SPEN

Bit 7: TIMER12 timer clock enable when sleep mode.

TIMER13SPEN

Bit 8: TIMER13 timer clock enable when sleep mode.

WWDGTSPEN

Bit 11: Window watchdog timer clock enable when sleep mode.

SPI1SPEN

Bit 14: SPI1 clock enable when sleep mode.

SPI2SPEN

Bit 15: SPI2 clock enable when sleep mode.

USART1SPEN

Bit 17: USART1 clock enable when sleep mode.

USART2SPEN

Bit 18: USART2 clock enable when sleep mode.

UART3SPEN

Bit 19: UART3 clock enable when sleep mode.

UART4SPEN

Bit 20: UART4 clock enable when sleep mode.

I2C0SPEN

Bit 21: I2C0 clock enable when sleep mode.

I2C1SPEN

Bit 22: I2C1 clock enable when sleep mode.

I2C2SPEN

Bit 23: I2C2 clock enable when sleep mode.

CAN0SPEN

Bit 25: CAN0 clock enable when sleep mode.

CAN1SPEN

Bit 26: CAN1 clock enable when sleep mode.

PMUSPEN

Bit 28: Power control clock enable when sleep mode.

DACSPEN

Bit 29: DAC clock enable when sleep mode.

UART6SPEN

Bit 30: UART6 clock enable when sleep mode.

UART7SPEN

Bit 31: UART7 clock enable when sleep mode.

APB2SPEN

APB2 sleep mode enable register (RCU_APB2SPEN)

Offset: 0x64, reset: 0x04777F33, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TLISPEN
rw 		SPI5SPEN
rw 		SPI4SPEN
rw 		TIMER10SPEN
rw 		TIMER9SPEN
rw 		TIMER8SPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSCFGSPEN
rw 		SPI3SPEN
rw 		SPI0SPEN
rw 		SDIOSPEN
rw 		ADC2SPEN
rw 		ADC1SPEN
rw 		ADC0SPEN
rw 		USART5SPEN
rw 		USART0SPEN
rw 		TIMER7SPEN
rw 		TIMER0SPEN
rw
Toggle Fields.

TIMER0SPEN

Bit 0: TIMER0 clock enable when sleep mode.

TIMER7SPEN

Bit 1: TIMER7 clock enable when sleep mode.

USART0SPEN

Bit 4: USART0 clock enable when sleep mode.

USART5SPEN

Bit 5: USART5 clock enable when sleep mode.

ADC0SPEN

Bit 8: ADC0 clock enable when sleep mode.

ADC1SPEN

Bit 9: ADC1 clock enable when sleep mode.

ADC2SPEN

Bit 10: ADC2 clock enable when sleep mode.

SDIOSPEN

Bit 11: SDIO clock enable when sleep mode.

SPI0SPEN

Bit 12: SPI0 clock enable when sleep mode.

SPI3SPEN

Bit 13: SPI3 clock enable when sleep mode.

SYSCFGSPEN

Bit 14: SYSCFG clock enable when sleep mode.

TIMER8SPEN

Bit 16: TIMER8 clock enable when sleep mode.

TIMER9SPEN

Bit 17: TIMER9 clock enable when sleep mode.

TIMER10SPEN

Bit 18: TIMER10 clock enable when sleep mode.

SPI4SPEN

Bit 20: SPI4 clock enable when sleep mode.

SPI5SPEN

Bit 21: SPI5 clock enable when sleep mode.

TLISPEN

Bit 26: TLI clock enable when sleep mode.

BDCTL

Backup domain control register (RCU_BDCTL)

Offset: 0x70, reset: 0x00000000, access: Unspecified

1/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKPRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCEN
rw 		RTCSRC
rw 		LXTALDRI
rw 		LXTALBPS
rw 		LXTALSTB
r 		LXTALEN
rw
Toggle Fields.

LXTALEN

Bit 0: LXTAL enable.

LXTALSTB

Bit 1: External low-speed oscillator stabilization.

LXTALBPS

Bit 2: LXTAL bypass mode enable.

LXTALDRI

Bits 3-4: LXTAL drive capability.

RTCSRC

Bits 8-9: RTC clock entry selection.

RTCEN

Bit 15: RTC clock enable.

BKPRST

Bit 16: Backup domain reset.

RSTSCK

Reset source /clock register (RCU_RSTSCK)

Offset: 0x74, reset: 0x0E000000, access: Unspecified

8/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPRSTF
r 		WWDGTRSTF
r 		FWDGTRSTF
r 		SWRSTF
r 		PORRSTF
r 		EPRSTF
r 		BORRSTF
r 		RSTFC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRC32KSTB
r 		IRC32KEN
rw
Toggle Fields.

IRC32KEN

Bit 0: IRC32K enable.

IRC32KSTB

Bit 1: IRC32K stabilization.

RSTFC

Bit 24: Reset flag clear.

BORRSTF

Bit 25: BOR reset flag.

EPRSTF

Bit 26: External PIN reset flag.

PORRSTF

Bit 27: Power reset flag.

SWRSTF

Bit 28: Software reset flag.

FWDGTRSTF

Bit 29: Free Watchdog timer reset flag.

WWDGTRSTF

Bit 30: Window watchdog timer reset flag.

LPRSTF

Bit 31: Low-power reset flag.

PLLSSCTL

PLL clock spread spectrum control register (RCU_PLLSSCTL)

Offset: 0x80, reset: 0x00000000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSCGON
rw 		SS_TYPE
rw 		MODSTEP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODSTEP
rw 		MODCNT
rw
Toggle Fields.

MODCNT

Bits 0-12: configure PLL spread spectrum modulation profile amplitude and frequency.

MODSTEP

Bits 13-27: configure PLL spread spectrum modulation profile amplitude and frequency.

SS_TYPE

Bit 30: PLL spread spectrum modulation type select.

SSCGON

Bit 31: PLL spread spectrum modulation enable.

PLLI2S

PLLI2S register (RCU_PLLI2S)

Offset: 0x84, reset: 24003000, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLI2SR
rw 		PLLI2SQ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLI2SN
rw 		PLLI2SPSC
rw
Toggle Fields.

PLLI2SPSC

Bits 0-5: The PLLI2S VCO source clock prescaler.

PLLI2SN

Bits 6-14: The PLLI2S VCO clock multi factor.

PLLI2SQ

Bits 24-27: The PLLI2S Q output frequency division factor from PLLI2S VCO clock.

PLLI2SR

Bits 28-30: The PLLI2S R output frequency division factor from PLLI2S VCO clock.

PLLSAI

PLLSAI register (RCU_PLLSAI)

Offset: 0x88, reset: 24003010, access: Unspecified

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAIR
rw 		PLLSAIQ
rw 		PLLSAIP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLSAIN
rw
Toggle Fields.

PLLSAIN

Bits 6-14: The PLLSAI VCO clock multi factor.

PLLSAIP

Bits 16-17: The PLLSAI P output frequency division factor from PLLSAI VCO clock.

PLLSAIQ

Bits 24-27: The PLLI2S Q output frequency division factor from PLLI2S VCO clock.

PLLSAIR

Bits 28-30: The PLLSAI R output frequency division factor from PLLSAI VCO clock.

CFG1

Clock Configuration register 1

Offset: 0x8C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIMERSEL
rw 		PLLSAIRDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PLLSAIRDIV

Bits 16-17: The divider factor from PLLSAIR clock.

TIMERSEL

Bit 24: TIMER clock selection.

ADDCTL

Additional clock control register

Offset: 0xC0, reset: 0x00000000, access: Unspecified

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IRC48MCAL
r 		IRC48MSTB
r 		IRC48MEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL48MSEL
rw 		CK48MSEL
rw
Toggle Fields.

CK48MSEL

Bit 0: 48MHz clock selection.

PLL48MSEL

Bit 1: PLL48M clock selection.

IRC48MEN

Bit 16: Internal 48MHz RC oscillator enable.

IRC48MSTB

Bit 17: Internal 48MHz RC oscillator clock stabilization Flag.

IRC48MCAL

Bits 24-31: Internal 48MHz RC oscillator calibration value register.

ADDINT

Additional clock interrupt register

Offset: 0xCC, reset: 0x00000000, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IRC48MSTBIC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IRC48MSTBIE
rw 		IRC48MSTBIF
r
Toggle Fields.

IRC48MSTBIF

Bit 6: IRC48M stabilization interrupt flag.

IRC48MSTBIE

Bit 14: Internal 48 MHz RC oscillator Stabilization Interrupt Enable.

IRC48MSTBIC

Bit 22: Internal 48 MHz RC oscillator Stabilization Interrupt Clear.

ADDAPB1RST

APB1 additional reset register

Offset: 0xE0, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IREFRST
rw 		CTCRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

CTCRST

Bit 27: CTC reset.

IREFRST

Bit 31: IREF reset.

ADDAPB1EN

APB1 additional enable register

Offset: 0xE4, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IREFEN
rw 		CTCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

CTCEN

Bit 27: CTC clock enable.

IREFEN

Bit 31: IREF interface clock enable.

ADDAPB1SPEN

APB1 additional sleep mode enable register

Offset: 0xE8, reset: 0x88000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IREFSPEN
rw 		CTCSPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

CTCSPEN

Bit 27: CTC enable when sleep mode.

IREFSPEN

Bit 31: IREF enable when sleep mode.

VKEY

Voltage key register

Offset: 0x100, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-31: The key of RCU_DSV registe.

DSV

Deep sleep mode Voltage register

Offset: 0x134, reset: 0x00000000, access: Unspecified

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSLPVS
rw
Toggle Fields.

DSLPVS

Bits 0-2: Deep-sleep mode voltage select.

RTC

0x40002800: Real-time clock

20/142 fields covered. Toggle Registers.

TIME

time register

Offset: 0x0, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw 		HRT
rw 		HRU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw 		MNU
rw 		SCT
rw 		SCU
rw
Toggle Fields.

SCU

Bits 0-3: Second units in BCD format.

SCT

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HRU

Bits 16-19: Hour units in BCD format.

HRT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

DATE

date register

Offset: 0x4, reset: 0x00002101, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YRT
rw 		YRU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOW
rw 		MONT
rw 		MONU
rw 		DAYT
rw 		DAYU
rw
Toggle Fields.

DAYU

Bits 0-3: Date units in BCD code.

DAYT

Bits 4-5: Date tens in BCD code.

MONU

Bits 8-11: Month units in BCD code.

MONT

Bit 12: Month tens in BCD code.

DOW

Bits 13-15: Days of the week.

YRU

Bits 16-19: Year units in BCD code.

YRT

Bits 20-23: Year tens in BCD code.

CTL

control register

Offset: 0x8, reset: 0x00000000, access: Unspecified

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COEN
rw 		OS
rw 		OPOL
rw 		COS
rw 		DSM
rw 		S1H
w 		A1H
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIE
rw 		WTIE
rw 		ALRM1IE
rw 		ALRM0IE
rw 		TSEN
rw 		WTEN
rw 		ALRM1EN
rw 		ALRM0EN
rw 		CCEN
rw 		CS
rw 		BPSHAD
rw 		REFEN
rw 		TSEG
rw 		WTCS
rw
Toggle Fields.

WTCS

Bits 0-2: Auto-wakeup timer clock selection.

TSEG

Bit 3: Valid event edge of time-stamp.

REFEN

Bit 4: Reference clock detection function enable enable (50 or 60 Hz).

BPSHAD

Bit 5: Shadow registers bypass control.

CS

Bit 6: Clock System.

CCEN

Bit 7: Coarse calibration function enable.

ALRM0EN

Bit 8: Alarm-0 function enable.

ALRM1EN

Bit 9: Alarm-1 function enable.

WTEN

Bit 10: Auto-wakeup timer function enable.

TSEN

Bit 11: Time-stamp function enable.

ALRM0IE

Bit 12: RTC alarm-0 interrupt enable.

ALRM1IE

Bit 13: RTC alarm-1 interrupt enable.

WTIE

Bit 14: Auto-wakeup timer interrupt enable.

TSIE

Bit 15: Time-stamp interrupt enable.

A1H

Bit 16: Add 1 hour (summer time change).

S1H

Bit 17: Subtract 1 hour (winter time change).

DSM

Bit 18: Daylight saving mark.

COS

Bit 19: Calibration output selection.

OPOL

Bit 20: Output polarity.

OS

Bits 21-22: Output selection.

COEN

Bit 23: Calibration output enable.

STAT

status register

Offset: 0xC, reset: 0x00000007, access: Unspecified

6/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCPF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TP1F
rw 		TP0F
rw 		TSOVRF
rw 		TSF
rw 		WTF
rw 		ALRM1F
rw 		ALRM0F
rw 		INITM
rw 		INITF
r 		RSYNF
rw 		YCM
r 		SOPF
rw 		WTWF
r 		ALRM1WF
r 		ALRM0WF
r
Toggle Fields.

ALRM0WF

Bit 0: Alarm 0 configuration can be write flag.

ALRM1WF

Bit 1: Alarm 1 configuration can be write flag .

WTWF

Bit 2: Wakeup timer write enable flag .

SOPF

Bit 3: Shift function operation pending flag.

YCM

Bit 4: Year configuration mark.

RSYNF

Bit 5: Register synchronization flag.

INITF

Bit 6: Initialization state flag.

INITM

Bit 7: Enter initialization mode.

ALRM0F

Bit 8: Alarm-0 occurs flag.

ALRM1F

Bit 9: Alarm-1 occurs flag.

WTF

Bit 10: Wakeup timer flag.

TSF

Bit 11: Time-stamp flag.

TSOVRF

Bit 12: Time-stamp overflow flag.

TP0F

Bit 13: RTC_TAMP0 detected flag.

TP1F

Bit 14: RTC_TAMP1 detected flag.

SCPF

Bit 16: Smooth calibration pending flag.

PSC

prescaler register

Offset: 0x10, reset: 0x007F00FF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FACTOR_A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FACTOR_S
rw
Toggle Fields.

FACTOR_S

Bits 0-14: Synchronous prescaler factor.

FACTOR_A

Bits 16-22: Asynchronous prescaler factor.

WUT

Wakeup timer register

Offset: 0x14, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WTRV
rw
Toggle Fields.

WTRV

Bits 0-15: Auto-wakeup timer reloads value.

COSC

Coarse calibration register

Offset: 0x18, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COSD
rw 		COSS
rw
Toggle Fields.

COSS

Bits 0-4: Coarse Calibration step.

COSD

Bit 7: Coarse Calibration direction.

ALRM0TD

Alarm 0 time and date register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSKD
rw 		DOWS
rw 		DAYT
rw 		DAYU
rw 		MSKH
rw 		PM
rw 		HRT
rw 		HRU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSKM
rw 		MNT
rw 		MNU
rw 		MSKS
rw 		SCT
rw 		SCU
rw
Toggle Fields.

SCU

Bits 0-3: Second units in BCD code..

SCT

Bits 4-6: Second tens in BCD code..

MSKS

Bit 7: Alarm seconds mask bit.

MNU

Bits 8-11: Minute units in BCD code..

MNT

Bits 12-14: Minute tens in BCD code..

MSKM

Bit 15: Alarm minutes mask bit.

HRU

Bits 16-19: Hour units in BCD code..

HRT

Bits 20-21: Hour tens in BCD code..

PM

Bit 22: AM/PM flag.

MSKH

Bit 23: Alarm hours mask bit.

DAYU

Bits 24-27: Date units or week day in BCD code..

DAYT

Bits 28-29: Date tens in BCD code..

DOWS

Bit 30: Day of the week selected.

MSKD

Bit 31: Alarm date mask bit.

ALRM1TD

Alarm 1 time and date register

Offset: 0x20, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSKD
rw 		DOWS
rw 		DAYT
rw 		DAYU
rw 		MSKH
rw 		PM
rw 		HRT
rw 		HRU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSKM
rw 		MNT
rw 		MNU
rw 		MSKS
rw 		SCT
rw 		SCU
rw
Toggle Fields.

SCU

Bits 0-3: Second units in BCD code..

SCT

Bits 4-6: Second tens in BCD code..

MSKS

Bit 7: Alarm seconds mask bit.

MNU

Bits 8-11: Minute units in BCD code..

MNT

Bits 12-14: Minute tens in BCD code..

MSKM

Bit 15: Alarm minutes mask bit.

HRU

Bits 16-19: Hour units in BCD code..

HRT

Bits 20-21: Hour tens in BCD code..

PM

Bit 22: AM/PM flag.

MSKH

Bit 23: Alarm hours mask bit.

DAYU

Bits 24-27: Date units or week day in BCD code..

DAYT

Bits 28-29: Date tens in BCD code..

DOWS

Bit 30: Day of the week selected.

MSKD

Bit 31: Alarm date mask bit.

WPK

write protection register

Offset: 0x24, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WPK
w
Toggle Fields.

WPK

Bits 0-7: Write protection key.

SS

sub second register

Offset: 0x28, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSC
r
Toggle Fields.

SSC

Bits 0-15: Sub second value.

SHIFTCTL

shift function control register

Offset: 0x2C, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A1S
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SFS
w
Toggle Fields.

SFS

Bits 0-14: Subtract a fraction of a second.

A1S

Bit 31: One second add.

TTS

Time of time stamp register

Offset: 0x30, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
r 		HRT
r 		HRU
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
r 		MNU
r 		SCT
r 		SCU
r
Toggle Fields.

SCU

Bits 0-3: Second units in BCD code..

SCT

Bits 4-6: Second tens in BCD code..

MNU

Bits 8-11: Minute units in BCD code..

MNT

Bits 12-14: Minute tens in BCD code..

HRU

Bits 16-19: Hour units in BCD code..

HRT

Bits 20-21: Hour tens in BCD code..

PM

Bit 22: AM/PM mark.

DTS

Date of time stamp register

Offset: 0x34, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOW
r 		MONT
r 		MONU
r 		DAYT
r 		DAYU
r
Toggle Fields.

DAYU

Bits 0-3: Date units in BCD format.

DAYT

Bits 4-5: Date tens in BCD format.

MONU

Bits 8-11: Month units in BCD format.

MONT

Bit 12: Month tens in BCD format.

DOW

Bits 13-15: Week day units.

SSTS

Sub second of time stamp register

Offset: 0x38, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSC
r
Toggle Fields.

SSC

Bits 0-15: Sub second value.

HRFC

calibration register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FREQI
rw 		CWND8
rw 		CWND16
rw 		CMSK
rw
Toggle Fields.

CMSK

Bits 0-8: Calibration mask number.

CWND16

Bit 13: Frequency compensation window 16 second selected.

CWND8

Bit 14: Frequency compensation window 8 second selected.

FREQI

Bit 15: Increase RTC frequency by 488.5PPM.

TAMP

tamper and alternate function configuration register

Offset: 0x40, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AOT
rw 		TSSEL
rw 		TP0SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISPU
rw 		PRCH
rw 		FLT
rw 		FREQ
rw 		TPTS
rw 		TP1EG
rw 		TP1EN
rw 		TPIE
rw 		TP0EG
rw 		TP0EN
rw
Toggle Fields.

TP0EN

Bit 0: Tamper 0 detection enable.

TP0EG

Bit 1: Tamper 0 event trigger edge.

TPIE

Bit 2: Tamper detection interrupt enable.

TP1EN

Bit 3: Tamper 1 detection enable.

TP1EG

Bit 4: Tamper 1 event trigger edge.

TPTS

Bit 7: Make tamper function used for timestamp function.

FREQ

Bits 8-10: Sampling frequency of tamper event detection.

FLT

Bits 11-12: RTC_TAMPx filter count setting.

PRCH

Bits 13-14: Pre-charge duration time of RTC_TAMPx.

DISPU

Bit 15: RTC_TAMPx pull-up disable.

TP0SEL

Bit 16: Tamper 0 function input mapping selection.

TSSEL

Bit 17: Timestamp input mapping selection.

AOT

Bit 18: RTC_ALARM Output Type.

ALRM0SS

alarm A sub second register

Offset: 0x44, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSKSSC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSC
rw
Toggle Fields.

SSC

Bits 0-14: Alarm sub second value.

MSKSSC

Bits 24-27: Mask control bit of SSC.

ALRM1SS

Alarm 1 sub second register

Offset: 0x48, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSKSSC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSC
rw
Toggle Fields.

SSC

Bits 0-14: Alarm sub second value.

MSKSSC

Bits 24-27: Mask control bit of SSC.

BKP0

backup register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: BKP.

BKP1

backup register

Offset: 0x54, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

BKP2

backup register

Offset: 0x58, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

BKP3

backup register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

BKP4

backup register

Offset: 0x60, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

BKP5

backup register

Offset: 0x64, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

BKP6

backup register

Offset: 0x68, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

BKP7

backup register

Offset: 0x6C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

BKP8

backup register

Offset: 0x70, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

BKP9

backup register

Offset: 0x74, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

BKP10

backup register

Offset: 0x78, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

BKP11

backup register

Offset: 0x7C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

BKP12

backup register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

BKP13

backup register

Offset: 0x84, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

BKP14

backup register

Offset: 0x88, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

BKP15

backup register

Offset: 0x8C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

BKP16

backup register

Offset: 0x90, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

BKP17

backup register

Offset: 0x94, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

BKP18

backup register

Offset: 0x98, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

BKP19

backup register

Offset: 0x9C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

SDIO

0x40012C00: Secure digital input/output interface

31/99 fields covered. Toggle Registers.

PWRCTL

Power control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWRCTL
rw
Toggle Fields.

PWRCTL

Bits 0-1: SDIO power control bits.

CLKCTL

Clock control register

Offset: 0x4, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIV_8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HWCLKEN
rw 		CLKEDGE
rw 		BUSMODE
rw 		CLKBYP
rw 		CLKPWRSAV
rw 		CLKEN
rw 		DIV_0_7
rw
Toggle Fields.

DIV_0_7

Bits 0-7: Clock division.

CLKEN

Bit 8: SDIO_CLK clock output enable bit.

CLKPWRSAV

Bit 9: SDIO_CLK clock dynamic switch on/off for power saving.

CLKBYP

Bit 10: Clock bypass enable bit.

BUSMODE

Bits 11-12: SDIO card bus mode control bit.

CLKEDGE

Bit 13: SDIO_CLK clock edge selection bit.

HWCLKEN

Bit 14: Hardware Clock Control enable bit.

DIV_8

Bit 31: MSB of Clock division.

CMDAGMT

Command argument register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDAGMT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDAGMT
rw
Toggle Fields.

CMDAGMT

Bits 0-31: SDIO card command argument.

CMDCTL

Command control register

Offset: 0xC, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATAEN
rw 		NINTEN
rw 		ENCMDC
rw 		SUSPEND
rw 		CSMEN
rw 		WAITDEND
rw 		INTWAIT
rw 		CMDRESP
rw 		CMDIDX
rw
Toggle Fields.

CMDIDX

Bits 0-5: Command index.

CMDRESP

Bits 6-7: Command response type bits.

INTWAIT

Bit 8: Interrupt wait instead of timeout.

WAITDEND

Bit 9: Waits for ends of data transfer.

CSMEN

Bit 10: Command state machine (CSM) enable bit.

SUSPEND

Bit 11: SD I/O suspend command(SD I/O only).

ENCMDC

Bit 12: CMD completion signal enabled (CE-ATA only).

NINTEN

Bit 13: No CE-ATA Interrupt (CE-ATA only).

ATAEN

Bit 14: CE-ATA command enable(CE-ATA only).

RSPCMDIDX

Command index response register

Offset: 0x10, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSPCMDIDX
r
Toggle Fields.

RSPCMDIDX

Bits 0-5: Last response command index.

RESP0

Response register 0

Offset: 0x14, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESP0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESP0
r
Toggle Fields.

RESP0

Bits 0-31: Card state.

RESP1

Response register 1

Offset: 0x18, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESP1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESP1
r
Toggle Fields.

RESP1

Bits 0-31: Card state.

RESP2

Response register 2

Offset: 0x1C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESP2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESP2
r
Toggle Fields.

RESP2

Bits 0-31: Card state.

RESP3

Response register 3

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESP3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESP3
r
Toggle Fields.

RESP3

Bits 0-31: Response register 3.

DATATO

Data timeout register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATATO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATATO
rw
Toggle Fields.

DATATO

Bits 0-31: Data timeout period.

DATALEN

Data length register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATALEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATALEN
rw
Toggle Fields.

DATALEN

Bits 0-24: Data transfer length.

DATACTL

Data control register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOEN
rw 		RWTYPE
rw 		RWSTOP
rw 		RWEN
rw 		BLKSZ
rw 		DMAEN
rw 		TRANSMOD
rw 		DATADIR
rw 		DATAEN
rw
Toggle Fields.

DATAEN

Bit 0: Data transfer enabled bit.

DATADIR

Bit 1: Data transfer direction.

TRANSMOD

Bit 2: Data transfer mode.

DMAEN

Bit 3: DMA enable bit.

BLKSZ

Bits 4-7: Data block size.

RWEN

Bit 8: Read wait mode enabled.

RWSTOP

Bit 9: Read wait stop.

RWTYPE

Bit 10: Read wait type.

IOEN

Bit 11: SD I/O specific function enable.

DATACNT

Data counter register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATACNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATACNT
r
Toggle Fields.

DATACNT

Bits 0-24: Data count value.

STAT

Status register

Offset: 0x34, reset: 0x00000000, access: read-only

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATAEND
r 		SDIOINT
r 		RXDTVAL
r 		TXDTVAL
r 		RFE
r 		TFE
r 		RFF
r 		TFF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFH
r 		TFH
r 		RXRUN
r 		TXRUN
r 		CMDRUN
r 		DTBLKEND
r 		STBITE
r 		DTEND
r 		CMDSEND
r 		CMDRECV
r 		RXORE
r 		TXURE
r 		DTTMOUT
r 		CMDTMOUT
r 		DTCRCERR
r 		CCRCERR
r
Toggle Fields.

CCRCERR

Bit 0: Command response received.

DTCRCERR

Bit 1: Data block sent/received.

CMDTMOUT

Bit 2: Command response timeout.

DTTMOUT

Bit 3: Data timeout.

TXURE

Bit 4: Transmit FIFO underrun error occurs.

RXORE

Bit 5: Received FIFO overrun error occurs.

CMDRECV

Bit 6: Command response received.

CMDSEND

Bit 7: Command sent.

DTEND

Bit 8: Data end.

STBITE

Bit 9: Start bit error in the bus.

DTBLKEND

Bit 10: Data block sent/received.

CMDRUN

Bit 11: Command transmission in progress.

TXRUN

Bit 12: Data transmission in progress.

RXRUN

Bit 13: Data reception in progress.

TFH

Bit 14: Transmit FIFO is half empty.

RFH

Bit 15: Receive FIFO is half full.

TFF

Bit 16: Transmit FIFO is full.

RFF

Bit 17: Receive FIFO is full.

TFE

Bit 18: Transmit FIFO is empty.

RFE

Bit 19: Receive FIFO is empty.

TXDTVAL

Bit 20: Data is valid in transmit FIFO.

RXDTVAL

Bit 21: Data is valid in receive FIFO.

SDIOINT

Bit 22: SD I/O interrupt received.

ATAEND

Bit 23: CE-ATA command completion signal received.

INTC

Interrupt clear register

Offset: 0x38, reset: 0x00000000, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATAENDC
w 		SDIOINTC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTBLKENDC
w 		STBITEC
w 		DTENDC
w 		CMDSENDC
w 		CMDRECVC
w 		RXOREC
w 		TXUREC
w 		DTTMOUTC
w 		CMDTMOUTC
w 		DTCRCERRC
w 		CCRCERRC
w
Toggle Fields.

CCRCERRC

Bit 0: CCRCERR flag clear bit.

DTCRCERRC

Bit 1: DTCRCERR flag clear bit.

CMDTMOUTC

Bit 2: CMDTMOUT flag clear bit.

DTTMOUTC

Bit 3: DTTMOUT flag clear bit.

TXUREC

Bit 4: TXURE flag clear bit.

RXOREC

Bit 5: RXORE flag clear bit.

CMDRECVC

Bit 6: CMDRECV flag clear bit.

CMDSENDC

Bit 7: CMDSEND flag clear bit.

DTENDC

Bit 8: DTEND flag clear bit.

STBITEC

Bit 9: STBITE flag clear bit.

DTBLKENDC

Bit 10: DTBLKEND flag clear bit.

SDIOINTC

Bit 22: SDIOINT flag clear bit.

ATAENDC

Bit 23: ATAEND flag clear bit.

INTEN

Interrupt enable register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATAENDIE
rw 		SDIOINTIE
rw 		RXDTVALIE
rw 		TXDTVALIE
rw 		RFEIE
rw 		TFEIE
rw 		RFFIE
rw 		TFFIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFHIE
rw 		TFHIE
rw 		RXRUNIE
rw 		TXRUNIE
rw 		CMDRUNIE
rw 		DTBLKENDIE
rw 		STBITEIE
rw 		DTENDIE
rw 		CMDSENDIE
rw 		CMDRECVIE
rw 		RXOREIE
rw 		TXUREIE
rw 		DTTMOUTIE
rw 		CMDTMOUTIE
rw 		DTCRCERRIE
rw 		CCRCERRIE
rw
Toggle Fields.

CCRCERRIE

Bit 0: Command response CRC fail interrupt enable.

DTCRCERRIE

Bit 1: Data CRC fail interrupt enable.

CMDTMOUTIE

Bit 2: Command response timeout interrupt enable.

DTTMOUTIE

Bit 3: Data timeout interrupt enable.

TXUREIE

Bit 4: Transmit FIFO underrun error interrupt enable.

RXOREIE

Bit 5: Received FIFO overrun error interrupt enable.

CMDRECVIE

Bit 6: Command response received interrupt enable.

CMDSENDIE

Bit 7: Command sent interrupt enable.

DTENDIE

Bit 8: Data end interrupt enable.

STBITEIE

Bit 9: Start bit error interrupt enable.

DTBLKENDIE

Bit 10: Data block end interrupt enable.

CMDRUNIE

Bit 11: Command transmission interrupt enable.

TXRUNIE

Bit 12: Data transmission interrupt enable.

RXRUNIE

Bit 13: Data reception interrupt enable.

TFHIE

Bit 14: Transmit FIFO half empty interrupt enable.

RFHIE

Bit 15: Receive FIFO half full interrupt enable.

TFFIE

Bit 16: Transmit FIFO full interrupt enable.

RFFIE

Bit 17: Receive FIFO full interrupt enable.

TFEIE

Bit 18: Transmit FIFO empty interrupt enable.

RFEIE

Bit 19: Receive FIFO empty interrupt enable.

TXDTVALIE

Bit 20: Data valid in transmit FIFO interrupt enable.

RXDTVALIE

Bit 21: Data valid in receive FIFO interrupt enable.

SDIOINTIE

Bit 22: SD I/O interrupt received interrupt enable.

ATAENDIE

Bit 23: CE-ATA command completion signal received interrupt enable.

FIFOCNT

FIFO counter register

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCNT
r
Toggle Fields.

FIFOCNT

Bits 0-23: FIFO counter.

FIFO

FIFO data register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODT
rw
Toggle Fields.

FIFODT

Bits 0-31: Receive FIFO data or transmit FIFO data.

SPI0

0x40013000: Serial peripheral interface

9/45 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDEN
rw 		BDOEN
rw 		CRCEN
rw 		CRCNT
rw 		FF16
rw 		RO
rw 		SWNSSEN
rw 		SWNSS
rw 		LF
rw 		SPIEN
rw 		PSC
rw 		MSTMOD
rw 		CKPL
rw 		CKPH
rw
Toggle Fields.

CKPH

Bit 0: Clock Phase Selection.

CKPL

Bit 1: Clock polarity Selection.

MSTMOD

Bit 2: Master Mode Enable.

PSC

Bits 3-5: Master Clock Prescaler Selection.

SPIEN

Bit 6: SPI enable.

LF

Bit 7: LSB First Mode.

SWNSS

Bit 8: NSS Pin Selection In NSS Software Mode.

SWNSSEN

Bit 9: NSS Software Mode Selection.

RO

Bit 10: Receive only.

FF16

Bit 11: Data frame format.

CRCNT

Bit 12: CRC Next Transfer.

CRCEN

Bit 13: CRC Calculation Enable.

BDOEN

Bit 14: Bidirectional Transmit output enable .

BDEN

Bit 15: Bidirectional enable.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBEIE
rw 		RBNEIE
rw 		ERRIE
rw 		TMOD
rw 		NSSDRV
rw 		DMATEN
rw 		DMAREN
rw
Toggle Fields.

DMAREN

Bit 0: Rx buffer DMA enable.

DMATEN

Bit 1: Transmit Buffer DMA Enable.

NSSDRV

Bit 2: Drive NSS Output.

TMOD

Bit 4: SPI TI Mode Enable.

ERRIE

Bit 5: Error interrupt enable.

RBNEIE

Bit 6: RX buffer not empty interrupt enable.

TBEIE

Bit 7: Tx buffer empty interrupt enable.

STAT

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

7/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FERR
rw 		TRANS
r 		RXORERR
r 		CONFERR
r 		CRCERR
rw 		TXURERR
r 		I2SCH
r 		TBE
r 		RBNE
r
Toggle Fields.

RBNE

Bit 0: Receive Buffer Not Empty.

TBE

Bit 1: Transmit Buffer Empty.

I2SCH

Bit 2: I2S channel side.

TXURERR

Bit 3: Transmission underrun error bit.

CRCERR

Bit 4: SPI CRC Error Bit.

CONFERR

Bit 5: SPI Configuration error.

RXORERR

Bit 6: Reception Overrun Error Bit.

TRANS

Bit 7: Transmitting On-going Bit.

FERR

Bit 8: Format Error.

DATA

data register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI_DATA
rw
Toggle Fields.

SPI_DATA

Bits 0-15: Data transfer register.

CPCPOLY

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPR
rw
Toggle Fields.

CPR

Bits 0-15: CRC polynomial register.

RCRC

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCR
r
Toggle Fields.

RCR

Bits 0-15: RX CRC register.

TCRC

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCR
r
Toggle Fields.

TCR

Bits 0-15: Tx CRC register.

I2SCTL

I2S control register

Offset: 0x1C, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SSEL
rw 		I2SEN
rw 		I2SOPMOD
rw 		PCMSMOD
rw 		I2SSTD
rw 		CKPL
rw 		DTLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

DTLEN

Bits 1-2: Data length.

CKPL

Bit 3: Idle state clock polarity.

I2SSTD

Bits 4-5: I2S standard selection.

PCMSMOD

Bit 7: PCM frame synchronization mode.

I2SOPMOD

Bits 8-9: I2S operation mode.

I2SEN

Bit 10: I2S Enable.

I2SSEL

Bit 11: I2S mode selection.

I2SPSC

I2S prescaler register

Offset: 0x20, reset: 0x0002, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOEN
rw 		OF
rw 		DIV
rw
Toggle Fields.

DIV

Bits 0-7: Dividing factor for the prescaler.

OF

Bit 8: Odd factor for the prescaler.

MCKOEN

Bit 9: I2S_MCK output enable.

SPI1

0x40003800: Serial peripheral interface

9/45 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDEN
rw 		BDOEN
rw 		CRCEN
rw 		CRCNT
rw 		FF16
rw 		RO
rw 		SWNSSEN
rw 		SWNSS
rw 		LF
rw 		SPIEN
rw 		PSC
rw 		MSTMOD
rw 		CKPL
rw 		CKPH
rw
Toggle Fields.

CKPH

Bit 0: Clock Phase Selection.

CKPL

Bit 1: Clock polarity Selection.

MSTMOD

Bit 2: Master Mode Enable.

PSC

Bits 3-5: Master Clock Prescaler Selection.

SPIEN

Bit 6: SPI enable.

LF

Bit 7: LSB First Mode.

SWNSS

Bit 8: NSS Pin Selection In NSS Software Mode.

SWNSSEN

Bit 9: NSS Software Mode Selection.

RO

Bit 10: Receive only.

FF16

Bit 11: Data frame format.

CRCNT

Bit 12: CRC Next Transfer.

CRCEN

Bit 13: CRC Calculation Enable.

BDOEN

Bit 14: Bidirectional Transmit output enable .

BDEN

Bit 15: Bidirectional enable.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBEIE
rw 		RBNEIE
rw 		ERRIE
rw 		TMOD
rw 		NSSDRV
rw 		DMATEN
rw 		DMAREN
rw
Toggle Fields.

DMAREN

Bit 0: Rx buffer DMA enable.

DMATEN

Bit 1: Transmit Buffer DMA Enable.

NSSDRV

Bit 2: Drive NSS Output.

TMOD

Bit 4: SPI TI Mode Enable.

ERRIE

Bit 5: Error interrupt enable.

RBNEIE

Bit 6: RX buffer not empty interrupt enable.

TBEIE

Bit 7: Tx buffer empty interrupt enable.

STAT

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

7/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FERR
rw 		TRANS
r 		RXORERR
r 		CONFERR
r 		CRCERR
rw 		TXURERR
r 		I2SCH
r 		TBE
r 		RBNE
r
Toggle Fields.

RBNE

Bit 0: Receive Buffer Not Empty.

TBE

Bit 1: Transmit Buffer Empty.

I2SCH

Bit 2: I2S channel side.

TXURERR

Bit 3: Transmission underrun error bit.

CRCERR

Bit 4: SPI CRC Error Bit.

CONFERR

Bit 5: SPI Configuration error.

RXORERR

Bit 6: Reception Overrun Error Bit.

TRANS

Bit 7: Transmitting On-going Bit.

FERR

Bit 8: Format Error.

DATA

data register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI_DATA
rw
Toggle Fields.

SPI_DATA

Bits 0-15: Data transfer register.

CPCPOLY

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPR
rw
Toggle Fields.

CPR

Bits 0-15: CRC polynomial register.

RCRC

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCR
r
Toggle Fields.

RCR

Bits 0-15: RX CRC register.

TCRC

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCR
r
Toggle Fields.

TCR

Bits 0-15: Tx CRC register.

I2SCTL

I2S control register

Offset: 0x1C, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SSEL
rw 		I2SEN
rw 		I2SOPMOD
rw 		PCMSMOD
rw 		I2SSTD
rw 		CKPL
rw 		DTLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

DTLEN

Bits 1-2: Data length.

CKPL

Bit 3: Idle state clock polarity.

I2SSTD

Bits 4-5: I2S standard selection.

PCMSMOD

Bit 7: PCM frame synchronization mode.

I2SOPMOD

Bits 8-9: I2S operation mode.

I2SEN

Bit 10: I2S Enable.

I2SSEL

Bit 11: I2S mode selection.

I2SPSC

I2S prescaler register

Offset: 0x20, reset: 0x0002, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOEN
rw 		OF
rw 		DIV
rw
Toggle Fields.

DIV

Bits 0-7: Dividing factor for the prescaler.

OF

Bit 8: Odd factor for the prescaler.

MCKOEN

Bit 9: I2S_MCK output enable.

SPI2

0x40003C00: Serial peripheral interface

9/45 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDEN
rw 		BDOEN
rw 		CRCEN
rw 		CRCNT
rw 		FF16
rw 		RO
rw 		SWNSSEN
rw 		SWNSS
rw 		LF
rw 		SPIEN
rw 		PSC
rw 		MSTMOD
rw 		CKPL
rw 		CKPH
rw
Toggle Fields.

CKPH

Bit 0: Clock Phase Selection.

CKPL

Bit 1: Clock polarity Selection.

MSTMOD

Bit 2: Master Mode Enable.

PSC

Bits 3-5: Master Clock Prescaler Selection.

SPIEN

Bit 6: SPI enable.

LF

Bit 7: LSB First Mode.

SWNSS

Bit 8: NSS Pin Selection In NSS Software Mode.

SWNSSEN

Bit 9: NSS Software Mode Selection.

RO

Bit 10: Receive only.

FF16

Bit 11: Data frame format.

CRCNT

Bit 12: CRC Next Transfer.

CRCEN

Bit 13: CRC Calculation Enable.

BDOEN

Bit 14: Bidirectional Transmit output enable .

BDEN

Bit 15: Bidirectional enable.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBEIE
rw 		RBNEIE
rw 		ERRIE
rw 		TMOD
rw 		NSSDRV
rw 		DMATEN
rw 		DMAREN
rw
Toggle Fields.

DMAREN

Bit 0: Rx buffer DMA enable.

DMATEN

Bit 1: Transmit Buffer DMA Enable.

NSSDRV

Bit 2: Drive NSS Output.

TMOD

Bit 4: SPI TI Mode Enable.

ERRIE

Bit 5: Error interrupt enable.

RBNEIE

Bit 6: RX buffer not empty interrupt enable.

TBEIE

Bit 7: Tx buffer empty interrupt enable.

STAT

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

7/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FERR
rw 		TRANS
r 		RXORERR
r 		CONFERR
r 		CRCERR
rw 		TXURERR
r 		I2SCH
r 		TBE
r 		RBNE
r
Toggle Fields.

RBNE

Bit 0: Receive Buffer Not Empty.

TBE

Bit 1: Transmit Buffer Empty.

I2SCH

Bit 2: I2S channel side.

TXURERR

Bit 3: Transmission underrun error bit.

CRCERR

Bit 4: SPI CRC Error Bit.

CONFERR

Bit 5: SPI Configuration error.

RXORERR

Bit 6: Reception Overrun Error Bit.

TRANS

Bit 7: Transmitting On-going Bit.

FERR

Bit 8: Format Error.

DATA

data register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI_DATA
rw
Toggle Fields.

SPI_DATA

Bits 0-15: Data transfer register.

CPCPOLY

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPR
rw
Toggle Fields.

CPR

Bits 0-15: CRC polynomial register.

RCRC

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCR
r
Toggle Fields.

RCR

Bits 0-15: RX CRC register.

TCRC

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCR
r
Toggle Fields.

TCR

Bits 0-15: Tx CRC register.

I2SCTL

I2S control register

Offset: 0x1C, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SSEL
rw 		I2SEN
rw 		I2SOPMOD
rw 		PCMSMOD
rw 		I2SSTD
rw 		CKPL
rw 		DTLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

DTLEN

Bits 1-2: Data length.

CKPL

Bit 3: Idle state clock polarity.

I2SSTD

Bits 4-5: I2S standard selection.

PCMSMOD

Bit 7: PCM frame synchronization mode.

I2SOPMOD

Bits 8-9: I2S operation mode.

I2SEN

Bit 10: I2S Enable.

I2SSEL

Bit 11: I2S mode selection.

I2SPSC

I2S prescaler register

Offset: 0x20, reset: 0x0002, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOEN
rw 		OF
rw 		DIV
rw
Toggle Fields.

DIV

Bits 0-7: Dividing factor for the prescaler.

OF

Bit 8: Odd factor for the prescaler.

MCKOEN

Bit 9: I2S_MCK output enable.

SPI3

0x40013400: Serial peripheral interface

9/45 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDEN
rw 		BDOEN
rw 		CRCEN
rw 		CRCNT
rw 		FF16
rw 		RO
rw 		SWNSSEN
rw 		SWNSS
rw 		LF
rw 		SPIEN
rw 		PSC
rw 		MSTMOD
rw 		CKPL
rw 		CKPH
rw
Toggle Fields.

CKPH

Bit 0: Clock Phase Selection.

CKPL

Bit 1: Clock polarity Selection.

MSTMOD

Bit 2: Master Mode Enable.

PSC

Bits 3-5: Master Clock Prescaler Selection.

SPIEN

Bit 6: SPI enable.

LF

Bit 7: LSB First Mode.

SWNSS

Bit 8: NSS Pin Selection In NSS Software Mode.

SWNSSEN

Bit 9: NSS Software Mode Selection.

RO

Bit 10: Receive only.

FF16

Bit 11: Data frame format.

CRCNT

Bit 12: CRC Next Transfer.

CRCEN

Bit 13: CRC Calculation Enable.

BDOEN

Bit 14: Bidirectional Transmit output enable .

BDEN

Bit 15: Bidirectional enable.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBEIE
rw 		RBNEIE
rw 		ERRIE
rw 		TMOD
rw 		NSSDRV
rw 		DMATEN
rw 		DMAREN
rw
Toggle Fields.

DMAREN

Bit 0: Rx buffer DMA enable.

DMATEN

Bit 1: Transmit Buffer DMA Enable.

NSSDRV

Bit 2: Drive NSS Output.

TMOD

Bit 4: SPI TI Mode Enable.

ERRIE

Bit 5: Error interrupt enable.

RBNEIE

Bit 6: RX buffer not empty interrupt enable.

TBEIE

Bit 7: Tx buffer empty interrupt enable.

STAT

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

7/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FERR
rw 		TRANS
r 		RXORERR
r 		CONFERR
r 		CRCERR
rw 		TXURERR
r 		I2SCH
r 		TBE
r 		RBNE
r
Toggle Fields.

RBNE

Bit 0: Receive Buffer Not Empty.

TBE

Bit 1: Transmit Buffer Empty.

I2SCH

Bit 2: I2S channel side.

TXURERR

Bit 3: Transmission underrun error bit.

CRCERR

Bit 4: SPI CRC Error Bit.

CONFERR

Bit 5: SPI Configuration error.

RXORERR

Bit 6: Reception Overrun Error Bit.

TRANS

Bit 7: Transmitting On-going Bit.

FERR

Bit 8: Format Error.

DATA

data register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI_DATA
rw
Toggle Fields.

SPI_DATA

Bits 0-15: Data transfer register.

CPCPOLY

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPR
rw
Toggle Fields.

CPR

Bits 0-15: CRC polynomial register.

RCRC

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCR
r
Toggle Fields.

RCR

Bits 0-15: RX CRC register.

TCRC

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCR
r
Toggle Fields.

TCR

Bits 0-15: Tx CRC register.

I2SCTL

I2S control register

Offset: 0x1C, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SSEL
rw 		I2SEN
rw 		I2SOPMOD
rw 		PCMSMOD
rw 		I2SSTD
rw 		CKPL
rw 		DTLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

DTLEN

Bits 1-2: Data length.

CKPL

Bit 3: Idle state clock polarity.

I2SSTD

Bits 4-5: I2S standard selection.

PCMSMOD

Bit 7: PCM frame synchronization mode.

I2SOPMOD

Bits 8-9: I2S operation mode.

I2SEN

Bit 10: I2S Enable.

I2SSEL

Bit 11: I2S mode selection.

I2SPSC

I2S prescaler register

Offset: 0x20, reset: 0x0002, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOEN
rw 		OF
rw 		DIV
rw
Toggle Fields.

DIV

Bits 0-7: Dividing factor for the prescaler.

OF

Bit 8: Odd factor for the prescaler.

MCKOEN

Bit 9: I2S_MCK output enable.

SPI4

0x40015000: Serial peripheral interface

9/45 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDEN
rw 		BDOEN
rw 		CRCEN
rw 		CRCNT
rw 		FF16
rw 		RO
rw 		SWNSSEN
rw 		SWNSS
rw 		LF
rw 		SPIEN
rw 		PSC
rw 		MSTMOD
rw 		CKPL
rw 		CKPH
rw
Toggle Fields.

CKPH

Bit 0: Clock Phase Selection.

CKPL

Bit 1: Clock polarity Selection.

MSTMOD

Bit 2: Master Mode Enable.

PSC

Bits 3-5: Master Clock Prescaler Selection.

SPIEN

Bit 6: SPI enable.

LF

Bit 7: LSB First Mode.

SWNSS

Bit 8: NSS Pin Selection In NSS Software Mode.

SWNSSEN

Bit 9: NSS Software Mode Selection.

RO

Bit 10: Receive only.

FF16

Bit 11: Data frame format.

CRCNT

Bit 12: CRC Next Transfer.

CRCEN

Bit 13: CRC Calculation Enable.

BDOEN

Bit 14: Bidirectional Transmit output enable .

BDEN

Bit 15: Bidirectional enable.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBEIE
rw 		RBNEIE
rw 		ERRIE
rw 		TMOD
rw 		NSSDRV
rw 		DMATEN
rw 		DMAREN
rw
Toggle Fields.

DMAREN

Bit 0: Rx buffer DMA enable.

DMATEN

Bit 1: Transmit Buffer DMA Enable.

NSSDRV

Bit 2: Drive NSS Output.

TMOD

Bit 4: SPI TI Mode Enable.

ERRIE

Bit 5: Error interrupt enable.

RBNEIE

Bit 6: RX buffer not empty interrupt enable.

TBEIE

Bit 7: Tx buffer empty interrupt enable.

STAT

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

7/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FERR
rw 		TRANS
r 		RXORERR
r 		CONFERR
r 		CRCERR
rw 		TXURERR
r 		I2SCH
r 		TBE
r 		RBNE
r
Toggle Fields.

RBNE

Bit 0: Receive Buffer Not Empty.

TBE

Bit 1: Transmit Buffer Empty.

I2SCH

Bit 2: I2S channel side.

TXURERR

Bit 3: Transmission underrun error bit.

CRCERR

Bit 4: SPI CRC Error Bit.

CONFERR

Bit 5: SPI Configuration error.

RXORERR

Bit 6: Reception Overrun Error Bit.

TRANS

Bit 7: Transmitting On-going Bit.

FERR

Bit 8: Format Error.

DATA

data register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI_DATA
rw
Toggle Fields.

SPI_DATA

Bits 0-15: Data transfer register.

CPCPOLY

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPR
rw
Toggle Fields.

CPR

Bits 0-15: CRC polynomial register.

RCRC

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCR
r
Toggle Fields.

RCR

Bits 0-15: RX CRC register.

TCRC

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCR
r
Toggle Fields.

TCR

Bits 0-15: Tx CRC register.

I2SCTL

I2S control register

Offset: 0x1C, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SSEL
rw 		I2SEN
rw 		I2SOPMOD
rw 		PCMSMOD
rw 		I2SSTD
rw 		CKPL
rw 		DTLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

DTLEN

Bits 1-2: Data length.

CKPL

Bit 3: Idle state clock polarity.

I2SSTD

Bits 4-5: I2S standard selection.

PCMSMOD

Bit 7: PCM frame synchronization mode.

I2SOPMOD

Bits 8-9: I2S operation mode.

I2SEN

Bit 10: I2S Enable.

I2SSEL

Bit 11: I2S mode selection.

I2SPSC

I2S prescaler register

Offset: 0x20, reset: 0x0002, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOEN
rw 		OF
rw 		DIV
rw
Toggle Fields.

DIV

Bits 0-7: Dividing factor for the prescaler.

OF

Bit 8: Odd factor for the prescaler.

MCKOEN

Bit 9: I2S_MCK output enable.

SPI5

0x40015400: Serial peripheral interface

9/48 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BDEN
rw 		BDOEN
rw 		CRCEN
rw 		CRCNT
rw 		FF16
rw 		RO
rw 		SWNSSEN
rw 		SWNSS
rw 		LF
rw 		SPIEN
rw 		PSC
rw 		MSTMOD
rw 		CKPL
rw 		CKPH
rw
Toggle Fields.

CKPH

Bit 0: Clock Phase Selection.

CKPL

Bit 1: Clock polarity Selection.

MSTMOD

Bit 2: Master Mode Enable.

PSC

Bits 3-5: Master Clock Prescaler Selection.

SPIEN

Bit 6: SPI enable.

LF

Bit 7: LSB First Mode.

SWNSS

Bit 8: NSS Pin Selection In NSS Software Mode.

SWNSSEN

Bit 9: NSS Software Mode Selection.

RO

Bit 10: Receive only.

FF16

Bit 11: Data frame format.

CRCNT

Bit 12: CRC Next Transfer.

CRCEN

Bit 13: CRC Calculation Enable.

BDOEN

Bit 14: Bidirectional Transmit output enable .

BDEN

Bit 15: Bidirectional enable.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBEIE
rw 		RBNEIE
rw 		ERRIE
rw 		TMOD
rw 		NSSDRV
rw 		DMATEN
rw 		DMAREN
rw
Toggle Fields.

DMAREN

Bit 0: Rx buffer DMA enable.

DMATEN

Bit 1: Transmit Buffer DMA Enable.

NSSDRV

Bit 2: Drive NSS Output.

TMOD

Bit 4: SPI TI Mode Enable.

ERRIE

Bit 5: Error interrupt enable.

RBNEIE

Bit 6: RX buffer not empty interrupt enable.

TBEIE

Bit 7: Tx buffer empty interrupt enable.

STAT

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

7/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FERR
rw 		TRANS
r 		RXORERR
r 		CONFERR
r 		CRCERR
rw 		TXURERR
r 		I2SCH
r 		TBE
r 		RBNE
r
Toggle Fields.

RBNE

Bit 0: Receive Buffer Not Empty.

TBE

Bit 1: Transmit Buffer Empty.

I2SCH

Bit 2: I2S channel side.

TXURERR

Bit 3: Transmission underrun error bit.

CRCERR

Bit 4: SPI CRC Error Bit.

CONFERR

Bit 5: SPI Configuration error.

RXORERR

Bit 6: Reception Overrun Error Bit.

TRANS

Bit 7: Transmitting On-going Bit.

FERR

Bit 8: Format Error.

DATA

data register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI_DATA
rw
Toggle Fields.

SPI_DATA

Bits 0-15: Data transfer register.

CPCPOLY

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPR
rw
Toggle Fields.

CPR

Bits 0-15: CRC polynomial register.

RCRC

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCR
r
Toggle Fields.

RCR

Bits 0-15: RX CRC register.

TCRC

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCR
r
Toggle Fields.

TCR

Bits 0-15: Tx CRC register.

I2SCTL

I2S control register

Offset: 0x1C, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SSEL
rw 		I2SEN
rw 		I2SOPMOD
rw 		PCMSMOD
rw 		I2SSTD
rw 		CKPL
rw 		DTLEN
rw 		CHLEN
rw
Toggle Fields.

CHLEN

Bit 0: Channel length (number of bits per audio channel).

DTLEN

Bits 1-2: Data length to be transferred.

CKPL

Bit 3: Idle state clock polarity.

I2SSTD

Bits 4-5: I2S standard selection.

PCMSMOD

Bit 7: PCM frame synchronization mode.

I2SOPMOD

Bits 8-9: I2S operation mode.

I2SEN

Bit 10: I2S Enable.

I2SSEL

Bit 11: I2S mode selection.

I2SPSC

I2S prescaler register

Offset: 0x20, reset: 0x0002, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKOEN
rw 		OF
rw 		DIV
rw
Toggle Fields.

DIV

Bits 0-7: Dividing factor for the prescaler.

OF

Bit 8: Odd factor for the prescaler.

MCKOEN

Bit 9: I2S_MCK output enable.

QCTL

Quad-SPI mode control register

Offset: 0x80, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IO23_DRV
rw 		QRD
rw 		QMOD
rw
Toggle Fields.

QMOD

Bit 0: Quad-SPI mode enable.

QRD

Bit 1: Quad-SPI mode read select.

IO23_DRV

Bit 2: Drive IO2 and IO3 enable.

SYSCFG

0x40013800: System configuration controller

0/22 fields covered. Toggle Registers.

CFG0

Configuration register 0

Offset: 0x0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMC_SWP
rw 		FMC_SWP
rw 		BOOT_MODE
rw
Toggle Fields.

BOOT_MODE

Bits 0-2: Boot mode.

FMC_SWP

Bit 8: FMC memory mapping swap .

EXMC_SWP

Bits 10-11: EXMC memory mapping swap.

CFG1

Configuration register 1

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENET_PHY_SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

ENET_PHY_SEL

Bit 23: Ethernet PHY selection.

EXTISS0

EXTI sources selection register 0

Offset: 0x8, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3_SS
rw 		EXTI2_SS
rw 		EXTI1_SS
rw 		EXTI0_SS
rw
Toggle Fields.

EXTI0_SS

Bits 0-3: EXTI 0 sources selection.

EXTI1_SS

Bits 4-7: EXTI 1 sources selection.

EXTI2_SS

Bits 8-11: EXTI 2 sources selection.

EXTI3_SS

Bits 12-15: EXTI 3 sources selection.

EXTISS1

EXTI sources selection register 1

Offset: 0xC, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7_SS
rw 		EXTI6_SS
rw 		EXTI5_SS
rw 		EXTI4_SS
rw
Toggle Fields.

EXTI4_SS

Bits 0-3: EXTI 4 sources selection.

EXTI5_SS

Bits 4-7: EXTI 5 sources selection.

EXTI6_SS

Bits 8-11: EXTI 6 sources selection.

EXTI7_SS

Bits 12-15: EXTI 7 sources selection.

EXTISS2

EXTI sources selection register 2

Offset: 0x10, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11_SS
rw 		EXTI10_SS
rw 		EXTI9_SS
rw 		EXTI8_SS
rw
Toggle Fields.

EXTI8_SS

Bits 0-3: EXTI 8 sources selection.

EXTI9_SS

Bits 4-7: EXTI 9 sources selection.

EXTI10_SS

Bits 8-11: EXTI 10 sources selection.

EXTI11_SS

Bits 12-15: EXTI 11 sources selection.

EXTISS3

EXTI sources selection register 3

Offset: 0x14, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15_SS
rw 		EXTI14_SS
rw 		EXTI13_SS
rw 		EXTI12_SS
rw
Toggle Fields.

EXTI12_SS

Bits 0-3: EXTI 12 sources selection.

EXTI13_SS

Bits 4-7: EXTI 13 sources selection.

EXTI14_SS

Bits 8-11: EXTI 14 sources selection.

EXTI15_SS

Bits 12-15: EXTI 15 sources selection.

CPSCTL

I/O compensation control register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPS_RDY
rw 		CPS_EN
rw
Toggle Fields.

CPS_EN

Bit 0: I/O compensation cell enable.

CPS_RDY

Bit 8: I/O compensation cell is ready or not.

TIMER0

0x40010000: Advanced-timers

0/129 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

SPM

Bit 3: Single pulse mode.

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISO3
rw 		ISO2N
rw 		ISO2
rw 		ISO1N
rw 		ISO1
rw 		ISO0N
rw 		ISO0
rw 		TI0S
rw 		MMC
rw 		DMAS
rw 		CCUC
rw 		CCSE
rw
Toggle Fields.

CCSE

Bit 0: Commutation control shadow enable.

CCUC

Bit 2: Commutation control shadow register update control.

DMAS

Bit 3: DMA request source selection.

MMC

Bits 4-6: Master mode control.

TI0S

Bit 7: Channel 0 trigger input selection.

ISO0

Bit 8: Idle state of channel 0 output.

ISO0N

Bit 9: Idle state of channel 0 complementary output.

ISO1

Bit 10: Idle state of channel 1 output.

ISO1N

Bit 11: Idle state of channel 1 complementary output.

ISO2

Bit 12: Idle state of channel 2 output.

ISO2N

Bit 13: Idle state of channel 2 complementary output.

ISO3

Bit 14: Idle state of channel 3 output.

SMCFG

slave mode configuration register

Offset: 0x8, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SCM1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode selection.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETFC

Bits 8-11: External trigger filter control.

ETPSC

Bits 12-13: External trigger prescaler.

SCM1

Bit 14: Part of SMC for enable External clock mode1.

ETP

Bit 15: External trigger polarity.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CMTDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		BRKIE
rw 		TRGIE
rw 		CMTIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

CMTIE

Bit 5: commutation interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

BRKIE

Bit 7: Break interrupt enable.

UPDEN

Bit 8: Update DMA request enable.

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

CMTDEN

Bit 13: Commutation DMA request enable.

TRGDEN

Bit 14: Trigger DMA request enable.

INTF

Interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		BRKIF
rw 		TRGIF
rw 		CMTIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

CH2IF

Bit 3: Channel 2 capture/compare interrupt flag.

CH3IF

Bit 4: Channel 3 capture/compare interrupt flag.

CMTIF

Bit 5: Channel commutation interrupt flag.

TRGIF

Bit 6: Trigger interrupt flag.

BRKIF

Bit 7: Break interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

CH2OF

Bit 11: Channel 2 over capture flag.

CH3OF

Bit 12: Channel 3 over capture flag.

SWEVG

Software event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRKG
w 		TRGG
w 		CMTG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update event generation.

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

CH2G

Bit 3: Channel 2 capture or compare event generation.

CH3G

Bit 4: Channel 3 capture or compare event generation.

CMTG

Bit 5: Channel commutation event generation.

TRGG

Bit 6: Trigger event generation.

BRKG

Bit 7: Break event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

CH3MS

Bits 8-9: Channel 3 mode selection.

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2NEN
rw 		CH2P
rw 		CH2EN
rw 		CH1NP
rw 		CH1NEN
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0NEN
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH0NEN

Bit 2: Channel 0 complementary output enable.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CH1NEN

Bit 6: Channel 1 complementary output enable.

CH1NP

Bit 7: Channel 1 complementary output polarity.

CH2EN

Bit 8: Channel 2 capture/compare function enable.

CH2P

Bit 9: Channel 2 capture/compare function polarity.

CH2NEN

Bit 10: Channel 2 complementary output enable.

CH2NP

Bit 11: Channel 2 complementary output polarity.

CH3EN

Bit 12: Channel 3 capture/compare function enable.

CH3P

Bit 13: Channel 3 capture/compare function polarity.

CNT

counter

Offset: 0x24, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

CREP

Counter repetition register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CREP
rw
Toggle Fields.

CREP

Bits 0-7: Counter repetition value.

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel0.

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: Capture or compare value of channel 2.

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: Capture or compare value of channel 3.

CCHP

channel complementary protection register

Offset: 0x44, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POEN
rw 		OAEN
rw 		BRKP
rw 		BRKEN
rw 		ROS
rw 		IOS
rw 		PROT
rw 		DTCFG
rw
Toggle Fields.

DTCFG

Bits 0-7: Dead time configure.

PROT

Bits 8-9: Complementary register protect control.

IOS

Bit 10: Idle mode off-state configure.

ROS

Bit 11: Run mode off-state configure.

BRKEN

Bit 12: Break enable.

BRKP

Bit 13: Break polarity.

OAEN

Bit 14: Output automatic enable.

POEN

Bit 15: Primary output enable.

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

DMATC

Bits 8-12: DMA transfer count.

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

CFG

Configuration register

Offset: 0xFC, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw 		OUTSEL
rw
Toggle Fields.

OUTSEL

Bit 0: The output value selection.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER1

0x40000000: General-purpose-timers

0/102 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

SPM

Bit 3: Single pulse mode.

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI0S
rw 		MMC
rw 		DMAS
rw
Toggle Fields.

DMAS

Bit 3: DMA request source selection.

MMC

Bits 4-6: Master mode control.

TI0S

Bit 7: Channel 0 trigger input selection.

SMCFG

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master-slave mode.

ETFC

Bits 8-11: External trigger filter control.

ETPSC

Bits 12-13: External trigger prescaler.

SMC1

Bit 14: Part of SMC for enable External clock mode1.

ETP

Bit 15: External trigger polarity.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		TRGIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

UPDEN

Bit 8: Update DMA request enable.

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

TRGDEN

Bit 14: Trigger DMA request enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

CH2IF

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IF

Bit 4: Channel 3 capture/compare interrupt enable.

TRGIF

Bit 6: Trigger interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

CH2OF

Bit 11: Channel 2 over capture flag.

CH3OF

Bit 12: Channel 3 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

CH2G

Bit 3: Channel 2 capture or compare event generation.

CH3G

Bit 4: Channel 3 capture or compare event generation.

TRGG

Bit 6: Trigger event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

CH3MS

Bits 8-9: Channel 3 mode selection.

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2P
rw 		CH2EN
rw 		CH1NP
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CH1NP

Bit 7: Channel 1 complementary output polarity.

CH2EN

Bit 8: Channel 2 capture/compare function enable.

CH2P

Bit 9: Channel 2 capture/compare function polarity.

CH2NP

Bit 11: Channel 2 complementary output polarity.

CH3EN

Bit 12: Channel 3 capture/compare function enable.

CH3P

Bit 13: Channel 3 capture/compare function polarity.

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-31: counter value.

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARL
rw
Toggle Fields.

CARL

Bits 0-31: Counter auto reload value.

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH0VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-31: Capture or compare value of channel 0.

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-31: Capture or compare value of channel1.

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH2VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-31: Capture or compare value of channel 2.

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH3VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-31: Capture or compare value of channel 3.

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

DMATC

Bits 8-12: DMA transfer count.

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

IRMP

Input remap register

Offset: 0x50, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITI1_RMP
rw 		CI3_RMP
rw
Toggle Fields.

CI3_RMP

Bits 6-7: Channel 3 input remap.

ITI1_RMP

Bits 10-11: Internal trigger input1 remap.

CFG

Configuration

Offset: 0xFC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER10

0x40014800: General-purpose-timers

0/28 fields covered. Toggle Registers.

CTL0

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

ARSE

Bit 7: Auto-reload shadow enable.

CKDIV

Bits 8-9: Clock division.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0OF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

CH0G

Bit 1: Channel 0 capture or compare event generation.

CHCTL0_Input

Channel control register 0 ( (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CNT

Counter register

Offset: 0x24, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARL
rw
Toggle Fields.

CARL

Bits 0-15: Counter auto reload value.

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

IRMP

channel input remap register

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITI1_RMP
rw
Toggle Fields.

ITI1_RMP

Bits 10-11: Internal trigger input1 remap.

CFG

configuration register

Offset: 0xFC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER11

0x40001800: General-purpose-timers

0/49 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

SPM

Bit 3: Single pulse mode.

ARSE

Bit 7: Auto-reload shadow enable.

CKDIV

Bits 8-9: Clock division.

SMCFG

slave mode configuration register

Offset: 0x8, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master-slave mode.

DMAINTEN

DMA and interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGIE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

TRGIF

Bit 6: Trigger interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

TRGG

Bit 6: Trigger event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1NP
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CH1NP

Bit 7: Channel 1 complementary output polarity.

CNT

Counter register

Offset: 0x24, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARL
rw
Toggle Fields.

CARL

Bits 0-15: Counter auto reload value.

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel0.

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

CFG

configuration register

Offset: 0xFC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER12

0x40001C00: General-purpose-timers

0/28 fields covered. Toggle Registers.

CTL0

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

ARSE

Bit 7: Auto-reload shadow enable.

CKDIV

Bits 8-9: Clock division.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0OF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

CH0G

Bit 1: Channel 0 capture or compare event generation.

CHCTL0_Input

Channel control register 0 ( (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CNT

Counter register

Offset: 0x24, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARL
rw
Toggle Fields.

CARL

Bits 0-15: Counter auto reload value.

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

IRMP

channel input remap register

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITI1_RMP
rw
Toggle Fields.

ITI1_RMP

Bits 10-11: Internal trigger input1 remap.

CFG

configuration register

Offset: 0xFC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER13

0x40002000: General-purpose-timers

0/28 fields covered. Toggle Registers.

CTL0

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

ARSE

Bit 7: Auto-reload shadow enable.

CKDIV

Bits 8-9: Clock division.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0OF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

CH0G

Bit 1: Channel 0 capture or compare event generation.

CHCTL0_Input

Channel control register 0 ( (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CNT

Counter register

Offset: 0x24, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARL
rw
Toggle Fields.

CARL

Bits 0-15: Counter auto reload value.

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

IRMP

channel input remap register

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITI1_RMP
rw
Toggle Fields.

ITI1_RMP

Bits 10-11: Internal trigger input1 remap.

CFG

configuration register

Offset: 0xFC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER2

0x40000400: General-purpose-timers

0/102 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

SPM

Bit 3: Single pulse mode.

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI0S
rw 		MMC
rw 		DMAS
rw
Toggle Fields.

DMAS

Bit 3: DMA request source selection.

MMC

Bits 4-6: Master mode control.

TI0S

Bit 7: Channel 0 trigger input selection.

SMCFG

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master-slave mode.

ETFC

Bits 8-11: External trigger filter control.

ETPSC

Bits 12-13: External trigger prescaler.

SMC1

Bit 14: Part of SMC for enable External clock mode1.

ETP

Bit 15: External trigger polarity.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		TRGIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

UPDEN

Bit 8: Update DMA request enable.

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

TRGDEN

Bit 14: Trigger DMA request enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

CH2IF

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IF

Bit 4: Channel 3 capture/compare interrupt enable.

TRGIF

Bit 6: Trigger interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

CH2OF

Bit 11: Channel 2 over capture flag.

CH3OF

Bit 12: Channel 3 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

CH2G

Bit 3: Channel 2 capture or compare event generation.

CH3G

Bit 4: Channel 3 capture or compare event generation.

TRGG

Bit 6: Trigger event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

CH3MS

Bits 8-9: Channel 3 mode selection.

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2P
rw 		CH2EN
rw 		CH1NP
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CH1NP

Bit 7: Channel 1 complementary output polarity.

CH2EN

Bit 8: Channel 2 capture/compare function enable.

CH2P

Bit 9: Channel 2 capture/compare function polarity.

CH2NP

Bit 11: Channel 2 complementary output polarity.

CH3EN

Bit 12: Channel 3 capture/compare function enable.

CH3P

Bit 13: Channel 3 capture/compare function polarity.

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-31: counter value.

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARL
rw
Toggle Fields.

CARL

Bits 0-31: Counter auto reload value.

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH0VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-31: Capture or compare value of channel 0.

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-31: Capture or compare value of channel1.

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH2VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-31: Capture or compare value of channel 2.

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH3VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-31: Capture or compare value of channel 3.

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

DMATC

Bits 8-12: DMA transfer count.

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

IRMP

Input remap register

Offset: 0x50, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITI1_RMP
rw 		CI3_RMP
rw
Toggle Fields.

CI3_RMP

Bits 6-7: Channel 3 input remap.

ITI1_RMP

Bits 10-11: Internal trigger input1 remap.

CFG

Configuration

Offset: 0xFC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER3

0x40000800: General-purpose-timers

0/102 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

SPM

Bit 3: Single pulse mode.

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI0S
rw 		MMC
rw 		DMAS
rw
Toggle Fields.

DMAS

Bit 3: DMA request source selection.

MMC

Bits 4-6: Master mode control.

TI0S

Bit 7: Channel 0 trigger input selection.

SMCFG

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master-slave mode.

ETFC

Bits 8-11: External trigger filter control.

ETPSC

Bits 12-13: External trigger prescaler.

SMC1

Bit 14: Part of SMC for enable External clock mode1.

ETP

Bit 15: External trigger polarity.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		TRGIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

UPDEN

Bit 8: Update DMA request enable.

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

TRGDEN

Bit 14: Trigger DMA request enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

CH2IF

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IF

Bit 4: Channel 3 capture/compare interrupt enable.

TRGIF

Bit 6: Trigger interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

CH2OF

Bit 11: Channel 2 over capture flag.

CH3OF

Bit 12: Channel 3 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

CH2G

Bit 3: Channel 2 capture or compare event generation.

CH3G

Bit 4: Channel 3 capture or compare event generation.

TRGG

Bit 6: Trigger event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

CH3MS

Bits 8-9: Channel 3 mode selection.

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2P
rw 		CH2EN
rw 		CH1NP
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CH1NP

Bit 7: Channel 1 complementary output polarity.

CH2EN

Bit 8: Channel 2 capture/compare function enable.

CH2P

Bit 9: Channel 2 capture/compare function polarity.

CH2NP

Bit 11: Channel 2 complementary output polarity.

CH3EN

Bit 12: Channel 3 capture/compare function enable.

CH3P

Bit 13: Channel 3 capture/compare function polarity.

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-31: counter value.

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARL
rw
Toggle Fields.

CARL

Bits 0-31: Counter auto reload value.

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH0VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-31: Capture or compare value of channel 0.

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-31: Capture or compare value of channel1.

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH2VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-31: Capture or compare value of channel 2.

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH3VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-31: Capture or compare value of channel 3.

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

DMATC

Bits 8-12: DMA transfer count.

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

IRMP

Input remap register

Offset: 0x50, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITI1_RMP
rw 		CI3_RMP
rw
Toggle Fields.

CI3_RMP

Bits 6-7: Channel 3 input remap.

ITI1_RMP

Bits 10-11: Internal trigger input1 remap.

CFG

Configuration

Offset: 0xFC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER4

0x40000C00: General-purpose-timers

0/102 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

SPM

Bit 3: Single pulse mode.

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI0S
rw 		MMC
rw 		DMAS
rw
Toggle Fields.

DMAS

Bit 3: DMA request source selection.

MMC

Bits 4-6: Master mode control.

TI0S

Bit 7: Channel 0 trigger input selection.

SMCFG

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SMC1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master-slave mode.

ETFC

Bits 8-11: External trigger filter control.

ETPSC

Bits 12-13: External trigger prescaler.

SMC1

Bit 14: Part of SMC for enable External clock mode1.

ETP

Bit 15: External trigger polarity.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		TRGIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

UPDEN

Bit 8: Update DMA request enable.

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

TRGDEN

Bit 14: Trigger DMA request enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

CH2IF

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IF

Bit 4: Channel 3 capture/compare interrupt enable.

TRGIF

Bit 6: Trigger interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

CH2OF

Bit 11: Channel 2 over capture flag.

CH3OF

Bit 12: Channel 3 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

CH2G

Bit 3: Channel 2 capture or compare event generation.

CH3G

Bit 4: Channel 3 capture or compare event generation.

TRGG

Bit 6: Trigger event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

CH3MS

Bits 8-9: Channel 3 mode selection.

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2P
rw 		CH2EN
rw 		CH1NP
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CH1NP

Bit 7: Channel 1 complementary output polarity.

CH2EN

Bit 8: Channel 2 capture/compare function enable.

CH2P

Bit 9: Channel 2 capture/compare function polarity.

CH2NP

Bit 11: Channel 2 complementary output polarity.

CH3EN

Bit 12: Channel 3 capture/compare function enable.

CH3P

Bit 13: Channel 3 capture/compare function polarity.

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-31: counter value.

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARL
rw
Toggle Fields.

CARL

Bits 0-31: Counter auto reload value.

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH0VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-31: Capture or compare value of channel 0.

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH1VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-31: Capture or compare value of channel1.

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH2VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-31: Capture or compare value of channel 2.

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH3VAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-31: Capture or compare value of channel 3.

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

DMATC

Bits 8-12: DMA transfer count.

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

IRMP

Input remap register

Offset: 0x50, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITI1_RMP
rw 		CI3_RMP
rw
Toggle Fields.

CI3_RMP

Bits 6-7: Channel 3 input remap.

ITI1_RMP

Bits 10-11: Internal trigger input1 remap.

CFG

Configuration

Offset: 0xFC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER5

0x40001000: Basic-timers

0/13 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARSE
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

SPM

Bit 3: Single pulse mode.

ARSE

Bit 7: Auto-reload shadow enable.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMC
rw
Toggle Fields.

MMC

Bits 4-6: Master mode control.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPDEN
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

UPDEN

Bit 8: Update DMA request enable.

INTF

Interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Low counter value.

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

TIMER6

0x40001400: Basic-timers

0/13 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARSE
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

SPM

Bit 3: Single pulse mode.

ARSE

Bit 7: Auto-reload shadow enable.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMC
rw
Toggle Fields.

MMC

Bits 4-6: Master mode control.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPDEN
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

UPDEN

Bit 8: Update DMA request enable.

INTF

Interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

CNT

Counter register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Low counter value.

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

TIMER7

0x40010400: Advanced-timers

0/129 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		CAM
rw 		DIR
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

SPM

Bit 3: Single pulse mode.

DIR

Bit 4: Direction.

CAM

Bits 5-6: Counter aligns mode selection.

ARSE

Bit 7: Auto-reload shadow enable.

CKDIV

Bits 8-9: Clock division.

CTL1

control register 1

Offset: 0x4, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISO3
rw 		ISO2N
rw 		ISO2
rw 		ISO1N
rw 		ISO1
rw 		ISO0N
rw 		ISO0
rw 		TI0S
rw 		MMC
rw 		DMAS
rw 		CCUC
rw 		CCSE
rw
Toggle Fields.

CCSE

Bit 0: Commutation control shadow enable.

CCUC

Bit 2: Commutation control shadow register update control.

DMAS

Bit 3: DMA request source selection.

MMC

Bits 4-6: Master mode control.

TI0S

Bit 7: Channel 0 trigger input selection.

ISO0

Bit 8: Idle state of channel 0 output.

ISO0N

Bit 9: Idle state of channel 0 complementary output.

ISO1

Bit 10: Idle state of channel 1 output.

ISO1N

Bit 11: Idle state of channel 1 complementary output.

ISO2

Bit 12: Idle state of channel 2 output.

ISO2N

Bit 13: Idle state of channel 2 complementary output.

ISO3

Bit 14: Idle state of channel 3 output.

SMCFG

slave mode configuration register

Offset: 0x8, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		SCM1
rw 		ETPSC
rw 		ETFC
rw 		MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode selection.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETFC

Bits 8-11: External trigger filter control.

ETPSC

Bits 12-13: External trigger prescaler.

SCM1

Bit 14: Part of SMC for enable External clock mode1.

ETP

Bit 15: External trigger polarity.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGDEN
rw 		CMTDEN
rw 		CH3DEN
rw 		CH2DEN
rw 		CH1DEN
rw 		CH0DEN
rw 		UPDEN
rw 		BRKIE
rw 		TRGIE
rw 		CMTIE
rw 		CH3IE
rw 		CH2IE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

CH2IE

Bit 3: Channel 2 capture/compare interrupt enable.

CH3IE

Bit 4: Channel 3 capture/compare interrupt enable.

CMTIE

Bit 5: commutation interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

BRKIE

Bit 7: Break interrupt enable.

UPDEN

Bit 8: Update DMA request enable.

CH0DEN

Bit 9: Channel 0 capture/compare DMA request enable.

CH1DEN

Bit 10: Channel 1 capture/compare DMA request enable.

CH2DEN

Bit 11: Channel 2 capture/compare DMA request enable.

CH3DEN

Bit 12: Channel 3 capture/compare DMA request enable.

CMTDEN

Bit 13: Commutation DMA request enable.

TRGDEN

Bit 14: Trigger DMA request enable.

INTF

Interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3OF
rw 		CH2OF
rw 		CH1OF
rw 		CH0OF
rw 		BRKIF
rw 		TRGIF
rw 		CMTIF
rw 		CH3IF
rw 		CH2IF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

CH2IF

Bit 3: Channel 2 capture/compare interrupt flag.

CH3IF

Bit 4: Channel 3 capture/compare interrupt flag.

CMTIF

Bit 5: Channel commutation interrupt flag.

TRGIF

Bit 6: Trigger interrupt flag.

BRKIF

Bit 7: Break interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

CH2OF

Bit 11: Channel 2 over capture flag.

CH3OF

Bit 12: Channel 3 over capture flag.

SWEVG

Software event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRKG
w 		TRGG
w 		CMTG
w 		CH3G
w 		CH2G
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update event generation.

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

CH2G

Bit 3: Channel 2 capture or compare event generation.

CH3G

Bit 4: Channel 3 capture or compare event generation.

CMTG

Bit 5: Channel commutation event generation.

TRGG

Bit 6: Trigger event generation.

BRKG

Bit 7: Break event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL1_Input

Channel control register 1 (input mode)

Offset: 0x1C, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3CAPFLT
rw 		CH3CAPPSC
rw 		CH3MS
rw 		CH2CAPFLT
rw 		CH2CAPPSC
rw 		CH2MS
rw
Toggle Fields.

CH2MS

Bits 0-1: Channel 2 mode selection.

CH2CAPPSC

Bits 2-3: Channel 2 input capture prescaler.

CH2CAPFLT

Bits 4-7: Channel 2 input capture filter control.

CH3MS

Bits 8-9: Channel 3 mode selection.

CH3CAPPSC

Bits 10-11: Channel 3 input capture prescaler.

CH3CAPFLT

Bits 12-15: Channel 3 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3P
rw 		CH3EN
rw 		CH2NP
rw 		CH2NEN
rw 		CH2P
rw 		CH2EN
rw 		CH1NP
rw 		CH1NEN
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0NEN
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH0NEN

Bit 2: Channel 0 complementary output enable.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CH1NEN

Bit 6: Channel 1 complementary output enable.

CH1NP

Bit 7: Channel 1 complementary output polarity.

CH2EN

Bit 8: Channel 2 capture/compare function enable.

CH2P

Bit 9: Channel 2 capture/compare function polarity.

CH2NEN

Bit 10: Channel 2 complementary output enable.

CH2NP

Bit 11: Channel 2 complementary output polarity.

CH3EN

Bit 12: Channel 3 capture/compare function enable.

CH3P

Bit 13: Channel 3 capture/compare function polarity.

CNT

counter

Offset: 0x24, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAR
rw
Toggle Fields.

CAR

Bits 0-15: Counter auto reload value.

CREP

Counter repetition register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CREP
rw
Toggle Fields.

CREP

Bits 0-7: Counter repetition value.

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel0.

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

CH2CV

Channel 2 capture/compare value register

Offset: 0x3C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH2VAL
rw
Toggle Fields.

CH2VAL

Bits 0-15: Capture or compare value of channel 2.

CH3CV

Channel 3 capture/compare value register

Offset: 0x40, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH3VAL
rw
Toggle Fields.

CH3VAL

Bits 0-15: Capture or compare value of channel 3.

CCHP

channel complementary protection register

Offset: 0x44, reset: 0x0000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POEN
rw 		OAEN
rw 		BRKP
rw 		BRKEN
rw 		ROS
rw 		IOS
rw 		PROT
rw 		DTCFG
rw
Toggle Fields.

DTCFG

Bits 0-7: Dead time configure.

PROT

Bits 8-9: Complementary register protect control.

IOS

Bit 10: Idle mode off-state configure.

ROS

Bit 11: Run mode off-state configure.

BRKEN

Bit 12: Break enable.

BRKP

Bit 13: Break polarity.

OAEN

Bit 14: Output automatic enable.

POEN

Bit 15: Primary output enable.

DMACFG

DMA configuration register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATC
rw 		DMATA
rw
Toggle Fields.

DMATA

Bits 0-4: DMA transfer access start address.

DMATC

Bits 8-12: DMA transfer count.

DMATB

DMA transfer buffer register

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMATB
rw
Toggle Fields.

DMATB

Bits 0-15: DMA transfer buffer.

CFG

Configuration register

Offset: 0xFC, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw 		OUTSEL
rw
Toggle Fields.

OUTSEL

Bit 0: The output value selection.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER8

0x40014000: General-purpose-timers

0/49 fields covered. Toggle Registers.

CTL0

control register 0

Offset: 0x0, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		SPM
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

SPM

Bit 3: Single pulse mode.

ARSE

Bit 7: Auto-reload shadow enable.

CKDIV

Bits 8-9: Clock division.

SMCFG

slave mode configuration register

Offset: 0x8, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw 		TRGS
rw 		SMC
rw
Toggle Fields.

SMC

Bits 0-2: Slave mode control.

TRGS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master-slave mode.

DMAINTEN

DMA and interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGIE
rw 		CH1IE
rw 		CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

CH1IE

Bit 2: Channel 1 capture/compare interrupt enable.

TRGIE

Bit 6: Trigger interrupt enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1OF
rw 		CH0OF
rw 		TRGIF
rw 		CH1IF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH1IF

Bit 2: Channel 1 capture/compare interrupt flag.

TRGIF

Bit 6: Trigger interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

CH1OF

Bit 10: Channel 1 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGG
w 		CH1G
w 		CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

CH0G

Bit 1: Channel 0 capture or compare event generation.

CH1G

Bit 2: Channel 1 capture or compare event generation.

TRGG

Bit 6: Trigger event generation.

CHCTL0_Input

Channel control register 0 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1CAPFLT
rw 		CH1CAPPSC
rw 		CH1MS
rw 		CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CH1MS

Bits 8-9: Channel 1 mode selection.

CH1CAPPSC

Bits 10-11: Channel 1 input capture prescaler.

CH1CAPFLT

Bits 12-15: Channel 1 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1NP
rw 		CH1P
rw 		CH1EN
rw 		CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare function polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CH1EN

Bit 4: Channel 1 capture/compare function enable.

CH1P

Bit 5: Channel 1 capture/compare function polarity.

CH1NP

Bit 7: Channel 1 complementary output polarity.

CNT

Counter register

Offset: 0x24, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARL
rw
Toggle Fields.

CARL

Bits 0-15: Counter auto reload value.

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel0.

CH1CV

Channel 1 capture/compare value register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH1VAL
rw
Toggle Fields.

CH1VAL

Bits 0-15: Capture or compare value of channel1.

CFG

configuration register

Offset: 0xFC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TIMER9

0x40014400: General-purpose-timers

0/28 fields covered. Toggle Registers.

CTL0

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDIV
rw 		ARSE
rw 		UPS
rw 		UPDIS
rw 		CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

UPDIS

Bit 1: Update disable.

UPS

Bit 2: Update source.

ARSE

Bit 7: Auto-reload shadow enable.

CKDIV

Bits 8-9: Clock division.

DMAINTEN

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0IE
rw 		UPIE
rw
Toggle Fields.

UPIE

Bit 0: Update interrupt enable.

CH0IE

Bit 1: Channel 0 capture/compare interrupt enable.

INTF

interrupt flag register

Offset: 0x10, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0OF
rw 		CH0IF
rw 		UPIF
rw
Toggle Fields.

UPIF

Bit 0: Update interrupt flag.

CH0IF

Bit 1: Channel 0 capture/compare interrupt flag.

CH0OF

Bit 9: Channel 0 over capture flag.

SWEVG

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0G
w 		UPG
w
Toggle Fields.

UPG

Bit 0: Update generation.

CH0G

Bit 1: Channel 0 capture or compare event generation.

CHCTL0_Input

Channel control register 0 ( (input mode)

Offset: 0x18, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0CAPFLT
rw 		CH0CAPPSC
rw 		CH0MS
rw
Toggle Fields.

CH0MS

Bits 0-1: Channel 0 mode selection.

CH0CAPPSC

Bits 2-3: Channel 0 input capture prescaler.

CH0CAPFLT

Bits 4-7: Channel 0 input capture filter control.

CHCTL2

Channel control register 2

Offset: 0x20, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0NP
rw 		CH0P
rw 		CH0EN
rw
Toggle Fields.

CH0EN

Bit 0: Channel 0 capture/compare function enable.

CH0P

Bit 1: Channel 0 capture/compare polarity.

CH0NP

Bit 3: Channel 0 complementary output polarity.

CNT

Counter register

Offset: 0x24, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: current counter value.

PSC

Prescaler register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value of the counter clock.

CAR

Counter auto reload register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARL
rw
Toggle Fields.

CARL

Bits 0-15: Counter auto reload value.

CH0CV

Channel 0 capture/compare value register

Offset: 0x34, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0VAL
rw
Toggle Fields.

CH0VAL

Bits 0-15: Capture or compare value of channel 0.

IRMP

channel input remap register

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITI1_RMP
rw
Toggle Fields.

ITI1_RMP

Bits 10-11: Internal trigger input1 remap.

CFG

configuration register

Offset: 0xFC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHVSEL
rw
Toggle Fields.

CHVSEL

Bit 1: Write CHxVAL register selection.

TLI

0x40016800: TFT-LCD interface

10/93 fields covered. Toggle Registers.

SPSZ

Synchronous pulse size register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HPSZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPSZ
rw
Toggle Fields.

VPSZ

Bits 0-11: size of vertical synchronous pluse.

HPSZ

Bits 16-27: size of horizontal synchronous pluse.

BPSZ

Back-porch size register

Offset: 0xC, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HBPSZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBPSZ
rw
Toggle Fields.

VBPSZ

Bits 0-11: Size of the vertical back porch plus synchronous pulse.

HBPSZ

Bits 16-27: Size of the horizontal back porch plus synchronous pulse.

ASZ

Active size register

Offset: 0x10, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HASZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VASZ
rw
Toggle Fields.

VASZ

Bits 0-11: Size of the vertical active area width plus back porch and synchronous pulse.

HASZ

Bits 16-27: Size of the horizontal active area width plus back porch and synchronous pulse.

TSZ

Total size register

Offset: 0x14, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTSZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VTSZ
rw
Toggle Fields.

VTSZ

Bits 0-11: Vertical total size of the display.

HTSZ

Bits 16-27: Horizontal total size of the display.

CTL

Control register

Offset: 0x18, reset: 0x00002220, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HPPS
rw 		VPPS
rw 		DEPS
rw 		CLKPS
rw 		DFEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDB
rw 		GDB
rw 		BDB
rw 		TLIEN
rw
Toggle Fields.

TLIEN

Bit 0: TLI enable bit.

BDB

Bits 4-6: Blue channel Dither Bits Number.

GDB

Bits 8-10: Green channel Dither Bits Number.

RDB

Bits 12-14: Red channel Dither Bits Number.

DFEN

Bit 16: Dither Function Enable .

CLKPS

Bit 28: Pixel Clock Polarity Selection .

DEPS

Bit 29: Data Enable Polarity Selection.

VPPS

Bit 30: Vertical Pulse Polarity Selection.

HPPS

Bit 31: Horizontal Pulse Polarity Selection .

RL

Reload layer register

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FBR
rw 		RQR
rw
Toggle Fields.

RQR

Bit 0: Request Reload.

FBR

Bit 1: Frame Blank Reload.

BGC

Background color register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BVR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BVG
rw 		BVB
rw
Toggle Fields.

BVB

Bits 0-7: Background value blue .

BVG

Bits 8-15: Background value green .

BVR

Bits 16-23: Background value red .

INTEN

Interrupt enable register

Offset: 0x34, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCRIE
rw 		TEIE
rw 		FEIE
rw 		LMIE
rw
Toggle Fields.

LMIE

Bit 0: Line Mark Interrupt Enable.

FEIE

Bit 1: FIFO Error Interrupt Enable.

TEIE

Bit 2: Transaction Error Interrupt Enable.

LCRIE

Bit 3: Layer Configuration Reloaded Interrupt Enable.

INTF

Interrupt flag register

Offset: 0x38, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCRF
r 		TEF
r 		FEF
r 		LMF
r
Toggle Fields.

LMF

Bit 0: Line Mark Flag.

FEF

Bit 1: FIFO Error Flag.

TEF

Bit 2: Transaction Error Flag.

LCRF

Bit 3: Layer Configuration Reloaded Flag.

INTC

Interrupt flag clear register

Offset: 0x3C, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCRC
w 		TEC
w 		FEC
w 		LMC
w
Toggle Fields.

LMC

Bit 0: Line Mark Flag Clear.

FEC

Bit 1: FIFO Error Flag Clear.

TEC

Bit 2: Transaction Error Flag Clear.

LCRC

Bit 3: Layer Configuration Reloaded Flag Clear.

LM

Line mark register

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LM
rw
Toggle Fields.

LM

Bits 0-10: Line Mark value.

CPPOS

Current pixel position register

Offset: 0x44, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HPOS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPOS
r
Toggle Fields.

VPOS

Bits 0-15: Vertical position.

HPOS

Bits 16-31: Horizontal position.

STAT

Status register

Offset: 0x48, reset: 0x0000000F, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HS
r 		VS
r 		HDE
r 		VDE
r
Toggle Fields.

VDE

Bit 0: Current VDE status.

HDE

Bit 1: Current HDE status.

VS

Bit 2: Current VS staus of the TLI .

HS

Bit 3: Current HS staus of the TLI .

L0CTL

Layer 0 control register

Offset: 0x84, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LUTEN
rw 		CKEYEN
rw 		LEN
rw
Toggle Fields.

LEN

Bit 0: Layer enable.

CKEYEN

Bit 1: Color keying enable.

LUTEN

Bit 4: LUT enable .

L0HPOS

Layer 0 horizontal position parameters register

Offset: 0x88, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WLP
rw
Toggle Fields.

WLP

Bits 0-11: Window left position.

WRP

Bits 16-27: Window right position.

L0VPOS

Layer 0 vertical position parameters register

Offset: 0x8C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WBP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WTP
rw
Toggle Fields.

WTP

Bits 0-11: Window top position.

WBP

Bits 16-27: Window bottom position.

L0CKEY

Layer 0 color key register

Offset: 0x90, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKEYR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKEYG
rw 		CKEYB
rw
Toggle Fields.

CKEYB

Bits 0-7: Color Key Blue.

CKEYG

Bits 8-15: Color Key Green.

CKEYR

Bits 16-23: Color Key Red.

L0PPF

Layer 0 packeted pixel format register

Offset: 0x94, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PPF
rw
Toggle Fields.

PPF

Bits 0-2: Packeted Pixel Format.

L0SA

Layer 0 specified alpha register

Offset: 0x98, reset: 0x000000FF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SA
rw
Toggle Fields.

SA

Bits 0-7: Specified alpha.

L0DC

Layer 0 default color register

Offset: 0x9C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DCA
rw 		DCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCG
rw 		DCB
rw
Toggle Fields.

DCB

Bits 0-7: The default color blue.

DCG

Bits 8-15: The default color green.

DCR

Bits 16-23: The default color red.

DCA

Bits 24-31: The default color ALPHA.

L0BLEND

Layer 0 blending register

Offset: 0xA0, reset: 0x00000607, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACF1
rw 		ACF2
rw
Toggle Fields.

ACF2

Bits 0-2: Alpha Calculation Factor 2 of Blending Method.

ACF1

Bits 8-10: Alpha Calculation Factor 1 of Blending Method.

L0FBADDR

Layer 0 frame base address register

Offset: 0xAC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FBADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FBADD
rw
Toggle Fields.

FBADD

Bits 0-31: Frame Buffer base Address.

L0FLLEN

Layer 0 frame line length register

Offset: 0xB0, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STDOFF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLL
rw
Toggle Fields.

FLL

Bits 0-13: Frame Line Length.

STDOFF

Bits 16-29: Frame Buffer Stride Offset.

L0FTLN

Layer 0 frame total line number register

Offset: 0xB4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLN
rw
Toggle Fields.

FTLN

Bits 0-10: Frame Total Line Number.

L0LUT

Layer 0 look up table register

Offset: 0xC4, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TADD
rw 		TR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
rw 		TB
rw
Toggle Fields.

TB

Bits 0-7: Blue channel of a LUT entry.

TG

Bits 8-15: Green channel of a LUT entry.

TR

Bits 16-23: Red Channel of a LUT entry.

TADD

Bits 24-31: Look Up Table Write Address.

L1CTL

Layer 1 control register

Offset: 0x104, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LUTEN
rw 		CKEYEN
rw 		LEN
rw
Toggle Fields.

LEN

Bit 0: Layer enable.

CKEYEN

Bit 1: Color keying enable.

LUTEN

Bit 4: LUT enable .

L1HPOS

Layer 1 horizontal position parameters register

Offset: 0x108, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WLP
rw
Toggle Fields.

WLP

Bits 0-11: Window left position.

WRP

Bits 16-27: Window right position.

L1VPOS

Layer 1 vertical position parameters register

Offset: 0x10C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WBP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WTP
rw
Toggle Fields.

WTP

Bits 0-11: Window top position.

WBP

Bits 16-27: Window bottom position.

L1CKEY

Layer 1 color key register

Offset: 0x110, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKEYR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKEYG
rw 		CKEYB
rw
Toggle Fields.

CKEYB

Bits 0-7: Color Key Blue.

CKEYG

Bits 8-15: Color Key Green.

CKEYR

Bits 16-23: Color Key Red.

L1PPF

Layer 1 packeted pixel format register

Offset: 0x114, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PPF
rw
Toggle Fields.

PPF

Bits 0-2: Packeted Pixel Format.

L1SA

Layer 1 specified alpha register

Offset: 0x118, reset: 0x000000FF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SA
rw
Toggle Fields.

SA

Bits 0-7: Specified alpha.

L1DC

Layer 1 default color register

Offset: 0x11C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DCA
rw 		DCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCG
rw 		DCB
rw
Toggle Fields.

DCB

Bits 0-7: The default color blue.

DCG

Bits 8-15: The default color green.

DCR

Bits 16-23: The default color red.

DCA

Bits 24-31: The default color ALPHA.

L1BLEND

Layer 1 blending register

Offset: 0x120, reset: 0x00000607, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACF1
rw 		ACF2
rw
Toggle Fields.

ACF2

Bits 0-2: Alpha Calculation Factor 2 of Blending Method.

ACF1

Bits 8-10: Alpha Calculation Factor 1 of Blending Method.

L1FBADDR

Layer 1 frame base address register

Offset: 0x12C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FBADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FBADD
rw
Toggle Fields.

FBADD

Bits 0-31: Frame Buffer base Address.

L1FLLEN

Layer 1 frame line length register

Offset: 0x130, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STDOFF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLL
rw
Toggle Fields.

FLL

Bits 0-13: Frame Line Length.

STDOFF

Bits 16-29: Frame Buffer Stride Offset.

L1FTLN

Layer 1 frame total line number register

Offset: 0x134, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLN
rw
Toggle Fields.

FTLN

Bits 0-10: Frame Total Line Number.

L1LUT

Layer 1 look up table register

Offset: 0x144, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TADD
rw 		TR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
rw 		TB
rw
Toggle Fields.

TB

Bits 0-7: Blue channel of a LUT entry.

TG

Bits 8-15: Green channel of a LUT entry.

TR

Bits 16-23: Red channel of a LUT entry.

TADD

Bits 24-31: Look Up Table Write Address.

TRNG

0x50060800: Ture random number generator

4/8 fields covered. Toggle Registers.

CTL

Control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IE
rw 		TRNGEN
rw
Toggle Fields.

TRNGEN

Bit 2: TRNG enable bit.

IE

Bit 3: Interrupt bit.

STAT

Status register

Offset: 0x4, reset: 0x00000000, access: Unspecified

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEIF
rw 		CEIF
rw 		SECS
r 		CECS
r 		DRDY
r
Toggle Fields.

DRDY

Bit 0: Random data ready status bit.

CECS

Bit 1: Clock error current status.

SECS

Bit 2: Seed error current status.

CEIF

Bit 5: Clock error interrupt flag.

SEIF

Bit 6: Seed error interrupt flag.

DATA

data register

Offset: 0x8, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRNDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRNDATA
r
Toggle Fields.

TRNDATA

Bits 0-31: 32-bit random data.

UART3

0x40004C00: Universal asynchronous receiver transmitter

10/55 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSF
r 		LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS change flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

INTDIV

Bits 4-15: Integer part of baud-rate divider.

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVSMOD
rw 		UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

RWU

Bit 1: Receiver wakeup from mute mode.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE line detected interrupt enable.

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

PERRIE

Bit 8: Parity error interrupt enable.

PM

Bit 9: Parity mode.

PCEN

Bit 10: Parity check function enable.

WM

Bit 11: Wakeup method in mute mode.

WL

Bit 12: Word length.

UEN

Bit 13: USART enable.

OVSMOD

Bit 15: Oversampling mode.

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

LBLEN

Bit 5: LIN break frame length.

LBDIE

Bit 6: LIN break detection interrupt enable.

CLEN

Bit 8: CK Length.

CPH

Bit 9: Clock phase.

CPL

Bit 10: Clock polarity.

CKEN

Bit 11: CK pin enable.

STB

Bits 12-13: STOP bits length.

LMEN

Bit 14: LIN mode enable.

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSB
rw 		CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDEN

Bit 3: Half-duplex selection.

NKEN

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DENR

Bit 6: DMA request enable for reception.

DENT

Bit 7: DMA request enable for transmission.

RTSEN

Bit 8: RTS enable.

CTSEN

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

OSB

Bit 11: One sample bit method enable.

GP

Guard time and prescaler register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GUAT

Bits 8-15: Guard time value in Smartcard mode.

CHC

Coherence control register

Offset: 0xC0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPERR
rw 		BCM
rw 		PCM
rw 		HCM
rw
Toggle Fields.

HCM

Bit 0: Hardware flow control coherence mode.

PCM

Bit 1: Parity check coherence mode.

BCM

Bit 2: Break frame coherence mode.

EPERR

Bit 8: Early parity error flag.

UART4

0x40005000: Universal asynchronous receiver transmitter

10/55 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSF
r 		LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS change flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

INTDIV

Bits 4-15: Integer part of baud-rate divider.

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVSMOD
rw 		UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

RWU

Bit 1: Receiver wakeup from mute mode.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE line detected interrupt enable.

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

PERRIE

Bit 8: Parity error interrupt enable.

PM

Bit 9: Parity mode.

PCEN

Bit 10: Parity check function enable.

WM

Bit 11: Wakeup method in mute mode.

WL

Bit 12: Word length.

UEN

Bit 13: USART enable.

OVSMOD

Bit 15: Oversampling mode.

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

LBLEN

Bit 5: LIN break frame length.

LBDIE

Bit 6: LIN break detection interrupt enable.

CLEN

Bit 8: CK Length.

CPH

Bit 9: Clock phase.

CPL

Bit 10: Clock polarity.

CKEN

Bit 11: CK pin enable.

STB

Bits 12-13: STOP bits length.

LMEN

Bit 14: LIN mode enable.

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSB
rw 		CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDEN

Bit 3: Half-duplex selection.

NKEN

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DENR

Bit 6: DMA request enable for reception.

DENT

Bit 7: DMA request enable for transmission.

RTSEN

Bit 8: RTS enable.

CTSEN

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

OSB

Bit 11: One sample bit method enable.

GP

Guard time and prescaler register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GUAT

Bits 8-15: Guard time value in Smartcard mode.

CHC

Coherence control register

Offset: 0xC0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPERR
rw 		BCM
rw 		PCM
rw 		HCM
rw
Toggle Fields.

HCM

Bit 0: Hardware flow control coherence mode.

PCM

Bit 1: Parity check coherence mode.

BCM

Bit 2: Break frame coherence mode.

EPERR

Bit 8: Early parity error flag.

UART6

0x40007800: Universal asynchronous receiver transmitter

10/55 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSF
r 		LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS change flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

INTDIV

Bits 4-15: Integer part of baud-rate divider.

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVSMOD
rw 		UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

RWU

Bit 1: Receiver wakeup from mute mode.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE line detected interrupt enable.

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

PERRIE

Bit 8: Parity error interrupt enable.

PM

Bit 9: Parity mode.

PCEN

Bit 10: Parity check function enable.

WM

Bit 11: Wakeup method in mute mode.

WL

Bit 12: Word length.

UEN

Bit 13: USART enable.

OVSMOD

Bit 15: Oversampling mode.

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

LBLEN

Bit 5: LIN break frame length.

LBDIE

Bit 6: LIN break detection interrupt enable.

CLEN

Bit 8: CK Length.

CPH

Bit 9: Clock phase.

CPL

Bit 10: Clock polarity.

CKEN

Bit 11: CK pin enable.

STB

Bits 12-13: STOP bits length.

LMEN

Bit 14: LIN mode enable.

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSB
rw 		CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDEN

Bit 3: Half-duplex selection.

NKEN

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DENR

Bit 6: DMA request enable for reception.

DENT

Bit 7: DMA request enable for transmission.

RTSEN

Bit 8: RTS enable.

CTSEN

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

OSB

Bit 11: One sample bit method enable.

GP

Guard time and prescaler register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GUAT

Bits 8-15: Guard time value in Smartcard mode.

CHC

Coherence control register

Offset: 0xC0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPERR
rw 		BCM
rw 		PCM
rw 		HCM
rw
Toggle Fields.

HCM

Bit 0: Hardware flow control coherence mode.

PCM

Bit 1: Parity check coherence mode.

BCM

Bit 2: Break frame coherence mode.

EPERR

Bit 8: Early parity error flag.

UART7

0x40007C00: Universal asynchronous receiver transmitter

10/55 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSF
r 		LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS change flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

INTDIV

Bits 4-15: Integer part of baud-rate divider.

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVSMOD
rw 		UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

RWU

Bit 1: Receiver wakeup from mute mode.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE line detected interrupt enable.

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

PERRIE

Bit 8: Parity error interrupt enable.

PM

Bit 9: Parity mode.

PCEN

Bit 10: Parity check function enable.

WM

Bit 11: Wakeup method in mute mode.

WL

Bit 12: Word length.

UEN

Bit 13: USART enable.

OVSMOD

Bit 15: Oversampling mode.

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

LBLEN

Bit 5: LIN break frame length.

LBDIE

Bit 6: LIN break detection interrupt enable.

CLEN

Bit 8: CK Length.

CPH

Bit 9: Clock phase.

CPL

Bit 10: Clock polarity.

CKEN

Bit 11: CK pin enable.

STB

Bits 12-13: STOP bits length.

LMEN

Bit 14: LIN mode enable.

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSB
rw 		CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDEN

Bit 3: Half-duplex selection.

NKEN

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DENR

Bit 6: DMA request enable for reception.

DENT

Bit 7: DMA request enable for transmission.

RTSEN

Bit 8: RTS enable.

CTSEN

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

OSB

Bit 11: One sample bit method enable.

GP

Guard time and prescaler register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GUAT

Bits 8-15: Guard time value in Smartcard mode.

CHC

Coherence control register

Offset: 0xC0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPERR
rw 		BCM
rw 		PCM
rw 		HCM
rw
Toggle Fields.

HCM

Bit 0: Hardware flow control coherence mode.

PCM

Bit 1: Parity check coherence mode.

BCM

Bit 2: Break frame coherence mode.

EPERR

Bit 8: Early parity error flag.

USART0

0x40011000: Universal synchronous asynchronous receiver transmitter

11/68 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSF
r 		LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS change flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

INTDIV

Bits 4-15: Integer part of baud-rate divider.

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVSMOD
rw 		UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

RWU

Bit 1: Receiver wakeup from mute mode.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE line detected interrupt enable.

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

PERRIE

Bit 8: Parity error interrupt enable.

PM

Bit 9: Parity mode.

PCEN

Bit 10: Parity check function enable.

WM

Bit 11: Wakeup method in mute mode.

WL

Bit 12: Word length.

UEN

Bit 13: USART enable.

OVSMOD

Bit 15: Oversampling mode.

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

LBLEN

Bit 5: LIN break frame length.

LBDIE

Bit 6: LIN break detection interrupt enable.

CLEN

Bit 8: CK Length.

CPH

Bit 9: Clock phase.

CPL

Bit 10: Clock polarity.

CKEN

Bit 11: CK pin enable.

STB

Bits 12-13: STOP bits length.

LMEN

Bit 14: LIN mode enable.

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSB
rw 		CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDEN

Bit 3: Half-duplex selection.

NKEN

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DENR

Bit 6: DMA request enable for reception.

DENT

Bit 7: DMA request enable for transmission.

RTSEN

Bit 8: RTS enable.

CTSEN

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

OSB

Bit 11: One sample bit method enable.

GP

Guard time and prescaler register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GUAT

Bits 8-15: Guard time value in Smartcard mode.

CTL3

Control register 3

Offset: 0x80, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSBF
rw 		DINV
rw 		TINV
rw 		RINV
rw 		EBIE
rw 		RTIE
rw 		SCRTNUM
rw 		RTEN
rw
Toggle Fields.

RTEN

Bit 0: Receiver timeout enable.

SCRTNUM

Bits 1-3: Smartcard auto-retry number.

RTIE

Bit 4: Interrupt enable bit of receive timeout event.

EBIE

Bit 5: Interrupt enable bit of end of block event.

RINV

Bit 8: RX pin level inversion.

TINV

Bit 9: TX pin level inversion.

DINV

Bit 10: Data bit level inversion.

MSBF

Bit 11: Most significant bit first.

RT

Receiver timeout register

Offset: 0x84, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BL
rw 		RT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT
rw
Toggle Fields.

RT

Bits 0-23: Receiver timeout threshold.

BL

Bits 24-31: Block Length.

STAT1

Status register 1

Offset: 0x88, reset: 0x000000C0, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBF
w 		RTF
w
Toggle Fields.

RTF

Bit 11: Receiver timeout flag.

EBF

Bit 12: End of block flag.

BSY

Bit 16: Busy flag.

CHC

Coherence control register

Offset: 0xC0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPERR
rw 		BCM
rw 		PCM
rw 		HCM
rw
Toggle Fields.

HCM

Bit 0: Hardware flow control coherence mode.

PCM

Bit 1: Parity check coherence mode.

BCM

Bit 2: Break frame coherence mode.

EPERR

Bit 8: Early parity error flag.

USART1

0x40004400: Universal synchronous asynchronous receiver transmitter

11/68 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSF
r 		LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS change flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

INTDIV

Bits 4-15: Integer part of baud-rate divider.

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVSMOD
rw 		UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

RWU

Bit 1: Receiver wakeup from mute mode.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE line detected interrupt enable.

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

PERRIE

Bit 8: Parity error interrupt enable.

PM

Bit 9: Parity mode.

PCEN

Bit 10: Parity check function enable.

WM

Bit 11: Wakeup method in mute mode.

WL

Bit 12: Word length.

UEN

Bit 13: USART enable.

OVSMOD

Bit 15: Oversampling mode.

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

LBLEN

Bit 5: LIN break frame length.

LBDIE

Bit 6: LIN break detection interrupt enable.

CLEN

Bit 8: CK Length.

CPH

Bit 9: Clock phase.

CPL

Bit 10: Clock polarity.

CKEN

Bit 11: CK pin enable.

STB

Bits 12-13: STOP bits length.

LMEN

Bit 14: LIN mode enable.

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSB
rw 		CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDEN

Bit 3: Half-duplex selection.

NKEN

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DENR

Bit 6: DMA request enable for reception.

DENT

Bit 7: DMA request enable for transmission.

RTSEN

Bit 8: RTS enable.

CTSEN

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

OSB

Bit 11: One sample bit method enable.

GP

Guard time and prescaler register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GUAT

Bits 8-15: Guard time value in Smartcard mode.

CTL3

Control register 3

Offset: 0x80, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSBF
rw 		DINV
rw 		TINV
rw 		RINV
rw 		EBIE
rw 		RTIE
rw 		SCRTNUM
rw 		RTEN
rw
Toggle Fields.

RTEN

Bit 0: Receiver timeout enable.

SCRTNUM

Bits 1-3: Smartcard auto-retry number.

RTIE

Bit 4: Interrupt enable bit of receive timeout event.

EBIE

Bit 5: Interrupt enable bit of end of block event.

RINV

Bit 8: RX pin level inversion.

TINV

Bit 9: TX pin level inversion.

DINV

Bit 10: Data bit level inversion.

MSBF

Bit 11: Most significant bit first.

RT

Receiver timeout register

Offset: 0x84, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BL
rw 		RT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT
rw
Toggle Fields.

RT

Bits 0-23: Receiver timeout threshold.

BL

Bits 24-31: Block Length.

STAT1

Status register 1

Offset: 0x88, reset: 0x000000C0, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBF
w 		RTF
w
Toggle Fields.

RTF

Bit 11: Receiver timeout flag.

EBF

Bit 12: End of block flag.

BSY

Bit 16: Busy flag.

CHC

Coherence control register

Offset: 0xC0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPERR
rw 		BCM
rw 		PCM
rw 		HCM
rw
Toggle Fields.

HCM

Bit 0: Hardware flow control coherence mode.

PCM

Bit 1: Parity check coherence mode.

BCM

Bit 2: Break frame coherence mode.

EPERR

Bit 8: Early parity error flag.

USART2

0x40004800: Universal synchronous asynchronous receiver transmitter

11/68 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSF
r 		LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS change flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

INTDIV

Bits 4-15: Integer part of baud-rate divider.

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVSMOD
rw 		UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

RWU

Bit 1: Receiver wakeup from mute mode.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE line detected interrupt enable.

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

PERRIE

Bit 8: Parity error interrupt enable.

PM

Bit 9: Parity mode.

PCEN

Bit 10: Parity check function enable.

WM

Bit 11: Wakeup method in mute mode.

WL

Bit 12: Word length.

UEN

Bit 13: USART enable.

OVSMOD

Bit 15: Oversampling mode.

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

LBLEN

Bit 5: LIN break frame length.

LBDIE

Bit 6: LIN break detection interrupt enable.

CLEN

Bit 8: CK Length.

CPH

Bit 9: Clock phase.

CPL

Bit 10: Clock polarity.

CKEN

Bit 11: CK pin enable.

STB

Bits 12-13: STOP bits length.

LMEN

Bit 14: LIN mode enable.

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSB
rw 		CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDEN

Bit 3: Half-duplex selection.

NKEN

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DENR

Bit 6: DMA request enable for reception.

DENT

Bit 7: DMA request enable for transmission.

RTSEN

Bit 8: RTS enable.

CTSEN

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

OSB

Bit 11: One sample bit method enable.

GP

Guard time and prescaler register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GUAT

Bits 8-15: Guard time value in Smartcard mode.

CTL3

Control register 3

Offset: 0x80, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSBF
rw 		DINV
rw 		TINV
rw 		RINV
rw 		EBIE
rw 		RTIE
rw 		SCRTNUM
rw 		RTEN
rw
Toggle Fields.

RTEN

Bit 0: Receiver timeout enable.

SCRTNUM

Bits 1-3: Smartcard auto-retry number.

RTIE

Bit 4: Interrupt enable bit of receive timeout event.

EBIE

Bit 5: Interrupt enable bit of end of block event.

RINV

Bit 8: RX pin level inversion.

TINV

Bit 9: TX pin level inversion.

DINV

Bit 10: Data bit level inversion.

MSBF

Bit 11: Most significant bit first.

RT

Receiver timeout register

Offset: 0x84, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BL
rw 		RT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT
rw
Toggle Fields.

RT

Bits 0-23: Receiver timeout threshold.

BL

Bits 24-31: Block Length.

STAT1

Status register 1

Offset: 0x88, reset: 0x000000C0, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBF
w 		RTF
w
Toggle Fields.

RTF

Bit 11: Receiver timeout flag.

EBF

Bit 12: End of block flag.

BSY

Bit 16: Busy flag.

CHC

Coherence control register

Offset: 0xC0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPERR
rw 		BCM
rw 		PCM
rw 		HCM
rw
Toggle Fields.

HCM

Bit 0: Hardware flow control coherence mode.

PCM

Bit 1: Parity check coherence mode.

BCM

Bit 2: Break frame coherence mode.

EPERR

Bit 8: Early parity error flag.

USART5

0x40011400: Universal synchronous asynchronous receiver transmitter

11/68 fields covered. Toggle Registers.

STAT0

Status register 0

Offset: 0x0, reset: 0x000000C0, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSF
r 		LBDF
r 		TBE
r 		TC
r 		RBNE
r 		IDLEF
r 		ORERR
r 		NERR
r 		FERR
r 		PERR
r
Toggle Fields.

PERR

Bit 0: Parity error flag.

FERR

Bit 1: Frame error flag.

NERR

Bit 2: Noise error flag.

ORERR

Bit 3: Overrun error.

IDLEF

Bit 4: IDLE frame detected flag.

RBNE

Bit 5: Read data buffer not empty.

TC

Bit 6: Transmission complete.

TBE

Bit 7: Transmit data buffer empty.

LBDF

Bit 8: LIN break detection flag.

CTSF

Bit 9: CTS change flag.

DATA

Data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-8: Transmit or read data value.

BAUD

Baud rate register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTDIV
rw 		FRADIV
rw
Toggle Fields.

FRADIV

Bits 0-3: Fraction part of baud-rate divider.

INTDIV

Bits 4-15: Integer part of baud-rate divider.

CTL0

Control register 0

Offset: 0xC, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVSMOD
rw 		UEN
rw 		WL
rw 		WM
rw 		PCEN
rw 		PM
rw 		PERRIE
rw 		TBEIE
rw 		TCIE
rw 		RBNEIE
rw 		IDLEIE
rw 		TEN
rw 		REN
rw 		RWU
rw 		SBKCMD
rw
Toggle Fields.

SBKCMD

Bit 0: Send break command.

RWU

Bit 1: Receiver wakeup from mute mode.

REN

Bit 2: Receiver enable.

TEN

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE line detected interrupt enable.

RBNEIE

Bit 5: Read data buffer not empty interrupt and overrun error interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TBEIE

Bit 7: Transmitter buffer empty interrupt enable.

PERRIE

Bit 8: Parity error interrupt enable.

PM

Bit 9: Parity mode.

PCEN

Bit 10: Parity check function enable.

WM

Bit 11: Wakeup method in mute mode.

WL

Bit 12: Word length.

UEN

Bit 13: USART enable.

OVSMOD

Bit 15: Oversampling mode.

CTL1

Control register 1

Offset: 0x10, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LMEN
rw 		STB
rw 		CKEN
rw 		CPL
rw 		CPH
rw 		CLEN
rw 		LBDIE
rw 		LBLEN
rw 		ADDR
rw
Toggle Fields.

ADDR

Bits 0-3: Address of the USART.

LBLEN

Bit 5: LIN break frame length.

LBDIE

Bit 6: LIN break detection interrupt enable.

CLEN

Bit 8: CK Length.

CPH

Bit 9: Clock phase.

CPL

Bit 10: Clock polarity.

CKEN

Bit 11: CK pin enable.

STB

Bits 12-13: STOP bits length.

LMEN

Bit 14: LIN mode enable.

CTL2

Control register 2

Offset: 0x14, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSB
rw 		CTSIE
rw 		CTSEN
rw 		RTSEN
rw 		DENT
rw 		DENR
rw 		SCEN
rw 		NKEN
rw 		HDEN
rw 		IRLP
rw 		IREN
rw 		ERRIE
rw
Toggle Fields.

ERRIE

Bit 0: Error interrupt enable.

IREN

Bit 1: IrDA mode enable.

IRLP

Bit 2: IrDA low-power.

HDEN

Bit 3: Half-duplex selection.

NKEN

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DENR

Bit 6: DMA request enable for reception.

DENT

Bit 7: DMA request enable for transmission.

RTSEN

Bit 8: RTS enable.

CTSEN

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

OSB

Bit 11: One sample bit method enable.

GP

Guard time and prescaler register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GUAT
rw 		PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GUAT

Bits 8-15: Guard time value in Smartcard mode.

CTL3

Control register 3

Offset: 0x80, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSBF
rw 		DINV
rw 		TINV
rw 		RINV
rw 		EBIE
rw 		RTIE
rw 		SCRTNUM
rw 		RTEN
rw
Toggle Fields.

RTEN

Bit 0: Receiver timeout enable.

SCRTNUM

Bits 1-3: Smartcard auto-retry number.

RTIE

Bit 4: Interrupt enable bit of receive timeout event.

EBIE

Bit 5: Interrupt enable bit of end of block event.

RINV

Bit 8: RX pin level inversion.

TINV

Bit 9: TX pin level inversion.

DINV

Bit 10: Data bit level inversion.

MSBF

Bit 11: Most significant bit first.

RT

Receiver timeout register

Offset: 0x84, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BL
rw 		RT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT
rw
Toggle Fields.

RT

Bits 0-23: Receiver timeout threshold.

BL

Bits 24-31: Block Length.

STAT1

Status register 1

Offset: 0x88, reset: 0x000000C0, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBF
w 		RTF
w
Toggle Fields.

RTF

Bit 11: Receiver timeout flag.

EBF

Bit 12: End of block flag.

BSY

Bit 16: Busy flag.

CHC

Coherence control register

Offset: 0xC0, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPERR
rw 		BCM
rw 		PCM
rw 		HCM
rw
Toggle Fields.

HCM

Bit 0: Hardware flow control coherence mode.

PCM

Bit 1: Parity check coherence mode.

BCM

Bit 2: Break frame coherence mode.

EPERR

Bit 8: Early parity error flag.

WWDGT

0x40002C00: Window watchdog timer

0/6 fields covered. Toggle Registers.

CTL

Control register

Offset: 0x0, reset: 0x0000007F, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGTEN
rw 		CNT
rw
Toggle Fields.

CNT

Bits 0-6: 7-bit counter.

WDGTEN

Bit 7: Activation bit.

CFG

Configuration register

Offset: 0x4, reset: 0x0000007F, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIE
rw 		PSC
rw 		WIN
rw
Toggle Fields.

WIN

Bits 0-6: 7-bit window value.

PSC

Bits 7-8: Prescaler.

EWIE

Bit 9: Early wakeup interrupt.

STAT

Status register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
rw
Toggle Fields.

EWIF

Bit 0: Early wakeup interrupt flag.