Fields In DBG_CTL0 (0x40015800, 0x0004)
Field | Offset | Width |
gd32c103 |
gd32c113 |
gd32e103 |
gd32e230 |
gd32e231 |
gd32e503 |
gd32e505 |
gd32e507 |
gd32e508 |
gd32f130 |
gd32f150 |
gd32f170 |
gd32f190 |
gd32f205 |
gd32f207 |
gd32f303 |
gd32f305 |
gd32f307 |
gd32f425 |
TIMER13_HOLD | 27 | 1 |
✘ |
✘ |
✘ |
✔ |
✔ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
TIMER5_HOLD | 19 | 1 |
✘ |
✘ |
✘ |
✔ |
✔ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
I2C1_HOLD | 16 | 1 |
✘ |
✘ |
✘ |
✔ |
✔ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
I2C0_HOLD | 15 | 1 |
✘ |
✘ |
✘ |
✔ |
✔ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
TIMER2_HOLD | 12 | 1 |
✘ |
✘ |
✘ |
✔ |
✔ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
TIMER0_HOLD | 10 | 1 |
✘ |
✘ |
✘ |
✔ |
✔ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
WWDGT_HOLD | 9 | 1 |
✘ |
✘ |
✘ |
✔ |
✔ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
FWDGT_HOLD | 8 | 1 |
✘ |
✘ |
✘ |
✔ |
✔ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
STB_HOLD | 2 | 1 |
✘ |
✘ |
✘ |
✔ |
✔ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
DSLP_HOLD | 1 | 1 |
✘ |
✘ |
✘ |
✔ |
✔ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
SLP_HOLD | 0 | 1 |
✘ |
✘ |
✘ |
✔ |
✔ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |
✘ |