GD32E505 1.0 GD32E50x ARM 32-bit Cortex-M33 Microcontroller based device CM33 r0p0 little 1 1 4 0 8 32 0x20 0x0 0xFFFFFFFF ADC0 Analog to digital converter ADC 0x40012400 0x0 0x400 registers ADC0_1 18 STAT STAT status register 0x0 0x20 read-write 0x00000000 WDE2 Analog watchdog 2 event flag 31 1 WDE1 Analog watchdog 1 event flag 30 1 STRC Start flag of regular channel group 4 1 STIC Start flag of inserted channel group 3 1 EOIC End of inserted group conversion flag 2 1 EOC End of group conversion flag 1 1 WDE0 Analog watchdog event flag 0 1 CTL0 CTL0 control register 0 0x4 0x20 read-write 0x00000000 WDE2IE Interrupt enable for WDE2 31 1 WDE1IE Interrupt enable for WDE1 30 1 RWD0EN Regular channel analog watchdog 0 enable 23 1 IWD0EN Inserted channel analog watchdog 0 enable 22 1 SYNCM sync mode selection 16 4 DISNUM Number of conversions in discontinuous mode 13 3 DISIC Discontinuous mode on inserted channels 12 1 DISRC Discontinuous mode on regular channels 11 1 ICA Inserted channel group convert automatically 10 1 WD0SC When in scan mode, analog watchdog 0 is effective on a single channel 9 1 SM Scan mode 8 1 EOICIE Interrupt enable for EOIC 7 1 WDE0IE Interrupt enable for WDE0 6 1 EOCIE Interrupt enable for EOC 5 1 WD0CHSEL Analog watchdog 0 channel select 0 5 CTL1 CTL1 control register 1 0x08 0x20 read-write 0x00000000 ETSRC_3 The third bit of ETSRC 31 1 ETSIC_3 The third bit of ETSIC 30 1 TSVREN Channel 16 and 17 enable of ADC0 23 1 SWRCST Start on regular channel 22 1 SWICST Start on inserted channel 21 1 ETERC External trigger enable for regular channel 20 1 ETSRC External trigger select for regular channel 17 3 ETEIC External trigger enable for inserted channel 15 1 ETSIC External trigger select for inserted channel 12 3 DAL Data alignment 11 1 DMA DMA request enable 8 1 CALNUM Calibration Times 4 3 RSTCLB Reset calibration 3 1 CLB ADC calibration 2 1 CTN Continuous mode 1 1 ADCON ADC on 0 1 SAMPT0 SAMPT0 Sample time register 0 0x0C 0x20 read-write 0x00000000 SPT10 Channel 10 sample time selection 0 3 SPT11 Channel 11 sample time selection 3 3 SPT12 Channel 12 sample time selection 6 3 SPT13 Channel 13 sample time selection 9 3 SPT14 Channel 14 sample time selection 12 3 SPT15 Channel 15 sample time selection 15 3 SPT16 Channel 16 sample time selection 18 3 SPT17 Channel 17 sample time selection 21 3 SAMPT1 SAMPT1 Sample time register 1 0x10 0x20 read-write 0x00000000 SPT0 Channel 0 sample time selection 0 3 SPT1 Channel 1 sample time selection 3 3 SPT2 Channel 2 sample time selection 6 3 SPT3 Channel 3 sample time selection 9 3 SPT4 Channel 4 sample time selection 12 3 SPT5 Channel 5 sample time selection 15 3 SPT6 Channel 6 sample time selection 18 3 SPT7 Channel 7 sample time selection 21 3 SPT8 Channel 8 sample time selection 24 3 SPT9 Channel 9 sample time selection 27 3 IOFF0 IOFF0 Inserted channel data offset register 0 0x14 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 0 0 12 IOFF1 IOFF1 Inserted channel data offset register 1 0x18 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 1 0 12 IOFF2 IOFF2 Inserted channel data offset register 2 0x1C 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 2 0 12 IOFF3 IOFF3 Inserted channel data offset register 3 0x20 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 3 0 12 WDHT WDHT0 watchdog higher threshold register 0 0x24 0x20 read-write 0x00000FFF WDHT0 Analog watchdog 0 higher threshold 0 12 WDLT0 WDLT0 watchdog lower threshold register 0x28 0x20 read-write 0x00000000 WDLT0 Analog watchdog 0 lower threshold 0 12 RSQ0 RSQ0 regular sequence register 0 0x2C 0x20 read-write 0x00000000 RL Regular channel group length 20 4 RSQ15 16th conversion in regular sequence 15 5 RSQ14 15th conversion in regular sequence 10 5 RSQ13 14th conversion in regular sequence 5 5 RSQ12 13th conversion in regular sequence 0 5 RSQ1 RSQ1 regular sequence register 1 0x30 0x20 read-write 0x00000000 RSQ11 12th conversion in regular sequence 25 5 RSQ10 11th conversion in regular sequence 20 5 RSQ9 10th conversion in regular sequence 15 5 RSQ8 9th conversion in regular sequence 10 5 RSQ7 8th conversion in regular sequence 5 5 RSQ6 7th conversion in regular sequence 0 5 RSQ2 RSQ2 regular sequence register 2 0x34 0x20 read-write 0x00000000 RSQ5 6th conversion in regular sequence 25 5 RSQ4 5th conversion in regular sequence 20 5 RSQ3 4th conversion in regular sequence 15 5 RSQ2 3rd conversion in regular sequence 10 5 RSQ1 2nd conversion in regular sequence 5 5 RSQ0 1st conversion in regular sequence 0 5 ISQ ISQ Inserted sequence register 0x38 0x20 read-write 0x00000000 IL Inserted channel group length 20 2 ISQ3 4th conversion in inserted sequence 15 5 ISQ2 3rd conversion in inserted sequence 10 5 ISQ1 2nd conversion in inserted sequence 5 5 ISQ0 1st conversion in inserted sequence 0 5 IDATA0 IDATA0 Inserted data register 0 0x3C 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 IDATA1 IDATA1 Inserted data register 1 0x40 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 IDATA2 IDATA2 Inserted data register 2 0x44 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 IDATA3 IDATA3 Inserted data register 3 0x48 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 RDATA RDATA regular data register 0x4C 0x20 read-only 0x00000000 ADC1RDTR ADCegular channel data 16 16 RDATA Regular channel data 0 16 OVSAMPCTL OVSAMPCTL Oversample control register 0x80 0x20 read-write 0x00000000 DRES ADC resolution 12 2 TOVS Triggered Oversampling 9 1 OVSS Oversampling shift 5 4 OVSR Oversampling ratio 2 3 OVSEN Oversampling Enable 0 1 WD1SR WD1SR Watchdog 1 Channel Selection Register 0xA0 0x20 read-write 0x00000000 AWD1CS Analog watchdog 1 channel selection 0 18 WD2SR WD2SR Watchdog 2 Channel Selection Register 0xA4 0x20 read-write 0x00000000 AWD2CS Analog watchdog 2 channel selection 0 18 WDT1 WDT1 Watchdog threshold register 1 0xA8 0x20 read-write 0x00FF0000 WDHT1 Analog watchdog 1 high threshold 16 8 WDLT1 Analog watchdog 1 low threshold 0 8 WDT2 WDT2 Watchdog threshold register 2 0xAC 0x20 read-write 0x00FF0000 WDHT2 Analog watchdog 2 high threshold 16 8 WDLT2 Analog watchdog 2 low threshold 0 8 DIFCTL DIFCTL Differential mode control register 0xB0 0x20 0x00000000 DIFCTL_17_15 Differential mode for channel 17 to 15 15 3 read-only DIFCTL_14_0 Differential mode for channel 14 to 0 0 15 read-write ADC1 Analog to digital converter ADC 0x40012800 0x0 0x400 registers ADC0_1 18 STAT STAT status register 0x0 0x20 read-write 0x00000000 WDE2 Analog watchdog 2 event flag 31 1 WDE1 Analog watchdog 1 event flag 30 1 STRC Start flag of regular channel group 4 1 STIC Start flag of inserted channel group 3 1 EOIC End of inserted group conversion flag 2 1 EOC End of group conversion flag 1 1 WDE0 Analog watchdog event flag 0 1 CTL0 CTL0 control register 0 0x4 0x20 read-write 0x00000000 WDE2IE Interrupt enable for WDE2 31 1 WDE1IE Interrupt enable for WDE1 30 1 RWD0EN Regular channel analog watchdog 0 enable 23 1 IWD0EN Inserted channel analog watchdog 0 enable 22 1 DISNUM Number of conversions in discontinuous mode 13 3 DISIC Discontinuous mode on inserted channels 12 1 DISRC Discontinuous mode on regular channels 11 1 ICA Inserted channel group convert automatically 10 1 WD0SC When in scan mode, analog watchdog 0 is effective on a single channel 9 1 SM Scan mode 8 1 EOICIE Interrupt enable for EOIC 7 1 WDE0IE Interrupt enable for WDE0 6 1 EOCIE Interrupt enable for EOC 5 1 WD0CHSEL Analog watchdog 0 channel select 0 5 CTL1 CTL1 control register 1 0x08 0x20 read-write 0x00000000 ETSRC_3 The third bit of ETSRC 31 1 ETSIC_3 The third bit of ETSIC 30 1 TSVREN Channel 16 and 17 enable of ADC0 23 1 SWRCST Start on regular channel 22 1 SWICST Start on inserted channel 21 1 ETERC External trigger enable for regular channel 20 1 ETSRC External trigger select for regular channel 17 3 ETEIC External trigger enable for inserted channel 15 1 ETSIC External trigger select for inserted channel 12 3 DAL Data alignment 11 1 DMA DMA request enable 8 1 CALNUM Calibration Times 4 3 RSTCLB Reset calibration 3 1 CLB ADC calibration 2 1 CTN Continuous mode 1 1 ADCON ADC on 0 1 SAMPT0 SAMPT0 Sample time register 0 0x0C 0x20 read-write 0x00000000 SPT10 Channel 10 sample time selection 0 3 SPT11 Channel 11 sample time selection 3 3 SPT12 Channel 12 sample time selection 6 3 SPT13 Channel 13 sample time selection 9 3 SPT14 Channel 14 sample time selection 12 3 SPT15 Channel 15 sample time selection 15 3 SPT16 Channel 16 sample time selection 18 3 SPT17 Channel 17 sample time selection 21 3 SAMPT1 SAMPT1 Sample time register 1 0x10 0x20 read-write 0x00000000 SPT0 Channel 0 sample time selection 0 3 SPT1 Channel 1 sample time selection 3 3 SPT2 Channel 2 sample time selection 6 3 SPT3 Channel 3 sample time selection 9 3 SPT4 Channel 4 sample time selection 12 3 SPT5 Channel 5 sample time selection 15 3 SPT6 Channel 6 sample time selection 18 3 SPT7 Channel 7 sample time selection 21 3 SPT8 Channel 8 sample time selection 24 3 SPT9 Channel 9 sample time selection 27 3 IOFF0 IOFF0 Inserted channel data offset register 0 0x14 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 0 0 12 IOFF1 IOFF1 Inserted channel data offset register 1 0x18 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 1 0 12 IOFF2 IOFF2 Inserted channel data offset register 2 0x1C 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 2 0 12 IOFF3 IOFF3 Inserted channel data offset register 3 0x20 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 3 0 12 WDHT WDHT0 watchdog higher threshold register 0 0x24 0x20 read-write 0x00000FFF WDHT0 Analog watchdog 0 higher threshold 0 12 WDLT0 WDLT0 watchdog lower threshold register 0x28 0x20 read-write 0x00000000 WDLT0 Analog watchdog 0 lower threshold 0 12 RSQ0 RSQ0 regular sequence register 0 0x2C 0x20 read-write 0x00000000 RL Regular channel group length 20 4 RSQ15 16th conversion in regular sequence 15 5 RSQ14 15th conversion in regular sequence 10 5 RSQ13 14th conversion in regular sequence 5 5 RSQ12 13th conversion in regular sequence 0 5 RSQ1 RSQ1 regular sequence register 1 0x30 0x20 read-write 0x00000000 RSQ11 12th conversion in regular sequence 25 5 RSQ10 11th conversion in regular sequence 20 5 RSQ9 10th conversion in regular sequence 15 5 RSQ8 9th conversion in regular sequence 10 5 RSQ7 8th conversion in regular sequence 5 5 RSQ6 7th conversion in regular sequence 0 5 RSQ2 RSQ2 regular sequence register 2 0x34 0x20 read-write 0x00000000 RSQ5 6th conversion in regular sequence 25 5 RSQ4 5th conversion in regular sequence 20 5 RSQ3 4th conversion in regular sequence 15 5 RSQ2 3rd conversion in regular sequence 10 5 RSQ1 2nd conversion in regular sequence 5 5 RSQ0 1st conversion in regular sequence 0 5 ISQ ISQ Inserted sequence register 0x38 0x20 read-write 0x00000000 IL Inserted channel group length 20 2 ISQ3 4th conversion in inserted sequence 15 5 ISQ2 3rd conversion in inserted sequence 10 5 ISQ1 2nd conversion in inserted sequence 5 5 ISQ0 1st conversion in inserted sequence 0 5 IDATA0 IDATA0 Inserted data register 0 0x3C 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 IDATA1 IDATA1 Inserted data register 1 0x40 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 IDATA2 IDATA2 Inserted data register 2 0x44 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 IDATA3 IDATA3 Inserted data register 3 0x48 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 RDATA RDATA regular data register 0x4C 0x20 read-only 0x00000000 ADC1RDTR ADCegular channel data 16 16 RDATA Regular channel data 0 16 OVSAMPCTL OVSAMPCTL Oversample control register 0x80 0x20 read-write 0x00000000 DRES ADC resolution 12 2 TOVS Triggered Oversampling 9 1 OVSS Oversampling shift 5 4 OVSR Oversampling ratio 2 3 OVSEN Oversampling Enable 0 1 WD1SR WD1SR Watchdog 1 Channel Selection Register 0xA0 0x20 read-write 0x00000000 AWD1CS Analog watchdog 1 channel selection 0 18 WD2SR WD2SR Watchdog 2 Channel Selection Register 0xA4 0x20 read-write 0x00000000 AWD2CS Analog watchdog 2 channel selection 0 18 WDT1 WDT1 Watchdog threshold register 1 0xA8 0x20 read-write 0x00FF0000 WDHT1 Analog watchdog 1 high threshold 16 8 WDLT1 Analog watchdog 1 low threshold 0 8 WDT2 WDT2 Watchdog threshold register 2 0xAC 0x20 read-write 0x00FF0000 WDHT2 Analog watchdog 2 high threshold 16 8 WDLT2 Analog watchdog 2 low threshold 0 8 DIFCTL DIFCTL Differential mode control register 0xB0 0x20 0x00000000 DIFCTL_17_15 Differential mode for channel 17 to 15 15 3 read-only DIFCTL_14_0 Differential mode for channel 14 to 0 0 15 read-write ADC2 Analog to digital converter ADC 0x40013C00 0x0 0x400 registers ADC2 47 STAT STAT status register 0x0 0x20 read-write 0x00000000 WDE2 Analog watchdog 2 event flag 31 1 WDE1 Analog watchdog 1 event flag 30 1 STRC Start flag of regular channel group 4 1 STIC Start flag of inserted channel group 3 1 EOIC End of inserted group conversion flag 2 1 EOC End of group conversion flag 1 1 WDE0 Analog watchdog event flag 0 1 CTL0 CTL0 control register 0 0x4 0x20 read-write 0x00000000 WDE2IE Interrupt enable for WDE2 31 1 WDE1IE Interrupt enable for WDE1 30 1 RWD0EN Regular channel analog watchdog 0 enable 23 1 IWD0EN Inserted channel analog watchdog 0 enable 22 1 DISNUM Number of conversions in discontinuous mode 13 3 DISIC Discontinuous mode on inserted channels 12 1 DISRC Discontinuous mode on regular channels 11 1 ICA Inserted channel group convert automatically 10 1 WD0SC When in scan mode, analog watchdog 0 is effective on a single channel 9 1 SM Scan mode 8 1 EOICIE Interrupt enable for EOIC 7 1 WDE0IE Interrupt enable for WDE0 6 1 EOCIE Interrupt enable for EOC 5 1 WD0CHSEL Analog watchdog 0 channel select 0 5 CTL1 CTL1 control register 1 0x08 0x20 read-write 0x00000000 ETSRC_3 The third bit of ETSRC 31 1 ETSIC_3 The third bit of ETSIC 30 1 TSVREN Channel 16 and 17 enable of ADC0 23 1 SWRCST Start on regular channel 22 1 SWICST Start on inserted channel 21 1 ETERC External trigger enable for regular channel 20 1 ETSRC External trigger select for regular channel 17 3 ETEIC External trigger enable for inserted channel 15 1 ETSIC External trigger select for inserted channel 12 3 DAL Data alignment 11 1 DMA DMA request enable 8 1 CALNUM Calibration Times 4 3 RSTCLB Reset calibration 3 1 CLB ADC calibration 2 1 CTN Continuous mode 1 1 ADCON ADC on 0 1 SAMPT0 SAMPT0 Sample time register 0 0x0C 0x20 read-write 0x00000000 SPT10 Channel 10 sample time selection 0 3 SPT11 Channel 11 sample time selection 3 3 SPT12 Channel 12 sample time selection 6 3 SPT13 Channel 13 sample time selection 9 3 SPT14 Channel 14 sample time selection 12 3 SPT15 Channel 15 sample time selection 15 3 SPT16 Channel 16 sample time selection 18 3 SPT17 Channel 17 sample time selection 21 3 SAMPT1 SAMPT1 Sample time register 1 0x10 0x20 read-write 0x00000000 SPT0 Channel 0 sample time selection 0 3 SPT1 Channel 1 sample time selection 3 3 SPT2 Channel 2 sample time selection 6 3 SPT3 Channel 3 sample time selection 9 3 SPT4 Channel 4 sample time selection 12 3 SPT5 Channel 5 sample time selection 15 3 SPT6 Channel 6 sample time selection 18 3 SPT7 Channel 7 sample time selection 21 3 SPT8 Channel 8 sample time selection 24 3 SPT9 Channel 9 sample time selection 27 3 IOFF0 IOFF0 Inserted channel data offset register 0 0x14 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 0 0 12 IOFF1 IOFF1 Inserted channel data offset register 1 0x18 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 1 0 12 IOFF2 IOFF2 Inserted channel data offset register 2 0x1C 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 2 0 12 IOFF3 IOFF3 Inserted channel data offset register 3 0x20 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 3 0 12 WDHT WDHT0 watchdog higher threshold register 0 0x24 0x20 read-write 0x00000FFF WDHT0 Analog watchdog 0 higher threshold 0 12 WDLT0 WDLT0 watchdog lower threshold register 0x28 0x20 read-write 0x00000000 WDLT0 Analog watchdog 0 lower threshold 0 12 RSQ0 RSQ0 regular sequence register 0 0x2C 0x20 read-write 0x00000000 RL Regular channel group length 20 4 RSQ15 16th conversion in regular sequence 15 5 RSQ14 15th conversion in regular sequence 10 5 RSQ13 14th conversion in regular sequence 5 5 RSQ12 13th conversion in regular sequence 0 5 RSQ1 RSQ1 regular sequence register 1 0x30 0x20 read-write 0x00000000 RSQ11 12th conversion in regular sequence 25 5 RSQ10 11th conversion in regular sequence 20 5 RSQ9 10th conversion in regular sequence 15 5 RSQ8 9th conversion in regular sequence 10 5 RSQ7 8th conversion in regular sequence 5 5 RSQ6 7th conversion in regular sequence 0 5 RSQ2 RSQ2 regular sequence register 2 0x34 0x20 read-write 0x00000000 RSQ5 6th conversion in regular sequence 25 5 RSQ4 5th conversion in regular sequence 20 5 RSQ3 4th conversion in regular sequence 15 5 RSQ2 3rd conversion in regular sequence 10 5 RSQ1 2nd conversion in regular sequence 5 5 RSQ0 1st conversion in regular sequence 0 5 ISQ ISQ Inserted sequence register 0x38 0x20 read-write 0x00000000 IL Inserted channel group length 20 2 ISQ3 4th conversion in inserted sequence 15 5 ISQ2 3rd conversion in inserted sequence 10 5 ISQ1 2nd conversion in inserted sequence 5 5 ISQ0 1st conversion in inserted sequence 0 5 IDATA0 IDATA0 Inserted data register 0 0x3C 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 IDATA1 IDATA1 Inserted data register 1 0x40 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 IDATA2 IDATA2 Inserted data register 2 0x44 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 IDATA3 IDATA3 Inserted data register 3 0x48 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 RDATA RDATA regular data register 0x4C 0x20 read-only 0x00000000 ADC1RDTR ADCegular channel data 16 16 RDATA Regular channel data 0 16 OVSAMPCTL OVSAMPCTL Oversample control register 0x80 0x20 read-write 0x00000000 DRES ADC resolution 12 2 TOVS Triggered Oversampling 9 1 OVSS Oversampling shift 5 4 OVSR Oversampling ratio 2 3 OVSEN Oversampling Enable 0 1 WD1SR WD1SR Watchdog 1 Channel Selection Register 0xA0 0x20 read-write 0x00000000 AWD1CS Analog watchdog 1 channel selection 0 18 WD2SR WD2SR Watchdog 2 Channel Selection Register 0xA4 0x20 read-write 0x00000000 AWD2CS Analog watchdog 2 channel selection 0 18 WDT1 WDT1 Watchdog threshold register 1 0xA8 0x20 read-write 0x00FF0000 WDHT1 Analog watchdog 1 high threshold 16 8 WDLT1 Analog watchdog 1 low threshold 0 8 WDT2 WDT2 Watchdog threshold register 2 0xAC 0x20 read-write 0x00FF0000 WDHT2 Analog watchdog 2 high threshold 16 8 WDLT2 Analog watchdog 2 low threshold 0 8 DIFCTL DIFCTL Differential mode control register 0xB0 0x20 0x00000000 DIFCTL_17_15 Differential mode for channel 17 to 15 15 3 read-only DIFCTL_14_0 Differential mode for channel 14 to 0 0 15 read-write AFIO Alternate-function I/Os AFIO 0x40010000 0x0 0x400 registers EC EC Event control register 0x0 0x20 read-write 0x00000000 EOE Event output enable 7 1 PORT Event output port selection 4 3 PIN Event output pin selection 0 4 PCF0 PCF0 AFIO port configuration register 0 0x4 0x20 read-write 0x00000000 PTP_PPS_REMAP Ethernet PTP PPS remapping 30 1 TIMER1ITR0_REMAP TIMER1 internal trigger 0 remapping 29 1 SPI2_REMAP SPI2/I2S2 remapping 28 1 SWJ_CFG Serial wire JTAG configuration 24 3 ENET_PHY_SEL Ethernet MII or RMII PHY selection 23 1 ENET_REMAP Ethernet MAC I/O remapping 21 1 TIMER4CH3_IREMAP TIMER4 channel3 internal remapping 16 1 PD01_REMAP Port D0/Port D1 mapping on OSC_IN/OSC_OUT 15 1 TIMER3_REMAP TIMER3 remapping 12 1 TIMER2_REMAP TIMER2 remapping 10 2 TIMER1_REMAP TIMER1 remapping 8 2 TIMER0_REMAP TIMER0 remapping 6 2 USART2_REMAP USART2 remapping 4 2 USART1_REMAP USART1 remapping 3 1 USART0_REMAP USART0 remapping 2 1 I2C0_REMAP I2C0 remapping 1 1 SPI0_REMAP SPI0 remapping 0 1 EXTISS0 EXTISS0 EXTI sources selection register 0 0x08 0x20 read-write 0x00000000 EXTI3_SS EXTI 3 sources selection 12 4 EXTI2_SS EXTI 2 sources selection 8 4 EXTI1_SS EXTI 1 sources selection 4 4 EXTI0_SS EXTI 0 sources selection 0 4 EXTISS1 EXTISS1 EXTI sources selection register 1 0x0C 0x20 read-write 0x00000000 EXTI7_SS EXTI 7 sources selection 12 4 EXTI6_SS EXTI 6 sources selection 8 4 EXTI5_SS EXTI 5 sources selection 4 4 EXTI4_SS EXTI 4 sources selection 0 4 EXTISS2 EXTISS2 EXTI sources selection register 2 0x10 0x20 read-write 0x00000000 EXTI11_SS EXTI 11 sources selection 12 4 EXTI10_SS EXTI 10 sources selection 8 4 EXTI9_SS EXTI 9 sources selection 4 4 EXTI8_SS EXTI 8 sources selection 0 4 EXTISS3 EXTISS3 EXTI sources selection register 3 0x14 0x20 read-write 0x00000000 EXTI15_SS EXTI 15 sources selection 12 4 EXTI14_SS EXTI 14 sources selection 8 4 EXTI13_SS EXTI 13 sources selection 4 4 EXTI12_SS EXTI 12 sources selection 0 4 PCF1 PCF1 AFIO port configuration register 1 0x1C 0x20 read-write 0x00000000 CTC_REMAP CTC remapping 11 2 EXMC_NADV EXMC_NADV connect/disconnect 10 1 TIMER13_REMAP TIMER13 remapping 9 1 TIMER12_REMAP TIMER12 remapping 8 1 TIMER10_REMAP TIMER10 remapping 7 1 TIMER9_REMAP TIMER9 remapping 6 1 TIMER8_REMAP TIMER8 remapping 5 1 CPSCTL CPSCTL IO compensation control register 0x20 0x20 0x00000000 CPS_RDY I/O compensation cell is really or not 8 1 read-only CPS_EN I/O compensation cell enable 0 1 read-write PCFA PCFA AFIO port configuration register A 0x3C 0x20 read-write 0x00000000 PA15_AFCFG PA15 AF function configuration bit 30 1 PA12_AFCFG PA12 AF function configuration bitse 24 2 PA11_AFCFG PA11 AF function configuration bitse 22 2 PA10_AFCFG PA10 AF function configuration bitse 20 2 PA9_AFCFG PA9 AF function configuration bitse 18 2 PA8_AFCFG PA8 AF function configuration bitse 16 2 PA5_AFCFG PA5 AF function configuration bitse 10 1 PA3_AFCFG PA3 AF function configuration bitse 6 1 PA2_AFCFG PA2 AF function configuration bitse 4 1 PCFB PCFB AFIO port configuration register B 0x40 0x20 read-write 0x00000000 PB15_AFCFG PB15 AF function configuration bit 30 1 PB14_AFCFG PB14 AF function configuration bit 28 2 PB13_AFCFG PB13 AF function configuration bit 26 2 PB12_AFCFG PB12 AF function configuration bitse 24 2 PB11_AFCFG PB11 AF function configuration bitse 22 2 PB10_AFCFG PB10 AF function configuration bitse 20 2 PB9_AFCFG PB9 AF function configuration bitse 18 2 PB8_AFCFG PB8 AF function configuration bitse 16 2 PB7_AFCFG PB7 AF function configuration bitse 14 1 PB6_AFCFG PB6 AF function configuration bitse 12 1 PB5_AFCFG PB5 AF function configuration bitse 10 2 PB4_AFCFG PB4 AF function configuration bitse 8 2 PB3_AFCFG PB3 AF function configuration bitse 6 1 PB2_AFCFG PB2 AF function configuration bitse 4 2 PB1_AFCFG PB1 AF function configuration bitse 2 2 PB0_AFCFG PB0 AF function configuration bitse 0 1 PCFC PCFC AFIO port configuration register C 0x44 0x20 read-write 0x00000000 PC12_AFCFG PC12 AF function configuration bitse 24 1 PC11_AFCFG PC11 AF function configuration bitse 22 2 PC10_AFCFG PC10 AF function configuration bitse 20 1 PC9_AFCFG PC9 AF function configuration bitse 18 2 PC8_AFCFG PC8 AF function configuration bitse 16 2 PC7_AFCFG PC7 AF function configuration bitse 14 2 PC6_AFCFG PC6 AF function configuration bitse 12 2 PC3_AFCFG PC3 AF function configuration bitse 6 1 PC2_AFCFG PC2 AF function configuration bitse 4 2 PC0_AFCFG PC0 AF function configuration bitse 0 1 PCFD PCFD AFIO port configuration register D 0x48 0x20 read-write 0x00000000 PD5_AFCFG PD5 AF function configuration bitse 10 1 PD4_AFCFG PD4 AF function configuration bitse 8 1 PCFE PCFE AFIO port configuration register E 0x4C 0x20 read-write 0x00000000 PE13_AFCFG PE13 AF function configuration bitse 26 1 PE12_AFCFG PE12 AF function configuration bitse 24 1 PE11_AFCFG PE11 AF function configuration bitse 22 2 PE10_AFCFG PE10 AF function configuration bitse 20 1 PE9_AFCFG PE9 AF function configuration bitse 18 2 PE8_AFCFG PE8 AF function configuration bitse 16 2 PE1_AFCFG PE1 AF function configuration bitse 2 2 PE0_AFCFG PE0 AF function configuration bitse 0 2 PCFG PCFG AFIO port configuration register G 0x54 0x20 read-write 0x00000000 PG14_AFCFG PG14 AF function configuration bitse 28 1 PG13_AFCFG PG13 AF function configuration bitse 26 1 PG12_AFCFG PG12 AF function configuration bitse 24 1 PG11_AFCFG PG11 AF function configuration bitse 22 2 PG10_AFCFG PG10 AF function configuration bitse 20 1 PG9_AFCFG PG9 AF function configuration bitse 18 2 PG7_AFCFG PG7 AF function configuration bitse 14 2 PG6_AFCFG PG6 AF function configuration bitse 12 1 BKP Backup registers BKP 0x40006C00 0x0 0x400 registers Tamper 2 DATA0 DATA0 Backup data register 0 0x4 0x10 read-write 0x0000 DATA Backup data 0 16 DATA1 DATA1 Backup data register 1 0x8 0x10 read-write 0x0000 DATA Backup data 0 16 DATA2 DATA2 Backup data register 2 0xC 0x10 read-write 0x0000 DATA Backup data 0 16 DATA3 DATA3 Backup data register 3 0x10 0x10 read-write 0x0000 DATA Backup data 0 16 DATA4 DATA4 Backup data register 4 0x14 0x10 read-write 0x0000 DATA Backup data 0 16 DATA5 DATA5 Backup data register 5 0x18 0x10 read-write 0x0000 DATA Backup data 0 16 DATA6 DATA6 Backup data register 6 0x1C 0x10 read-write 0x0000 DATA Backup data 0 16 DATA7 DATA7 Backup data register 7 0x20 0x10 read-write 0x0000 DATA Backup data 0 16 DATA8 DATA8 Backup data register 8 0x24 0x10 read-write 0x0000 DATA Backup data 0 16 DATA9 DATA9 Backup data register 9 0x28 0x10 read-write 0x0000 DATA Backup data 0 16 DATA10 DATA10 Backup data register 10 0x40 0x10 read-write 0x0000 DATA Backup data 0 16 DATA11 DATA11 Backup data register 11 0x44 0x10 read-write 0x0000 DATA Backup data 0 16 DATA12 DATA12 Backup data register 12 0x48 0x10 read-write 0x0000 DATA Backup data 0 16 DATA13 DATA13 Backup data register 13 0x4C 0x10 read-write 0x0000 DATA Backup data 0 16 DATA14 DATA14 Backup data register 14 0x50 0x10 read-write 0x0000 DATA Backup data 0 16 DATA15 DATA15 Backup data register 15 0x54 0x10 read-write 0x0000 DATA Backup data 0 16 DATA16 DATA16 Backup data register 16 0x58 0x10 read-write 0x0000 DATA Backup data 0 16 DATA17 DATA17 Backup data register 17 0x5C 0x10 read-write 0x0000 DATA Backup data 0 16 DATA18 DATA18 Backup data register 18 0x60 0x10 read-write 0x0000 DATA Backup data 0 16 DATA19 DATA19 Backup data register 19 0x64 0x10 read-write 0x0000 DATA Backup data 0 16 DATA20 DATA20 Backup data register 20 0x68 0x10 read-write 0x0000 DATA Backup data 0 16 DATA21 DATA21 Backup data register 21 0x6C 0x10 read-write 0x0000 DATA Backup data 0 16 DATA22 DATA22 Backup data register 22 0x70 0x10 read-write 0x0000 DATA Backup data 0 16 DATA23 DATA23 Backup data register 23 0x74 0x10 read-write 0x0000 DATA Backup data 0 16 DATA24 DATA24 Backup data register 24 0x78 0x10 read-write 0x0000 DATA Backup data 0 16 DATA25 DATA25 Backup data register 25 0x7C 0x10 read-write 0x0000 DATA Backup data 0 16 DATA26 DATA26 Backup data register 26 0x80 0x10 read-write 0x0000 DATA Backup data 0 16 DATA27 DATA27 Backup data register 27 0x84 0x10 read-write 0x0000 DATA Backup data 0 16 DATA28 DATA28 Backup data register 28 0x88 0x10 read-write 0x0000 DATA Backup data 0 16 DATA29 DATA29 Backup data register 29 0x8C 0x10 read-write 0x0000 DATA Backup data 0 16 DATA30 DATA30 Backup data register 30 0x90 0x10 read-write 0x0000 DATA Backup data 0 16 DATA31 DATA31 Backup data register 31 0x94 0x10 read-write 0x0000 DATA Backup data 0 16 DATA32 DATA32 Backup data register 32 0x98 0x10 read-write 0x0000 DATA Backup data 0 16 DATA33 DATA33 Backup data register 33 0x9C 0x10 read-write 0x0000 DATA Backup data 0 16 DATA34 DATA34 Backup data register 34 0xA0 0x10 read-write 0x0000 DATA Backup data 0 16 DATA35 DATA35 Backup data register 35 0xA4 0x10 read-write 0x0000 DATA Backup data 0 16 DATA36 DATA36 Backup data register 36 0xA8 0x10 read-write 0x0000 DATA Backup data 0 16 DATA37 DATA37 Backup data register 37 0xAC 0x10 read-write 0x0000 DATA Backup data 0 16 DATA38 DATA38 Backup data register 38 0xB0 0x10 read-write 0x0000 DATA Backup data 0 16 DATA39 DATA39 Backup data register 39 0xB4 0x10 read-write 0x0000 DATA Backup data 0 16 DATA40 DATA40 Backup data register 40 0xB8 0x10 read-write 0x0000 DATA Backup data 0 16 DATA41 DATA41 Backup data register 41 0xBC 0x10 read-write 0x0000 DATA Backup data 0 16 OCTL OCTL RTC signal output control register 0x2C 0x10 read-write 0x0000 CALDIR RTC clock calibration direction 15 1 CCOSEL RTC clock output selection 14 1 ROSEL RTC output selection 9 1 ASOEN RTC alarm or second signal output enable 8 1 COEN RTC clock calibration output enable 7 1 RCCV RTC clock calibration value 0 7 TPCTL TPCTL Tamper pin control register 0x30 0x10 read-write 0x0000 TPAL TAMPER pin active level 1 1 TPEN TAMPER detection enable 0 1 TPCS TPCS Tamper control and status register 0x34 0x10 read-write 0x0000 TIF Tamper interrupt flag 9 1 TEF Tamper event flag 8 1 TPIE Tamper interrupt enable 2 1 TIR Tamper interrupt reset 1 1 TER Tamper event reset 0 1 CAN0 Controller area network CAN 0x40006400 0x0 0x400 registers USBD_HP_CAN0_TX 19 USBD_LP_CAN0_RX0 20 CAN0_RX1 21 CAN0_EWMC 22 CTL CTL Control register 0x0 0x20 read-write 0x00010002 DFZ Debug freeze 16 1 SWRST Software reset 15 1 TTC Time-triggered communication 7 1 ABOR Automatic bus-off recovery 6 1 AWU Automatic wakeup 5 1 ARD Automatic retransmission disable 4 1 RFOD Receive FIFO overwrite disable 3 1 TFO Transmit FIFO order 2 1 SLPWMOD Sleep working mode 1 1 IWMOD Initial working mode 0 1 STAT STAT Status register 0x04 0x20 0x00000C02 RXL RX level 11 1 read-only LASTRX Last sample value of RX pin 10 1 read-only RS Receiving state 9 1 read-only TS Transmitting state 8 1 read-only SLPIF Status change interrupt flag of sleep working mode entering 4 1 read-write WUIF Status change interrupt flag of wakeup from sleep working mode 3 1 read-write ERRIF Error interrupt flag 2 1 read-write SLPWS Sleep working state 1 1 read-only IWS Initial working state 0 1 read-only TSTAT TSTAT Transmit status register 0x8 0x20 0x1C000000 TMLS2 Transmit mailbox 2 last sending in transmit FIFO 31 1 read-only TMLS1 Transmit mailbox 1 last sending in transmit FIFO 30 1 read-only TMLS0 Transmit mailbox 0 last sending in transmit FIFO 29 1 read-only TME2 Transmit mailbox 2 empty 28 1 read-only TME1 Transmit mailbox 1 empty 27 1 read-only TME0 Transmit mailbox 0 empty 26 1 read-only NUM number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty 24 2 read-only MST2 Mailbox 2 stop transmitting 23 1 read-write MTE2 Mailbox 2 transmit error 19 1 read-write MAL2 Mailbox 2 arbitration lost 18 1 read-write MTFNERR2 Mailbox 2 transmit finished and no error 17 1 read-write MTF2 Mailbox 2 transmit finished 16 1 read-write MST1 Mailbox 1 stop transmitting 15 1 read-write MTE1 Mailbox 1 transmit error 11 1 read-write MAL1 Mailbox 1 arbitration lost 10 1 read-write MTFNERR1 Mailbox 1 transmit finished and no error 9 1 read-write MTF1 Mailbox 1 transmit finished 8 1 read-write MST0 Mailbox 0 stop transmitting 7 1 read-write MTE0 Mailbox 0 transmit error 3 1 read-write MAL0 Mailbox 0 arbitration lost 2 1 read-write MTFNERR0 Mailbox 0 transmit finished and no error 1 1 read-write MTF0 Mailbox 0 transmit finished 0 1 read-write RFIFO0 RFIFO0 Receive message FIFO0 register 0x0C 0x20 0x00000000 RFD0 Receive FIFO0 dequeue 5 1 read-write RFO0 Receive FIFO0 overfull 4 1 read-write RFF0 Receive FIFO0 full 3 1 read-write RFL0 Receive FIFO0 length 0 2 read-only RFIFO1 RFIFO1 Receive message FIFO1 register 0x10 0x20 0x00000000 RFD1 Receive FIFO1 dequeue 5 1 read-write RFO1 Receive FIFO1 overfull 4 1 read-write RFF1 Receive FIFO1 full 3 1 read-write RFL1 Receive FIFO1 length 0 2 read-only INTEN INTEN Interrupt enable register 0x14 0x20 read-write 0x00000000 SLPWIE Sleep working interrupt enable 17 1 WIE Wakeup interrupt enable 16 1 ERRIE Error interrupt enable 15 1 ERRNIE Error number interrupt enable 11 1 BOIE Bus-off interrupt enable 10 1 PERRIE Passive error interrupt enable 9 1 WERRIE Warning error interrupt enable 8 1 RFOIE1 Receive FIFO1 overfull interrupt enable 6 1 RFFIE1 Receive FIFO1 full interrupt enable 5 1 RFNEIE1 Receive FIFO1 not empty interrupt enable 4 1 RFOIE0 Receive FIFO0 overfull interrupt enable 3 1 RFFIE0 Receive FIFO0 full interrupt enable 2 1 RFNEIE0 Receive FIFO0 not empty interrupt enable 1 1 TMEIE Transmit mailbox empty interrupt enable 0 1 ERR ERR Error register 0x18 0x20 0x00000000 RECNT Receive Error Count defined by the CAN standard 24 8 read-only TECNT Transmit Error Count defined by the CAN standard 16 8 read-only ERRN Error number 4 3 read-write BOERR Bus-off error 2 1 read-only PERR Passive error 1 1 read-only WERR Warning error 0 1 read-only BT BT Bit timing register 0x1C 0x20 read-write 0x01230000 SCMOD Silent communication mode 31 1 LCMOD Loopback communication mode 30 1 SJW Resynchronization jump width 24 5 BS2 Bit segment 2 20 3 BS1 Bit segment 1 16 4 BAUDPSC Baud rate prescaler 0 10 TMI0 TMI0 Transmit mailbox identifier register 0 0x180 0x20 read-write 0x00000000 SFID_EFID The frame identifier 21 11 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 TEN Transmit enable 0 1 TMP0 TMP0 Transmit mailbox property register 0 0x184 0x20 read-write 0x00000000 TS Time stamp 16 16 TSEN Time stamp enable 8 1 DLENC Data length code 0 4 TMDATA00 TMDATA00 Transmit mailbox data0 register 0x188 0x20 read-write 0x00000000 DB3 Data byte 3 24 8 DB2 Data byte 2 16 8 DB1 Data byte 1 8 8 DB0 Data byte 0 0 8 TMDATA10 TMDATA10 Transmit mailbox data1 register 0x18C 0x20 read-write 0x00000000 DB7 Data byte 7 24 8 DB6 Data byte 6 16 8 DB5 Data byte 5 8 8 DB4 Data byte 4 0 8 TMI1 TMI1 Transmit mailbox identifier register 1 0x190 0x20 read-write 0x00000000 SFID_EFID The frame identifier 21 11 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 TEN Transmit enable 0 1 TMP1 TMP1 Transmit mailbox property register 1 0x194 0x20 read-write 0x00000000 TS Time stamp 16 16 TSEN Time stamp enable 8 1 DLENC Data length code 0 4 TMDATA01 TMDATA01 Transmit mailbox data0 register 0x198 0x20 read-write 0x00000000 DB3 Data byte 3 24 8 DB2 Data byte 2 16 8 DB1 Data byte 1 8 8 DB0 Data byte 0 0 8 TMDATA11 TMDATA11 Transmit mailbox data1 register 0x19C 0x20 read-write 0x00000000 DB7 Data byte 7 24 8 DB6 Data byte 6 16 8 DB5 Data byte 5 8 8 DB4 Data byte 4 0 8 TMI2 TMI2 Transmit mailbox identifier register 2 0x1A0 0x20 read-write 0x00000000 SFID_EFID The frame identifier 21 11 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 TEN Transmit enable 0 1 TMP2 TMP2 Transmit mailbox property register 2 0x1A4 0x20 read-write 0x00000000 TS Time stamp 16 16 TSEN Time stamp enable 8 1 DLENC Data length code 0 4 TMDATA02 TMDATA02 Transmit mailbox data0 register 0x1A8 0x20 read-write 0x00000000 DB3 Data byte 3 24 8 DB2 Data byte 2 16 8 DB1 Data byte 1 8 8 DB0 Data byte 0 0 8 TMDATA12 TMDATA12 Transmit mailbox data1 register 0x1AC 0x20 read-write 0x00000000 DB7 Data byte 7 24 8 DB6 Data byte 6 16 8 DB5 Data byte 5 8 8 DB4 Data byte 4 0 8 RFIFOMI0 RFIFOMI0 Receive FIFO mailbox identifier register 0x1B0 0x20 read-only 0x00000000 SFID_EFID The frame identifier 21 11 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 RFIFOMP0 RFIFOMP0 Receive FIFO0 mailbox property register 0x1B4 0x20 read-only 0x00000000 TS Time stamp 16 16 FI Filtering index 8 8 DLENC Data length code 0 4 RFIFOMDATA00 RFIFOMDATA00 Receive FIFO0 mailbox data0 register 0x1B8 0x20 read-only 0x00000000 DB3 Data byte 3 24 8 DB2 Data byte 2 16 8 DB1 Data byte 1 8 8 DB0 Data byte 0 0 8 RFIFOMDATA10 RFIFOMDATA10 Receive FIFO0 mailbox data1 register 0x1BC 0x20 read-only 0x00000000 DB7 Data byte 7 24 8 DB6 Data byte 6 16 8 DB5 Data byte 5 8 8 DB4 Data byte 4 0 8 RFIFOMI1 RFIFOMI1 Receive FIFO1 mailbox identifier register 0x1C0 0x20 read-only 0x00000000 SFID_EFID The frame identifier 21 11 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 RFIFOMP1 RFIFOMP1 Receive FIFO1 mailbox property register 0x1C4 0x20 read-only 0x00000000 TS Time stamp 16 16 FI Filtering index 8 8 DLENC Data length code 0 4 RFIFOMDATA01 RFIFOMDATA01 Receive FIFO1 mailbox data0 register 0x1C8 0x20 read-only 0x00000000 DB3 Data byte 3 24 8 DB2 Data byte 2 16 8 DB1 Data byte 1 8 8 DB0 Data byte 0 0 8 RFIFOMDATA11 RFIFOMDATA11 Receive FIFO1 mailbox data1 register 0x1CC 0x20 read-only 0x00000000 DB7 Data byte 7 24 8 DB6 Data byte 6 16 8 DB5 Data byte 5 8 8 DB4 Data byte 4 0 8 FCTL FCTL Filter control register 0x200 0x20 read-write 0x2A1C0E01 HBC1F Header bank of CAN1 filter 8 6 FLD Filter lock disable 0 1 FMCFG FMCFG Filter mode configuration register 0x204 0x20 read-write 0x00000000 FMOD27 Filter mode 27 1 FMOD26 Filter mode 26 1 FMOD25 Filter mode 25 1 FMOD24 Filter mode 24 1 FMOD23 Filter mode 23 1 FMOD22 Filter mode 22 1 FMOD21 Filter mode 21 1 FMOD20 Filter mode 20 1 FMOD19 Filter mode 19 1 FMOD18 Filter mode 18 1 FMOD17 Filter mode 17 1 FMOD16 Filter mode 16 1 FMOD15 Filter mode 15 1 FMOD14 Filter mode 14 1 FMOD13 Filter mode 13 1 FMOD12 Filter mode 12 1 FMOD11 Filter mode 11 1 FMOD10 Filter mode 10 1 FMOD9 Filter mode 9 1 FMOD8 Filter mode 8 1 FMOD7 Filter mode 7 1 FMOD6 Filter mode 6 1 FMOD5 Filter mode 5 1 FMOD4 Filter mode 4 1 FMOD3 Filter mode 3 1 FMOD2 Filter mode 2 1 FMOD1 Filter mode 1 1 FMOD0 Filter mode 0 1 FSCFG FSCFG Filter scale configuration register 0x20C 0x20 read-write 0x00000000 FS0 Filter scale configuration 0 1 FS1 Filter scale configuration 1 1 FS2 Filter scale configuration 2 1 FS3 Filter scale configuration 3 1 FS4 Filter scale configuration 4 1 FS5 Filter scale configuration 5 1 FS6 Filter scale configuration 6 1 FS7 Filter scale configuration 7 1 FS8 Filter scale configuration 8 1 FS9 Filter scale configuration 9 1 FS10 Filter scale configuration 10 1 FS11 Filter scale configuration 11 1 FS12 Filter scale configuration 12 1 FS13 Filter scale configuration 13 1 FS14 Filter scale configuration 14 1 FS15 Filter scale configuration 15 1 FS16 Filter scale configuration 16 1 FS17 Filter scale configuration 17 1 FS18 Filter scale configuration 18 1 FS19 Filter scale configuration 19 1 FS20 Filter scale configuration 20 1 FS21 Filter scale configuration 21 1 FS22 Filter scale configuration 22 1 FS23 Filter scale configuration 23 1 FS24 Filter scale configuration 24 1 FS25 Filter scale configuration 25 1 FS26 Filter scale configuration 26 1 FS27 Filter scale configuration 27 1 FAFIFO FAFIFO Filter associated FIFO register 0x214 0x20 read-write 0x00000000 FAF0 Filter 0 associated with FIFO 0 1 FAF1 Filter 1 associated with FIFO 1 1 FAF2 Filter 2 associated with FIFO 2 1 FAF3 Filter 3 associated with FIFO 3 1 FAF4 Filter 4 associated with FIFO 4 1 FAF5 Filter 5 associated with FIFO 5 1 FAF6 Filter 6 associated with FIFO 6 1 FAF7 Filter 7 associated with FIFO 7 1 FAF8 Filter 8 associated with FIFO 8 1 FAF9 Filter 9 associated with FIFO 9 1 FAF10 Filter 10 associated with FIFO 10 1 FAF11 Filter 11 associated with FIFO 11 1 FAF12 Filter 12 associated with FIFO 12 1 FAF13 Filter 13 associated with FIFO 13 1 FAF14 Filter 14 associated with FIFO 14 1 FAF15 Filter 15 associated with FIFO 15 1 FAF16 Filter 16 associated with FIFO 16 1 FAF17 Filter 17 associated with FIFO 17 1 FAF18 Filter 18 associated with FIFO 18 1 FAF19 Filter 19 associated with FIFO 19 1 FAF20 Filter 20 associated with FIFO 20 1 FAF21 Filter 21 associated with FIFO 21 1 FAF22 Filter 22 associated with FIFO 22 1 FAF23 Filter 23 associated with FIFO 23 1 FAF24 Filter 24 associated with FIFO 24 1 FAF25 Filter 25 associated with FIFO 25 1 FAF26 Filter 26 associated with FIFO 26 1 FAF27 Filter 27 associated with FIFO 27 1 FW FW Filter working register 0x21C 0x20 read-write 0x00000000 FW0 Filter working 0 1 FW1 Filter working 1 1 FW2 Filter working 2 1 FW3 Filter working 3 1 FW4 Filter working 4 1 FW5 Filter working 5 1 FW6 Filter working 6 1 FW7 Filter working 7 1 FW8 Filter working 8 1 FW9 Filter working 9 1 FW10 Filter working 10 1 FW11 Filter working 11 1 FW12 Filter working 12 1 FW13 Filter working 13 1 FW14 Filter working 14 1 FW15 Filter working 15 1 FW16 Filter working 16 1 FW17 Filter working 17 1 FW18 Filter working 18 1 FW19 Filter working 19 1 FW20 Filter working 20 1 FW21 Filter working 21 1 FW22 Filter working 22 1 FW23 Filter working 23 1 FW24 Filter working 24 1 FW25 Filter working 25 1 FW26 Filter working 26 1 FW27 Filter working 27 1 F0DATA0 F0DATA0 Filter 0 data 0 register 0x240 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F0DATA1 F0DATA1 Filter 0 data 1 register 0x244 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F1DATA0 F1DATA0 Filter 1 data 0 register 0x248 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F1DATA1 F1DATA1 Filter 1 data 1 register 0x24C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F2DATA0 F2DATA0 Filter 2 data 0 register 0x250 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F2DATA1 F2DATA1 Filter 2 data 1 register 0x254 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F3DATA0 F3DATA0 Filter 3 data 0 register 0x258 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F3DATA1 F3DATA1 Filter 3 data 1 register 0x25C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F4DATA0 F4DATA0 Filter 4 data 0 register 0x260 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F4DATA1 F4DATA1 Filter 4 data 1 register 0x264 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F5DATA0 F5DATA0 Filter 5 data 0 register 0x268 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F5DATA1 F5DATA1 Filter 5 data 1 register 0x26C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F6DATA0 F6DATA0 Filter 6 data 0 register 0x270 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F6DATA1 F6DATA1 Filter 6 data 1 register 0x274 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F7DATA0 F7DATA0 Filter 7 data 0 register 0x278 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F7DATA1 F7DATA1 Filter 7 data 1 register 0x27C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F8DATA0 F8DATA0 Filter 8 data 0 register 0x280 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F8DATA1 F8DATA1 Filter 8 data 1 register 0x284 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F9DATA0 F9DATA0 Filter 9 data 0 register 0x288 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F9DATA1 F9DATA1 Filter 9 data 1 register 0x28C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F10DATA0 F10DATA0 Filter 10 data 0 register 0x290 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F10DATA1 F10DATA1 Filter 10 data 1 register 0x294 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F11DATA0 F11DATA0 Filter 11 data 0 register 0x298 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F11DATA1 F11DATA1 Filter 11 data 1 register 0x29C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F12DATA0 F12DATA0 Filter 12 data 0 register 0x2A0 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F12DATA1 F12DATA1 Filter 12 data 1 register 0x2A4 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F13DATA0 F13DATA0 Filter 13 data 0 register 0x2A8 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F13DATA1 F13DATA1 Filter 13 data 1 register 0x2AC 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F14DATA0 F14DATA0 Filter 14 data 0 register 0x2B0 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F14DATA1 F14DATA1 Filter 14 data 1 register 0x2B4 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F15DATA0 F15DATA0 Filter 15 data 0 register 0x2B8 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F15DATA1 F15DATA1 Filter 15 data 1 register 0x2BC 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F16DATA0 F16DATA0 Filter 16 data 0 register 0x2C0 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F16DATA1 F16DATA1 Filter 16 data 1 register 0x2C4 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F17DATA0 F17DATA0 Filter 17 data 0 register 0x2C8 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F17DATA1 F17DATA1 Filter 17 data 1 register 0x2CC 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F18DATA0 F18DATA0 Filter 18 data 0 register 0x2D0 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F18DATA1 F18DATA1 Filter 18 data 1 register 0x2D4 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F19DATA0 F19DATA0 Filter 19 data 0 register 0x2D8 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F19DATA1 F19DATA1 Filter 19 data 1 register 0x2DC 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F20DATA0 F20DATA0 Filter 20 data 0 register 0x2E0 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F20DATA1 F20DATA1 Filter 20 data 1 register 0x2E4 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F21DATA0 F21DATA0 Filter 21 data 0 register 0x2E8 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F21DATA1 F21DATA1 Filter 21 data 1 register 0x2EC 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F22DATA0 F22DATA0 Filter 22 data 0 register 0x2F0 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F22DATA1 F22DATA1 Filter 22 data 1 register 0x2F4 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F23DATA0 F23DATA0 Filter 23 data 0 register 0x2F8 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F23DATA1 F23DATA1 Filter 23 data 1 register 0x2FC 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F24DATA0 F24DATA0 Filter 24 data 0 register 0x300 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F24DATA1 F24DATA1 Filter 24 data 1 register 0x304 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F25DATA0 F25DATA0 Filter 25 data 0 register 0x308 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F25DATA1 F25DATA1 Filter 25 data 1 register 0x30C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F26DATA0 F26DATA0 Filter 26 data 0 register 0x310 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F26DATA1 F26DATA1 Filter 26 data 1 register 0x314 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F27DATA0 F27DATA0 Filter 27 data 0 register 0x318 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F27DATA1 F27DATA1 Filter 27 data 1 register 0x31C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 CAN1 Controller area network CAN 0x40006800 0x0 0x400 registers CAN1_TX 63 CAN1_RX0 64 CAN1_RX1 65 CAN1_EWMC 66 CTL CTL Control register 0x0 0x20 read-write 0x00010002 DFZ Debug freeze 16 1 SWRST Software reset 15 1 TTC Time-triggered communication 7 1 ABOR Automatic bus-off recovery 6 1 AWU Automatic wakeup 5 1 ARD Automatic retransmission disable 4 1 RFOD Receive FIFO overwrite disable 3 1 TFO Transmit FIFO order 2 1 SLPWMOD Sleep working mode 1 1 IWMOD Initial working mode 0 1 STAT STAT Status register 0x04 0x20 0x00000C02 RXL RX level 11 1 read-only LASTRX Last sample value of RX pin 10 1 read-only RS Receiving state 9 1 read-only TS Transmitting state 8 1 read-only SLPIF Status change interrupt flag of sleep working mode entering 4 1 read-write WUIF Status change interrupt flag of wakeup from sleep working mode 3 1 read-write ERRIF Error interrupt flag 2 1 read-write SLPWS Sleep working state 1 1 read-only IWS Initial working state 0 1 read-only TSTAT TSTAT Transmit status register 0x8 0x20 0x1C000000 TMLS2 Transmit mailbox 2 last sending in transmit FIFO 31 1 read-only TMLS1 Transmit mailbox 1 last sending in transmit FIFO 30 1 read-only TMLS0 Transmit mailbox 0 last sending in transmit FIFO 29 1 read-only TME2 Transmit mailbox 2 empty 28 1 read-only TME1 Transmit mailbox 1 empty 27 1 read-only TME0 Transmit mailbox 0 empty 26 1 read-only NUM number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty 24 2 read-only MST2 Mailbox 2 stop transmitting 23 1 read-write MTE2 Mailbox 2 transmit error 19 1 read-write MAL2 Mailbox 2 arbitration lost 18 1 read-write MTFNERR2 Mailbox 2 transmit finished and no error 17 1 read-write MTF2 Mailbox 2 transmit finished 16 1 read-write MST1 Mailbox 1 stop transmitting 15 1 read-write MTE1 Mailbox 1 transmit error 11 1 read-write MAL1 Mailbox 1 arbitration lost 10 1 read-write MTFNERR1 Mailbox 1 transmit finished and no error 9 1 read-write MTF1 Mailbox 1 transmit finished 8 1 read-write MST0 Mailbox 0 stop transmitting 7 1 read-write MTE0 Mailbox 0 transmit error 3 1 read-write MAL0 Mailbox 0 arbitration lost 2 1 read-write MTFNERR0 Mailbox 0 transmit finished and no error 1 1 read-write MTF0 Mailbox 0 transmit finished 0 1 read-write RFIFO0 RFIFO0 Receive message FIFO0 register 0x0C 0x20 0x00000000 RFD0 Receive FIFO0 dequeue 5 1 read-write RFO0 Receive FIFO0 overfull 4 1 read-write RFF0 Receive FIFO0 full 3 1 read-write RFL0 Receive FIFO0 length 0 2 read-only RFIFO1 RFIFO1 Receive message FIFO1 register 0x10 0x20 0x00000000 RFD1 Receive FIFO1 dequeue 5 1 read-write RFO1 Receive FIFO1 overfull 4 1 read-write RFF1 Receive FIFO1 full 3 1 read-write RFL1 Receive FIFO1 length 0 2 read-only INTEN INTEN Interrupt enable register 0x14 0x20 read-write 0x00000000 SLPWIE Sleep working interrupt enable 17 1 WIE Wakeup interrupt enable 16 1 ERRIE Error interrupt enable 15 1 ERRNIE Error number interrupt enable 11 1 BOIE Bus-off interrupt enable 10 1 PERRIE Passive error interrupt enable 9 1 WERRIE Warning error interrupt enable 8 1 RFOIE1 Receive FIFO1 overfull interrupt enable 6 1 RFFIE1 Receive FIFO1 full interrupt enable 5 1 RFNEIE1 Receive FIFO1 not empty interrupt enable 4 1 RFOIE0 Receive FIFO0 overfull interrupt enable 3 1 RFFIE0 Receive FIFO0 full interrupt enable 2 1 RFNEIE0 Receive FIFO0 not empty interrupt enable 1 1 TMEIE Transmit mailbox empty interrupt enable 0 1 ERR ERR Error register 0x18 0x20 0x00000000 RECNT Receive Error Count defined by the CAN standard 24 8 read-only TECNT Transmit Error Count defined by the CAN standard 16 8 read-only ERRN Error number 4 3 read-write BOERR Bus-off error 2 1 read-only PERR Passive error 1 1 read-only WERR Warning error 0 1 read-only BT BT Bit timing register 0x1C 0x20 read-write 0x01230000 SCMOD Silent communication mode 31 1 LCMOD Loopback communication mode 30 1 SJW Resynchronization jump width 24 5 BS2 Bit segment 2 20 3 BS1 Bit segment 1 16 4 BAUDPSC Baud rate prescaler 0 10 TMI0 TMI0 Transmit mailbox identifier register 0 0x180 0x20 read-write 0x00000000 SFID_EFID The frame identifier 21 11 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 TEN Transmit enable 0 1 TMP0 TMP0 Transmit mailbox property register 0 0x184 0x20 read-write 0x00000000 TS Time stamp 16 16 TSEN Time stamp enable 8 1 DLENC Data length code 0 4 TMDATA00 TMDATA00 Transmit mailbox data0 register 0x188 0x20 read-write 0x00000000 DB3 Data byte 3 24 8 DB2 Data byte 2 16 8 DB1 Data byte 1 8 8 DB0 Data byte 0 0 8 TMDATA10 TMDATA10 Transmit mailbox data1 register 0x18C 0x20 read-write 0x00000000 DB7 Data byte 7 24 8 DB6 Data byte 6 16 8 DB5 Data byte 5 8 8 DB4 Data byte 4 0 8 TMI1 TMI1 Transmit mailbox identifier register 1 0x190 0x20 read-write 0x00000000 SFID_EFID The frame identifier 21 11 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 TEN Transmit enable 0 1 TMP1 TMP1 Transmit mailbox property register 1 0x194 0x20 read-write 0x00000000 TS Time stamp 16 16 TSEN Time stamp enable 8 1 DLENC Data length code 0 4 TMDATA01 TMDATA01 Transmit mailbox data0 register 0x198 0x20 read-write 0x00000000 DB3 Data byte 3 24 8 DB2 Data byte 2 16 8 DB1 Data byte 1 8 8 DB0 Data byte 0 0 8 TMDATA11 TMDATA11 Transmit mailbox data1 register 0x19C 0x20 read-write 0x00000000 DB7 Data byte 7 24 8 DB6 Data byte 6 16 8 DB5 Data byte 5 8 8 DB4 Data byte 4 0 8 TMI2 TMI2 Transmit mailbox identifier register 2 0x1A0 0x20 read-write 0x00000000 SFID_EFID The frame identifier 21 11 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 TEN Transmit enable 0 1 TMP2 TMP2 Transmit mailbox property register 2 0x1A4 0x20 read-write 0x00000000 TS Time stamp 16 16 TSEN Time stamp enable 8 1 FDF CAN FD frame flag 7 1 BRS Bit rate of data switch 5 1 ESI Error status indicator 4 1 DLENC Data length code 0 4 TMDATA02 TMDATA02 Transmit mailbox data0 register 0x1A8 0x20 read-write 0x00000000 DB3 Data byte 3 24 8 DB2 Data byte 2 16 8 DB1 Data byte 1 8 8 DB0 Data byte 0 0 8 TMDATA12 TMDATA12 Transmit mailbox data1 register 0x1AC 0x20 read-write 0x00000000 DB7 Data byte 7 24 8 DB6 Data byte 6 16 8 DB5 Data byte 5 8 8 DB4 Data byte 4 0 8 RFIFOMI0 RFIFOMI0 Receive FIFO mailbox identifier register 0x1B0 0x20 read-only 0x00000000 SFID_EFID The frame identifier 21 11 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 RFIFOMP0 RFIFOMP0 Receive FIFO0 mailbox property register 0x1B4 0x20 read-only 0x00000000 TS Time stamp 16 16 FI Filtering index 8 8 DLENC Data length code 0 4 RFIFOMDATA00 RFIFOMDATA00 Receive FIFO0 mailbox data0 register 0x1B8 0x20 read-only 0x00000000 DB3 Data byte 3 24 8 DB2 Data byte 2 16 8 DB1 Data byte 1 8 8 DB0 Data byte 0 0 8 RFIFOMDATA10 RFIFOMDATA10 Receive FIFO0 mailbox data1 register 0x1BC 0x20 read-only 0x00000000 DB7 Data byte 7 24 8 DB6 Data byte 6 16 8 DB5 Data byte 5 8 8 DB4 Data byte 4 0 8 RFIFOMI1 RFIFOMI1 Receive FIFO1 mailbox identifier register 0x1C0 0x20 read-only 0x00000000 SFID_EFID The frame identifier 21 11 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 RFIFOMP1 RFIFOMP1 Receive FIFO1 mailbox property register 0x1C4 0x20 read-only 0x00000000 TS Time stamp 16 16 FI Filtering index 8 8 DLENC Data length code 0 4 RFIFOMDATA01 RFIFOMDATA01 Receive FIFO1 mailbox data0 register 0x1C8 0x20 read-only 0x00000000 DB3 Data byte 3 24 8 DB2 Data byte 2 16 8 DB1 Data byte 1 8 8 DB0 Data byte 0 0 8 RFIFOMDATA11 RFIFOMDATA11 Receive FIFO1 mailbox data1 register 0x1CC 0x20 read-only 0x00000000 DB7 Data byte 7 24 8 DB6 Data byte 6 16 8 DB5 Data byte 5 8 8 DB4 Data byte 4 0 8 CAN2 Controller area network CAN 0x4000CC00 0x0 0x400 registers CAN2_TX 78 CAN2_RX0 79 CAN2_RX1 80 CAN2_EWMC 81 CTL CTL Control register 0x0 0x20 read-write 0x00010002 DFZ Debug freeze 16 1 SWRST Software reset 15 1 TTC Time-triggered communication 7 1 ABOR Automatic bus-off recovery 6 1 AWU Automatic wakeup 5 1 ARD Automatic retransmission disable 4 1 RFOD Receive FIFO overwrite disable 3 1 TFO Transmit FIFO order 2 1 SLPWMOD Sleep working mode 1 1 IWMOD Initial working mode 0 1 STAT STAT Status register 0x04 0x20 0x00000C02 RXL RX level 11 1 read-only LASTRX Last sample value of RX pin 10 1 read-only RS Receiving state 9 1 read-only TS Transmitting state 8 1 read-only SLPIF Status change interrupt flag of sleep working mode entering 4 1 read-write WUIF Status change interrupt flag of wakeup from sleep working mode 3 1 read-write ERRIF Error interrupt flag 2 1 read-write SLPWS Sleep working state 1 1 read-only IWS Initial working state 0 1 read-only TSTAT TSTAT Transmit status register 0x8 0x20 0x1C000000 TMLS2 Transmit mailbox 2 last sending in transmit FIFO 31 1 read-only TMLS1 Transmit mailbox 1 last sending in transmit FIFO 30 1 read-only TMLS0 Transmit mailbox 0 last sending in transmit FIFO 29 1 read-only TME2 Transmit mailbox 2 empty 28 1 read-only TME1 Transmit mailbox 1 empty 27 1 read-only TME0 Transmit mailbox 0 empty 26 1 read-only NUM number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty 24 2 read-only MST2 Mailbox 2 stop transmitting 23 1 read-write MTE2 Mailbox 2 transmit error 19 1 read-write MAL2 Mailbox 2 arbitration lost 18 1 read-write MTFNERR2 Mailbox 2 transmit finished and no error 17 1 read-write MTF2 Mailbox 2 transmit finished 16 1 read-write MST1 Mailbox 1 stop transmitting 15 1 read-write MTE1 Mailbox 1 transmit error 11 1 read-write MAL1 Mailbox 1 arbitration lost 10 1 read-write MTFNERR1 Mailbox 1 transmit finished and no error 9 1 read-write MTF1 Mailbox 1 transmit finished 8 1 read-write MST0 Mailbox 0 stop transmitting 7 1 read-write MTE0 Mailbox 0 transmit error 3 1 read-write MAL0 Mailbox 0 arbitration lost 2 1 read-write MTFNERR0 Mailbox 0 transmit finished and no error 1 1 read-write MTF0 Mailbox 0 transmit finished 0 1 read-write RFIFO0 RFIFO0 Receive message FIFO0 register 0x0C 0x20 0x00000000 RFD0 Receive FIFO0 dequeue 5 1 read-write RFO0 Receive FIFO0 overfull 4 1 read-write RFF0 Receive FIFO0 full 3 1 read-write RFL0 Receive FIFO0 length 0 2 read-only RFIFO1 RFIFO1 Receive message FIFO1 register 0x10 0x20 0x00000000 RFD1 Receive FIFO1 dequeue 5 1 read-write RFO1 Receive FIFO1 overfull 4 1 read-write RFF1 Receive FIFO1 full 3 1 read-write RFL1 Receive FIFO1 length 0 2 read-only INTEN INTEN Interrupt enable register 0x14 0x20 read-write 0x00000000 SLPWIE Sleep working interrupt enable 17 1 WIE Wakeup interrupt enable 16 1 ERRIE Error interrupt enable 15 1 ERRNIE Error number interrupt enable 11 1 BOIE Bus-off interrupt enable 10 1 PERRIE Passive error interrupt enable 9 1 WERRIE Warning error interrupt enable 8 1 RFOIE1 Receive FIFO1 overfull interrupt enable 6 1 RFFIE1 Receive FIFO1 full interrupt enable 5 1 RFNEIE1 Receive FIFO1 not empty interrupt enable 4 1 RFOIE0 Receive FIFO0 overfull interrupt enable 3 1 RFFIE0 Receive FIFO0 full interrupt enable 2 1 RFNEIE0 Receive FIFO0 not empty interrupt enable 1 1 TMEIE Transmit mailbox empty interrupt enable 0 1 ERR ERR Error register 0x18 0x20 0x00000000 RECNT Receive Error Count defined by the CAN standard 24 8 read-only TECNT Transmit Error Count defined by the CAN standard 16 8 read-only ERRN Error number 4 3 read-write BOERR Bus-off error 2 1 read-only PERR Passive error 1 1 read-only WERR Warning error 0 1 read-only BT BT Bit timing register 0x1C 0x20 read-write 0x01230000 SCMOD Silent communication mode 31 1 LCMOD Loopback communication mode 30 1 SJW Resynchronization jump width 24 5 BS2 Bit segment 2 20 3 BS1 Bit segment 1 16 4 BAUDPSC Baud rate prescaler 0 10 TMI0 TMI0 Transmit mailbox identifier register 0 0x180 0x20 read-write 0x00000000 SFID_EFID The frame identifier 21 11 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 TEN Transmit enable 0 1 TMP0 TMP0 Transmit mailbox property register 0 0x184 0x20 read-write 0x00000000 TS Time stamp 16 16 TSEN Time stamp enable 8 1 DLENC Data length code 0 4 TMDATA00 TMDATA00 Transmit mailbox data0 register 0x188 0x20 read-write 0x00000000 DB3 Data byte 3 24 8 DB2 Data byte 2 16 8 DB1 Data byte 1 8 8 DB0 Data byte 0 0 8 TMDATA10 TMDATA10 Transmit mailbox data1 register 0x18C 0x20 read-write 0x00000000 DB7 Data byte 7 24 8 DB6 Data byte 6 16 8 DB5 Data byte 5 8 8 DB4 Data byte 4 0 8 TMI1 TMI1 Transmit mailbox identifier register 1 0x190 0x20 read-write 0x00000000 SFID_EFID The frame identifier 21 11 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 TEN Transmit enable 0 1 TMP1 TMP1 Transmit mailbox property register 1 0x194 0x20 read-write 0x00000000 TS Time stamp 16 16 TSEN Time stamp enable 8 1 DLENC Data length code 0 4 TMDATA01 TMDATA01 Transmit mailbox data0 register 0x198 0x20 read-write 0x00000000 DB3 Data byte 3 24 8 DB2 Data byte 2 16 8 DB1 Data byte 1 8 8 DB0 Data byte 0 0 8 TMDATA11 TMDATA11 Transmit mailbox data1 register 0x19C 0x20 read-write 0x00000000 DB7 Data byte 7 24 8 DB6 Data byte 6 16 8 DB5 Data byte 5 8 8 DB4 Data byte 4 0 8 TMI2 TMI2 Transmit mailbox identifier register 2 0x1A0 0x20 read-write 0x00000000 SFID_EFID The frame identifier 21 11 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 TEN Transmit enable 0 1 TMP2 TMP2 Transmit mailbox property register 2 0x1A4 0x20 read-write 0x00000000 TS Time stamp 16 16 TSEN Time stamp enable 8 1 FDF CAN FD frame flag 7 1 BRS Bit rate of data switch 5 1 ESI Error status indicator 4 1 DLENC Data length code 0 4 TMDATA02 TMDATA02 Transmit mailbox data0 register 0x1A8 0x20 read-write 0x00000000 DB3 Data byte 3 24 8 DB2 Data byte 2 16 8 DB1 Data byte 1 8 8 DB0 Data byte 0 0 8 TMDATA12 TMDATA12 Transmit mailbox data1 register 0x1AC 0x20 read-write 0x00000000 DB7 Data byte 7 24 8 DB6 Data byte 6 16 8 DB5 Data byte 5 8 8 DB4 Data byte 4 0 8 RFIFOMI0 RFIFOMI0 Receive FIFO mailbox identifier register 0x1B0 0x20 read-only 0x00000000 SFID_EFID The frame identifier 21 11 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 RFIFOMP0 RFIFOMP0 Receive FIFO0 mailbox property register 0x1B4 0x20 read-only 0x00000000 TS Time stamp 16 16 FI Filtering index 8 8 DLENC Data length code 0 4 RFIFOMDATA00 RFIFOMDATA00 Receive FIFO0 mailbox data0 register 0x1B8 0x20 read-only 0x00000000 DB3 Data byte 3 24 8 DB2 Data byte 2 16 8 DB1 Data byte 1 8 8 DB0 Data byte 0 0 8 RFIFOMDATA10 RFIFOMDATA10 Receive FIFO0 mailbox data1 register 0x1BC 0x20 read-only 0x00000000 DB7 Data byte 7 24 8 DB6 Data byte 6 16 8 DB5 Data byte 5 8 8 DB4 Data byte 4 0 8 RFIFOMI1 RFIFOMI1 Receive FIFO1 mailbox identifier register 0x1C0 0x20 read-only 0x00000000 SFID_EFID The frame identifier 21 11 EFID The frame identifier 3 18 FF Frame format 2 1 FT Frame type 1 1 RFIFOMP1 RFIFOMP1 Receive FIFO1 mailbox property register 0x1C4 0x20 read-only 0x00000000 TS Time stamp 16 16 FI Filtering index 8 8 DLENC Data length code 0 4 RFIFOMDATA01 RFIFOMDATA01 Receive FIFO1 mailbox data0 register 0x1C8 0x20 read-only 0x00000000 DB3 Data byte 3 24 8 DB2 Data byte 2 16 8 DB1 Data byte 1 8 8 DB0 Data byte 0 0 8 RFIFOMDATA11 RFIFOMDATA11 Receive FIFO1 mailbox data1 register 0x1CC 0x20 read-only 0x00000000 DB7 Data byte 7 24 8 DB6 Data byte 6 16 8 DB5 Data byte 5 8 8 DB4 Data byte 4 0 8 FCTL FCTL Filter control register 0x200 0x20 read-write 0x2A1C0E01 FLD Filter lock disable 0 1 FMCFG FMCFG Filter mode configuration register 0x204 0x20 read-write 0x00000000 FMOD13 Filter mode 13 1 FMOD12 Filter mode 12 1 FMOD11 Filter mode 11 1 FMOD10 Filter mode 10 1 FMOD9 Filter mode 9 1 FMOD8 Filter mode 8 1 FMOD7 Filter mode 7 1 FMOD6 Filter mode 6 1 FMOD5 Filter mode 5 1 FMOD4 Filter mode 4 1 FMOD3 Filter mode 3 1 FMOD2 Filter mode 2 1 FMOD1 Filter mode 1 1 FMOD0 Filter mode 0 1 FSCFG FSCFG Filter scale configuration register 0x20C 0x20 read-write 0x00000000 FS0 Filter scale configuration 0 1 FS1 Filter scale configuration 1 1 FS2 Filter scale configuration 2 1 FS3 Filter scale configuration 3 1 FS4 Filter scale configuration 4 1 FS5 Filter scale configuration 5 1 FS6 Filter scale configuration 6 1 FS7 Filter scale configuration 7 1 FS8 Filter scale configuration 8 1 FS9 Filter scale configuration 9 1 FS10 Filter scale configuration 10 1 FS11 Filter scale configuration 11 1 FS12 Filter scale configuration 12 1 FS13 Filter scale configuration 13 1 FAFIFO FAFIFO Filter associated FIFO register 0x214 0x20 read-write 0x00000000 FAF0 Filter 0 associated with FIFO 0 1 FAF1 Filter 1 associated with FIFO 1 1 FAF2 Filter 2 associated with FIFO 2 1 FAF3 Filter 3 associated with FIFO 3 1 FAF4 Filter 4 associated with FIFO 4 1 FAF5 Filter 5 associated with FIFO 5 1 FAF6 Filter 6 associated with FIFO 6 1 FAF7 Filter 7 associated with FIFO 7 1 FAF8 Filter 8 associated with FIFO 8 1 FAF9 Filter 9 associated with FIFO 9 1 FAF10 Filter 10 associated with FIFO 10 1 FAF11 Filter 11 associated with FIFO 11 1 FAF12 Filter 12 associated with FIFO 12 1 FAF13 Filter 13 associated with FIFO 13 1 FW FW Filter working register 0x21C 0x20 read-write 0x00000000 FW0 Filter working 0 1 FW1 Filter working 1 1 FW2 Filter working 2 1 FW3 Filter working 3 1 FW4 Filter working 4 1 FW5 Filter working 5 1 FW6 Filter working 6 1 FW7 Filter working 7 1 FW8 Filter working 8 1 FW9 Filter working 9 1 FW10 Filter working 10 1 FW11 Filter working 11 1 FW12 Filter working 12 1 FW13 Filter working 13 1 F0DATA0 F0DATA0 Filter 0 data 0 register 0x240 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F0DATA1 F0DATA1 Filter 0 data 1 register 0x244 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F1DATA0 F1DATA0 Filter 1 data 0 register 0x248 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F1DATA1 F1DATA1 Filter 1 data 1 register 0x24C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F2DATA0 F2DATA0 Filter 2 data 0 register 0x250 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F2DATA1 F2DATA1 Filter 2 data 1 register 0x254 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F3DATA0 F3DATA0 Filter 3 data 0 register 0x258 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F3DATA1 F3DATA1 Filter 3 data 1 register 0x25C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F4DATA0 F4DATA0 Filter 4 data 0 register 0x260 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F4DATA1 F4DATA1 Filter 4 data 1 register 0x264 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F5DATA0 F5DATA0 Filter 5 data 0 register 0x268 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F5DATA1 F5DATA1 Filter 5 data 1 register 0x26C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F6DATA0 F6DATA0 Filter 6 data 0 register 0x270 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F6DATA1 F6DATA1 Filter 6 data 1 register 0x274 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F7DATA0 F7DATA0 Filter 7 data 0 register 0x278 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F7DATA1 F7DATA1 Filter 7 data 1 register 0x27C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F8DATA0 F8DATA0 Filter 8 data 0 register 0x280 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F8DATA1 F8DATA1 Filter 8 data 1 register 0x284 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F9DATA0 F9DATA0 Filter 9 data 0 register 0x288 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F9DATA1 F9DATA1 Filter 9 data 1 register 0x28C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F10DATA0 F10DATA0 Filter 10 data 0 register 0x290 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F10DATA1 F10DATA1 Filter 10 data 1 register 0x294 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F11DATA0 F11DATA0 Filter 11 data 0 register 0x298 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F11DATA1 F11DATA1 Filter 11 data 1 register 0x29C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F12DATA0 F12DATA0 Filter 12 data 0 register 0x2A0 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F12DATA1 F12DATA1 Filter 12 data 1 register 0x2A4 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F13DATA0 F13DATA0 Filter 13 data 0 register 0x2A8 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F13DATA1 F13DATA1 Filter 13 data 1 register 0x2AC 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 CMP Comparator CMP 0x40017C00 0x0 0x400 registers CMP1_CS CMP1_CS CMP1 control and status register 0x20 0x20 0x00000000 CMP1EN Comparator 1 enable 0 1 read-write CMP1MSEL Comparator 1 input selection 4 3 read-write CMP1OSEL Comparator 1 output selection 10 4 read-write CMP1PL Polarity of comparator 1 output 15 1 read-write CMP1BLK CMP1 output blanking source 18 3 read-write CMP1MSEL_3 CMP1_IM input selection 22 1 read-write CMP1O CMP1 output 30 1 read-only CMP1LK Comparator 1 lock 31 1 read-write CMP3_CS CMP3_CS CMP3 control and status register 0x28 0x20 0x00000000 CMP3EN Comparator 3 enable 0 1 read-write CMP3MSEL Comparator 3 input selection 4 3 read-write CMP3OSEL Comparator 3 output selection 10 4 read-write CMP3PL Polarity of comparator 3 output 15 1 read-write CMP3BLK CMP3 output blanking source 18 3 read-write CMP3MSEL_3 CMP3_IM input selection 22 1 read-write CMP3O CMP3 output 30 1 read-only CMP3LK Comparator 3 lock 31 1 read-write CMP5_CS CMP5_CS CMP5 control and status register 0x30 0x20 0x00000000 CMP5EN Comparator 5 enable 0 1 read-write CMP5MSEL Comparator 5 input selection 4 3 read-write CMP5OSEL Comparator 5 output selection 10 4 read-write CMP5PL Polarity of comparator 5 output 15 1 read-write CMP5BLK CMP5 output blanking source 18 3 read-write CMP5MSEL_3 CMP5_IM input selection 22 1 read-write CMP5O CMP5 output 30 1 read-only CMP5LK Comparator 5 lock 31 1 read-write CRC cyclic redundancy check calculation unit CRC 0x40023000 0x0 0x400 registers DATA DATA Data register 0x0 0x20 read-write 0xFFFFFFFF DATA CRC calculation result bits 0 32 04294967295 FDATA FDATA Free data register 0x04 0x20 read-write 0x00000000 FDATA Free Data Register bits 0 8 0255 CTL CTL Control register 0x08 0x20 read-write 0x00000000 REV_O Reverse output data value in bit order 7 1 REV_I Reverse type for input data 5 2 PS Size of polynomial 3 2 RST reset bit 0 1 RSTWwriteResetResets the DATA register to IDATA, with no effect on FDATA1 IDATA IDATA Initialization data register 0x10 0x20 read-write 0xFFFFFFFF IDATA Configurable initial CRC data value 0 32 POLY POLY Polynomial register 0x14 0x20 read-write 0x04C11DB7 POLY User configurable polynomial value 0 32 CTC Clock trim controller CTC 0x4000C800 0x0 0x400 registers RCU_CTC 5 CTL0 CTL0 Control register 0 0x0 0x20 read-write 0x00002000 CKOKIE Clock trim ok interrupt enable 0 1 CKWARNIE Clock trim warning interrupt enable 1 1 ERRIE Error interrupt enable 2 1 EREFIE EREFIF interrupt enable 3 1 CNTEN CTC counter enable 5 1 AUTOTRIM Hardware automatically trim mode 6 1 SWREFPUL Software reference source sync pulse 7 1 TRIMVALUE IRC48M trim value 8 6 CTL1 CTL1 Control register 1 0x04 0x20 read-write 0x2022BB7F REFPOL Reference signal source polarity 31 1 REFSEL Reference signal source selection 28 2 REFPSC Reference signal source prescaler 24 3 CKLIM Clock trim base limit value 16 8 RLVALUE CTC counter reload value 0 16 STAT STAT Status register 0x08 0x20 read-only 0x00000000 CKOKIF Clock trim OK interrupt flag 0 1 CKWARNIF Clock trim warning interrupt flag 1 1 ERRIF Error interrupt flag 2 1 EREFIF Expect reference interrupt flag 3 1 CKERR Clock trim error bit 8 1 REFMISS Reference sync pulse miss 9 1 TRIMERR Trim value error bit 10 1 REFDIR CTC trim counter direction when reference sync pulse 15 1 REFCAP CTC counter capture when reference sync pulse 16 16 INTC INTC Interrupt clear register 0x0c 0x20 write-only 0x00000000 CKOKIC CKOKIF interrupt clear bit 0 1 CKWARNIC CKWARNIF interrupt clear bit 1 1 ERRIC ERRIF interrupt clear bit 2 1 EREFIC EREFIF interrupt clear bit 3 1 DAC Digital-to-analog converter DAC 0x40007400 0x0 0x400 registers CTL0 CTL0 control register 0 0x0 0x20 read-write 0x00000000 DEN0 DAC0 enable 0 1 DBOFF0 DAC0 output buffer turn off 1 1 DTEN0 DAC0 trigger enable 2 1 DTSEL0 DAC0 trigger selection 3 3 DWM0 DAC0 noise wave mode 6 2 DWBW0 DAC0 noise wave bit width 8 4 DDMAEN0 DAC0 DMA enable 12 1 DDUDRIE0 DAC_OUT0 DMA underrun interrupt enable 13 1 DTSEL0_3 DAC_OUT0 trigger selection bit[3], refer to DTSEL0[2:0] 14 1 DEN1 DAC1 enable 16 1 DBOFF1 DAC1 output buffer turn off 17 1 DTEN1 DAC1 trigger enable 18 1 DTSEL1 DAC1 trigger selection 19 3 DWM1 DAC1 noise wave mode 22 2 DWBW1 DAC1 noise wave bit width 24 4 DDMAEN1 DAC1 DMA enable 28 1 DDUDRIE1 DAC_OUT1 DMA underrun interrupt enable 29 1 DTSEL1_3 DAC_OUT1 trigger selection bit[3], refer to DTSEL1[2:0] 30 1 SWT SWT software trigger register 0x04 0x20 write-only 0x00000000 SWTR0 DAC0 software trigger 0 1 SWTR1 DAC1 software trigger 1 1 OUT0_R12DH OUT0_R12DH DAC_OUT0 12-bit right-aligned data holding register 0x08 0x20 read-write 0x00000000 OUT0_DH DAC_OUT0 12-bit right-aligned data 0 12 OUT0_L12DH OUT0_L12DH DAC_OUT0 12-bit left-aligned data holding register 0x0C 0x20 read-write 0x00000000 OUT0_DH DAC_OUT0 12-bit left-aligned data 4 12 OUT0_R8DH OUT0_R8DH DAC_OUT0 8-bit right aligned data holding register 0x10 0x20 read-write 0x00000000 OUT0_DH DAC_OUT0 8-bit right-aligned data 0 8 OUT1_R12DH OUT1_R12DH DAC_OUT1 12-bit right-aligned data holding register 0x14 0x20 read-write 0x00000000 OUT1_DH DAC_OUT1 12-bit right-aligned data 0 12 OUT1_L12DH OUT1_L12DH DAC_OUT1 12-bit left aligned data holding register 0x18 0x20 read-write 0x00000000 OUT1_DH DAC_OUT1 12-bit left-aligned data 4 12 OUT1_R8DH OUT1_R8DH DAC_OUT1 8-bit right aligned data holding register 0x1C 0x20 read-write 0x00000000 OUT1_DH DAC_OUT1 8-bit right-aligned data 0 8 DACC_R12DH DACC_R12DH DAC concurrent mode 12-bit right-aligned data holding register 0x20 0x20 read-write 0x00000000 OUT0_DH DAC_OUT0 12-bit right-aligned data 0 12 OUT1_DH DAC_OUT1 12-bit right-aligned data 16 12 DACC_L12DH DACC_L12DH DAC concurrent mode 12-bit left aligned data holding register 0x24 0x20 read-write 0x00000000 OUT0_DH DAC_OUT0 12-bit left-aligned data 4 12 OUT1_DH DAC_OUT1 12-bit left-aligned data 20 12 DACC_R8DH DACC_R8DH DAC concurrent mode 8-bit right aligned data holding register 0x28 0x20 read-write 0x00000000 OUT0_DH DAC_OUT0 8-bit right-aligned data 0 8 OUT1_DH DAC_OUT1 8-bit right-aligned data 8 8 OUT0_DO DAC0_DO DAC_OUT0 data output register 0x2C 0x20 read-only 0x00000000 OUT0_DO DAC_OUT0 data output 0 12 OUT1_DO OUT1_DO DAC_OUT1 data output register 0x30 0x20 read-only 0x00000000 OUT1_DO DAC_OUT1 data output 0 12 STAT0 STAT0 DAC Status register 0 0x34 0x20 read-write 0x00000000 DDUDR1 DAC_OUT1 DMA underrun flag 29 1 DDUDR0 DAC_OUT0 DMA underrun flag 13 1 CTL1 CTL1 DAC Control Register 1 0x80 0x20 read-write 0x00000000 FIFOUDRIE1 DAC_OUT1 FIFO underflow interrupt enable 18 1 FIFOOVRIE1 DAC_OUT1 FIFO overflow interrupt enable 17 1 FIFOEN1 DAC_OUT1 data FIFO enable 16 1 FIFOUDRIE0 DAC_OUT0 FIFO underflow interrupt enable 2 1 FIFOOVRIE0 DAC_OUT0 FIFO overflow interrupt enable 1 1 FIFOEN0 DAC_OUT0 data FIFO enable 0 1 STAT1 STAT1 DAC Status register 1 0x84 0x20 0x00000002 FIFONUM1 Number of data in the DAC_OUT1 FIFO 20 3 read-only FIFOUDR1 DAC_OUT1 FIFO underflow flag 19 1 read-write FIFOOVR1 DAC_OUT1 FIFO overflow flag 18 1 read-write FE1 DAC_OUT1 FIFO empty flag 17 1 read-only FF1 DAC_OUT1 FIFO full flag 16 1 read-only FIFONUM0 Number of data in the DAC_OUT0 FIFO 4 3 read-only FIFOUDR0 DAC_OUT0 FIFO underflow flag 3 1 read-write FIFOOVR0 DAC_OUT0 FIFO overflow flag 2 1 read-write FE0 DAC_OUT0 FIFO empty flag 1 1 read-only FF0 DAC_OUT0 FIFO full flag 0 1 read-only DBG Debug support DBG 0xE0044000 0x0 0x400 registers ID ID ID code register 0x0 0x20 read-only 0x00000000 ID_CODE DBG ID code register 0 32 CTL0 CTL0 Control register 0 0x4 0x20 read-write 0x00000000 SLP_HOLD Sleep mode hold register 0 1 DSLP_HOLD Deep-sleep mode hold register 1 1 STB_HOLD Standby mode hold register 2 1 CAN2_HOLD CAN2 hold bit 3 1 TRACE_IOEN Trace pin allocation enable 5 1 TRACE_MODE Trace pin allocation mode 6 2 FWDGT_HOLD FWDGT hold bit 8 1 WWDGT_HOLD WWDGT hold bit 9 1 TIMER0_HOLD TIMER 0 hold bit 10 1 TIMER1_HOLD TIMER 1 hold bit 11 1 TIMER2_HOLD TIMER 2 hold bit 12 1 TIMER3_HOLD TIMER 23 hold bit 13 1 CAN0_HOLD CAN0 hold bit 14 1 I2C0_HOLD I2C0 hold bit 15 1 I2C1_HOLD I2C1 hold bit 16 1 TIMER7_HOLD TIMER7_HOLD 17 1 TIMER4_HOLD TIMER4_HOLD 18 1 TIMER5_HOLD TIMER 5 hold bit 19 1 TIMER6_HOLD TIMER 6 hold bit 20 1 CAN1_HOLD CAN1 hold bit 21 1 I2C2_HOLD I2C2 hold bit 22 1 TIMER11_HOLD TIMER 11 hold bit 25 1 TIMER12_HOLD TIMER 12 hold bit 26 1 TIMER13_HOLD TIMER 13 hold bit 27 1 TIMER8_HOLD TIMER 8 hold bit 28 1 TIMER9_HOLD TIMER 9 hold bit 29 1 TIMER10_HOLD TIMER 10 hold bit 30 1 SHRTIMER_HOLD SHRTIMER hold bit 31 1 DMA0 DMA controller DMA 0x40020000 0x0 0x400 registers DMA0_Channel0 11 DMA0_Channel1 12 DMA0_Channel2 13 DMA0_Channel3 14 DMA0_Channel4 15 DMA0_Channel5 16 DMA0_Channel6 17 INTF INTF Interrupt flag register 0x0 0x20 read-only 0x00000000 GIF0 Global interrupt flag of channel 0 0 1 GIF0read-writeNoEventNo transfer error, half event, complete event0EventA transfer error, half event or complete event has occured1 FTFIF0 Full Transfer finish flag of channe 0 1 1 FTFIF0read-writeNotCompleteNo transfer complete event0CompleteA transfer complete event has occured1 HTFIF0 Half transfer finish flag of channel 0 2 1 HTFIF0read-writeNotHalfNo half transfer event0HalfA half transfer event has occured1 ERRIF0 Error flag of channel 0 3 1 ERRIF0read-writeNoErrorNo transfer error0ErrorA transfer error has occured1 GIF1 Global interrupt flag of channel 1 4 1 FTFIF1 Full Transfer finish flag of channe 1 5 1 HTFIF1 Half transfer finish flag of channel 1 6 1 ERRIF1 Error flag of channel 1 7 1 GIF2 Global interrupt flag of channel 2 8 1 FTFIF2 Full Transfer finish flag of channe 2 9 1 HTFIF2 Half transfer finish flag of channel 2 10 1 ERRIF2 Error flag of channel 2 11 1 GIF3 Global interrupt flag of channel 3 12 1 FTFIF3 Full Transfer finish flag of channe 3 13 1 HTFIF3 Half transfer finish flag of channel 3 14 1 ERRIF3 Error flag of channel 3 15 1 GIF4 Global interrupt flag of channel 4 16 1 FTFIF4 Full Transfer finish flag of channe 4 17 1 HTFIF4 Half transfer finish flag of channel 4 18 1 ERRIF4 Error flag of channel 4 19 1 GIF5 Global interrupt flag of channel 5 20 1 FTFIF5 Full Transfer finish flag of channe 5 21 1 HTFIF5 Half transfer finish flag of channel 5 22 1 ERRIF5 Error flag of channel 5 23 1 GIF6 Global interrupt flag of channel 6 24 1 FTFIF6 Full Transfer finish flag of channe 6 25 1 HTFIF6 Half transfer finish flag of channel 6 26 1 ERRIF6 Error flag of channel 6 27 1 INTC INTC Interrupt flag clear register 0x04 0x20 write-only 0x00000000 GIFC0 Clear global interrupt flag of channel 0 0 1 GIFC0read-writeClearClears the GIF flag in INTF1 FTFIFC0 Clear bit for full transfer finish flag of channel 0 1 1 FTFIFC0read-writeClearClears the FDFIF flag in INTF1 HTFIFC0 Clear bit for half transfer finish flag of channel 0 2 1 HTFIFC0read-writeClearClears the HTFIF flag in INTF1 ERRIFC0 Clear bit for error flag of channel 0 3 1 ERRIFC0read-writeClearClears the ERRIF flag in INTF1 GIFC1 Clear global interrupt flag of channel 1 4 1 FTFIFC1 Clear bit for full transfer finish flag of channel 1 5 1 HTFIFC1 Clear bit for half transfer finish flag of channel 1 6 1 ERRIFC1 Clear bit for error flag of channel 1 7 1 GIFC2 Clear global interrupt flag of channel 2 8 1 FTFIFC2 Clear bit for full transfer finish flag of channel 2 9 1 HTFIFC2 Clear bit for half transfer finish flag of channel 2 10 1 ERRIFC2 Clear bit for error flag of channel 2 11 1 GIFC3 Clear global interrupt flag of channel 3 12 1 FTFIFC3 Clear bit for full transfer finish flag of channel 3 13 1 HTFIFC3 Clear bit for half transfer finish flag of channel 3 14 1 ERRIFC3 Clear bit for error flag of channel 3 15 1 GIFC4 Clear global interrupt flag of channel 4 16 1 FTFIFC4 Clear bit for full transfer finish flag of channel 4 17 1 HTFIFC4 Clear bit for half transfer finish flag of channel 4 18 1 ERRIFC4 Clear bit for error flag of channel 4 19 1 GIFC5 Clear global interrupt flag of channel 5 20 1 FTFIFC5 Clear bit for full transfer finish flag of channel 5 21 1 HTFIFC5 Clear bit for half transfer finish flag of channel 5 22 1 ERRIFC5 Clear bit for error flag of channel 5 23 1 GIFC6 Clear global interrupt flag of channel 6 24 1 FTFIFC6 Clear bit for full transfer finish flag of channel 6 25 1 HTFIFC6 Clear bit for half transfer finish flag of channel 6 26 1 ERRIFC6 Clear bit for error flag of channel 6 27 1 CH0CTL CH0CTL Channel 0 control register 0x08 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for channel full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for channel half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for channel error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer direction 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority level 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to Memory Mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH0CNT CH0CNT Channel 0 counter register 0x0C 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH0PADDR CH0PADDR Channel 0 peripheral base address register 0x10 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH0MADDR CH0MADDR Channel 0 memory base address register 0x14 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH1CTL CH1CTL Channel 1 control register 0x1C 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for channel full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for channel half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for channel error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer direction 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority level 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to Memory Mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH1CNT CH1CNT Channel 1 counter register 0x20 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH1PADDR CH1PADDR Channel 1 peripheral base address register 0x24 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH1MADDR CH1MADDR Channel 1 memory base address register 0x28 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH2CTL CH2CTL Channel 2 control register 0x30 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for channel full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for channel half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for channel error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer direction 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority level 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to Memory Mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH2CNT CH2CNT Channel 2 counter register 0x34 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH2PADDR CH2PADDR Channel 2 peripheral base address register 0x38 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH2MADDR CH2MADDR Channel 2 memory base address register 0x3C 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH3CTL CH3CTL Channel 3 control register 0x44 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for channel full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for channel half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for channel error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer direction 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority level 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to Memory Mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH3CNT CH3CNT Channel 3 counter register 0x48 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH3PADDR CH3PADDR Channel 3 peripheral base address register 0x4C 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH3MADDR CH3MADDR Channel 3 memory base address register 0x50 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH4CTL CH4CTL Channel 4 control register 0x58 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for channel full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for channel half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for channel error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer direction 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority level 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to Memory Mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH4CNT CH4CNT Channel 4 counter register 0x5C 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH4PADDR CH4PADDR Channel 4 peripheral base address register 0x60 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH4MADDR CH4MADDR Channel 4 memory base address register 0x64 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH5CTL CH5CTL Channel 5 control register 0x6C 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for channel full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for channel half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for channel error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer direction 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority level 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to Memory Mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH5CNT CH5CNT Channel 5 counter register 0x70 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH5PADDR CH5PADDR Channel 5 peripheral base address register 0x74 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH5MADDR CH5MADDR Channel 5 memory base address register 0x78 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH6CTL CH6CTL Channel 6 control register 0x80 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for channel full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for channel half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for channel error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer direction 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority level 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to Memory Mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH6CNT CH6CNT Channel 6 counter register 0x84 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH6PADDR CH6PADDR Channel 6 peripheral base address register 0x88 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH6MADDR CH6MADDR Channel 6 memory base address register 0x8C 0x20 read-write 0x00000000 MADDR Memory base address 0 32 DMA1 DMA controller DMA 0x40020400 0x0 0x400 registers DMA1_Channel0 56 DMA1_Channel1 57 DMA1_Channel2 58 DMA1_Channel3_DMA1_Channel4 59 INTF INTF Interrupt flag register 0x0 0x20 read-only 0x00000000 GIF0 Global interrupt flag of channel 0 0 1 GIF0read-writeNoEventNo transfer error, half event, complete event0EventA transfer error, half event or complete event has occured1 FTFIF0 Full Transfer finish flag of channe 0 1 1 FTFIF0read-writeNotCompleteNo transfer complete event0CompleteA transfer complete event has occured1 HTFIF0 Half transfer finish flag of channel 0 2 1 HTFIF0read-writeNotHalfNo half transfer event0HalfA half transfer event has occured1 ERRIF0 Error flag of channel 0 3 1 ERRIF0read-writeNoErrorNo transfer error0ErrorA transfer error has occured1 GIF1 Global interrupt flag of channel 1 4 1 FTFIF1 Full Transfer finish flag of channe 1 5 1 HTFIF1 Half transfer finish flag of channel 1 6 1 ERRIF1 Error flag of channel 1 7 1 GIF2 Global interrupt flag of channel 2 8 1 FTFIF2 Full Transfer finish flag of channe 2 9 1 HTFIF2 Half transfer finish flag of channel 2 10 1 ERRIF2 Error flag of channel 2 11 1 GIF3 Global interrupt flag of channel 3 12 1 FTFIF3 Full Transfer finish flag of channe 3 13 1 HTFIF3 Half transfer finish flag of channel 3 14 1 ERRIF3 Error flag of channel 3 15 1 GIF4 Global interrupt flag of channel 4 16 1 FTFIF4 Full Transfer finish flag of channe 4 17 1 HTFIF4 Half transfer finish flag of channel 4 18 1 ERRIF4 Error flag of channel 4 19 1 INTC INTC Interrupt flag clear register 0x04 0x20 write-only 0x00000000 GIFC0 Clear global interrupt flag of channel 0 0 1 GIFC0read-writeClearClears the GIF flag in INTF1 FTFIFC0 Clear bit for full transfer finish flag of channel 0 1 1 FTFIFC0read-writeClearClears the FDFIF flag in INTF1 HTFIFC0 Clear bit for half transfer finish flag of channel 0 2 1 HTFIFC0read-writeClearClears the HTFIF flag in INTF1 ERRIFC0 Clear bit for error flag of channel 0 3 1 ERRIFC0read-writeClearClears the ERRIF flag in INTF1 GIFC1 Clear global interrupt flag of channel 1 4 1 FTFIFC1 Clear bit for full transfer finish flag of channel 1 5 1 HTFIFC1 Clear bit for half transfer finish flag of channel 1 6 1 ERRIFC1 Clear bit for error flag of channel 1 7 1 GIFC2 Clear global interrupt flag of channel 2 8 1 FTFIFC2 Clear bit for full transfer finish flag of channel 2 9 1 HTFIFC2 Clear bit for half transfer finish flag of channel 2 10 1 ERRIFC2 Clear bit for error flag of channel 2 11 1 GIFC3 Clear global interrupt flag of channel 3 12 1 FTFIFC3 Clear bit for full transfer finish flag of channel 3 13 1 HTFIFC3 Clear bit for half transfer finish flag of channel 3 14 1 ERRIFC3 Clear bit for error flag of channel 3 15 1 GIFC4 Clear global interrupt flag of channel 4 16 1 FTFIFC4 Clear bit for full transfer finish flag of channel 4 17 1 HTFIFC4 Clear bit for half transfer finish flag of channel 4 18 1 ERRIFC4 Clear bit for error flag of channel 4 19 1 CH0CTL CH0CTL Channel 0 control register 0x08 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for channel full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for channel half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for channel error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer direction 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority level 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to Memory Mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH0CNT CH0CNT Channel 0 counter register 0x0C 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH0PADDR CH0PADDR Channel 0 peripheral base address register 0x10 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH0MADDR CH0MADDR Channel 0 memory base address register 0x14 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH1CTL CH1CTL Channel 1 control register 0x1C 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for channel full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for channel half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for channel error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer direction 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority level 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to Memory Mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH1CNT CH1CNT Channel 1 counter register 0x20 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH1PADDR CH1PADDR Channel 1 peripheral base address register 0x24 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH1MADDR CH1MADDR Channel 1 memory base address register 0x28 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH2CTL CH2CTL Channel 2 control register 0x30 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for channel full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for channel half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for channel error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer direction 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority level 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to Memory Mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH2CNT CH2CNT Channel 2 counter register 0x34 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH2PADDR CH2PADDR Channel 2 peripheral base address register 0x38 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH2MADDR CH2MADDR Channel 2 memory base address register 0x3C 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH3CTL CH3CTL Channel 3 control register 0x44 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for channel full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for channel half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for channel error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer direction 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority level 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to Memory Mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH3CNT CH3CNT Channel 3 counter register 0x48 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH3PADDR CH3PADDR Channel 3 peripheral base address register 0x4C 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH3MADDR CH3MADDR Channel 3 memory base address register 0x50 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH4CTL CH4CTL Channel 4 control register 0x58 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for channel full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for channel half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for channel error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer direction 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority level 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to Memory Mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH4CNT CH4CNT Channel 4 counter register 0x5C 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH4PADDR CH4PADDR Channel 4 peripheral base address register 0x60 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH4MADDR CH4MADDR Channel 4 memory base address register 0x64 0x20 read-write 0x00000000 MADDR Memory base address 0 32 ENET_DMA Ethernet: DMA controller operation ENET 0x40029000 0x0 0x60 registers DMA_BCTL DMA_BCTL Ethernet DMA bus control register 0x0 0x20 read-write 0x00020101 SWR Software reset 0 1 DAB DMA Arbitration 1 1 DPSL Descriptor skip length 2 5 DFM Descriptor format mode 7 1 PGBL Programmable burst length 8 6 RTPR RxDMA and TxDMA transfer priority ratio 14 2 FB Fixed burst 16 1 RXDP Rx DMA PGBL 17 6 UIP Use independent PGBL 23 1 FPBL Four times PGBL mode 24 1 AA Address-aligned 25 1 MB Mixed burst 26 1 DMA_TPEN DMA_TPEN Ethernet DMA transmit poll enable register 0x4 0x20 read-write 0x00000000 TPE Transmit poll enable 0 32 DMA_RPEN DMA_RPEN Ethernet DMA receive poll enable register 0x8 0x20 read-write 0x00000000 RPE Receive poll enable 0 32 DMA_RDTADDR DMA_RDTADDR Ethernet DMA receive descriptor table address register 0xC 0x20 read-write 0x00000000 SRT Start address of receive table 0 32 DMA_TDTADDR DMA_TDTADDR Ethernet DMA transmit descriptor table address register 0x10 0x20 read-write 0x00000000 STT Start address of transmit table 0 32 DMA_STAT DMA_STAT Ethernet DMA status register 0x14 0x20 0x00000000 TS Transmit status 0 1 read-write TPS Transmit process stopped status 1 1 read-write TBU Transmit buffer unavailable status 2 1 read-write TJT Transmit jabber timeout status 3 1 read-write RO Receive overflow status 4 1 read-write TU Transmit underflow status 5 1 read-write RS Receive status 6 1 read-write RBU Receive buffer unavailable status 7 1 read-write RPS Receive process stopped status 8 1 read-write RWT Receive watchdog timeout status 9 1 read-write ET Early transmit status 10 1 read-write FBE Fatal bus error status 13 1 read-write ER Early receive status 14 1 read-write AI Abnormal interrupt summary 15 1 read-write NI Normal interrupt summary 16 1 read-write RP Receive process state 17 3 read-only TP Transmit process state 20 3 read-only EB Error bits status 23 3 read-only MSC MSC status 27 1 read-only WUM WUM status 28 1 read-only TST Time stamp trigger status 29 1 read-only DMA_CTL DMA_CTL Ethernet DMA control register 0x18 0x20 read-write 0x00000000 SRE Start/stop receive enable 1 1 OSF Operate on second frame 2 1 RTHC Receive threshold control 3 2 FUF Forward undersized good frames 6 1 FERF Forward error frames 7 1 STE Start/stop transmission enable 13 1 TTHC Transmit threshold control 14 3 FTF Flush transmit FIFO 20 1 TSFD Transmit Store-and-Forward 21 1 DAFRF Disable flushing of received frames 24 1 RSFD Receive Store-and-Forward 25 1 DTCERFD Dropping of TCP/IP checksum error frames disable 26 1 DMA_INTEN DMA_INTEN Ethernet DMA interrupt enable register 0x1C 0x20 read-write 0x00000000 TIE Transmit interrupt enable 0 1 TPSIE Transmit process stopped interrupt enable 1 1 TBUIE Transmit buffer unavailable interrupt enable 2 1 TJTIE Transmit jabber timeout interrupt enable 3 1 ROIE Receive overflow interrupt enable 4 1 TUIE Transmit underflow interrupt enable 5 1 RIE Receive interrupt enable 6 1 RBUIE Receive buffer unavailable interrupt enable 7 1 RPSIE Receive process stopped interrupt enable 8 1 RWTIE receive watchdog timeout interrupt enable 9 1 ETIE Early transmit interrupt enable 10 1 FBEIE Fatal bus error interrupt enable 13 1 ERIE Early receive interrupt enable 14 1 AIE Abnormal interrupt summary enable 15 1 NIE Normal interrupt summary enable 16 1 DMA_MFBOCNT DMA_MFBOCNT Ethernet DMA missed frame and buffer overflow counter register 0x20 0x20 read-only 0x00000000 MSFC Missed frames by the controller 0 16 MSFA Missed frames by the application 17 11 DMA_RSWDC DMA_RSWDC Ethernet DMA receive state watchdog counter register 0x24 0x20 read-write 0x00000000 WDCFRS Watchdog counter for receive status (RS) 0 8 DMA_CTDADDR DMA_CTDADDR DMA current transmit descriptor address register 0x48 0x20 read-only 0x00000000 TDAP transmit descriptor address pointer 0 32 DMA_CRDADDR DMA_CRDADDR Ethernet DMA current receive descriptor address register 0x4C 0x20 read-only 0x00000000 RDAP Receive descriptor address pointer 0 32 DMA_CTBADDR DMA_CTBADDR Ethernet DMA current transmit buffer address register 0x50 0x20 read-only 0x00000000 TBAP Transmit buffer address pointer 0 32 DMA_CRBADDR DMA_CRBADDR Ethernet DMA current receive buffer address register 0x54 0x20 read-only 0x00000000 RBAP receive buffer address pointer 0 32 ENET_MAC_FCTH MAC flow control threshold register ENET 0x40029080 0x00 0x20 registers MAC_FCTH MAC_FCTH Ethernet MAC flow control threshold register 0x00 0x20 read-write 0x00000015 RFA Threshold of active flow control 0 3 RFD Threshold of deactive flow control 4 3 ENET_MAC Ethernet: media access control ENET 0x40028000 0x0 0x100 registers ENET 61 ENET_WKUP 62 MAC_CFG MAC_CFG Ethernet MAC configuration register (MAC_CFG) 0x0 0x20 read-write 0x00008000 REN Receiver enable 2 1 TEN Transmitter enable 3 1 DFC Deferral check 4 1 BOL Back-off limit 5 2 APCD Automatic pad/CRC drop 7 1 RTD Retry disable 9 1 IPFCO IP frame checksum offload 10 1 DPM Duplex mode 11 1 LBM Loopback mode 12 1 ROD Receive own disable 13 1 SPD Fast Ethernet speed 14 1 CSD Carrier sense disable 16 1 IGBS Inter frame gap bit selection 17 3 JBD Jabber disable 22 1 WDD Watchdog disable 23 1 TFCD Type Frame CRC Dropping 25 1 MAC_FRMF MAC_FRMF Ethernet MAC frame filter register (MAC_FRMF) 0x4 0x20 read-write 0x00000000 PM Promiscuous mode 0 1 HUF Hash unicast filter 1 1 HMF Hash multicast filter 2 1 DAIFLT Destination address inverse filtering 3 1 MFD multicast filter disable 4 1 BFRMD Broadcast frames disable 5 1 PCFRM Pass control frames 6 2 SAIFLT Source address inverse filtering 8 1 SAFLT Source address filter 9 1 HPFLT Hash or perfect filter 10 1 FAR Frames all receive 31 1 MAC_HLH MAC_HLH Ethernet MAC hash list high register 0x8 0x20 read-write 0x00000000 HLH Hash list high 0 32 MAC_HLL MAC_HLL Ethernet MAC hash list low register 0xC 0x20 read-write 0x00000000 HLL Hash list low 0 32 MAC_PHY_CTL MAC_PHY_CTL Ethernet MAC PHY control register (MAC_PHY_CTL) 0x10 0x20 read-write 0x00000000 PB PHY busy 0 1 PW PHY write 1 1 CLR Clock range 2 3 PR PHY register 6 5 PA PHY address 11 5 MAC_PHY_DATA MAC_PHY_DATA Ethernet MAC MII data register (MAC_PHY_DATA) 0x14 0x20 read-write 0x00000000 PD PHY data 0 16 MAC_FCTL MAC_FCTL Ethernet MAC flow control register (MAC_FCTL) 0x18 0x20 read-write 0x00000000 FLCB_BKPA Flow control busy/back pressure activate 0 1 TFCEN Transmit flow control enable 1 1 RFCEN Receive flow control enable 2 1 UPFDT Unicast pause frame detect 3 1 PLTS Pause low threshold 4 2 DZQP Disable Zero-quanta pause 7 1 PTM Pause time 16 16 MAC_VLT MAC_VLT Ethernet MAC VLAN tag register (MAC_VLT) 0x1C 0x20 read-write 0x00000000 VLTI VLAN tag identifier (for receive frames) 0 16 VLTC 12-bit VLAN tag comparison 16 1 MAC_RWFF MAC_RWFF Ethernet MAC remote wakeup frame filter register (MAC_RWFF) 0x28 0x20 read-write 0x00000000 MAC_WUM MAC_WUM Ethernet MAC wakeup management register (MAC_WUM) 0x2C 0x20 read-write 0x00000000 PWD Power down 0 1 MPEN Magic Packet enable 1 1 WFEN Wakeup frame enable 2 1 MPKR Magic packet received 5 1 WUFR Wakeup frame received 6 1 GU Global unicast 9 1 WUFFRPR Wakeup frame filter register pointer reset 31 1 MAC_DBG MAC_DBG Ethernet MAC debug register (MAC_DBG) 0x34 0x20 read-only 0x00000000 MRNI MAC receive state not idle 0 1 RXAFS Rx asynchronous FIFO status 1 2 RXFW RxFIFO is writing 4 1 RXFRS RxFIFO read operation status 5 2 RXFS RxFIFO state 8 2 MTNI MAC transmit state not idle 16 1 SOMT Status of MAC transmitter 17 2 PCS Pause condition status 19 1 TXFRS TxFIFO read operation status 20 2 TXFW TxFIFO is writing 22 1 TXFNE TxFIFO not empty flag 24 1 TXFF TxFIFO Full flag 25 1 MAC_INTF MAC_INTF Ethernet MAC interrupt flag register (MAC_INTF) 0x38 0x20 read-only 0x00000000 WUM WUM status 3 1 MSC MSC status 4 1 MSCR MSC receive status 5 1 MSCT MSC transmit status 6 1 TMST Time stamp trigger status 9 1 MAC_INTMSK MAC_INTMSK Ethernet MAC interrupt mask register (MAC_INTMSK) 0x3C 0x20 read-write 0x00000000 WUMIM WUM interrupt mask 3 1 TMSTIM Time stamp trigger interrupt mask 9 1 MAC_ADDR0H MAC_ADDR0H Ethernet MAC address 0 high register (MAC_ADDR0H) 0x40 0x20 0x8000FFFF ADDR0H MAC address0 high 0 16 read-write MO Always 1 31 1 read-write MAC_ADDR0L MAC_ADDR0L Ethernet MAC address 0 low register 0x44 0x20 read-write 0xFFFFFFFF ADDR0L MAC address0 low 0 32 MAC_ADDR1H MAC_ADDR1H Ethernet MAC address 1 high register (MAC_ADDR1H) 0x48 0x20 read-write 0x0000FFFF ADDR1H MAC address1 high 0 16 MB Mask byte 24 6 SAF Source address filter 30 1 AFE Address filter enable 31 1 MAC_ADDR1L MAC_ADDR1L Ethernet MAC address1 low register 0x4C 0x20 read-write 0xFFFFFFFF ADDR1L MAC address1 low 0 32 MAC_ADDR2H MAC_ADDR2H Ethernet MAC address 2 high register (MAC_ADDR2H) 0x50 0x20 read-write 0x0000FFFF ADDR2H Ethernet MAC address 2 high register 0 16 MB Mask byte 24 6 SAF Source address filter 30 1 AFE Address filter enable 31 1 MAC_ADDR2L MAC_ADDR2L Ethernet MAC address 2 low register 0x54 0x20 read-write 0xFFFFFFFF ADDR2L MAC address2 low 0 32 MAC_ADDR3H MAC_ADDR3H Ethernet MAC address 3 high register (MAC_ADDR3H) 0x58 0x20 read-write 0x0000FFFF ADDR3H MAC address3 high 0 16 MB Mask byte 24 6 SAF Source address filter 30 1 AFE Address filter enable 31 1 MAC_ADDR3L MAC_ADDR3L Ethernet MAC address 3 low register 0x5C 0x20 read-write 0xFFFFFFFF ADDR3L MAC address3 low 0 32 ENET_MSC Ethernet: MAC statistics counters ENET 0x40028100 0x0 0x400 registers MSC_CTL MSC_CTL Ethernet MSC control register (MSC_CTL) 0x0 0x20 read-write 0x00000000 CTR Counter reset 0 1 CTSR Counter stop rollover 1 1 RTOR Reset on read 2 1 MCFZ MSC counter freeze 3 1 PMC Preset MSC counter 4 1 write-only AFHPM Almost full or half preset mode 5 1 MSC_RINTF MSC_RINTF Ethernet MSC receive interrupt flag register (MSC_RINTF) 0x4 0x20 read-only 0x00000000 RFCE Received frames CRC error 5 1 RFAE Received frames alignment error 6 1 RGUF Received Good Unicast Frames 17 1 MSC_TINTF MSC_TINTF Ethernet MSC transmit interrupt flag register (MSC_TINTF) 0x8 0x20 read-only 0x00000000 TGFSC Transmitted good frames single collision 14 1 TGFMSC Transmitted good frames more single collision 15 1 TGF Transmitted good frames 21 1 MSC_RINTMSK MSC_RINTMSK Ethernet MSC receive interrupt mask register (MSC_RINTMSK) 0xC 0x20 read-write 0x00000000 RFCEIM Received frame CRC error interrupt mask 5 1 RFAEIM Received frames alignment error interrupt mask 6 1 RGUFIM Received good unicast frames interrupt mask 17 1 MSC_TINTMSK MSC_TINTMSK Ethernet MSC transmit interrupt mask register (MSC_TINTMSK) 0x10 0x20 read-write 0x00000000 TGFSCIM Transmitted good frames single collision interrupt mask 14 1 TGFMSCIM Transmitted good frames more single interrupt collision mask 15 1 TGFIM Transmitted good frames interrupt mask 21 1 MSC_SCCNT MSC_SCCNT Ethernet MSC transmitted good frames after a single collision counter 0x4C 0x20 read-only 0x00000000 SCC Transmitted good frames after a single collision counter 0 32 MSC_MSCCNT MSC_MSCCNT Ethernet MSC transmitted good frames after more than a single collision 0x50 0x20 read-only 0x00000000 MSCC Transmitted good frames after more than a single collision counter 0 32 MSC_TGFCNT MSC_TGFCNT Ethernet MSC transmitted good frames counter register 0x68 0x20 read-only 0x00000000 TGF Transmitted good frames counter 0 32 MSC_RFCECNT MSC_RFCECNT Ethernet MSC received frames with CRC error counter register 0x94 0x20 read-only 0x00000000 RFCER Received frames with CRC error counter 0 32 MSC_RFAECNT MSC_RFAECNT Ethernet MSC received frames with alignment error counter register 0x98 0x20 read-only 0x00000000 RFAER Received frames with alignment error counter 0 32 MSC_RGUFCNT MSC_RGUFCNT MSC received good unicast frames counter register 0xC4 0x20 read-only 0x00000000 RGUF Received good unicast frames counter 0 32 ENET_PTP Ethernet: Precision time protocol ENET 0x40028700 0x0 0x400 registers PTP_TSCTL PTP_TSCTL Ethernet PTP time stamp control register (PTP_TSCTL) 0x0 0x20 read-write 0x00000000 TMSEN Time stamp enable 0 1 TMSFCU Time stamp fine or coarse update 1 1 TMSSTI Time stamp system time initialize 2 1 TMSSTU Time stamp system time update 3 1 TMSITEN Time stamp interrupt trigger enable 4 1 TMSARU Time stamp addend register update 5 1 ARFSEN All received frames snapshot enable 8 1 SCROM Subsecond counter rollover mode 9 1 PFSV PTP frame snooping version 10 1 ESEN Received Ethernet snapshot enable 11 1 IP6SEN Received IPv6 snapshot enable 12 1 IP4SEN Received IPv4 snapshot enable 13 1 ETMSEN Received event type message snapshot enable 14 1 MNMSEN Received master node message snapshot enable 15 1 CKNT Clock node type for time stamp 16 2 MAFEN MAC address filter enable for PTP frame 18 1 PTP_SSINC PTP_SSINC Ethernet PTP subsecond increment register 0x4 0x20 read-write 0x00000000 STMSSI System time subsecond increment 0 8 PTP_TSH PTP_TSH Ethernet PTP time stamp high register 0x8 0x20 read-only 0x00000000 STMS System time second 0 32 PTP_TSL PTP_TSL Ethernet PTP time stamp low register (PTP_TSL) 0xC 0x20 read-only 0x00000000 STMSS System time subseconds 0 31 STS System time sign 31 1 PTP_TSUH PTP_TSUH Ethernet PTP time stamp high update register 0x10 0x20 read-write 0x00000000 TMSUS Time stamp update second 0 32 PTP_TSUL PTP_TSUL Ethernet PTP time stamp low update register (PTP_TSUL) 0x14 0x20 read-write 0x00000000 TMSUSS Time stamp update subseconds 0 31 TMSUPNS Time stamp update positive or negative sign 31 1 PTP_TSADDEND PTP_TSADDEND Ethernet PTP time stamp addend register 0x18 0x20 read-write 0x00000000 TMSA Time stamp addend 0 32 PTP_ETH PTP_ETH Ethernet PTP expected time high register 0x1C 0x20 read-write 0x00000000 ETSH Expected time stamp high 0 32 PTP_ETL PTP_ETL Ethernet PTP expected time low register 0x20 0x20 read-write 0x00000000 ETSL Expected time stamp low 0 32 PTP_TSF PTP_TSF Ethernet PTP time stamp flag register 0x28 0x20 read-only 0x00000000 TSSCO Timestamp second counter overflow 0 1 TTM Target time match 1 1 PTP_PPSCTL PTP_PPSCTL Ethernet PTP PPS control register 0x2C 0x20 read-write 0x00000000 PPSOFC PPS output frequency configure 0 4 EXMC External memory controller EXMC 0xA0000000 0x0 0x1000 registers EXMC 48 SNCTL0 SNCTL0 SRAM/NOR flash control register 0 0x0 0x20 read-write 0x000030DA SYNCWR Synchronous write 19 1 CPS CRAM page size 16 3 ASYNCWAIT Asynchronous wait 15 1 EXMODEN Extended mode enable 14 1 NRWTEN NWAIT signal enable 13 1 WREN Write enable 12 1 NRWTCFG NWAIT signal configuration, only work in synchronous mode 11 1 WRAPEN Wrapped burst mode enable 10 1 NRWTPOL NWAIT signal polarity 9 1 SBRSTEN Synchronous burst enable 8 1 NREN NOR Flash access enable 6 1 NRW NOR bank memory data bus width 4 2 NRTP NOR bank memory type 2 2 NRMUX NOR bank memory address/data multiplexing 1 1 NRBKEN NOR bank enable 0 1 SNTCFG0 SNTCFG0 SRAM/NOR flash timing configuration register 0 0x4 0x20 read-write 0x0FFFFFFF ASYNCMOD Asynchronous access mode 28 2 DLAT Data latency for NOR Flash 24 4 CKDIV Synchronous clock divide ratio 20 4 BUSLAT Bus latency 16 4 DSET Data setup time 8 8 AHLD Address hold time 4 4 ASET Address setup time 0 4 SNCTL1 SNCTL1 SRAM/NOR flash control register 1 0x8 0x20 read-write 0x000030D2 SYNCWR Synchronous write 19 1 CPS CRAM page size 16 3 ASYNCWAIT Asynchronous wait 15 1 EXMODEN Extended mode enable 14 1 NRWTEN NWAIT signal enable 13 1 WREN Write enable 12 1 NRWTCFG NWAIT signal configuration, only work in synchronous mode 11 1 WRAPEN Wrapped burst mode enable 10 1 NRWTPOL NWAIT signal polarity 9 1 SBRSTEN Synchronous burst enable 8 1 NREN NOR Flash access enable 6 1 NRW NOR bank memory data bus width 4 2 NRTP NOR bank memory type 2 2 NRMUX NOR bank memory address/data multiplexing 1 1 NRBKEN NOR bank enable 0 1 SNTCFG1 SNTCFG1 SRAM/NOR flash timing configuration register 1 0xC 0x20 read-write 0x0FFFFFFF ASYNCMOD Asynchronous access mode 28 2 DLAT Data latency for NOR Flash 24 4 CKDIV Synchronous clock divide ratio 20 4 BUSLAT Bus latency 16 4 DSET Data setup time 8 8 AHLD Address hold time 4 4 ASET Address setup time 0 4 SNCTL2 SNCTL2 SRAM/NOR flash control register 2 0x10 0x20 read-write 0x000030D2 SYNCWR Synchronous write 19 1 CPS CRAM page size 16 3 ASYNCWAIT Asynchronous wait 15 1 EXMODEN Extended mode enable 14 1 NRWTEN NWAIT signal enable 13 1 WREN Write enable 12 1 NRWTCFG NWAIT signal configuration, only work in synchronous mode 11 1 WRAPEN Wrapped burst mode enable 10 1 NRWTPOL NWAIT signal polarity 9 1 SBRSTEN Synchronous burst enable 8 1 NREN NOR Flash access enable 6 1 NRW NOR bank memory data bus width 4 2 NRTP NOR bank memory type 2 2 NRMUX NOR bank memory address/data multiplexing 1 1 NRBKEN NOR bank enable 0 1 SNTCFG2 SNTCFG2 SRAM/NOR flash timing configuration register 2 0x14 0x20 read-write 0x0FFFFFFF ASYNCMOD Asynchronous access mode 28 2 DLAT Data latency for NOR Flash 24 4 CKDIV Synchronous clock divide ratio 20 4 BUSLAT Bus latency 16 4 DSET Data setup time 8 8 AHLD Address hold time 4 4 ASET Address setup time 0 4 SNCTL3 SNCTL3 SRAM/NOR flash control register 3 0x18 0x20 read-write 0x000030D2 SYNCWR Synchronous write 19 1 CPS CRAM page size 16 3 ASYNCWAIT Asynchronous wait 15 1 EXMODEN Extended mode enable 14 1 NRWTEN NWAIT signal enable 13 1 WREN Write enable 12 1 NRWTCFG NWAIT signal configuration, only work in synchronous mode 11 1 WRAPEN Wrapped burst mode enable 10 1 NRWTPOL NWAIT signal polarity 9 1 SBRSTEN Synchronous burst enable 8 1 NREN NOR Flash access enable 6 1 NRW NOR bank memory data bus width 4 2 NRTP NOR bank memory type 2 2 NRMUX NOR bank memory address/data multiplexing 1 1 NRBKEN NOR bank enable 0 1 SNTCFG3 SNTCFG3 SRAM/NOR flash timing configuration register 3 0x1C 0x20 read-write 0x0FFFFFFF ASYNCMOD Asynchronous access mode 28 2 DLAT Data latency for NOR Flash 24 4 CKDIV Synchronous clock divide ratio 20 4 BUSLAT Bus latency 16 4 DSET Data setup time 8 8 AHLD Address hold time 4 4 ASET Address setup time 0 4 SNWTCFG0 SNWTCFG0 SRAM/NOR flash write timing configuration register 0 0x104 0x20 read-write 0x0FFFFFFF WASYNCMOD Asynchronous access mode 28 2 WBUSLAT Bus latency 16 4 WDSET Data setup time 8 8 WAHLD Address hold time 4 4 WASET Address setup time 0 4 SNWTCFG1 SNWTCFG1 SRAM/NOR flash write timing configuration register 1 0x10C 0x20 read-write 0x0FFFFFFF WASYNCMOD Asynchronous access mode 28 2 WBUSLAT Bus latency 16 4 WDSET Data setup time 8 8 WAHLD Address hold time 4 4 WASET Address setup time 0 4 SNWTCFG2 SNWTCFG2 SRAM/NOR flash write timing configuration register 2 0x114 0x20 read-write 0x0FFFFFFF WASYNCMOD Asynchronous access mode 28 2 WBUSLAT Bus latency 16 4 WDSET Data setup time 8 8 WAHLD Address hold time 4 4 WASET Address setup time 0 4 SNWTCFG3 SNWTCFG3 SRAM/NOR flash write timing configuration register 3 0x11C 0x20 read-write 0x0FFFFFFF WASYNCMOD Asynchronous access mode 28 2 WBUSLAT Bus latency 16 4 WDSET Data setup time 8 8 WAHLD Address hold time 4 4 WASET Address setup time 0 4 NPCTL1 NPCTL1 NAND flash/PC card control register 1 0x60 0x20 read-write 0x00000018 ECCSZ ECC size 17 3 ATR ALE to RE delay 13 4 CTR CLE to RE delay 9 4 ECCEN ECC enable 6 1 NDW NAND bank memory data bus width 4 2 NDTP NAND bank memory type 3 1 NDBKEN NAND bank enable 2 1 NDWTEN Wait feature enable 1 1 NPCTL2 NPCTL2 NAND flash/PC card control register 2 0x80 0x20 read-write 0x00000018 ECCSZ ECC size 17 3 ATR ALE to RE delay 13 4 CTR CLE to RE delay 9 4 ECCEN ECC enable 6 1 NDW NAND bank memory data bus width 4 2 NDTP NAND bank memory type 3 1 NDBKEN NAND bank enable 2 1 NDWTEN Wait feature enable 1 1 NPCTL3 NPCTL3 NAND flash/PC card control register 3 0xA0 0x20 read-write 0x00000018 ECCSZ ECC size 17 3 ATR ALE to RE delay 13 4 CTR CLE to RE delay 9 4 ECCEN ECC enable 6 1 NDW NAND bank memory data bus width 4 2 NDTP NAND bank memory type 3 1 NDBKEN NAND bank enable 2 1 NDWTEN Wait feature enable 1 1 NPINTEN1 NPINTEN1 NAND flash/PC card interrupt enable register 1 0x64 0x20 read-write 0x00000042 FFEPT FIFO empty flag 6 1 INTFEN Interrupt falling edge detection enable 5 1 INTHEN Interrupt high-level detection enable 4 1 INTREN Interrupt rising edge detection enable bit 3 1 INTFS Interrupt falling edge status 2 1 INTHS Interrupt high-level status 1 1 INTRS Interrupt rising edge status 0 1 NPINTEN2 NPINTEN2 NAND flash/PC card interrupt enable register 2 0x84 0x20 read-write 0x00000042 FFEPT FIFO empty flag 6 1 INTFEN Interrupt falling edge detection enable 5 1 INTHEN Interrupt high-level detection enable 4 1 INTREN Interrupt rising edge detection enable bit 3 1 INTFS Interrupt falling edge status 2 1 INTHS Interrupt high-level status 1 1 INTRS Interrupt rising edge status 0 1 NPINTEN3 NPINTEN3 NAND flash/PC card interrupt enable register 3 0xA4 0x20 read-write 0x00000042 FFEPT FIFO empty flag 6 1 INTFEN Interrupt falling edge detection enable 5 1 INTHEN Interrupt high-level detection enable 4 1 INTREN Interrupt rising edge detection enable bit 3 1 INTFS Interrupt falling edge status 2 1 INTHS Interrupt high-level status 1 1 INTRS Interrupt rising edge status 0 1 NPCTCFG1 NPCTCFG1 NAND flash/PC card common space timing configuration register 1 0x68 0x20 read-write 0xFFFFFFFF COMHIZ Common memory data bus HiZ time 24 8 COMHLD Common memory hold time 16 8 COMWAIT Common memory wait time 8 8 COMSET Common memory setup time 0 8 NPCTCFG2 NPCTCFG2 NAND flash/PC card common space timing configuration register 2 0x88 0x20 read-write 0xFFFFFFFF COMHIZ Common memory data bus HiZ time 24 8 COMHLD Common memory hold time 16 8 COMWAIT Common memory wait time 8 8 COMSET Common memory setup time 0 8 NPCTCFG3 NPCTCFG3 NAND flash/PC card common space timing configuration register 3 0xA8 0x20 read-write 0xFFFFFFFF COMHIZ Common memory data bus HiZ time 24 8 COMHLD Common memory hold time 16 8 COMWAIT Common memory wait time 8 8 COMSET Common memory setup time 0 8 NPATCFG1 NPATCFG1 NAND flash/PC card attribute space timing configuration register 1 0x6C 0x20 read-write 0xFFFFFFFF ATTHIZ Attribute memory data bus HiZ time 24 8 ATTHLD Attribute memory hold time 16 8 ATTWAIT Attribute memory wait time 8 8 ATTSET Attribute memory setup time 0 8 NPATCFG2 NPATCFG2 NAND flash/PC card attribute space timing configuration register 2 0x8C 0x20 read-write 0xFFFFFFFF ATTHIZ Attribute memory data bus HiZ time 24 8 ATTHLD Attribute memory hold time 16 8 ATTWAIT Attribute memory wait time 8 8 ATTSET Attribute memory setup time 0 8 NPATCFG3 NPATCFG3 NAND flash/PC card attribute space timing configuration register 3 0xAC 0x20 read-write 0xFFFFFFFF ATTHIZ Attribute memory data bus HiZ time 24 8 ATTHLD Attribute memory hold time 16 8 ATTWAIT Attribute memory wait time 8 8 ATTSET Attribute memory setup time 0 8 PIOTCFG3 PIOTCFG3 PC card I/O space timing configuration register 0xB0 0x20 read-write 0xFFFFFFFF IOHIZ IO space data bus HiZ time 24 8 IOHLD IO space hold time 16 8 IOWAIT IO space wait time 8 8 IOSET IO space setup time 0 8 NECC1 NECC1 NAND flash ECC register 1 0x74 0x20 0x00000000 ECC ECC result 0 32 read-only NECC2 NECC2 NAND flash ECC register 2 0x94 0x20 0x00000000 ECC ECC result 0 32 read-only EXTI External interrupt/event controller EXTI 0x40010400 0x0 0x400 registers EXTI_Line0 6 EXTI_Line1 7 EXTI_Line2 8 EXTI_Line3 9 EXTI_Line4 10 EXTI_line9_5 23 EXTI_line15_10 40 INTEN INTEN Interrupt enable register (EXTI_INTEN) 0x0 0x20 read-write 0x00000000 INTEN0 Enable Interrupt on line 0 0 1 INTEN0read-writeMaskedInterrupt from line is disabled0UnmaskedInterrupt from line is enabled1 INTEN1 Enable Interrupt on line 1 1 1 INTEN2 Enable Interrupt on line 2 2 1 INTEN3 Enable Interrupt on line 3 3 1 INTEN4 Enable Interrupt on line 4 4 1 INTEN5 Enable Interrupt on line 5 5 1 INTEN6 Enable Interrupt on line 6 6 1 INTEN7 Enable Interrupt on line 7 7 1 INTEN8 Enable Interrupt on line 8 8 1 INTEN9 Enable Interrupt on line 9 9 1 INTEN10 Enable Interrupt on line 10 10 1 INTEN11 Enable Interrupt on line 11 11 1 INTEN12 Enable Interrupt on line 12 12 1 INTEN13 Enable Interrupt on line 13 13 1 INTEN14 Enable Interrupt on line 14 14 1 INTEN15 Enable Interrupt on line 15 15 1 INTEN16 Enable Interrupt on line 16 16 1 INTEN17 Enable Interrupt on line 17 17 1 INTEN18 Enable Interrupt on line 18 18 1 INTEN19 Enable Interrupt on line 19 19 1 INTEN20 Enable Interrupt on line 20 20 1 INTEN21 Enable Interrupt on line 21 21 1 EVEN EVEN Event enable register (EXTI_EVEN) 0x04 0x20 read-write 0x00000000 EVEN0 Enable Event on line 0 0 1 EVEN0read-writeMaskedEvent from line is disabled0UnmaskedEvent from line is enabled1 EVEN1 Enable Event on line 1 1 1 EVEN2 Enable Event on line 2 2 1 EVEN3 Enable Event on line 3 3 1 EVEN4 Enable Event on line 4 4 1 EVEN5 Enable Event on line 5 5 1 EVEN6 Enable Event on line 6 6 1 EVEN7 Enable Event on line 7 7 1 EVEN8 Enable Event on line 8 8 1 EVEN9 Enable Event on line 9 9 1 EVEN10 Enable Event on line 10 10 1 EVEN11 Enable Event on line 11 11 1 EVEN12 Enable Event on line 12 12 1 EVEN13 Enable Event on line 13 13 1 EVEN14 Enable Event on line 14 14 1 EVEN15 Enable Event on line 15 15 1 EVEN16 Enable Event on line 16 16 1 EVEN17 Enable Event on line 17 17 1 EVEN18 Enable Event on line 18 18 1 EVEN19 Enable Event on line 19 19 1 EVEN20 Enable Event on line 20 20 1 EVEN21 Enable Event on line 21 21 1 RTEN RTEN Rising Edge Trigger Enable register (EXTI_RTEN) 0x08 0x20 read-write 0x00000000 RTEN0 Rising edge trigger enable of line 0 0 1 RTEN0read-writeDisabledRising edge trigger is disabled0EnabledRising edge trigger is enabled1 RTEN1 Rising edge trigger enable of line 1 1 1 RTEN2 Rising edge trigger enable of line 2 2 1 RTEN3 Rising edge trigger enable of line 3 3 1 RTEN4 Rising edge trigger enable of line 4 4 1 RTEN5 Rising edge trigger enable of line 5 5 1 RTEN6 Rising edge trigger enable of line 6 6 1 RTEN7 Rising edge trigger enable of line 7 7 1 RTEN8 Rising edge trigger enable of line 8 8 1 RTEN9 Rising edge trigger enable of line 9 9 1 RTEN10 Rising edge trigger enable of line 10 10 1 RTEN11 Rising edge trigger enable of line 11 11 1 RTEN12 Rising edge trigger enable of line 12 12 1 RTEN13 Rising edge trigger enable of line 13 13 1 RTEN14 Rising edge trigger enable of line 14 14 1 RTEN15 Rising edge trigger enable of line 15 15 1 RTEN16 Rising edge trigger enable of line 16 16 1 RTEN17 Rising edge trigger enable of line 17 17 1 RTEN18 Rising edge trigger enable of line 18 18 1 RTEN19 Rising edge trigger enable of line 19 19 1 RTEN20 Rising edge trigger enable of line 20 20 1 RTEN21 Rising edge trigger enable of line 21 21 1 FTEN FTEN Falling Egde Trigger Enable register (EXTI_FTEN) 0x0C 0x20 read-write 0x00000000 FTEN0 Falling edge trigger enable of line 0 0 1 FTEN0read-writeDisabledFalling edge trigger is disabled0EnabledFalling edge trigger is enabled1 FTEN1 Falling edge trigger enable of line 1 1 1 FTEN2 Falling edge trigger enable of line 2 2 1 FTEN3 Falling edge trigger enable of line 3 3 1 FTEN4 Falling edge trigger enable of line 4 4 1 FTEN5 Falling edge trigger enable of line 5 5 1 FTEN6 Falling edge trigger enable of line 6 6 1 FTEN7 Falling edge trigger enable of line 7 7 1 FTEN8 Falling edge trigger enable of line 8 8 1 FTEN9 Falling edge trigger enable of line 9 9 1 FTEN10 Falling edge trigger enable of line 10 10 1 FTEN11 Falling edge trigger enable of line 11 11 1 FTEN12 Falling edge trigger enable of line 12 12 1 FTEN13 Falling edge trigger enable of line 13 13 1 FTEN14 Falling edge trigger enable of line 14 14 1 FTEN15 Falling edge trigger enable of line 15 15 1 FTEN16 Falling edge trigger enable of line 16 16 1 FTEN17 Falling edge trigger enable of line 17 17 1 FTEN18 Falling edge trigger enable of line 18 18 1 FTEN19 Falling edge trigger enable of line 19 19 1 FTEN20 Falling edge trigger enable of line 20 20 1 FTEN21 Falling edge trigger enable of line 21 21 1 SWIEV SWIEV Software interrupt event register (EXTI_SWIEV) 0x10 0x20 read-write 0x00000000 SWIEV0 Interrupt/Event software trigger on line 0 0 1 SWIEV0WwritePendGenerates an interrupt request1 SWIEV1 Interrupt/Event software trigger on line 1 1 1 SWIEV2 Interrupt/Event software trigger on line 2 2 1 SWIEV3 Interrupt/Event software trigger on line 3 3 1 SWIEV4 Interrupt/Event software trigger on line 4 4 1 SWIEV5 Interrupt/Event software trigger on line 5 5 1 SWIEV6 Interrupt/Event software trigger on line 6 6 1 SWIEV7 Interrupt/Event software trigger on line 7 7 1 SWIEV8 Interrupt/Event software trigger on line 8 8 1 SWIEV9 Interrupt/Event software trigger on line 9 9 1 SWIEV10 Interrupt/Event software trigger on line 10 10 1 SWIEV11 Interrupt/Event software trigger on line 11 11 1 SWIEV12 Interrupt/Event software trigger on line 12 12 1 SWIEV13 Interrupt/Event software trigger on line 13 13 1 SWIEV14 Interrupt/Event software trigger on line 14 14 1 SWIEV15 Interrupt/Event software trigger on line 15 15 1 SWIEV16 Interrupt/Event software trigger on line 16 16 1 SWIEV17 Interrupt/Event software trigger on line 17 17 1 SWIEV18 Interrupt/Event software trigger on line 18 18 1 SWIEV19 Interrupt/Event software trigger on line 19 19 1 SWIEV20 Interrupt/Event software trigger on line 20 20 1 SWIEV21 Interrupt/Event software trigger on line 21 21 1 PD PD Pending register (EXTI_PD) 0x14 0x20 read-write 0x00000000 PD0 Interrupt pending status of line 0 0 1 PD0RreadNotPendingNo trigger request occurred0PendingSelected trigger request occurred1 PD0WwriteClearClears pending bit1 PD1 Interrupt pending status of line 1 1 1 PD2 Interrupt pending status of line 2 2 1 PD3 Interrupt pending status of line 3 3 1 PD4 Interrupt pending status of line 4 4 1 PD5 Interrupt pending status of line 5 5 1 PD6 Interrupt pending status of line 6 6 1 PD7 Interrupt pending status of line 7 7 1 PD8 Interrupt pending status of line 8 8 1 PD9 Interrupt pending status of line 9 9 1 PD10 Interrupt pending status of line 10 10 1 PD11 Interrupt pending status of line 11 11 1 PD12 Interrupt pending status of line 12 12 1 PD13 Interrupt pending status of line 13 13 1 PD14 Interrupt pending status of line 14 14 1 PD15 Interrupt pending status of line 15 15 1 PD16 Interrupt pending status of line 16 16 1 PD17 Interrupt pending status of line 17 17 1 PD18 Interrupt pending status of line 18 18 1 PD19 Interrupt pending status of line 19 19 1 PD20 Interrupt pending status of line 20 20 1 PD21 Interrupt pending status of line 21 21 1 FMC FMC FMC 0x40022000 0x0 0x400 registers FMC 4 WS WS wait state counter register 0x0 0x20 read-write 0x00000630 WSCNT wait state counter register 0 3 WSCNTread-writeWS00 wait states added0WS11 wait state added1WS22 wait states added2 PFEN Pre-fetch enable 4 1 ICEN IBUS cache enable 9 1 DCEN DBUS cache enable 10 1 ICRST IBUS cache reset 11 1 DCRST DBUS cache reset 12 1 KEY KEY Unlock key register 0x04 0x20 write-only 0x00000000 KEY FMC_CTL unlock register 0 32 04294967295 OBKEY OBKEY Option byte unlock key register 0x08 0x20 write-only 0x00000000 OBKEY FMC_ OBCTL0 option byte operation unlock register 0 32 04294967295 STAT STAT Status register 0x0C 0x20 0x00000000 ENDF End of operation flag bit 5 1 read-write ENDFRreadNoEventNo end of operation occurred0EventAn end of operation event occurred1 ENDFWwriteClearClears flag1 WPERR Erase/Program protection error flag bit 4 1 read-write WPERRRreadNoErrorThere was no error0ErrorThere was an error erasing/programming protected pages1 WPERRWwriteClearClears flag1 PGAERR Program alignment error flag bit 3 1 read-write PGERR Program error flag bit 2 1 read-write PGERRRreadNoErrorThere was no error0ErrorThere was an error programming flash1 PGERRWwriteClearClears flag1 BUSY The flash is busy bit 0 1 read-only BUSYRreadInactiveNo operation is in progress0ActiveAn operation is in progress1 CTL CTL Control register 0x10 0x20 read-write 0x00000080 ENDIE End of operation interrupt enable bit 12 1 ENDIEread-writeDisabledEnd of operation interrupt disabled0EnabledEnd of operation interrupt enabled1 ERRIE Error interrupt enable bit 10 1 ERRIEread-writeDisabledError interrupt generation disabled0EnabledError interrupt generation enabled1 OBWEN Option byte erase/program enable bit 9 1 OBWENRreadDisabledOption byte write disabled0EnabledOption byte write enabled1 OBWENWwriteDisableDisable option byte write0 LK FMC_CTL0 lock bit 7 1 LKRreadUnlockedCTL register is unlocked0LockedCTL register is locked1 LKWwriteLockLock CTL register1 START Send erase command to FMC bit 6 1 STARTWwriteStartTrigger an erase operation1 OBER Option bytes erase command bit 5 1 OBERread-writeOptionByteEraseErase option byte activated1 OBPG Option bytes program command bit 4 1 OBPGread-writeOptionByteProgrammingProgram option byte activated1 MER Main flash mass erase for bank0 command bit 2 1 MERread-writeMassEraseErase activated for all user sectors1 PER Main flash page erase for bank0 command bit 1 1 PERread-writePageEraseErase activated for selected page1 PG Main flash program for bank0 command bit 0 1 PGread-writeProgramFlash programming activated1 ADDR ADDR Address register 0x14 0x20 write-only 0x00000000 ADDR Flash erase/program command address bits 0 32 04294967295 OBSTAT OBSTAT Option byte status register 0x1C 0x20 read-only 0x00000000 OBERR Option bytes read error bit 0 1 SPC Option bytes security protection code 1 1 USER Store USER of option bytes block after system reset 2 8 DATA Store DATA[15:0] of option bytes block after system reset 10 16 WP WP Erase/Program Protection register 0x20 0x20 read-only 0xFFFFFFFF WP Store WP[31:0] of option bytes block after system reset 0 32 PID PID Product ID register 0x100 0x20 read-only 0x00000000 PID Product reserved ID code register 0 32 04294967295 FWDGT free watchdog timer FWDGT 0x40003000 0x0 0x400 registers CTL CTL Control register 0x00 0x20 write-only 0x00000000 CMD Key value 0 16 CMDread-writeEnableEnable access to PR, RLR and WINR registers (0x5555)21845ResetReset the watchdog value (0xAAAA)43690StartStart the watchdog (0xCCCC)52428 PSC PSC Prescaler register 0x04 0x20 read-write 0x00000000 PSC Free watchdog timer prescaler selection 0 3 PSCread-writeDivideBy4Divider /40DivideBy8Divider /81DivideBy16Divider /162DivideBy32Divider /323DivideBy64Divider /644DivideBy128Divider /1285DivideBy256Divider /2566DivideBy256bisDivider /2567 RLD RLD Reload register 0x08 0x20 read-write 0x00000FFF RLD Free watchdog timer counter reload value 0 12 04095 STAT STAT Status register 0x0C 0x20 read-only 0x00000000 PUD Free watchdog timer prescaler value update 0 1 PUDread-writeValidThe value read from the PSC register is valid0OngoingA write operation to to the PSC register is ongoing, so the value read is invalid1 RUD Free watchdog timer counter reload value update 1 1 RUDread-writeValidThe value read from the RLD register is valid0OngoingA write operation to to the RLD register is ongoing, so the value read is invalid1 GPIOA General-purpose I/Os GPIO 0x40010800 0x0 0x400 registers CTL0 CTL0 port control register 0 0x0 0x20 read-write 0x44444444 CTL7 Port x configuration bits (x = 7) 30 2 MD7 Port x mode bits (x = 7) 28 2 CTL6 Port x configuration bits (x = 6) 26 2 MD6 Port x mode bits (x = 6) 24 2 CTL5 Port x configuration bits (x = 5) 22 2 MD5 Port x mode bits (x = 5) 20 2 CTL4 Port x configuration bits (x = 4) 18 2 MD4 Port x mode bits (x = 4) 16 2 CTL3 Port x configuration bits (x = 3) 14 2 MD3 Port x mode bits (x = 3 ) 12 2 CTL2 Port x configuration bits (x = 2) 10 2 MD2 Port x mode bits (x = 2 ) 8 2 CTL1 Port x configuration bits (x = 1) 6 2 MD1 Port x mode bits (x = 1) 4 2 CTL0 Port x configuration bits (x = 0) 2 2 CTL0read-writeAnalogOrPushPullAnalog mode/GPIO output with push-pull0FloatingOrOpenDrainFloating input/GPIO output with open-drain1InputOrAfioPPInput with pull-up pull-down/AFIO output with push-pull2RSVDOrAfioODReserved/AFIO output with open-drain3 MD0 Port x mode bits (x = 0) 0 2 MD0read-writeInputInput mode (reset state)0Speed10MOutput mode ,max speed 10MHz1Speed2MOutput mode ,max speed 2MHz2Speed50MOutput mode ,max speed 50MHz3 CTL1 CTL1 port control register 1 0x04 0x20 read-write 0x44444444 CTL15 Port x configuration bits (x = 15) 30 2 MD15 Port x mode bits (x = 15) 28 2 CTL14 Port x configuration bits (x = 14) 26 2 MD14 Port x mode bits (x = 14) 24 2 CTL13 Port x configuration bits (x = 13) 22 2 MD13 Port x mode bits (x = 13) 20 2 CTL12 Port x configuration bits (x = 12) 18 2 MD12 Port x mode bits (x = 12) 16 2 CTL11 Port x configuration bits (x = 11) 14 2 MD11 Port x mode bits (x = 11 ) 12 2 CTL10 Port x configuration bits (x = 10) 10 2 MD10 Port x mode bits (x = 10 ) 8 2 CTL9 Port x configuration bits (x = 9) 6 2 MD9 Port x mode bits (x = 9) 4 2 CTL8 Port x configuration bits (x = 8) 2 2 CTL8read-writeAnalogOrPushPullAnalog mode/GPIO output with push-pull0FloatingOrOpenDrainFloating input/GPIO output with open-drain1InputOrAfioPPInput with pull-up pull-down/AFIO output with push-pull2RSVDOrAfioODReserved/AFIO output with open-drain3 MD8 Port x mode bits (x = 8) 0 2 MD8read-writeInputInput mode (reset state)0Speed10MOutput mode ,max speed 10MHz1Speed2MOutput mode ,max speed 2MHz2Speed50MOutput mode ,max speed 50MHz3 ISTAT ISTAT Port input status register 0x08 0x20 read-only 0x00000000 ISTAT15 Port input status 15 1 ISTAT14 Port input status 14 1 ISTAT13 Port input status 13 1 ISTAT12 Port input status 12 1 ISTAT11 Port input status 11 1 ISTAT10 Port input status 10 1 ISTAT9 Port input status 9 1 ISTAT8 Port input status 8 1 ISTAT7 Port input status 7 1 ISTAT6 Port input status 6 1 ISTAT5 Port input status 5 1 ISTAT4 Port input status 4 1 ISTAT3 Port input status 3 1 ISTAT2 Port input status 2 1 ISTAT1 Port input status 1 1 ISTAT0 Port input status 0 1 ISTAT0read-writeLowInput is logic low0HighInput is logic high1 OCTL OCTL Port output control register 0x0C 0x20 read-write 0x00000000 OCTL15 Port output control 15 1 OCTL14 Port output control 14 1 OCTL13 Port output control 13 1 OCTL12 Port output control 12 1 OCTL11 Port output control 11 1 OCTL10 Port output control 10 1 OCTL9 Port output control 9 1 OCTL8 Port output control 8 1 OCTL7 Port output control 7 1 OCTL6 Port output control 6 1 OCTL5 Port output control 5 1 OCTL4 Port output control 4 1 OCTL3 Port output control 3 1 OCTL2 Port output control 2 1 OCTL1 Port output control 1 1 OCTL0 Port output control 0 1 OCTL0read-writeLowSet output to logic low0HighSet output to logic high1 BOP BOP Port bit operate register 0x10 0x20 write-only 0x00000000 CR15 Port 15 Clear bit 31 1 CR14 Port 14 Clear bit 30 1 CR13 Port 13 Clear bit 29 1 CR12 Port 12 Clear bit 28 1 CR11 Port 11 Clear bit 27 1 CR10 Port 10 Clear bit 26 1 CR9 Port 9 Clear bit 25 1 CR8 Port 8 Clear bit 24 1 CR7 Port 7 Clear bit 23 1 CR6 Port 6 Clear bit 22 1 CR5 Port 5 Clear bit 21 1 CR4 Port 4 Clear bit 20 1 CR3 Port 3 Clear bit 19 1 CR2 Port 2 Clear bit 18 1 CR1 Port 1 Clear bit 17 1 CR0 Port 0 Clear bit 16 1 CR0WwriteResetResets the corresponding OCTLx bit1 BOP15 Port 15 Set bit 15 1 BOP14 Port 14 Set bit 14 1 BOP13 Port 13 Set bit 13 1 BOP12 Port 12 Set bit 12 1 BOP11 Port 11 Set bit 11 1 BOP10 Port 10 Set bit 10 1 BOP9 Port 9 Set bit 9 1 BOP8 Port 8 Set bit 8 1 BOP7 Port 7 Set bit 7 1 BOP6 Port 6 Set bit 6 1 BOP5 Port 5 Set bit 5 1 BOP4 Port 4 Set bit 4 1 BOP3 Port 3 Set bit 3 1 BOP2 Port 2 Set bit 2 1 BOP1 Port 1 Set bit 1 1 BOP0 Port 0 Set bit 0 1 BOP0WwriteSetSets the corresponding OCTLx bit1 BC BC Port bit clear register 0x14 0x20 write-only 0x00000000 CR15 Port 15 Clear bit 15 1 CR14 Port 14 Clear bit 14 1 CR13 Port 13 Clear bit 13 1 CR12 Port 12 Clear bit 12 1 CR11 Port 11 Clear bit 11 1 CR10 Port 10 Clear bit 10 1 CR9 Port 9 Clear bit 9 1 CR8 Port 8 Clear bit 8 1 CR7 Port 7 Clear bit 7 1 CR6 Port 6 Clear bit 6 1 CR5 Port 5 Clear bit 5 1 CR4 Port 4 Clear bit 4 1 CR3 Port 3 Clear bit 3 1 CR2 Port 2 Clear bit 2 1 CR1 Port 1 Clear bit 1 1 CR0 Port 0 Clear bit 0 1 CR0WwriteResetResets the corresponding OCTLx bit1 LOCK LOCK GPIO port configuration lock register 0x18 0x20 read-write 0x00000000 LKK Lock sequence key 16 1 LKKread-writeNotActivePort configuration lock key not active0ActivePort configuration lock key active1 LK15 Port Lock bit 15 15 1 LK14 Port Lock bit 14 14 1 LK13 Port Lock bit 13 13 1 LK12 Port Lock bit 12 12 1 LK11 Port Lock bit 11 11 1 LK10 Port Lock bit 10 10 1 LK9 Port Lock bit 9 9 1 LK8 Port Lock bit 8 8 1 LK7 Port Lock bit 7 7 1 LK6 Port Lock bit 6 6 1 LK5 Port Lock bit 5 5 1 LK4 Port Lock bit 4 4 1 LK3 Port Lock bit 3 3 1 LK2 Port Lock bit 2 2 1 LK1 Port Lock bit 1 1 1 LK0 Port Lock bit 0 0 1 LK0read-writeUnlockedPort configuration not locked0LockedPort configuration locked1 SPD SPD Port bit speed register 0x3C 0x20 read-write 0x00000000 SPD15 Port 15 output max speed bits 15 1 SPD14 Port 14 output max speed bits 14 1 SPD13 Port 13 output max speed bits 13 1 SPD12 Port 12 output max speed bits 12 1 SPD11 Port 11 output max speed bits 11 1 SPD10 Port 10 output max speed bits 10 1 SPD9 Port 9 output max speed bits 9 1 SPD8 Port 8 output max speed bits 8 1 SPD7 Port 7 output max speed bits 7 1 SPD6 Port 6 output max speed bits 6 1 SPD5 Port 5 output max speed bits 5 1 SPD4 Port 4 output max speed bits 4 1 SPD3 Port 3 output max speed bits 3 1 SPD2 Port 2 output max speed bits 2 1 SPD1 Port 1 output max speed bits 1 1 SPD0 Port 0 output max speed bits 0 1 GPIOB General-purpose I/Os GPIO 0x40010C00 0x0 0x400 registers CTL0 CTL0 port control register 0 0x0 0x20 read-write 0x44444444 CTL7 Port x configuration bits (x = 7) 30 2 MD7 Port x mode bits (x = 7) 28 2 CTL6 Port x configuration bits (x = 6) 26 2 MD6 Port x mode bits (x = 6) 24 2 CTL5 Port x configuration bits (x = 5) 22 2 MD5 Port x mode bits (x = 5) 20 2 CTL4 Port x configuration bits (x = 4) 18 2 MD4 Port x mode bits (x = 4) 16 2 CTL3 Port x configuration bits (x = 3) 14 2 MD3 Port x mode bits (x = 3 ) 12 2 CTL2 Port x configuration bits (x = 2) 10 2 MD2 Port x mode bits (x = 2 ) 8 2 CTL1 Port x configuration bits (x = 1) 6 2 MD1 Port x mode bits (x = 1) 4 2 CTL0 Port x configuration bits (x = 0) 2 2 CTL0read-writeAnalogOrPushPullAnalog mode/GPIO output with push-pull0FloatingOrOpenDrainFloating input/GPIO output with open-drain1InputOrAfioPPInput with pull-up pull-down/AFIO output with push-pull2RSVDOrAfioODReserved/AFIO output with open-drain3 MD0 Port x mode bits (x = 0) 0 2 MD0read-writeInputInput mode (reset state)0Speed10MOutput mode ,max speed 10MHz1Speed2MOutput mode ,max speed 2MHz2Speed50MOutput mode ,max speed 50MHz3 CTL1 CTL1 port control register 1 0x04 0x20 read-write 0x44444444 CTL15 Port x configuration bits (x = 15) 30 2 MD15 Port x mode bits (x = 15) 28 2 CTL14 Port x configuration bits (x = 14) 26 2 MD14 Port x mode bits (x = 14) 24 2 CTL13 Port x configuration bits (x = 13) 22 2 MD13 Port x mode bits (x = 13) 20 2 CTL12 Port x configuration bits (x = 12) 18 2 MD12 Port x mode bits (x = 12) 16 2 CTL11 Port x configuration bits (x = 11) 14 2 MD11 Port x mode bits (x = 11 ) 12 2 CTL10 Port x configuration bits (x = 10) 10 2 MD10 Port x mode bits (x = 10 ) 8 2 CTL9 Port x configuration bits (x = 9) 6 2 MD9 Port x mode bits (x = 9) 4 2 CTL8 Port x configuration bits (x = 8) 2 2 CTL8read-writeAnalogOrPushPullAnalog mode/GPIO output with push-pull0FloatingOrOpenDrainFloating input/GPIO output with open-drain1InputOrAfioPPInput with pull-up pull-down/AFIO output with push-pull2RSVDOrAfioODReserved/AFIO output with open-drain3 MD8 Port x mode bits (x = 8) 0 2 MD8read-writeInputInput mode (reset state)0Speed10MOutput mode ,max speed 10MHz1Speed2MOutput mode ,max speed 2MHz2Speed50MOutput mode ,max speed 50MHz3 ISTAT ISTAT Port input status register 0x08 0x20 read-only 0x00000000 ISTAT15 Port input status 15 1 ISTAT14 Port input status 14 1 ISTAT13 Port input status 13 1 ISTAT12 Port input status 12 1 ISTAT11 Port input status 11 1 ISTAT10 Port input status 10 1 ISTAT9 Port input status 9 1 ISTAT8 Port input status 8 1 ISTAT7 Port input status 7 1 ISTAT6 Port input status 6 1 ISTAT5 Port input status 5 1 ISTAT4 Port input status 4 1 ISTAT3 Port input status 3 1 ISTAT2 Port input status 2 1 ISTAT1 Port input status 1 1 ISTAT0 Port input status 0 1 ISTAT0read-writeLowInput is logic low0HighInput is logic high1 OCTL OCTL Port output control register 0x0C 0x20 read-write 0x00000000 OCTL15 Port output control 15 1 OCTL14 Port output control 14 1 OCTL13 Port output control 13 1 OCTL12 Port output control 12 1 OCTL11 Port output control 11 1 OCTL10 Port output control 10 1 OCTL9 Port output control 9 1 OCTL8 Port output control 8 1 OCTL7 Port output control 7 1 OCTL6 Port output control 6 1 OCTL5 Port output control 5 1 OCTL4 Port output control 4 1 OCTL3 Port output control 3 1 OCTL2 Port output control 2 1 OCTL1 Port output control 1 1 OCTL0 Port output control 0 1 OCTL0read-writeLowSet output to logic low0HighSet output to logic high1 BOP BOP Port bit operate register 0x10 0x20 write-only 0x00000000 CR15 Port 15 Clear bit 31 1 CR14 Port 14 Clear bit 30 1 CR13 Port 13 Clear bit 29 1 CR12 Port 12 Clear bit 28 1 CR11 Port 11 Clear bit 27 1 CR10 Port 10 Clear bit 26 1 CR9 Port 9 Clear bit 25 1 CR8 Port 8 Clear bit 24 1 CR7 Port 7 Clear bit 23 1 CR6 Port 6 Clear bit 22 1 CR5 Port 5 Clear bit 21 1 CR4 Port 4 Clear bit 20 1 CR3 Port 3 Clear bit 19 1 CR2 Port 2 Clear bit 18 1 CR1 Port 1 Clear bit 17 1 CR0 Port 0 Clear bit 16 1 CR0WwriteResetResets the corresponding OCTLx bit1 BOP15 Port 15 Set bit 15 1 BOP14 Port 14 Set bit 14 1 BOP13 Port 13 Set bit 13 1 BOP12 Port 12 Set bit 12 1 BOP11 Port 11 Set bit 11 1 BOP10 Port 10 Set bit 10 1 BOP9 Port 9 Set bit 9 1 BOP8 Port 8 Set bit 8 1 BOP7 Port 7 Set bit 7 1 BOP6 Port 6 Set bit 6 1 BOP5 Port 5 Set bit 5 1 BOP4 Port 4 Set bit 4 1 BOP3 Port 3 Set bit 3 1 BOP2 Port 2 Set bit 2 1 BOP1 Port 1 Set bit 1 1 BOP0 Port 0 Set bit 0 1 BOP0WwriteSetSets the corresponding OCTLx bit1 BC BC Port bit clear register 0x14 0x20 write-only 0x00000000 CR15 Port 15 Clear bit 15 1 CR14 Port 14 Clear bit 14 1 CR13 Port 13 Clear bit 13 1 CR12 Port 12 Clear bit 12 1 CR11 Port 11 Clear bit 11 1 CR10 Port 10 Clear bit 10 1 CR9 Port 9 Clear bit 9 1 CR8 Port 8 Clear bit 8 1 CR7 Port 7 Clear bit 7 1 CR6 Port 6 Clear bit 6 1 CR5 Port 5 Clear bit 5 1 CR4 Port 4 Clear bit 4 1 CR3 Port 3 Clear bit 3 1 CR2 Port 2 Clear bit 2 1 CR1 Port 1 Clear bit 1 1 CR0 Port 0 Clear bit 0 1 CR0WwriteResetResets the corresponding OCTLx bit1 LOCK LOCK GPIO port configuration lock register 0x18 0x20 read-write 0x00000000 LKK Lock sequence key 16 1 LKKread-writeNotActivePort configuration lock key not active0ActivePort configuration lock key active1 LK15 Port Lock bit 15 15 1 LK14 Port Lock bit 14 14 1 LK13 Port Lock bit 13 13 1 LK12 Port Lock bit 12 12 1 LK11 Port Lock bit 11 11 1 LK10 Port Lock bit 10 10 1 LK9 Port Lock bit 9 9 1 LK8 Port Lock bit 8 8 1 LK7 Port Lock bit 7 7 1 LK6 Port Lock bit 6 6 1 LK5 Port Lock bit 5 5 1 LK4 Port Lock bit 4 4 1 LK3 Port Lock bit 3 3 1 LK2 Port Lock bit 2 2 1 LK1 Port Lock bit 1 1 1 LK0 Port Lock bit 0 0 1 LK0read-writeUnlockedPort configuration not locked0LockedPort configuration locked1 SPD SPD Port bit speed register 0x3C 0x20 read-write 0x00000000 SPD15 Port 15 output max speed bits 15 1 SPD14 Port 14 output max speed bits 14 1 SPD13 Port 13 output max speed bits 13 1 SPD12 Port 12 output max speed bits 12 1 SPD11 Port 11 output max speed bits 11 1 SPD10 Port 10 output max speed bits 10 1 SPD9 Port 9 output max speed bits 9 1 SPD8 Port 8 output max speed bits 8 1 SPD7 Port 7 output max speed bits 7 1 SPD6 Port 6 output max speed bits 6 1 SPD5 Port 5 output max speed bits 5 1 SPD4 Port 4 output max speed bits 4 1 SPD3 Port 3 output max speed bits 3 1 SPD2 Port 2 output max speed bits 2 1 SPD1 Port 1 output max speed bits 1 1 SPD0 Port 0 output max speed bits 0 1 GPIOC General-purpose I/Os GPIO 0x40011000 0x0 0x400 registers CTL0 CTL0 port control register 0 0x0 0x20 read-write 0x44444444 CTL7 Port x configuration bits (x = 7) 30 2 MD7 Port x mode bits (x = 7) 28 2 CTL6 Port x configuration bits (x = 6) 26 2 MD6 Port x mode bits (x = 6) 24 2 CTL5 Port x configuration bits (x = 5) 22 2 MD5 Port x mode bits (x = 5) 20 2 CTL4 Port x configuration bits (x = 4) 18 2 MD4 Port x mode bits (x = 4) 16 2 CTL3 Port x configuration bits (x = 3) 14 2 MD3 Port x mode bits (x = 3 ) 12 2 CTL2 Port x configuration bits (x = 2) 10 2 MD2 Port x mode bits (x = 2 ) 8 2 CTL1 Port x configuration bits (x = 1) 6 2 MD1 Port x mode bits (x = 1) 4 2 CTL0 Port x configuration bits (x = 0) 2 2 CTL0read-writeAnalogOrPushPullAnalog mode/GPIO output with push-pull0FloatingOrOpenDrainFloating input/GPIO output with open-drain1InputOrAfioPPInput with pull-up pull-down/AFIO output with push-pull2RSVDOrAfioODReserved/AFIO output with open-drain3 MD0 Port x mode bits (x = 0) 0 2 MD0read-writeInputInput mode (reset state)0Speed10MOutput mode ,max speed 10MHz1Speed2MOutput mode ,max speed 2MHz2Speed50MOutput mode ,max speed 50MHz3 CTL1 CTL1 port control register 1 0x04 0x20 read-write 0x44444444 CTL15 Port x configuration bits (x = 15) 30 2 MD15 Port x mode bits (x = 15) 28 2 CTL14 Port x configuration bits (x = 14) 26 2 MD14 Port x mode bits (x = 14) 24 2 CTL13 Port x configuration bits (x = 13) 22 2 MD13 Port x mode bits (x = 13) 20 2 CTL12 Port x configuration bits (x = 12) 18 2 MD12 Port x mode bits (x = 12) 16 2 CTL11 Port x configuration bits (x = 11) 14 2 MD11 Port x mode bits (x = 11 ) 12 2 CTL10 Port x configuration bits (x = 10) 10 2 MD10 Port x mode bits (x = 10 ) 8 2 CTL9 Port x configuration bits (x = 9) 6 2 MD9 Port x mode bits (x = 9) 4 2 CTL8 Port x configuration bits (x = 8) 2 2 CTL8read-writeAnalogOrPushPullAnalog mode/GPIO output with push-pull0FloatingOrOpenDrainFloating input/GPIO output with open-drain1InputOrAfioPPInput with pull-up pull-down/AFIO output with push-pull2RSVDOrAfioODReserved/AFIO output with open-drain3 MD8 Port x mode bits (x = 8) 0 2 MD8read-writeInputInput mode (reset state)0Speed10MOutput mode ,max speed 10MHz1Speed2MOutput mode ,max speed 2MHz2Speed50MOutput mode ,max speed 50MHz3 ISTAT ISTAT Port input status register 0x08 0x20 read-only 0x00000000 ISTAT15 Port input status 15 1 ISTAT14 Port input status 14 1 ISTAT13 Port input status 13 1 ISTAT12 Port input status 12 1 ISTAT11 Port input status 11 1 ISTAT10 Port input status 10 1 ISTAT9 Port input status 9 1 ISTAT8 Port input status 8 1 ISTAT7 Port input status 7 1 ISTAT6 Port input status 6 1 ISTAT5 Port input status 5 1 ISTAT4 Port input status 4 1 ISTAT3 Port input status 3 1 ISTAT2 Port input status 2 1 ISTAT1 Port input status 1 1 ISTAT0 Port input status 0 1 ISTAT0read-writeLowInput is logic low0HighInput is logic high1 OCTL OCTL Port output control register 0x0C 0x20 read-write 0x00000000 OCTL15 Port output control 15 1 OCTL14 Port output control 14 1 OCTL13 Port output control 13 1 OCTL12 Port output control 12 1 OCTL11 Port output control 11 1 OCTL10 Port output control 10 1 OCTL9 Port output control 9 1 OCTL8 Port output control 8 1 OCTL7 Port output control 7 1 OCTL6 Port output control 6 1 OCTL5 Port output control 5 1 OCTL4 Port output control 4 1 OCTL3 Port output control 3 1 OCTL2 Port output control 2 1 OCTL1 Port output control 1 1 OCTL0 Port output control 0 1 OCTL0read-writeLowSet output to logic low0HighSet output to logic high1 BOP BOP Port bit operate register 0x10 0x20 write-only 0x00000000 CR15 Port 15 Clear bit 31 1 CR14 Port 14 Clear bit 30 1 CR13 Port 13 Clear bit 29 1 CR12 Port 12 Clear bit 28 1 CR11 Port 11 Clear bit 27 1 CR10 Port 10 Clear bit 26 1 CR9 Port 9 Clear bit 25 1 CR8 Port 8 Clear bit 24 1 CR7 Port 7 Clear bit 23 1 CR6 Port 6 Clear bit 22 1 CR5 Port 5 Clear bit 21 1 CR4 Port 4 Clear bit 20 1 CR3 Port 3 Clear bit 19 1 CR2 Port 2 Clear bit 18 1 CR1 Port 1 Clear bit 17 1 CR0 Port 0 Clear bit 16 1 CR0WwriteResetResets the corresponding OCTLx bit1 BOP15 Port 15 Set bit 15 1 BOP14 Port 14 Set bit 14 1 BOP13 Port 13 Set bit 13 1 BOP12 Port 12 Set bit 12 1 BOP11 Port 11 Set bit 11 1 BOP10 Port 10 Set bit 10 1 BOP9 Port 9 Set bit 9 1 BOP8 Port 8 Set bit 8 1 BOP7 Port 7 Set bit 7 1 BOP6 Port 6 Set bit 6 1 BOP5 Port 5 Set bit 5 1 BOP4 Port 4 Set bit 4 1 BOP3 Port 3 Set bit 3 1 BOP2 Port 2 Set bit 2 1 BOP1 Port 1 Set bit 1 1 BOP0 Port 0 Set bit 0 1 BOP0WwriteSetSets the corresponding OCTLx bit1 BC BC Port bit clear register 0x14 0x20 write-only 0x00000000 CR15 Port 15 Clear bit 15 1 CR14 Port 14 Clear bit 14 1 CR13 Port 13 Clear bit 13 1 CR12 Port 12 Clear bit 12 1 CR11 Port 11 Clear bit 11 1 CR10 Port 10 Clear bit 10 1 CR9 Port 9 Clear bit 9 1 CR8 Port 8 Clear bit 8 1 CR7 Port 7 Clear bit 7 1 CR6 Port 6 Clear bit 6 1 CR5 Port 5 Clear bit 5 1 CR4 Port 4 Clear bit 4 1 CR3 Port 3 Clear bit 3 1 CR2 Port 2 Clear bit 2 1 CR1 Port 1 Clear bit 1 1 CR0 Port 0 Clear bit 0 1 CR0WwriteResetResets the corresponding OCTLx bit1 LOCK LOCK GPIO port configuration lock register 0x18 0x20 read-write 0x00000000 LKK Lock sequence key 16 1 LK15 Port Lock bit 15 15 1 LK14 Port Lock bit 14 14 1 LK13 Port Lock bit 13 13 1 LK12 Port Lock bit 12 12 1 LK11 Port Lock bit 11 11 1 LK10 Port Lock bit 10 10 1 LK9 Port Lock bit 9 9 1 LK8 Port Lock bit 8 8 1 LK7 Port Lock bit 7 7 1 LK6 Port Lock bit 6 6 1 LK5 Port Lock bit 5 5 1 LK4 Port Lock bit 4 4 1 LK3 Port Lock bit 3 3 1 LK2 Port Lock bit 2 2 1 LK1 Port Lock bit 1 1 1 LK0 Port Lock bit 0 0 1 SPD SPD Port bit speed register 0x3C 0x20 read-write 0x00000000 SPD15 Port 15 output max speed bits 15 1 SPD14 Port 14 output max speed bits 14 1 SPD13 Port 13 output max speed bits 13 1 SPD12 Port 12 output max speed bits 12 1 SPD11 Port 11 output max speed bits 11 1 SPD10 Port 10 output max speed bits 10 1 SPD9 Port 9 output max speed bits 9 1 SPD8 Port 8 output max speed bits 8 1 SPD7 Port 7 output max speed bits 7 1 SPD6 Port 6 output max speed bits 6 1 SPD5 Port 5 output max speed bits 5 1 SPD4 Port 4 output max speed bits 4 1 SPD3 Port 3 output max speed bits 3 1 SPD2 Port 2 output max speed bits 2 1 SPD1 Port 1 output max speed bits 1 1 SPD0 Port 0 output max speed bits 0 1 GPIOD General-purpose I/Os GPIO 0x40011400 0x0 0x400 registers CTL0 CTL0 port control register 0 0x0 0x20 read-write 0x44444444 CTL7 Port x configuration bits (x = 7) 30 2 MD7 Port x mode bits (x = 7) 28 2 CTL6 Port x configuration bits (x = 6) 26 2 MD6 Port x mode bits (x = 6) 24 2 CTL5 Port x configuration bits (x = 5) 22 2 MD5 Port x mode bits (x = 5) 20 2 CTL4 Port x configuration bits (x = 4) 18 2 MD4 Port x mode bits (x = 4) 16 2 CTL3 Port x configuration bits (x = 3) 14 2 MD3 Port x mode bits (x = 3 ) 12 2 CTL2 Port x configuration bits (x = 2) 10 2 MD2 Port x mode bits (x = 2 ) 8 2 CTL1 Port x configuration bits (x = 1) 6 2 MD1 Port x mode bits (x = 1) 4 2 CTL0 Port x configuration bits (x = 0) 2 2 CTL0read-writeAnalogOrPushPullAnalog mode/GPIO output with push-pull0FloatingOrOpenDrainFloating input/GPIO output with open-drain1InputOrAfioPPInput with pull-up pull-down/AFIO output with push-pull2RSVDOrAfioODReserved/AFIO output with open-drain3 MD0 Port x mode bits (x = 0) 0 2 MD0read-writeInputInput mode (reset state)0Speed10MOutput mode ,max speed 10MHz1Speed2MOutput mode ,max speed 2MHz2Speed50MOutput mode ,max speed 50MHz3 CTL1 CTL1 port control register 1 0x04 0x20 read-write 0x44444444 CTL15 Port x configuration bits (x = 15) 30 2 MD15 Port x mode bits (x = 15) 28 2 CTL14 Port x configuration bits (x = 14) 26 2 MD14 Port x mode bits (x = 14) 24 2 CTL13 Port x configuration bits (x = 13) 22 2 MD13 Port x mode bits (x = 13) 20 2 CTL12 Port x configuration bits (x = 12) 18 2 MD12 Port x mode bits (x = 12) 16 2 CTL11 Port x configuration bits (x = 11) 14 2 MD11 Port x mode bits (x = 11 ) 12 2 CTL10 Port x configuration bits (x = 10) 10 2 MD10 Port x mode bits (x = 10 ) 8 2 CTL9 Port x configuration bits (x = 9) 6 2 MD9 Port x mode bits (x = 9) 4 2 CTL8 Port x configuration bits (x = 8) 2 2 CTL8read-writeAnalogOrPushPullAnalog mode/GPIO output with push-pull0FloatingOrOpenDrainFloating input/GPIO output with open-drain1InputOrAfioPPInput with pull-up pull-down/AFIO output with push-pull2RSVDOrAfioODReserved/AFIO output with open-drain3 MD8 Port x mode bits (x = 8) 0 2 MD8read-writeInputInput mode (reset state)0Speed10MOutput mode ,max speed 10MHz1Speed2MOutput mode ,max speed 2MHz2Speed50MOutput mode ,max speed 50MHz3 ISTAT ISTAT Port input status register 0x08 0x20 read-only 0x00000000 ISTAT15 Port input status 15 1 ISTAT14 Port input status 14 1 ISTAT13 Port input status 13 1 ISTAT12 Port input status 12 1 ISTAT11 Port input status 11 1 ISTAT10 Port input status 10 1 ISTAT9 Port input status 9 1 ISTAT8 Port input status 8 1 ISTAT7 Port input status 7 1 ISTAT6 Port input status 6 1 ISTAT5 Port input status 5 1 ISTAT4 Port input status 4 1 ISTAT3 Port input status 3 1 ISTAT2 Port input status 2 1 ISTAT1 Port input status 1 1 ISTAT0 Port input status 0 1 ISTAT0read-writeLowInput is logic low0HighInput is logic high1 OCTL OCTL Port output control register 0x0C 0x20 read-write 0x00000000 OCTL15 Port output control 15 1 OCTL14 Port output control 14 1 OCTL13 Port output control 13 1 OCTL12 Port output control 12 1 OCTL11 Port output control 11 1 OCTL10 Port output control 10 1 OCTL9 Port output control 9 1 OCTL8 Port output control 8 1 OCTL7 Port output control 7 1 OCTL6 Port output control 6 1 OCTL5 Port output control 5 1 OCTL4 Port output control 4 1 OCTL3 Port output control 3 1 OCTL2 Port output control 2 1 OCTL1 Port output control 1 1 OCTL0 Port output control 0 1 OCTL0read-writeLowSet output to logic low0HighSet output to logic high1 BOP BOP Port bit operate register 0x10 0x20 write-only 0x00000000 CR15 Port 15 Clear bit 31 1 CR14 Port 14 Clear bit 30 1 CR13 Port 13 Clear bit 29 1 CR12 Port 12 Clear bit 28 1 CR11 Port 11 Clear bit 27 1 CR10 Port 10 Clear bit 26 1 CR9 Port 9 Clear bit 25 1 CR8 Port 8 Clear bit 24 1 CR7 Port 7 Clear bit 23 1 CR6 Port 6 Clear bit 22 1 CR5 Port 5 Clear bit 21 1 CR4 Port 4 Clear bit 20 1 CR3 Port 3 Clear bit 19 1 CR2 Port 2 Clear bit 18 1 CR1 Port 1 Clear bit 17 1 CR0 Port 0 Clear bit 16 1 CR0WwriteResetResets the corresponding OCTLx bit1 BOP15 Port 15 Set bit 15 1 BOP14 Port 14 Set bit 14 1 BOP13 Port 13 Set bit 13 1 BOP12 Port 12 Set bit 12 1 BOP11 Port 11 Set bit 11 1 BOP10 Port 10 Set bit 10 1 BOP9 Port 9 Set bit 9 1 BOP8 Port 8 Set bit 8 1 BOP7 Port 7 Set bit 7 1 BOP6 Port 6 Set bit 6 1 BOP5 Port 5 Set bit 5 1 BOP4 Port 4 Set bit 4 1 BOP3 Port 3 Set bit 3 1 BOP2 Port 2 Set bit 2 1 BOP1 Port 1 Set bit 1 1 BOP0 Port 0 Set bit 0 1 BOP0WwriteSetSets the corresponding OCTLx bit1 BC BC Port bit clear register 0x14 0x20 write-only 0x00000000 CR15 Port 15 Clear bit 15 1 CR14 Port 14 Clear bit 14 1 CR13 Port 13 Clear bit 13 1 CR12 Port 12 Clear bit 12 1 CR11 Port 11 Clear bit 11 1 CR10 Port 10 Clear bit 10 1 CR9 Port 9 Clear bit 9 1 CR8 Port 8 Clear bit 8 1 CR7 Port 7 Clear bit 7 1 CR6 Port 6 Clear bit 6 1 CR5 Port 5 Clear bit 5 1 CR4 Port 4 Clear bit 4 1 CR3 Port 3 Clear bit 3 1 CR2 Port 2 Clear bit 2 1 CR1 Port 1 Clear bit 1 1 CR0 Port 0 Clear bit 0 1 CR0WwriteResetResets the corresponding OCTLx bit1 LOCK LOCK GPIO port configuration lock register 0x18 0x20 read-write 0x00000000 LKK Lock sequence key 16 1 LK15 Port Lock bit 15 15 1 LK14 Port Lock bit 14 14 1 LK13 Port Lock bit 13 13 1 LK12 Port Lock bit 12 12 1 LK11 Port Lock bit 11 11 1 LK10 Port Lock bit 10 10 1 LK9 Port Lock bit 9 9 1 LK8 Port Lock bit 8 8 1 LK7 Port Lock bit 7 7 1 LK6 Port Lock bit 6 6 1 LK5 Port Lock bit 5 5 1 LK4 Port Lock bit 4 4 1 LK3 Port Lock bit 3 3 1 LK2 Port Lock bit 2 2 1 LK1 Port Lock bit 1 1 1 LK0 Port Lock bit 0 0 1 SPD SPD Port bit speed register 0x3C 0x20 read-write 0x00000000 SPD15 Port 15 output max speed bits 15 1 SPD14 Port 14 output max speed bits 14 1 SPD13 Port 13 output max speed bits 13 1 SPD12 Port 12 output max speed bits 12 1 SPD11 Port 11 output max speed bits 11 1 SPD10 Port 10 output max speed bits 10 1 SPD9 Port 9 output max speed bits 9 1 SPD8 Port 8 output max speed bits 8 1 SPD7 Port 7 output max speed bits 7 1 SPD6 Port 6 output max speed bits 6 1 SPD5 Port 5 output max speed bits 5 1 SPD4 Port 4 output max speed bits 4 1 SPD3 Port 3 output max speed bits 3 1 SPD2 Port 2 output max speed bits 2 1 SPD1 Port 1 output max speed bits 1 1 SPD0 Port 0 output max speed bits 0 1 GPIOE General-purpose I/Os GPIO 0x40011800 0x0 0x400 registers CTL0 CTL0 port control register 0 0x0 0x20 read-write 0x44444444 CTL7 Port x configuration bits (x = 7) 30 2 MD7 Port x mode bits (x = 7) 28 2 CTL6 Port x configuration bits (x = 6) 26 2 MD6 Port x mode bits (x = 6) 24 2 CTL5 Port x configuration bits (x = 5) 22 2 MD5 Port x mode bits (x = 5) 20 2 CTL4 Port x configuration bits (x = 4) 18 2 MD4 Port x mode bits (x = 4) 16 2 CTL3 Port x configuration bits (x = 3) 14 2 MD3 Port x mode bits (x = 3 ) 12 2 CTL2 Port x configuration bits (x = 2) 10 2 MD2 Port x mode bits (x = 2 ) 8 2 CTL1 Port x configuration bits (x = 1) 6 2 MD1 Port x mode bits (x = 1) 4 2 CTL0 Port x configuration bits (x = 0) 2 2 CTL0read-writeAnalogOrPushPullAnalog mode/GPIO output with push-pull0FloatingOrOpenDrainFloating input/GPIO output with open-drain1InputOrAfioPPInput with pull-up pull-down/AFIO output with push-pull2RSVDOrAfioODReserved/AFIO output with open-drain3 MD0 Port x mode bits (x = 0) 0 2 MD0read-writeInputInput mode (reset state)0Speed10MOutput mode ,max speed 10MHz1Speed2MOutput mode ,max speed 2MHz2Speed50MOutput mode ,max speed 50MHz3 CTL1 CTL1 port control register 1 0x04 0x20 read-write 0x44444444 CTL15 Port x configuration bits (x = 15) 30 2 MD15 Port x mode bits (x = 15) 28 2 CTL14 Port x configuration bits (x = 14) 26 2 MD14 Port x mode bits (x = 14) 24 2 CTL13 Port x configuration bits (x = 13) 22 2 MD13 Port x mode bits (x = 13) 20 2 CTL12 Port x configuration bits (x = 12) 18 2 MD12 Port x mode bits (x = 12) 16 2 CTL11 Port x configuration bits (x = 11) 14 2 MD11 Port x mode bits (x = 11 ) 12 2 CTL10 Port x configuration bits (x = 10) 10 2 MD10 Port x mode bits (x = 10 ) 8 2 CTL9 Port x configuration bits (x = 9) 6 2 MD9 Port x mode bits (x = 9) 4 2 CTL8 Port x configuration bits (x = 8) 2 2 CTL8read-writeAnalogOrPushPullAnalog mode/GPIO output with push-pull0FloatingOrOpenDrainFloating input/GPIO output with open-drain1InputOrAfioPPInput with pull-up pull-down/AFIO output with push-pull2RSVDOrAfioODReserved/AFIO output with open-drain3 MD8 Port x mode bits (x = 8) 0 2 MD8read-writeInputInput mode (reset state)0Speed10MOutput mode ,max speed 10MHz1Speed2MOutput mode ,max speed 2MHz2Speed50MOutput mode ,max speed 50MHz3 ISTAT ISTAT Port input status register 0x08 0x20 read-only 0x00000000 ISTAT15 Port input status 15 1 ISTAT14 Port input status 14 1 ISTAT13 Port input status 13 1 ISTAT12 Port input status 12 1 ISTAT11 Port input status 11 1 ISTAT10 Port input status 10 1 ISTAT9 Port input status 9 1 ISTAT8 Port input status 8 1 ISTAT7 Port input status 7 1 ISTAT6 Port input status 6 1 ISTAT5 Port input status 5 1 ISTAT4 Port input status 4 1 ISTAT3 Port input status 3 1 ISTAT2 Port input status 2 1 ISTAT1 Port input status 1 1 ISTAT0 Port input status 0 1 ISTAT0read-writeLowInput is logic low0HighInput is logic high1 OCTL OCTL Port output control register 0x0C 0x20 read-write 0x00000000 OCTL15 Port output control 15 1 OCTL14 Port output control 14 1 OCTL13 Port output control 13 1 OCTL12 Port output control 12 1 OCTL11 Port output control 11 1 OCTL10 Port output control 10 1 OCTL9 Port output control 9 1 OCTL8 Port output control 8 1 OCTL7 Port output control 7 1 OCTL6 Port output control 6 1 OCTL5 Port output control 5 1 OCTL4 Port output control 4 1 OCTL3 Port output control 3 1 OCTL2 Port output control 2 1 OCTL1 Port output control 1 1 OCTL0 Port output control 0 1 OCTL0read-writeLowSet output to logic low0HighSet output to logic high1 BOP BOP Port bit operate register 0x10 0x20 write-only 0x00000000 CR15 Port 15 Clear bit 31 1 CR14 Port 14 Clear bit 30 1 CR13 Port 13 Clear bit 29 1 CR12 Port 12 Clear bit 28 1 CR11 Port 11 Clear bit 27 1 CR10 Port 10 Clear bit 26 1 CR9 Port 9 Clear bit 25 1 CR8 Port 8 Clear bit 24 1 CR7 Port 7 Clear bit 23 1 CR6 Port 6 Clear bit 22 1 CR5 Port 5 Clear bit 21 1 CR4 Port 4 Clear bit 20 1 CR3 Port 3 Clear bit 19 1 CR2 Port 2 Clear bit 18 1 CR1 Port 1 Clear bit 17 1 CR0 Port 0 Clear bit 16 1 CR0WwriteResetResets the corresponding OCTLx bit1 BOP15 Port 15 Set bit 15 1 BOP14 Port 14 Set bit 14 1 BOP13 Port 13 Set bit 13 1 BOP12 Port 12 Set bit 12 1 BOP11 Port 11 Set bit 11 1 BOP10 Port 10 Set bit 10 1 BOP9 Port 9 Set bit 9 1 BOP8 Port 8 Set bit 8 1 BOP7 Port 7 Set bit 7 1 BOP6 Port 6 Set bit 6 1 BOP5 Port 5 Set bit 5 1 BOP4 Port 4 Set bit 4 1 BOP3 Port 3 Set bit 3 1 BOP2 Port 2 Set bit 2 1 BOP1 Port 1 Set bit 1 1 BOP0 Port 0 Set bit 0 1 BOP0WwriteSetSets the corresponding OCTLx bit1 BC BC Port bit clear register 0x14 0x20 write-only 0x00000000 CR15 Port 15 Clear bit 15 1 CR14 Port 14 Clear bit 14 1 CR13 Port 13 Clear bit 13 1 CR12 Port 12 Clear bit 12 1 CR11 Port 11 Clear bit 11 1 CR10 Port 10 Clear bit 10 1 CR9 Port 9 Clear bit 9 1 CR8 Port 8 Clear bit 8 1 CR7 Port 7 Clear bit 7 1 CR6 Port 6 Clear bit 6 1 CR5 Port 5 Clear bit 5 1 CR4 Port 4 Clear bit 4 1 CR3 Port 3 Clear bit 3 1 CR2 Port 2 Clear bit 2 1 CR1 Port 1 Clear bit 1 1 CR0 Port 0 Clear bit 0 1 CR0WwriteResetResets the corresponding OCTLx bit1 LOCK LOCK GPIO port configuration lock register 0x18 0x20 read-write 0x00000000 LKK Lock sequence key 16 1 LK15 Port Lock bit 15 15 1 LK14 Port Lock bit 14 14 1 LK13 Port Lock bit 13 13 1 LK12 Port Lock bit 12 12 1 LK11 Port Lock bit 11 11 1 LK10 Port Lock bit 10 10 1 LK9 Port Lock bit 9 9 1 LK8 Port Lock bit 8 8 1 LK7 Port Lock bit 7 7 1 LK6 Port Lock bit 6 6 1 LK5 Port Lock bit 5 5 1 LK4 Port Lock bit 4 4 1 LK3 Port Lock bit 3 3 1 LK2 Port Lock bit 2 2 1 LK1 Port Lock bit 1 1 1 LK0 Port Lock bit 0 0 1 SPD SPD Port bit speed register 0x3C 0x20 read-write 0x00000000 SPD15 Port 15 output max speed bits 15 1 SPD14 Port 14 output max speed bits 14 1 SPD13 Port 13 output max speed bits 13 1 SPD12 Port 12 output max speed bits 12 1 SPD11 Port 11 output max speed bits 11 1 SPD10 Port 10 output max speed bits 10 1 SPD9 Port 9 output max speed bits 9 1 SPD8 Port 8 output max speed bits 8 1 SPD7 Port 7 output max speed bits 7 1 SPD6 Port 6 output max speed bits 6 1 SPD5 Port 5 output max speed bits 5 1 SPD4 Port 4 output max speed bits 4 1 SPD3 Port 3 output max speed bits 3 1 SPD2 Port 2 output max speed bits 2 1 SPD1 Port 1 output max speed bits 1 1 SPD0 Port 0 output max speed bits 0 1 GPIOF General-purpose I/Os GPIO 0x40011C00 0x0 0x400 registers CTL0 CTL0 port control register 0 0x0 0x20 read-write 0x44444444 CTL7 Port x configuration bits (x = 7) 30 2 MD7 Port x mode bits (x = 7) 28 2 CTL6 Port x configuration bits (x = 6) 26 2 MD6 Port x mode bits (x = 6) 24 2 CTL5 Port x configuration bits (x = 5) 22 2 MD5 Port x mode bits (x = 5) 20 2 CTL4 Port x configuration bits (x = 4) 18 2 MD4 Port x mode bits (x = 4) 16 2 CTL3 Port x configuration bits (x = 3) 14 2 MD3 Port x mode bits (x = 3 ) 12 2 CTL2 Port x configuration bits (x = 2) 10 2 MD2 Port x mode bits (x = 2 ) 8 2 CTL1 Port x configuration bits (x = 1) 6 2 MD1 Port x mode bits (x = 1) 4 2 CTL0 Port x configuration bits (x = 0) 2 2 CTL0read-writeAnalogOrPushPullAnalog mode/GPIO output with push-pull0FloatingOrOpenDrainFloating input/GPIO output with open-drain1InputOrAfioPPInput with pull-up pull-down/AFIO output with push-pull2RSVDOrAfioODReserved/AFIO output with open-drain3 MD0 Port x mode bits (x = 0) 0 2 MD0read-writeInputInput mode (reset state)0Speed10MOutput mode ,max speed 10MHz1Speed2MOutput mode ,max speed 2MHz2Speed50MOutput mode ,max speed 50MHz3 CTL1 CTL1 port control register 1 0x04 0x20 read-write 0x44444444 CTL15 Port x configuration bits (x = 15) 30 2 MD15 Port x mode bits (x = 15) 28 2 CTL14 Port x configuration bits (x = 14) 26 2 MD14 Port x mode bits (x = 14) 24 2 CTL13 Port x configuration bits (x = 13) 22 2 MD13 Port x mode bits (x = 13) 20 2 CTL12 Port x configuration bits (x = 12) 18 2 MD12 Port x mode bits (x = 12) 16 2 CTL11 Port x configuration bits (x = 11) 14 2 MD11 Port x mode bits (x = 11 ) 12 2 CTL10 Port x configuration bits (x = 10) 10 2 MD10 Port x mode bits (x = 10 ) 8 2 CTL9 Port x configuration bits (x = 9) 6 2 MD9 Port x mode bits (x = 9) 4 2 CTL8 Port x configuration bits (x = 8) 2 2 CTL8read-writeAnalogOrPushPullAnalog mode/GPIO output with push-pull0FloatingOrOpenDrainFloating input/GPIO output with open-drain1InputOrAfioPPInput with pull-up pull-down/AFIO output with push-pull2RSVDOrAfioODReserved/AFIO output with open-drain3 MD8 Port x mode bits (x = 8) 0 2 MD8read-writeInputInput mode (reset state)0Speed10MOutput mode ,max speed 10MHz1Speed2MOutput mode ,max speed 2MHz2Speed50MOutput mode ,max speed 50MHz3 ISTAT ISTAT Port input status register 0x08 0x20 read-only 0x00000000 ISTAT15 Port input status 15 1 ISTAT14 Port input status 14 1 ISTAT13 Port input status 13 1 ISTAT12 Port input status 12 1 ISTAT11 Port input status 11 1 ISTAT10 Port input status 10 1 ISTAT9 Port input status 9 1 ISTAT8 Port input status 8 1 ISTAT7 Port input status 7 1 ISTAT6 Port input status 6 1 ISTAT5 Port input status 5 1 ISTAT4 Port input status 4 1 ISTAT3 Port input status 3 1 ISTAT2 Port input status 2 1 ISTAT1 Port input status 1 1 ISTAT0 Port input status 0 1 ISTAT0read-writeLowInput is logic low0HighInput is logic high1 OCTL OCTL Port output control register 0x0C 0x20 read-write 0x00000000 OCTL15 Port output control 15 1 OCTL14 Port output control 14 1 OCTL13 Port output control 13 1 OCTL12 Port output control 12 1 OCTL11 Port output control 11 1 OCTL10 Port output control 10 1 OCTL9 Port output control 9 1 OCTL8 Port output control 8 1 OCTL7 Port output control 7 1 OCTL6 Port output control 6 1 OCTL5 Port output control 5 1 OCTL4 Port output control 4 1 OCTL3 Port output control 3 1 OCTL2 Port output control 2 1 OCTL1 Port output control 1 1 OCTL0 Port output control 0 1 OCTL0read-writeLowSet output to logic low0HighSet output to logic high1 BOP BOP Port bit operate register 0x10 0x20 write-only 0x00000000 CR15 Port 15 Clear bit 31 1 CR14 Port 14 Clear bit 30 1 CR13 Port 13 Clear bit 29 1 CR12 Port 12 Clear bit 28 1 CR11 Port 11 Clear bit 27 1 CR10 Port 10 Clear bit 26 1 CR9 Port 9 Clear bit 25 1 CR8 Port 8 Clear bit 24 1 CR7 Port 7 Clear bit 23 1 CR6 Port 6 Clear bit 22 1 CR5 Port 5 Clear bit 21 1 CR4 Port 4 Clear bit 20 1 CR3 Port 3 Clear bit 19 1 CR2 Port 2 Clear bit 18 1 CR1 Port 1 Clear bit 17 1 CR0 Port 0 Clear bit 16 1 CR0WwriteResetResets the corresponding OCTLx bit1 BOP15 Port 15 Set bit 15 1 BOP14 Port 14 Set bit 14 1 BOP13 Port 13 Set bit 13 1 BOP12 Port 12 Set bit 12 1 BOP11 Port 11 Set bit 11 1 BOP10 Port 10 Set bit 10 1 BOP9 Port 9 Set bit 9 1 BOP8 Port 8 Set bit 8 1 BOP7 Port 7 Set bit 7 1 BOP6 Port 6 Set bit 6 1 BOP5 Port 5 Set bit 5 1 BOP4 Port 4 Set bit 4 1 BOP3 Port 3 Set bit 3 1 BOP2 Port 2 Set bit 2 1 BOP1 Port 1 Set bit 1 1 BOP0 Port 0 Set bit 0 1 BOP0WwriteSetSets the corresponding OCTLx bit1 BC BC Port bit clear register 0x14 0x20 write-only 0x00000000 CR15 Port 15 Clear bit 15 1 CR14 Port 14 Clear bit 14 1 CR13 Port 13 Clear bit 13 1 CR12 Port 12 Clear bit 12 1 CR11 Port 11 Clear bit 11 1 CR10 Port 10 Clear bit 10 1 CR9 Port 9 Clear bit 9 1 CR8 Port 8 Clear bit 8 1 CR7 Port 7 Clear bit 7 1 CR6 Port 6 Clear bit 6 1 CR5 Port 5 Clear bit 5 1 CR4 Port 4 Clear bit 4 1 CR3 Port 3 Clear bit 3 1 CR2 Port 2 Clear bit 2 1 CR1 Port 1 Clear bit 1 1 CR0 Port 0 Clear bit 0 1 CR0WwriteResetResets the corresponding OCTLx bit1 LOCK LOCK GPIO port configuration lock register 0x18 0x20 read-write 0x00000000 LKK Lock sequence key 16 1 LK15 Port Lock bit 15 15 1 LK14 Port Lock bit 14 14 1 LK13 Port Lock bit 13 13 1 LK12 Port Lock bit 12 12 1 LK11 Port Lock bit 11 11 1 LK10 Port Lock bit 10 10 1 LK9 Port Lock bit 9 9 1 LK8 Port Lock bit 8 8 1 LK7 Port Lock bit 7 7 1 LK6 Port Lock bit 6 6 1 LK5 Port Lock bit 5 5 1 LK4 Port Lock bit 4 4 1 LK3 Port Lock bit 3 3 1 LK2 Port Lock bit 2 2 1 LK1 Port Lock bit 1 1 1 LK0 Port Lock bit 0 0 1 SPD SPD Port bit speed register 0x3C 0x20 read-write 0x00000000 SPD15 Port 15 output max speed bits 15 1 SPD14 Port 14 output max speed bits 14 1 SPD13 Port 13 output max speed bits 13 1 SPD12 Port 12 output max speed bits 12 1 SPD11 Port 11 output max speed bits 11 1 SPD10 Port 10 output max speed bits 10 1 SPD9 Port 9 output max speed bits 9 1 SPD8 Port 8 output max speed bits 8 1 SPD7 Port 7 output max speed bits 7 1 SPD6 Port 6 output max speed bits 6 1 SPD5 Port 5 output max speed bits 5 1 SPD4 Port 4 output max speed bits 4 1 SPD3 Port 3 output max speed bits 3 1 SPD2 Port 2 output max speed bits 2 1 SPD1 Port 1 output max speed bits 1 1 SPD0 Port 0 output max speed bits 0 1 GPIOG General-purpose I/Os GPIO 0x40012000 0x0 0x400 registers CTL0 CTL0 port control register 0 0x0 0x20 read-write 0x44444444 CTL7 Port x configuration bits (x = 7) 30 2 MD7 Port x mode bits (x = 7) 28 2 CTL6 Port x configuration bits (x = 6) 26 2 MD6 Port x mode bits (x = 6) 24 2 CTL5 Port x configuration bits (x = 5) 22 2 MD5 Port x mode bits (x = 5) 20 2 CTL4 Port x configuration bits (x = 4) 18 2 MD4 Port x mode bits (x = 4) 16 2 CTL3 Port x configuration bits (x = 3) 14 2 MD3 Port x mode bits (x = 3 ) 12 2 CTL2 Port x configuration bits (x = 2) 10 2 MD2 Port x mode bits (x = 2 ) 8 2 CTL1 Port x configuration bits (x = 1) 6 2 MD1 Port x mode bits (x = 1) 4 2 CTL0 Port x configuration bits (x = 0) 2 2 CTL0read-writeAnalogOrPushPullAnalog mode/GPIO output with push-pull0FloatingOrOpenDrainFloating input/GPIO output with open-drain1InputOrAfioPPInput with pull-up pull-down/AFIO output with push-pull2RSVDOrAfioODReserved/AFIO output with open-drain3 MD0 Port x mode bits (x = 0) 0 2 MD0read-writeInputInput mode (reset state)0Speed10MOutput mode ,max speed 10MHz1Speed2MOutput mode ,max speed 2MHz2Speed50MOutput mode ,max speed 50MHz3 CTL1 CTL1 port control register 1 0x04 0x20 read-write 0x44444444 CTL15 Port x configuration bits (x = 15) 30 2 MD15 Port x mode bits (x = 15) 28 2 CTL14 Port x configuration bits (x = 14) 26 2 MD14 Port x mode bits (x = 14) 24 2 CTL13 Port x configuration bits (x = 13) 22 2 MD13 Port x mode bits (x = 13) 20 2 CTL12 Port x configuration bits (x = 12) 18 2 MD12 Port x mode bits (x = 12) 16 2 CTL11 Port x configuration bits (x = 11) 14 2 MD11 Port x mode bits (x = 11 ) 12 2 CTL10 Port x configuration bits (x = 10) 10 2 MD10 Port x mode bits (x = 10 ) 8 2 CTL9 Port x configuration bits (x = 9) 6 2 MD9 Port x mode bits (x = 9) 4 2 CTL8 Port x configuration bits (x = 8) 2 2 CTL8read-writeAnalogOrPushPullAnalog mode/GPIO output with push-pull0FloatingOrOpenDrainFloating input/GPIO output with open-drain1InputOrAfioPPInput with pull-up pull-down/AFIO output with push-pull2RSVDOrAfioODReserved/AFIO output with open-drain3 MD8 Port x mode bits (x = 8) 0 2 MD8read-writeInputInput mode (reset state)0Speed10MOutput mode ,max speed 10MHz1Speed2MOutput mode ,max speed 2MHz2Speed50MOutput mode ,max speed 50MHz3 ISTAT ISTAT Port input status register 0x08 0x20 read-only 0x00000000 ISTAT15 Port input status 15 1 ISTAT14 Port input status 14 1 ISTAT13 Port input status 13 1 ISTAT12 Port input status 12 1 ISTAT11 Port input status 11 1 ISTAT10 Port input status 10 1 ISTAT9 Port input status 9 1 ISTAT8 Port input status 8 1 ISTAT7 Port input status 7 1 ISTAT6 Port input status 6 1 ISTAT5 Port input status 5 1 ISTAT4 Port input status 4 1 ISTAT3 Port input status 3 1 ISTAT2 Port input status 2 1 ISTAT1 Port input status 1 1 ISTAT0 Port input status 0 1 ISTAT0read-writeLowInput is logic low0HighInput is logic high1 OCTL OCTL Port output control register 0x0C 0x20 read-write 0x00000000 OCTL15 Port output control 15 1 OCTL14 Port output control 14 1 OCTL13 Port output control 13 1 OCTL12 Port output control 12 1 OCTL11 Port output control 11 1 OCTL10 Port output control 10 1 OCTL9 Port output control 9 1 OCTL8 Port output control 8 1 OCTL7 Port output control 7 1 OCTL6 Port output control 6 1 OCTL5 Port output control 5 1 OCTL4 Port output control 4 1 OCTL3 Port output control 3 1 OCTL2 Port output control 2 1 OCTL1 Port output control 1 1 OCTL0 Port output control 0 1 OCTL0read-writeLowSet output to logic low0HighSet output to logic high1 BOP BOP Port bit operate register 0x10 0x20 write-only 0x00000000 CR15 Port 15 Clear bit 31 1 CR14 Port 14 Clear bit 30 1 CR13 Port 13 Clear bit 29 1 CR12 Port 12 Clear bit 28 1 CR11 Port 11 Clear bit 27 1 CR10 Port 10 Clear bit 26 1 CR9 Port 9 Clear bit 25 1 CR8 Port 8 Clear bit 24 1 CR7 Port 7 Clear bit 23 1 CR6 Port 6 Clear bit 22 1 CR5 Port 5 Clear bit 21 1 CR4 Port 4 Clear bit 20 1 CR3 Port 3 Clear bit 19 1 CR2 Port 2 Clear bit 18 1 CR1 Port 1 Clear bit 17 1 CR0 Port 0 Clear bit 16 1 CR0WwriteResetResets the corresponding OCTLx bit1 BOP15 Port 15 Set bit 15 1 BOP14 Port 14 Set bit 14 1 BOP13 Port 13 Set bit 13 1 BOP12 Port 12 Set bit 12 1 BOP11 Port 11 Set bit 11 1 BOP10 Port 10 Set bit 10 1 BOP9 Port 9 Set bit 9 1 BOP8 Port 8 Set bit 8 1 BOP7 Port 7 Set bit 7 1 BOP6 Port 6 Set bit 6 1 BOP5 Port 5 Set bit 5 1 BOP4 Port 4 Set bit 4 1 BOP3 Port 3 Set bit 3 1 BOP2 Port 2 Set bit 2 1 BOP1 Port 1 Set bit 1 1 BOP0 Port 0 Set bit 0 1 BOP0WwriteSetSets the corresponding OCTLx bit1 BC BC Port bit clear register 0x14 0x20 write-only 0x00000000 CR15 Port 15 Clear bit 15 1 CR14 Port 14 Clear bit 14 1 CR13 Port 13 Clear bit 13 1 CR12 Port 12 Clear bit 12 1 CR11 Port 11 Clear bit 11 1 CR10 Port 10 Clear bit 10 1 CR9 Port 9 Clear bit 9 1 CR8 Port 8 Clear bit 8 1 CR7 Port 7 Clear bit 7 1 CR6 Port 6 Clear bit 6 1 CR5 Port 5 Clear bit 5 1 CR4 Port 4 Clear bit 4 1 CR3 Port 3 Clear bit 3 1 CR2 Port 2 Clear bit 2 1 CR1 Port 1 Clear bit 1 1 CR0 Port 0 Clear bit 0 1 CR0WwriteResetResets the corresponding OCTLx bit1 LOCK LOCK GPIO port configuration lock register 0x18 0x20 read-write 0x00000000 LKK Lock sequence key 16 1 LK15 Port Lock bit 15 15 1 LK14 Port Lock bit 14 14 1 LK13 Port Lock bit 13 13 1 LK12 Port Lock bit 12 12 1 LK11 Port Lock bit 11 11 1 LK10 Port Lock bit 10 10 1 LK9 Port Lock bit 9 9 1 LK8 Port Lock bit 8 8 1 LK7 Port Lock bit 7 7 1 LK6 Port Lock bit 6 6 1 LK5 Port Lock bit 5 5 1 LK4 Port Lock bit 4 4 1 LK3 Port Lock bit 3 3 1 LK2 Port Lock bit 2 2 1 LK1 Port Lock bit 1 1 1 LK0 Port Lock bit 0 0 1 SPD SPD Port bit speed register 0x3C 0x20 read-write 0x00000000 SPD15 Port 15 output max speed bits 15 1 SPD14 Port 14 output max speed bits 14 1 SPD13 Port 13 output max speed bits 13 1 SPD12 Port 12 output max speed bits 12 1 SPD11 Port 11 output max speed bits 11 1 SPD10 Port 10 output max speed bits 10 1 SPD9 Port 9 output max speed bits 9 1 SPD8 Port 8 output max speed bits 8 1 SPD7 Port 7 output max speed bits 7 1 SPD6 Port 6 output max speed bits 6 1 SPD5 Port 5 output max speed bits 5 1 SPD4 Port 4 output max speed bits 4 1 SPD3 Port 3 output max speed bits 3 1 SPD2 Port 2 output max speed bits 2 1 SPD1 Port 1 output max speed bits 1 1 SPD0 Port 0 output max speed bits 0 1 MASTER_TIMER SHRTIMER Master TIMER SHRTIMER 0x40017400 0x0 0x80 registers SHRTIMER_IRQ0 76 MTCTL0 MTCTL0 SHRTIMER Master_TIMER control register 0 0x00 0x20 read-write 0x00000000 UPSEL Update event selection 30 2 UPREP Update event generated by repetition event 29 1 SHWEN Shadow registers enable 27 1 DACTRGS Trigger source to DAC 25 2 ST4CEN The counter of Slave_TIMER4 enable 21 1 ST3CEN The counter of Slave_TIMER3 enable 20 1 ST2CEN The counter of Slave_TIMER2 enable 19 1 ST1CEN The counter of Slave_TIMER1 enable 18 1 ST0CEN The counter of Slave_TIMER0 enable 17 1 MTCEN The counter of Master_TIMER enable 16 1 SYNOSRC Synchronization output source 14 2 SYNOPLS Synchronization output pulse 12 2 SYNISTRT Synchronization input start counter 11 1 SYNIRST Synchronization input reset counter 10 1 SYNISRC Synchronization input source 8 2 HALFM Half mode 5 1 CNTRSTM Counter reset mode 4 1 CTNM Continuous mode 3 1 CNTCKDIV Counter clock division 0 2 MTINTF MTINTF SHRTIMER Master_TIMER interrupt flag register 0x04 0x20 read-only 0x00000000 UPIF Update interrupt flag 6 1 SYNIIF Synchronization input interrupt flag 5 1 REPIF Repetition interrupt flag 4 1 CMP3IF Compare 3 interrupt flag 3 1 CMP2IF Compare 2 interrupt flag 2 1 CMP1IF Compare 1 interrupt flag 1 1 CMP0IF Compare 0 interrupt flag 0 1 MTINTC MTINTC SHRTIMER Master_TIMER interrupt flag clear register 0x08 0x20 write-only 0x00000000 UPIFC Clear update interrupt flag 6 1 SYNIIFC Clear synchronization input interrupt flag 5 1 REPIFC Clear repetition interrupt flag 4 1 CMP3IFC Clear compare 3 interrupt flag 3 1 CMP2IFC Clear compare 2 interrupt flag 2 1 CMP1IFC Clear compare 1 interrupt flag 1 1 CMP0IFC Clear compare 0 interrupt flag 0 1 MTDMAINTEN MTDMAINTEN SHRTIMER Master_TIMER DMA and interrupt enable register 0x0C 0x20 read-write 0x00000000 UPDEN Update DMA request enable 22 1 SYNIDEN Synchronization input DMA request enable 21 1 REPDEN Repetition DMA request enable 20 1 CMP3DEN Compare 3 DMA request enable 19 1 CMP2DEN Compare 2 DMA request enable 18 1 CMP1DEN Compare 1 DMA request enable 17 1 CMP0DEN Compare 0 DMA request enable 16 1 UPIE Update interrupt enable 6 1 SYNIIE Synchronization input interrupt enable 5 1 REPIE Repetition interrupt enable 4 1 CMP3IE Compare 3 interrupt enable 3 1 CMP2IE Compare 2 interrupt enable 2 1 CMP1IE Compare 1 interrupt enable 1 1 CMP0IE Compare 0 interrupt enable 0 1 MTCNT MTCNT SHRTIMER Master_TIMER counter register 0x10 0x20 read-write 0x00000000 CNT The current counter value 0 16 MTCAR MTCAR SHRTIMER Master_TIMER counter auto reload register 0x14 0x20 read-write 0x00000000 CARL Counter auto reload value 0 16 MTCREP MTCREP SHRTIMER Master_TIMER counter repetition register 0x18 0x20 read-write 0x00000000 CREP Counter repetition value 0 8 MTCMP0V MTCMP0V SHRTIMER Master_TIMER compare 0 value register 0x1C 0x20 read-write 0x00000000 CMP0VAL Compare 0 value 0 16 MTCMP1V MTCMP1V SHRTIMER Master_TIMER compare 1 value register 0x24 0x20 read-write 0x00000000 CMP1VAL Compare 1 value 0 16 MTCMP2V MTCMP2V SHRTIMER Master_TIMER compare 2 value register 0x28 0x20 read-write 0x00000000 CMP2VAL Compare 2 value 0 16 MTCMP3V MTCMP3V SHRTIMER Master_TIMER compare 3 value register 0x2C 0x20 read-write 0x00000000 CMP3VAL Compare 3 value 0 16 MTACTL MTACTL SHRTIMER Master_TIMER additional control register 0x7C 0x20 read-write 0x00000000 CNTCKDIV_3 Counter clock division 3 1 SLAVE_TIMER0 SHRTIMER Slave TIMER0 registers( SHRTIMER 0x40017480 0x0 0x80 registers SHRTIMER_IRQ1 77 ST0CTL0 ST0CTL0 SHRTIMER Slave_TIMER0 control register 0 0x00 0x20 read-write 0x00000000 UPSEL Update event selection 28 4 SHWEN Shadow registers enable 27 1 DACTRGS Trigger source to DAC 25 2 UPBMT Update by Master_TIMER update event 24 1 UPBST4 Update by Slave_TIMER4 update event 23 1 UPBST3 Update by Slave_TIMER3 update event 22 1 UPBST2 Update by Slave_TIMER2 update event 21 1 UPBST1 Update by Slave_TIMER1 update event 20 1 UPRST Update event generated by reset event 18 1 UPREP Update event generated by repetition event 17 1 DELCMP3M Compare 3 delayed mode 14 2 DELCMP1M Compare 1 delayed mode 12 2 SYNISTRT Synchronization input start counter 11 1 SYNIRST Synchronization input reset counter 10 1 BLNMEN Balanced mode enable 6 1 HALFM Half mode 5 1 CNTRSTM Counter reset mode 4 1 CTNM Continuous mode 3 1 CNTCKDIV Counter clock division 0 3 ST0INTF ST0INTF SHRTIMER Slave_TIMER0 interrupt flag register 0x04 0x20 read-only 0x00000000 CH1F Channel 1 output flag 21 1 CH0F Channel 0 output flag 20 1 BLNIF Balanced IDLE flag 17 1 CBLNF Current balanced flag 16 1 DLYIIF Delayed IDLE mode entry interrupt flag 14 1 RSTIF Counter reset interrupt flag 13 1 CH1ONAIF Channel 1 output inactive interrupt flag 12 1 CH1OAIF Channel 1 output active interrupt flag 11 1 CH0ONAIF Channel 0 output inactive interrupt flag 10 1 CH0OAIF Channel 0 output active interrupt flag 9 1 CAP1IF Capture 1 interrupt flag 8 1 CAP0IF Capture 0 interrupt flag 7 1 UPIF Update interrupt flag 6 1 REPIF Repetition interrupt flag 4 1 CMP3IF Compare 3 interrupt flag 3 1 CMP2IF Compare 2 interrupt flag 2 1 CMP1IF Compare 1 interrupt flag 1 1 CMP0IF Compare 0 interrupt flag 0 1 ST0INTC ST0INTC SHRTIMER Slave_TIMER0 interrupt flag clear register 0x08 0x20 write-only 0x00000000 DLYIIFC Clear delayed IDLE mode entry interrupt flag 14 1 RSTIFC Clear counter reset interrupt flag 13 1 CH1ONAIFC Clear channel 1 output inactive interrupt flag 12 1 CH1OAIFC Clear channel 1 output active interrupt flag 11 1 CH0ONAIFC Clear channel 0 output inactive interrupt flag 10 1 CH0OAIFC Clear channel 0 output active interrupt flag 9 1 CAP1IFC Clear capture 1 interrupt flag 8 1 CAP0IFC Clear capture 0 interrupt flag 7 1 UPIFC Clear update interrupt flag 6 1 REPIFC Clear repetition interrupt flag 4 1 CMP3IFC Clear compare 3 interrupt flag 3 1 CMP2IFC Clear compare 2 interrupt flag 2 1 CMP1IFC Clear compare 1 interrupt flag 1 1 CMP0IFC Clear compare 0 interrupt flag 0 1 ST0DMAINTEN ST0DMAINTEN SHRTIMER Slave_TIMER0 DMA and interrupt enable register 0x0C 0x20 read-write 0x00000000 DLYIDEN Delayed IDLE mode entry DMA request enable 30 1 RSTDEN Counter reset DMA request enable 29 1 CH1ONADEN Channel 1 output inactive DMA request enable 28 1 CH1OADEN Channel 1 output active DMA request enable 27 1 CH0ONADEN Channel 0 output inactive DMA request enable 26 1 CH0ADEN Channel 0 output active DMA request enable 25 1 CAP1DEN Capture 1 DMA request enable 24 1 CAP0DEN Capture 0 DMA request enable 23 1 UPDEN Update DMA request enable 22 1 REPDEN Repetition DMA request enable 20 1 CMP3DEN Compare 3 DMA request enable 19 1 CMP2DEN Compare 2 DMA request enable 18 1 CMP1DEN Compare 1 DMA request enable 17 1 CMP0DEN Compare 0 DMA request enable 16 1 DLYIIE Delayed IDLE mode entry interrupt enable 14 1 RSTIE Counter reset interrupt enable 13 1 CH1ONAIE Channel 1 output inactive interrupt enable 12 1 CH1OAIE Channel 1 output active interrupt enable 11 1 CH0ONAIE Channel 0 output inactive interrupt enable 10 1 CH0OAIE Channel 0 output active interrupt enable 9 1 CAP1IE Capture 1 interrupt enable 8 1 CAP0IE Capture 0 interrupt enable 7 1 UPIE Update interrupt enable 6 1 REPIE Repetition interrupt enable 4 1 CMP3IE Compare 3 interrupt enable 3 1 CMP2IE Compare 2 interrupt enable 2 1 CMP1IE Compare 1 interrupt enable 1 1 CMP0IE Compare 0 interrupt enable 0 1 ST0CNT ST0CNT SHRTIMER Slave_TIMER0 counter register 0x10 0x20 read-write 0x00000000 CNT The current counter value 0 16 ST0CAR ST0CAR SHRTIMER Slave_TIMER0 counter auto reload register 0x14 0x20 read-write 0x00000000 CARL Counter auto reload value 0 16 ST0CREP ST0CREP SHRTIMER Slave_TIMER0 counter repetition register 0x18 0x20 read-write 0x00000000 CREP Counter repetition value 0 8 ST0CMP0V ST0CMP0V SHRTIMER Slave_TIMER0 compare 0 value register 0x1C 0x20 read-write 0x00000000 CMP0VAL Compare 0 value 0 16 ST0CMP0CP ST0CMP0CP SHRTIMER Slave_TIMER0 compare 0 composite register 0x20 0x20 read-write 0x00000000 CREP Counter repetition value 16 8 CMP0VAL Compare 0 value 0 16 ST0CMP1V ST0CMP1V SHRTIMER Slave_TIMER0 compare 1 value register 0x24 0x20 read-write 0x00000000 CMP1VAL Compare 1 value 0 16 ST0CMP2V ST0CMP2V SHRTIMER Slave_TIMER0 compare 2 value register 0x28 0x20 read-write 0x00000000 CMP2VAL Compare 2 value 0 16 ST0CMP3V ST0CMP3V SHRTIMER Slave_TIMER0 compare 3 value register 0x2C 0x20 read-write 0x00000000 CMP3VAL Compare 3 value 0 16 ST0CAP0V ST0CAP0V SHRTIMER Slave_TIMER0 capture 0 value register 0x30 0x20 read-write 0x00000000 CAP0VAL Capture 0 value 0 16 ST0CAP1V ST0CAP1V SHRTIMER Slave_TIMER0 capture 1 value register 0x34 0x20 read-write 0x00000000 CAP1VAL Capture 1 value 0 16 ST0DTCTL ST0DTCTL SHRTIMER Slave_TIMER0 dead-time control register 0x38 0x20 read-write 0x00000000 DTFSVPROT Dead-time falling edge protection for value and sign 31 1 DTFSPROT Dead-time falling edge protection for sign 30 1 DTFS The sign of falling edge dead-time value 25 1 DTFCFG Falling edge dead-time value 16 9 DTRSVPROT Dead-time rising edge protection for value and sign 15 1 DTRSPROT Dead-time rising edge protection for sign 14 1 DTGCKDIV Dead time generator clock division 10 4 DTRS The sign of falling edge dead-time value 9 1 DTRCFG Falling edge dead-time value 0 9 ST0CH0SET ST0CH0SET SHRTIMER Slave_TIMERx channel 0 set request register 0x3C 0x20 read-write 0x00000000 CH0SUP Update event generates channel 0 31 1 CH0SEXEV9 External event 9 generates channel 0 30 1 CH0SEXEV8 External event 8 generates channel 0 29 1 CH0SEXEV7 External event 7 generates channel 0 28 1 CH0SEXEV6 External event 6 generates channel 0 27 1 CH0SEXEV5 External event 5 generates channel 0 26 1 CH0SEXEV4 External event 4 generates channel 0 25 1 CH0SEXEV3 External event 3 generates channel 0 24 1 CH0SEXEV2 External event 2 generates channel 0 23 1 CH0SEXEV1 External event 1 generates channel 0 22 1 CH0SEXEV0 External event 0 generates channel 0 21 1 CH0SSTEV8 Slave_TIMER0 interconnection event 8 generates channel 0 20 1 CH0SSTEV7 Slave_TIMER0 interconnection event 7 generates channel 0 19 1 CH0SSTEV6 Slave_TIMER0 interconnection event 6 generates channel 0 18 1 CH0SSTEV5 Slave_TIMER0 interconnection event 5 generates channel 0 17 1 CH0SSTEV4 Slave_TIMER0 interconnection event 4 generates channel 0 16 1 CH0SSTEV3 Slave_TIMER0 interconnection event 3 generates channel 0 15 1 CH0SSTEV2 Slave_TIMER0 interconnection event 2 generates channel 0 14 1 CH0SSTEV1 Slave_TIMER0 interconnection event 1 generates channel 0 13 1 CH0SSTEV0 Slave_TIMER0 interconnection event 0 generates channel 0 12 1 CH0SMTCMP3 Master_TIMER compare 3 event generates channel 0 11 1 CH0SMTCMP2 Master_TIMER compare 2 event generates channel 0 10 1 CH0SMTCMP1 Master_TIMER compare 1 event generates channel 0 9 1 CH0SMTCMP0 Master_TIMER compare 0 event generates channel 0 8 1 CH0SMTPER Master_TIMER period event generates channel 0 7 1 CH0SCMP3 Slave_TIMER0 compare 3 event generates channel 0 6 1 CH0SCMP2 Slave_TIMER0 compare 2 event generates channel 0 5 1 CH0SCMP1 Slave_TIMER0 compare 1 event generates channel 0 4 1 CH0SCMP0 Slave_TIMER0 compare 0 event generates channel 0 3 1 CH0SPER Slave_TIMER0 period event generates channel 0 2 1 CH0SRST Slave_TIMER0 reset event generates channel 0 1 1 CH0SSEV Software event generates channel 0 0 1 ST0CH0RST ST0CH0RST SHRTIMER Slave_TIMER0 channel 0 reset request register 0x40 0x20 read-write 0x00000000 CH0RSUP Update event generates channel 0 31 1 CH0RSEXEV9 External event 9 generates channel 0 30 1 CH0RSEXEV8 External event 8 generates channel 0 29 1 CH0RSEXEV7 External event 7 generates channel 0 28 1 CH0RSEXEV6 External event 6 generates channel 0 27 1 CH0RSEXEV5 External event 5 generates channel 0 26 1 CH0RSEXEV4 External event 4 generates channel 0 25 1 CH0RSEXEV3 External event 3 generates channel 0 24 1 CH0RSEXEV2 External event 2 generates channel 0 23 1 CH0RSEXEV1 External event 1 generates channel 0 22 1 CH0RSEXEV0 External event 0 generates channel 0 21 1 CH0RSSTEV8 Slave_TIMER0 interconnection event 8 generates channel 0 20 1 CH0RSSTEV7 Slave_TIMER0 interconnection event 7 generates channel 0 19 1 CH0RSSTEV6 Slave_TIMER0 interconnection event 6 generates channel 0 18 1 CH0RSSTEV5 Slave_TIMER0 interconnection event 5 generates channel 0 17 1 CH0RSSTEV4 Slave_TIMER0 interconnection event 4 generates channel 0 16 1 CH0RSSTEV3 Slave_TIMER0 interconnection event 3 generates channel 0 15 1 CH0RSSTEV2 Slave_TIMER0 interconnection event 2 generates channel 0 14 1 CH0RSSTEV1 Slave_TIMER0 interconnection event 1 generates channel 0 13 1 CH0RSSTEV0 Slave_TIMER0 interconnection event 0 generates channel 0 12 1 CH0RSMTCMP3 Master_TIMER compare 3 event generates channel 0 11 1 CH0RSMTCMP2 Master_TIMER compare 2 event generates channel 0 10 1 CH0RSMTCMP1 Master_TIMER compare 1 event generates channel 0 9 1 CH0RSMTCMP0 Master_TIMER compare 0 event generates channel 0 8 1 CH0RSMTPER Master_TIMER period event generates channel 0 7 1 CH0RSCMP3 Slave_TIMER0 compare 3 event generates channel 0 6 1 CH0RSCMP2 Slave_TIMER0 compare 2 event generates channel 0 5 1 CH0RSCMP1 Slave_TIMER0 compare 1 event generates channel 0 4 1 CH0RSCMP0 Slave_TIMER0 compare 0 event generates channel 0 3 1 CH0RSPER Slave_TIMER0 period event generates channel 0 2 1 CH0RSRST Slave_TIMER0 reset event generates channel 0 1 1 CH0RSSEV Software event generates channel 0 0 1 ST0CH1SET ST0CH1SET SHRTIMER Slave_TIMER0 channel 1 set request register 0x44 0x20 read-write 0x00000000 CH1SUP Update event generates channel 1 31 1 CH1SEXEV9 External event 9 generates channel 1 30 1 CH1SEXEV8 External event 8 generates channel 1 29 1 CH1SEXEV7 External event 7 generates channel 1 28 1 CH1SEXEV6 External event 6 generates channel 1 27 1 CH1SEXEV5 External event 5 generates channel 1 26 1 CH1SEXEV4 External event 4 generates channel 1 25 1 CH1SEXEV3 External event 3 generates channel 1 24 1 CH1SEXEV2 External event 2 generates channel 1 23 1 CH1SEXEV1 External event 1 generates channel 1 22 1 CH1SEXEV0 External event 0 generates channel 1 21 1 CH1SSTEV8 Slave_TIMER0 interconnection event 8 generates channel 1 20 1 CH1SSTEV7 Slave_TIMER0 interconnection event 7 generates channel 1 19 1 CH1SSTEV6 Slave_TIMER0 interconnection event 6 generates channel 1 18 1 CH1SSTEV5 Slave_TIMER0 interconnection event 5 generates channel 1 17 1 CH1SSTEV4 Slave_TIMER0 interconnection event 4 generates channel 1 16 1 CH1SSTEV3 Slave_TIMER0 interconnection event 3 generates channel 1 15 1 CH1SSTEV2 Slave_TIMER0 interconnection event 2 generates channel 1 14 1 CH1SSTEV1 Slave_TIMER0 interconnection event 1 generates channel 1 13 1 CH1SSTEV0 Slave_TIMER0 interconnection event 0 generates channel 1 12 1 CH1SMTCMP3 Master_TIMER compare 3 event generates channel 1 11 1 CH1SMTCMP2 Master_TIMER compare 2 event generates channel 1 10 1 CH1SMTCMP1 Master_TIMER compare 1 event generates channel 1 9 1 CH1SMTCMP0 Master_TIMER compare 0 event generates channel 1 8 1 CH1SMTPER Master_TIMER period event generates channel 1 7 1 CH1SCMP3 Slave_TIMER0 compare 3 event generates channel 1 6 1 CH1SCMP2 Slave_TIMER0 compare 2 event generates channel 1 5 1 CH1SCMP1 Slave_TIMER0 compare 1 event generates channel 1 4 1 CH1SCMP0 Slave_TIMER0 compare 0 event generates channel 1 3 1 CH1SPER Slave_TIMER0 period event generates channel 1 2 1 CH1SRST Slave_TIMER0 reset event generates channel 1 1 1 CH1SSEV Software event generates channel 1 0 1 ST0CH1RST ST0CH1RST SHRTIMER Slave_TIMER0 channel 1 reset request register 0x48 0x20 read-write 0x00000000 CH1RSUP Update event generates channel 1 31 1 CH1RSEXEV9 External event 9 generates channel 1 30 1 CH1RSEXEV8 External event 8 generates channel 1 29 1 CH1RSEXEV7 External event 7 generates channel 1 28 1 CH1RSEXEV6 External event 6 generates channel 1 27 1 CH1RSEXEV5 External event 5 generates channel 1 26 1 CH1RSEXEV4 External event 4 generates channel 1 25 1 CH1RSEXEV3 External event 3 generates channel 1 24 1 CH1RSEXEV2 External event 2 generates channel 1 23 1 CH1RSEXEV1 External event 1 generates channel 1 22 1 CH1RSEXEV0 External event 0 generates channel 1 21 1 CH1RSSTEV8 Slave_TIMER0 interconnection event 8 generates channel 1 20 1 CH1RSSTEV7 Slave_TIMER0 interconnection event 7 generates channel 1 19 1 CH1RSSTEV6 Slave_TIMER0 interconnection event 6 generates channel 1 18 1 CH1RSSTEV5 Slave_TIMER0 interconnection event 5 generates channel 1 17 1 CH1RSSTEV4 Slave_TIMER0 interconnection event 4 generates channel 1 16 1 CH1RSSTEV3 Slave_TIMER0 interconnection event 3 generates channel 1 15 1 CH1RSSTEV2 Slave_TIMER0 interconnection event 2 generates channel 1 14 1 CH1RSSTEV1 Slave_TIMER0 interconnection event 1 generates channel 1 13 1 CH1RSSTEV0 Slave_TIMER0 interconnection event 0 generates channel 1 12 1 CH1RSMTCMP3 Master_TIMER compare 3 event generates channel 1 11 1 CH1RSMTCMP2 Master_TIMER compare 2 event generates channel 1 10 1 CH1RSMTCMP1 Master_TIMER compare 1 event generates channel 1 9 1 CH1RSMTCMP0 Master_TIMER compare 0 event generates channel 1 8 1 CH1RSMTPER Master_TIMER period event generates channel 1 7 1 CH1RSCMP3 Slave_TIMER0 compare 3 event generates channel 1 6 1 CH1RSCMP2 Slave_TIMER0 compare 2 event generates channel 1 5 1 CH1RSCMP1 Slave_TIMER0 compare 1 event generates channel 1 4 1 CH1RSCMP0 Slave_TIMER0 compare 0 event generates channel 1 3 1 CH1RSPER Slave_TIMER0 period event generates channel 1 2 1 CH1RSRST Slave_TIMER0 reset event generates channel 1 1 1 CH1RSSEV Software event generates channel 1 0 1 ST0EXEVFCFG0 ST0EXEVFCFG0 SHRTIMER Slave_TIMERx external event filter configuration register 0 0x4C 0x20 read-write 0x00000000 EXEV4FM External event 4 filter mode 25 4 EXEV4MEEN External event 4 memorized enable 24 1 EXEV3FM External event 3 filter mode 19 4 EXEV3MEEN External event 3 memorized enable 18 1 EXEV2FM External event 2 filter mode 13 4 EXEV2MEEN External event 2 memorized enable 12 1 EXEV1FM External event 1 filter mode 7 4 EXEV1MEEN External event 1 memorized enable 6 1 EXEV0FM External event 0 filter mode 1 4 EXEV0MEEN External event 0 memorized enable 0 1 ST0EXEVFCFG1 ST0EXEVFCFG1 SHRTIMER Slave_TIMERx external event filter configuration register 1 0x50 0x20 read-write 0x00000000 EXEV9FM External event 9 filter mode 25 4 EXEV9MEEN External event 9 memorized enable 24 1 EXEV8FM External event 8 filter mode 19 4 EXEV8MEEN External event 8 memorized enable 18 1 EXEV7FM External event 7 filter mode 13 4 EXEV7MEEN External event 7 memorized enable 12 1 EXEV6FM External event 6 filter mode 7 4 EXEV6MEEN External event 6 memorized enable 6 1 EXEV5FM External event 5 filter mode 1 4 EXEV5MEEN External event 5 memorized enable 0 1 ST0CNTRST ST0CNTRST SHRTIMER Slave_TIMER0 counter reset register 0x54 0x20 read-write 0x00000000 ST4CMP3RST Slave_TIMER4 compare 3 event resets counter 30 1 ST4CMP1RST Slave_TIMER4 compare 1 event resets counter 29 1 ST4CMP0RST Slave_TIMER4 compare 0 event resets counter 28 1 ST3CMP3RST Slave_TIMER3 compare 3 event resets counter 27 1 ST3CMP1RST Slave_TIMER3 compare 1 event resets counter 26 1 ST3CMP0RST Slave_TIMER3 compare 0 event resets counter 25 1 ST2CMP3RST Slave_TIMER2 compare 3 event resets counter 24 1 ST2CMP1RST Slave_TIMER2 compare 1 event resets counter 23 1 ST2CMP0RST Slave_TIMER2 compare 0 event resets counter 22 1 ST1CMP3RST Slave_TIMER1 compare 3 event resets counter 21 1 ST1CMP1RST Slave_TIMER1 compare 1 event resets counter 20 1 ST1CMP0RST Slave_TIMER1 compare 0 event resets counter 19 1 EXEV9RST External event 9 resets counter 18 1 EXEV8RST External event 8 resets counter 17 1 EXEV7RST External event 7 resets counter 16 1 EXEV6RST External event 6 resets counter 15 1 EXEV5RST External event 5 resets counter 14 1 EXEV4RST External event 4 resets counter 13 1 EXEV3RST External event 3 resets counter 12 1 EXEV2RST External event 2 resets counter 11 1 EXEV1RST External event 1 resets counter 10 1 EXEV0RST External event 0 resets counter 9 1 MTCMP3RST Master_TIMER compare 3 event resets counter 8 1 MTCMP2RST Master_TIMER compare 2 event resets counter 7 1 MTCMP1RST Master_TIMER compare 1 event resets counter 6 1 MTCMP0RST Master_TIMER compare 0 event resets counter 5 1 MTPERRST Master_TIMER period event resets counter 4 1 CMP3RST Slave_TIMER0 compare 3 event resets counter 3 1 CMP1RST Slave_TIMER0 compare 1 event resets counter 2 1 UPRST Slave_TIMER0 update event resets counter 1 1 ST0CSCTL ST0CSCTL SHRTIMER Slave_TIMERx carrier-signal control register 0x58 0x20 read-write 0x00000000 CSFSTPW First carrier-signal pulse width 7 4 CSDTY Carrier signal duty cycle 4 3 CSPRD Carrier signal period 0 4 ST0CAP0TRG ST0CAP0TRG SHRTIMER Slave_TIMER0 capture 0 trigger register 0x5C 0x20 read-write 0x00000000 CP0BST4CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER4 31 1 CP0BST4CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER4 30 1 CP0BST4NA Capture 0 triggered by ST4CH0_O output active to inactive transition 29 1 CP0BST4A Capture 0 triggered by ST4CH0_O output inactive to active transition 28 1 CP0BST3CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER3 27 1 CP0BST3CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER3 26 1 CP0BST3NA Capture 0 triggered by ST3CH0_O output active to inactive transition 25 1 CP0BST3A Capture 0 triggered by ST3CH0_O output inactive to active transition 24 1 CP0BST2CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER2 23 1 CP0BST2CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER2 22 1 CP0BST2NA Capture 0 triggered by ST2CH0_O output active to inactive transition 21 1 CP0BST2A Capture 0 triggered by ST2CH0_O output inactive to active transition 20 1 CP0BST1CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER1 19 1 CP0BST1CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER1 18 1 CP0BST1NA Capture 0 triggered by ST1CH0_O output active to inactive transition 17 1 CP0BST1A Capture 0 triggered by ST1CH0_O output inactive to active transition 16 1 CP0BEXEV9 Capture 0 triggered by external event 9 11 1 CP0BEXEV8 Capture 0 triggered by external event 8 10 1 CP0BEXEV7 Capture 0 triggered by external event 7 9 1 CP0BEXEV6 Capture 0 triggered by external event 6 8 1 CP0BEXEV5 Capture 0 triggered by external event 5 7 1 CP0BEXEV4 Capture 0 triggered by external event 4 6 1 CP0BEXEV3 Capture 0 triggered by external event 3 5 1 CP0BEXEV2 Capture 0 triggered by external event 2 4 1 CP0BEXEV1 Capture 0 triggered by external event 1 3 1 CP0BEXEV0 Capture 0 triggered by external event 0 2 1 CP0BUP Capture 0 triggered by update event 1 1 CP0BSW Capture 0 triggered by software 0 1 ST0CAP1TRG ST0CAP1TRG SHRTIMER Slave_TIMER0 capture 1 trigger register 0x60 0x20 read-write 0x00000000 CP1BST4CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER4 31 1 CP1BST4CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER4 30 1 CP1BST4NA Capture 1 triggered by ST4CH0_O output active to inactive transition 29 1 CP1BST4A Capture 1 triggered by ST4CH0_O output inactive to active transition 28 1 CP1BST3CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER3 27 1 CP1BST3CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER3 26 1 CP1BST3NA Capture 1 triggered by ST3CH0_O output active to inactive transition 25 1 CP1BST3A Capture 1 triggered by ST3CH0_O output inactive to active transition 24 1 CP1BST2CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER2 23 1 CP1BST2CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER2 22 1 CP1BST2NA Capture 1 triggered by ST2CH0_O output active to inactive transition 21 1 CP1BST2A Capture 1 triggered by ST2CH0_O output inactive to active transition 20 1 CP1BST1CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER1 19 1 CP1BST1CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER1 18 1 CP1BST1NA Capture 1 triggered by ST1CH0_O output active to inactive transition 17 1 CP1BST1A Capture 1 triggered by ST1CH0_O output inactive to active transition 16 1 CP1BEXEV9 Capture 1 triggered by external event 9 11 1 CP1BEXEV8 Capture 1 triggered by external event 8 10 1 CP1BEXEV7 Capture 1 triggered by external event 7 9 1 CP1BEXEV6 Capture 1 triggered by external event 6 8 1 CP1BEXEV5 Capture 1 triggered by external event 5 7 1 CP1BEXEV4 Capture 1 triggered by external event 4 6 1 CP1BEXEV3 Capture 1 triggered by external event 3 5 1 CP1BEXEV2 Capture 1 triggered by external event 2 4 1 CP1BEXEV1 Capture 1 triggered by external event 1 3 1 CP1BEXEV0 Capture 1 triggered by external event 0 2 1 CP1BUP Capture 1 triggered by update event 1 1 CP1BSW Capture 1 triggered by software 0 1 ST0CHOCTL ST0CHOCTL SHRTIMER Slave_TIMERx channel output control register 0x64 0x20 read-write 0x00000000 BMCH1DTI Channel 1 dead-time insert in bunch mode 23 1 CH1CSEN Channel 1 carrier-signal mode enable 22 1 CH1FLTOS Channel 1 Fault output state 20 2 ISO1 channel 1 output idle state 19 1 BMCH1IEN Channel 1 IDLE state enable in bunch mode 18 1 CH1P Channel 1 output polarity 17 1 DLYISCH Delayed IDLE source and channel 10 3 DLYISMEN Delayed IDLE state mode enable 9 1 DTEN Dead time enable 8 1 BMCH0DTI Channel 0 dead-time insert in bunch mode 7 1 CH0CSEN Channel 0 carrier-signal mode enable 6 1 CH0FLTOS Channel 0 Fault output state 4 2 ISO0 Channel 0 output idle state 3 1 BMCH0IEN Channel 0 IDLE state enable in bunch mode 2 1 CH0P Channel 0 output polarity 1 1 ST0FLTCTL ST0FLTCTL SHRTIMER Slave_TIMERx fault control register 0x68 0x20 read-write 0x00000000 FLTENPROT Protect fault enable 31 1 FLT4EN Fault 4 enable 4 1 FLT3EN Fault 3 enable 3 1 FLT2EN Fault 2 enable 2 1 FLT1EN Fault 1 enable 1 1 FLT0EN Fault 0 enable 0 1 ST0ACTL ST0ACTL SHRTIMER Slave_TIMERx additional control register 0x7C 0x20 read-write 0x00000000 DTFCFG_15_9 Falling edge dead-time value configure 25 7 DTRCFG_15_9 Rising edge dead-time value configure 9 7 CNTCKDIV_3 Counter clock division 3 1 SLAVE_TIMER1 SHRTIMER Slave TIMER1 registers( SHRTIMER 0x40017500 0x0 0x80 registers SHRTIMER_IRQ2 69 ST1CTL0 ST1CTL0 SHRTIMER Slave_TIMER1 control register 0 0x00 0x20 read-write 0x00000000 UPSEL Update event selection 28 4 SHWEN Shadow registers enable 27 1 DACTRGS Trigger source to DAC 25 2 UPBMT Update by Master_TIMER update event 24 1 UPBST4 Update by Slave_TIMER4 update event 23 1 UPBST3 Update by Slave_TIMER3 update event 22 1 UPBST2 Update by Slave_TIMER2 update event 21 1 UPBST0 Update by Slave_TIMER0 update event 19 1 UPRST Update event generated by reset event 18 1 UPREP Update event generated by repetition event 17 1 DELCMP3M Compare 3 delayed mode 14 2 DELCMP1M Compare 1 delayed mode 12 2 SYNISTRT Synchronization input start counter 11 1 SYNIRST Synchronization input reset counter 10 1 BLNMEN Balanced mode enable 6 1 HALFM Half mode 5 1 CNTRSTM Counter reset mode 4 1 CTNM Continuous mode 3 1 CNTCKDIV Counter clock division 0 3 ST1INTF ST1INTF SHRTIMER Slave_TIMER1 interrupt flag register 0x04 0x20 read-only 0x00000000 CH1F Channel 1 output flag 21 1 CH0F Channel 0 output flag 20 1 BLNIF Balanced IDLE flag 17 1 CBLNF Current balanced flag 16 1 DLYIIF Delayed IDLE mode entry interrupt flag 14 1 RSTIF Counter reset interrupt flag 13 1 CH1ONAIF Channel 1 output inactive interrupt flag 12 1 CH1OAIF Channel 1 output active interrupt flag 11 1 CH0ONAIF Channel 0 output inactive interrupt flag 10 1 CH0OAIF Channel 0 output active interrupt flag 9 1 CAP1IF Capture 1 interrupt flag 8 1 CAP0IF Capture 0 interrupt flag 7 1 UPIF Update interrupt flag 6 1 REPIF Repetition interrupt flag 4 1 CMP3IF Compare 3 interrupt flag 3 1 CMP2IF Compare 2 interrupt flag 2 1 CMP1IF Compare 1 interrupt flag 1 1 CMP0IF Compare 0 interrupt flag 0 1 ST1INTC ST1INTC SHRTIMER Slave_TIMER1 interrupt flag clear register 0x08 0x20 write-only 0x00000000 DLYIIFC Clear delayed IDLE mode entry interrupt flag 14 1 RSTIFC Clear counter reset interrupt flag 13 1 CH1ONAIFC Clear channel 1 output inactive interrupt flag 12 1 CH1OAIFC Clear channel 1 output active interrupt flag 11 1 CH0ONAIFC Clear channel 0 output inactive interrupt flag 10 1 CH0OAIFC Clear channel 0 output active interrupt flag 9 1 CAP1IFC Clear capture 1 interrupt flag 8 1 CAP0IFC Clear capture 0 interrupt flag 7 1 UPIFC Clear update interrupt flag 6 1 REPIFC Clear repetition interrupt flag 4 1 CMP3IFC Clear compare 3 interrupt flag 3 1 CMP2IFC Clear compare 2 interrupt flag 2 1 CMP1IFC Clear compare 1 interrupt flag 1 1 CMP0IFC Clear compare 0 interrupt flag 0 1 ST1DMAINTEN ST1DMAINTEN SHRTIMER Slave_TIMER1 DMA and interrupt enable register 0x0C 0x20 read-write 0x00000000 DLYIDEN Delayed IDLE mode entry DMA request enable 30 1 RSTDEN Counter reset DMA request enable 29 1 CH1ONADEN Channel 1 output inactive DMA request enable 28 1 CH1OADEN Channel 1 output active DMA request enable 27 1 CH0ONADEN Channel 0 output inactive DMA request enable 26 1 CH0ADEN Channel 0 output active DMA request enable 25 1 CAP1DEN Capture 1 DMA request enable 24 1 CAP0DEN Capture 0 DMA request enable 23 1 UPDEN Update DMA request enable 22 1 REPDEN Repetition DMA request enable 20 1 CMP3DEN Compare 3 DMA request enable 19 1 CMP2DEN Compare 2 DMA request enable 18 1 CMP1DEN Compare 1 DMA request enable 17 1 CMP0DEN Compare 0 DMA request enable 16 1 DLYIIE Delayed IDLE mode entry interrupt enable 14 1 RSTIE Counter reset interrupt enable 13 1 CH1ONAIE Channel 1 output inactive interrupt enable 12 1 CH1OAIE Channel 1 output active interrupt enable 11 1 CH0ONAIE Channel 0 output inactive interrupt enable 10 1 CH0OAIE Channel 0 output active interrupt enable 9 1 CAP1IE Capture 1 interrupt enable 8 1 CAP0IE Capture 0 interrupt enable 7 1 UPIE Update interrupt enable 6 1 REPIE Repetition interrupt enable 4 1 CMP3IE Compare 3 interrupt enable 3 1 CMP2IE Compare 2 interrupt enable 2 1 CMP1IE Compare 1 interrupt enable 1 1 CMP0IE Compare 0 interrupt enable 0 1 ST1CNT ST1CNT SHRTIMER Slave_TIMER1 counter register 0x10 0x20 read-write 0x00000000 CNT The current counter value 0 16 ST1CAR ST1CAR SHRTIMER Slave_TIMER1 counter auto reload register 0x14 0x20 read-write 0x00000000 CARL Counter auto reload value 0 16 ST1CREP ST1CREP SHRTIMER Slave_TIMER1 counter repetition register 0x18 0x20 read-write 0x00000000 CREP Counter repetition value 0 8 ST1CMP0V ST1CMP0V SHRTIMER Slave_TIMER1 compare 0 value register 0x1C 0x20 read-write 0x00000000 CMP0VAL Compare 0 value 0 16 ST1CMP0CP ST1CMP0CP SHRTIMER Slave_TIMER1 compare 0 composite register 0x20 0x20 read-write 0x00000000 CREP Counter repetition value 16 8 CMP0VAL Compare 0 value 0 16 ST1CMP1V ST1CMP1V SHRTIMER Slave_TIMER1 compare 1 value register 0x24 0x20 read-write 0x00000000 CMP1VAL Compare 1 value 0 16 ST1CMP2V ST1CMP2V SHRTIMER Slave_TIMER1 compare 2 value register 0x28 0x20 read-write 0x00000000 CMP2VAL Compare 2 value 0 16 ST1CMP3V ST1CMP3V SHRTIMER Slave_TIMER1 compare 3 value register 0x2C 0x20 read-write 0x00000000 CMP3VAL Compare 3 value 0 16 ST1CAP0V ST1CAP0V SHRTIMER Slave_TIMER1 capture 0 value register 0x30 0x20 read-write 0x00000000 CAP0VAL Capture 0 value 0 16 ST1CAP1V ST1CAP1V SHRTIMER Slave_TIMER1 capture 1 value register 0x34 0x20 read-write 0x00000000 CAP1VAL Capture 1 value 0 16 ST1DTCTL ST1DTCTL SHRTIMER Slave_TIMER1 dead-time control register 0x38 0x20 read-write 0x00000000 DTFSVPROT Dead-time falling edge protection for value and sign 31 1 DTFSPROT Dead-time falling edge protection for sign 30 1 DTFS The sign of falling edge dead-time value 25 1 DTFCFG Falling edge dead-time value 16 9 DTRSVPROT Dead-time rising edge protection for value and sign 15 1 DTRSPROT Dead-time rising edge protection for sign 14 1 DTGCKDIV Dead time generator clock division 10 4 DTRS The sign of falling edge dead-time value 9 1 DTRCFG Falling edge dead-time value 0 9 ST1CH0SET ST1CH0SET SHRTIMER Slave_TIMER1 channel 0 set request register 0x3C 0x20 read-write 0x00000000 CH0SUP Update event generates channel 0 31 1 CH0SEXEV9 External event 9 generates channel 0 30 1 CH0SEXEV8 External event 8 generates channel 0 29 1 CH0SEXEV7 External event 7 generates channel 0 28 1 CH0SEXEV6 External event 6 generates channel 0 27 1 CH0SEXEV5 External event 5 generates channel 0 26 1 CH0SEXEV4 External event 4 generates channel 0 25 1 CH0SEXEV3 External event 3 generates channel 0 24 1 CH0SEXEV2 External event 2 generates channel 0 23 1 CH0SEXEV1 External event 1 generates channel 0 22 1 CH0SEXEV0 External event 0 generates channel 0 21 1 CH0SSTEV8 Slave_TIMER1 interconnection event 8 generates channel 0 20 1 CH0SSTEV7 Slave_TIMER1 interconnection event 7 generates channel 0 19 1 CH0SSTEV6 Slave_TIMER1 interconnection event 6 generates channel 0 18 1 CH0SSTEV5 Slave_TIMER1 interconnection event 5 generates channel 0 17 1 CH0SSTEV4 Slave_TIMER1 interconnection event 4 generates channel 0 16 1 CH0SSTEV3 Slave_TIMER1 interconnection event 3 generates channel 0 15 1 CH0SSTEV2 Slave_TIMER1 interconnection event 2 generates channel 0 14 1 CH0SSTEV1 Slave_TIMER1 interconnection event 1 generates channel 0 13 1 CH0SSTEV0 Slave_TIMER1 interconnection event 0 generates channel 0 12 1 CH0SMTCMP3 Master_TIMER compare 3 event generates channel 0 11 1 CH0SMTCMP2 Master_TIMER compare 2 event generates channel 0 10 1 CH0SMTCMP1 Master_TIMER compare 1 event generates channel 0 9 1 CH0SMTCMP0 Master_TIMER compare 0 event generates channel 0 8 1 CH0SMTPER Master_TIMER period event generates channel 0 7 1 CH0SCMP3 Slave_TIMER1 compare 3 event generates channel 0 6 1 CH0SCMP2 Slave_TIMER1 compare 2 event generates channel 0 5 1 CH0SCMP1 Slave_TIMER1 compare 1 event generates channel 0 4 1 CH0SCMP0 Slave_TIMER1 compare 0 event generates channel 0 3 1 CH0SPER Slave_TIMER1 period event generates channel 0 2 1 CH0SRST Slave_TIMER1 reset event generates channel 0 1 1 CH0SSEV Software event generates channel 0 0 1 ST1CH0RST ST1CH0RST SHRTIMER Slave_TIMER1 channel 0 reset request register 0x40 0x20 read-write 0x00000000 CH0RSUP Update event generates channel 0 31 1 CH0RSEXEV9 External event 9 generates channel 0 30 1 CH0RSEXEV8 External event 8 generates channel 0 29 1 CH0RSEXEV7 External event 7 generates channel 0 28 1 CH0RSEXEV6 External event 6 generates channel 0 27 1 CH0RSEXEV5 External event 5 generates channel 0 26 1 CH0RSEXEV4 External event 4 generates channel 0 25 1 CH0RSEXEV3 External event 3 generates channel 0 24 1 CH0RSEXEV2 External event 2 generates channel 0 23 1 CH0RSEXEV1 External event 1 generates channel 0 22 1 CH0RSEXEV0 External event 0 generates channel 0 21 1 CH0RSSTEV8 Slave_TIMER1 interconnection event 8 generates channel 0 20 1 CH0RSSTEV7 Slave_TIMER1 interconnection event 7 generates channel 0 19 1 CH0RSSTEV6 Slave_TIMER1 interconnection event 6 generates channel 0 18 1 CH0RSSTEV5 Slave_TIMER1 interconnection event 5 generates channel 0 17 1 CH0RSSTEV4 Slave_TIMER1 interconnection event 4 generates channel 0 16 1 CH0RSSTEV3 Slave_TIMER1 interconnection event 3 generates channel 0 15 1 CH0RSSTEV2 Slave_TIMER1 interconnection event 2 generates channel 0 14 1 CH0RSSTEV1 Slave_TIMER1 interconnection event 1 generates channel 0 13 1 CH0RSSTEV0 Slave_TIMER1 interconnection event 0 generates channel 0 12 1 CH0RSMTCMP3 Master_TIMER compare 3 event generates channel 0 11 1 CH0RSMTCMP2 Master_TIMER compare 2 event generates channel 0 10 1 CH0RSMTCMP1 Master_TIMER compare 1 event generates channel 0 9 1 CH0RSMTCMP0 Master_TIMER compare 0 event generates channel 0 8 1 CH0RSMTPER Master_TIMER period event generates channel 0 7 1 CH0RSCMP3 Slave_TIMER1 compare 3 event generates channel 0 6 1 CH0RSCMP2 Slave_TIMER1 compare 2 event generates channel 0 5 1 CH0RSCMP1 Slave_TIMER1 compare 1 event generates channel 0 4 1 CH0RSCMP0 Slave_TIMER1 compare 0 event generates channel 0 3 1 CH0RSPER Slave_TIMER1 period event generates channel 0 2 1 CH0RSRST Slave_TIMER1 reset event generates channel 0 1 1 CH0RSSEV Software event generates channel 0 0 1 ST1CH1SET ST1CH1SET SHRTIMER Slave_TIMER1 channel 1 set request register 0x44 0x20 read-write 0x00000000 CH1SUP Update event generates channel 1 31 1 CH1SEXEV9 External event 9 generates channel 1 30 1 CH1SEXEV8 External event 8 generates channel 1 29 1 CH1SEXEV7 External event 7 generates channel 1 28 1 CH1SEXEV6 External event 6 generates channel 1 27 1 CH1SEXEV5 External event 5 generates channel 1 26 1 CH1SEXEV4 External event 4 generates channel 1 25 1 CH1SEXEV3 External event 3 generates channel 1 24 1 CH1SEXEV2 External event 2 generates channel 1 23 1 CH1SEXEV1 External event 1 generates channel 1 22 1 CH1SEXEV0 External event 0 generates channel 1 21 1 CH1SSTEV8 Slave_TIMERx interconnection event 8 generates channel 1 20 1 CH1SSTEV7 Slave_TIMERx interconnection event 7 generates channel 1 19 1 CH1SSTEV6 Slave_TIMERx interconnection event 6 generates channel 1 18 1 CH1SSTEV5 Slave_TIMERx interconnection event 5 generates channel 1 17 1 CH1SSTEV4 Slave_TIMERx interconnection event 4 generates channel 1 16 1 CH1SSTEV3 Slave_TIMERx interconnection event 3 generates channel 1 15 1 CH1SSTEV2 Slave_TIMERx interconnection event 2 generates channel 1 14 1 CH1SSTEV1 Slave_TIMERx interconnection event 1 generates channel 1 13 1 CH1SSTEV0 Slave_TIMERx interconnection event 0 generates channel 1 12 1 CH1SMTCMP3 Master_TIMER compare 3 event generates channel 1 11 1 CH1SMTCMP2 Master_TIMER compare 2 event generates channel 1 10 1 CH1SMTCMP1 Master_TIMER compare 1 event generates channel 1 9 1 CH1SMTCMP0 Master_TIMER compare 0 event generates channel 1 8 1 CH1SMTPER Master_TIMER period event generates channel 1 7 1 CH1SCMP3 Slave_TIMERx compare 3 event generates channel 1 6 1 CH1SCMP2 Slave_TIMERx compare 2 event generates channel 1 5 1 CH1SCMP1 Slave_TIMERx compare 1 event generates channel 1 4 1 CH1SCMP0 Slave_TIMERx compare 0 event generates channel 1 3 1 CH1SPER Slave_TIMERx period event generates channel 1 2 1 CH1SRST Slave_TIMERx reset event generates channel 1 1 1 CH1SSEV Software event generates channel 1 0 1 ST1CH1RST ST1CH1RST SHRTIMER Slave_TIMER1 channel 1 reset request register 0x48 0x20 read-write 0x00000000 CH1RSUP Update event generates channel 1 31 1 CH1RSEXEV9 External event 9 generates channel 1 30 1 CH1RSEXEV8 External event 8 generates channel 1 29 1 CH1RSEXEV7 External event 7 generates channel 1 28 1 CH1RSEXEV6 External event 6 generates channel 1 27 1 CH1RSEXEV5 External event 5 generates channel 1 26 1 CH1RSEXEV4 External event 4 generates channel 1 25 1 CH1RSEXEV3 External event 3 generates channel 1 24 1 CH1RSEXEV2 External event 2 generates channel 1 23 1 CH1RSEXEV1 External event 1 generates channel 1 22 1 CH1RSEXEV0 External event 0 generates channel 1 21 1 CH1RSSTEV8 Slave_TIMERx interconnection event 8 generates channel 1 20 1 CH1RSSTEV7 Slave_TIMERx interconnection event 7 generates channel 1 19 1 CH1RSSTEV6 Slave_TIMERx interconnection event 6 generates channel 1 18 1 CH1RSSTEV5 Slave_TIMERx interconnection event 5 generates channel 1 17 1 CH1RSSTEV4 Slave_TIMERx interconnection event 4 generates channel 1 16 1 CH1RSSTEV3 Slave_TIMERx interconnection event 3 generates channel 1 15 1 CH1RSSTEV2 Slave_TIMERx interconnection event 2 generates channel 1 14 1 CH1RSSTEV1 Slave_TIMERx interconnection event 1 generates channel 1 13 1 CH1RSSTEV0 Slave_TIMERx interconnection event 0 generates channel 1 12 1 CH1RSMTCMP3 Master_TIMER compare 3 event generates channel 1 11 1 CH1RSMTCMP2 Master_TIMER compare 2 event generates channel 1 10 1 CH1RSMTCMP1 Master_TIMER compare 1 event generates channel 1 9 1 CH1RSMTCMP0 Master_TIMER compare 0 event generates channel 1 8 1 CH1RSMTPER Master_TIMER period event generates channel 1 7 1 CH1RSCMP3 Slave_TIMERx compare 3 event generates channel 1 6 1 CH1RSCMP2 Slave_TIMERx compare 2 event generates channel 1 5 1 CH1RSCMP1 Slave_TIMERx compare 1 event generates channel 1 4 1 CH1RSCMP0 Slave_TIMERx compare 0 event generates channel 1 3 1 CH1RSPER Slave_TIMERx period event generates channel 1 2 1 CH1RSRST Slave_TIMERx reset event generates channel 1 1 1 CH1RSSEV Software event generates channel 1 0 1 ST1EXEVFCFG0 ST1EXEVFCFG0 SHRTIMER Slave_TIMERx external event filter configuration register 0 0x4C 0x20 read-write 0x00000000 EXEV4FM External event 4 filter mode 25 4 EXEV4MEEN External event 4 memorized enable 24 1 EXEV3FM External event 3 filter mode 19 4 EXEV3MEEN External event 3 memorized enable 18 1 EXEV2FM External event 2 filter mode 13 4 EXEV2MEEN External event 2 memorized enable 12 1 EXEV1FM External event 1 filter mode 7 4 EXEV1MEEN External event 1 memorized enable 6 1 EXEV0FM External event 0 filter mode 1 4 EXEV0MEEN External event 0 memorized enable 0 1 ST1EXEVFCFG1 ST1EXEVFCFG1 SHRTIMER Slave_TIMERx external event filter configuration register 1 0x50 0x20 read-write 0x00000000 EXEV9FM External event 9 filter mode 25 4 EXEV9MEEN External event 9 memorized enable 24 1 EXEV8FM External event 8 filter mode 19 4 EXEV8MEEN External event 8 memorized enable 18 1 EXEV7FM External event 7 filter mode 13 4 EXEV7MEEN External event 7 memorized enable 12 1 EXEV6FM External event 6 filter mode 7 4 EXEV6MEEN External event 6 memorized enable 6 1 EXEV5FM External event 5 filter mode 1 4 EXEV5MEEN External event 5 memorized enable 0 1 ST1CNTRST ST1CNTRST SHRTIMER Slave_TIMERx counter reset register 0x54 0x20 read-write 0x00000000 ST4CMP3RST Slave_TIMER4 compare 3 event resets counter 30 1 ST4CMP1RST Slave_TIMER4 compare 1 event resets counter 29 1 ST4CMP0RST Slave_TIMER4 compare 0 event resets counter 28 1 ST3CMP3RST Slave_TIMER3 compare 3 event resets counter 27 1 ST3CMP1RST Slave_TIMER3 compare 1 event resets counter 26 1 ST3CMP0RST Slave_TIMER3 compare 0 event resets counter 25 1 ST2CMP3RST Slave_TIMER2 compare 3 event resets counter 24 1 ST2CMP1RST Slave_TIMER2 compare 1 event resets counter 23 1 ST2CMP0RST Slave_TIMER2 compare 0 event resets counter 22 1 ST0CMP3RST Slave_TIMER0 compare 3 event resets counter 21 1 ST0CMP1RST Slave_TIMER0 compare 1 event resets counter 20 1 ST0CMP0RST Slave_TIMER0 compare 0 event resets counter 19 1 EXEV9RST External event 9 resets counter 18 1 EXEV8RST External event 8 resets counter 17 1 EXEV7RST External event 7 resets counter 16 1 EXEV6RST External event 6 resets counter 15 1 EXEV5RST External event 5 resets counter 14 1 EXEV4RST External event 4 resets counter 13 1 EXEV3RST External event 3 resets counter 12 1 EXEV2RST External event 2 resets counter 11 1 EXEV1RST External event 1 resets counter 10 1 EXEV0RST External event 0 resets counter 9 1 MTCMP3RST Master_TIMER compare 3 event resets counter 8 1 MTCMP2RST Master_TIMER compare 2 event resets counter 7 1 MTCMP1RST Master_TIMER compare 1 event resets counter 6 1 MTCMP0RST Master_TIMER compare 0 event resets counter 5 1 MTPERRST Master_TIMER period event resets counter 4 1 CMP3RST Slave_TIMER1 compare 3 event resets counter 3 1 CMP1RST Slave_TIMER1 compare 1 event resets counter 2 1 UPRST Slave_TIMER1 update event resets counter 1 1 ST1CSCTL ST1CSCTL SHRTIMER Slave_TIMERx carrier-signal control register 0x58 0x20 read-write 0x00000000 CSFSTPW First carrier-signal pulse width 7 4 CSDTY Carrier signal duty cycle 4 3 CSPRD Carrier signal period 0 4 ST1CAP0TRG ST1CAP0TRG SHRTIMER Slave_TIMERx capture 0 trigger register 0x5C 0x20 read-write 0x00000000 CP0BST4CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER4 31 1 CP0BST4CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER4 30 1 CP0BST4NA Capture 0 triggered by ST4CH0_O output active to inactive transition 29 1 CP0BST4A Capture 0 triggered by ST4CH0_O output inactive to active transition 28 1 CP0BST3CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER3 27 1 CP0BST3CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER3 26 1 CP0BST3NA Capture 0 triggered by ST3CH0_O output active to inactive transition 25 1 CP0BST3A Capture 0 triggered by ST3CH0_O output inactive to active transition 24 1 CP0BST2CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER2 23 1 CP0BST2CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER2 22 1 CP0BST2NA Capture 0 triggered by ST2CH0_O output active to inactive transition 21 1 CP0BST2A Capture 0 triggered by ST2CH0_O output inactive to active transition 20 1 CP0BST0CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER0 15 1 CP0BST0CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER0 14 1 CP0BST0NA Capture 0 triggered by ST0CH0_O output active to inactive transition 13 1 CP0BST0A Capture 0 triggered by ST0CH0_O output inactive to active transition 12 1 CP0BEXEV9 Capture 0 triggered by external event 9 11 1 CP0BEXEV8 Capture 0 triggered by external event 8 10 1 CP0BEXEV7 Capture 0 triggered by external event 7 9 1 CP0BEXEV6 Capture 0 triggered by external event 6 8 1 CP0BEXEV5 Capture 0 triggered by external event 5 7 1 CP0BEXEV4 Capture 0 triggered by external event 4 6 1 CP0BEXEV3 Capture 0 triggered by external event 3 5 1 CP0BEXEV2 Capture 0 triggered by external event 2 4 1 CP0BEXEV1 Capture 0 triggered by external event 1 3 1 CP0BEXEV0 Capture 0 triggered by external event 0 2 1 CP0BUP Capture 0 triggered by update event 1 1 CP0BSW Capture 0 triggered by software 0 1 ST1CAP1TRG ST1CAP1TRG SHRTIMER Slave_TIMERx capture 1 trigger register 0x60 0x20 read-write 0x00000000 CP1BST4CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER4 31 1 CP1BST4CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER4 30 1 CP1BST4NA Capture 1 triggered by ST4CH0_O output active to inactive transition 29 1 CP1BST4A Capture 1 triggered by ST4CH0_O output inactive to active transition 28 1 CP1BST3CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER3 27 1 CP1BST3CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER3 26 1 CP1BST3NA Capture 1 triggered by ST3CH0_O output active to inactive transition 25 1 CP1BST3A Capture 1 triggered by ST3CH0_O output inactive to active transition 24 1 CP1BST2CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER2 23 1 CP1BST2CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER2 22 1 CP1BST2NA Capture 1 triggered by ST2CH0_O output active to inactive transition 21 1 CP1BST2A Capture 1 triggered by ST2CH0_O output inactive to active transition 20 1 CP1BST0CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER0 15 1 CP1BST0CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER0 14 1 CP1BST0NA Capture 1 triggered by ST0CH0_O output active to inactive transition 13 1 CP1BST0A Capture 1 triggered by ST0CH0_O output inactive to active transition 12 1 CP1BEXEV9 Capture 1 triggered by external event 9 11 1 CP1BEXEV8 Capture 1 triggered by external event 8 10 1 CP1BEXEV7 Capture 1 triggered by external event 7 9 1 CP1BEXEV6 Capture 1 triggered by external event 6 8 1 CP1BEXEV5 Capture 1 triggered by external event 5 7 1 CP1BEXEV4 Capture 1 triggered by external event 4 6 1 CP1BEXEV3 Capture 1 triggered by external event 3 5 1 CP1BEXEV2 Capture 1 triggered by external event 2 4 1 CP1BEXEV1 Capture 1 triggered by external event 1 3 1 CP1BEXEV0 Capture 1 triggered by external event 0 2 1 CP1BUP Capture 1 triggered by update event 1 1 CP1BSW Capture 1 triggered by software 0 1 ST1CHOCTL ST1CHOCTL SHRTIMER Slave_TIMERx channel output control register 0x64 0x20 read-write 0x00000000 BMCH1DTI Channel 1 dead-time insert in bunch mode 23 1 CH1CSEN Channel 1 carrier-signal mode enable 22 1 CH1FLTOS Channel 1 Fault output state 20 2 ISO1 channel 1 output idle state 19 1 BMCH1IEN Channel 1 IDLE state enable in bunch mode 18 1 CH1P Channel 1 output polarity 17 1 DLYISCH Delayed IDLE source and channel 10 3 DLYISMEN Delayed IDLE state mode enable 9 1 DTEN Dead time enable 8 1 BMCH0DTI Channel 0 dead-time insert in bunch mode 7 1 CH0CSEN Channel 0 carrier-signal mode enable 6 1 CH0FLTOS Channel 0 Fault output state 4 2 ISO0 Channel 0 output idle state 3 1 BMCH0IEN Channel 0 IDLE state enable in bunch mode 2 1 CH0P Channel 0 output polarity 1 1 ST1FLTCTL ST1FLTCTL SHRTIMER Slave_TIMERx fault control register 0x68 0x20 read-write 0x00000000 FLTENPROT Protect fault enable 31 1 FLT4EN Fault 4 enable 4 1 FLT3EN Fault 3 enable 3 1 FLT2EN Fault 2 enable 2 1 FLT1EN Fault 1 enable 1 1 FLT0EN Fault 0 enable 0 1 ST1ACTL ST1ACTL SHRTIMER Slave_TIMERx additional control register 0x7C 0x20 read-write 0x00000000 DTFCFG_15_9 Falling edge dead-time value configure 25 7 DTRCFG_15_9 Rising edge dead-time value configure 9 7 CNTCKDIV_3 Counter clock division 3 1 SLAVE_TIMER2 SHRTIMER Slave TIMER2 registers( SHRTIMER 0x40017580 0x0 0x80 registers SHRTIMER_IRQ3 70 ST2CTL0 ST2CTL0 SHRTIMER Slave_TIMERx control register 0 0x00 0x20 read-write 0x00000000 UPSEL Update event selection 28 4 SHWEN Shadow registers enable 27 1 DACTRGS Trigger source to DAC 25 2 UPBMT Update by Master_TIMER update event 24 1 UPBST4 Update by Slave_TIMER4 update event 23 1 UPBST3 Update by Slave_TIMER3 update event 22 1 UPBST1 Update by Slave_TIMER1 update event 20 1 UPBST0 Update by Slave_TIMER0 update event 19 1 UPRST Update event generated by reset event 18 1 UPREP Update event generated by repetition event 17 1 DELCMP3M Compare 3 delayed mode 14 2 DELCMP1M Compare 1 delayed mode 12 2 SYNISTRT Synchronization input start counter 11 1 SYNIRST Synchronization input reset counter 10 1 BLNMEN Balanced mode enable 6 1 HALFM Half mode 5 1 CNTRSTM Counter reset mode 4 1 CTNM Continuous mode 3 1 CNTCKDIV Counter clock division 0 3 ST2INTF ST2INTF SHRTIMER Slave_TIMERx interrupt flag register 0x04 0x20 read-only 0x00000000 CH1F Channel 1 output flag 21 1 CH0F Channel 0 output flag 20 1 BLNIF Balanced IDLE flag 17 1 CBLNF Current balanced flag 16 1 DLYIIF Delayed IDLE mode entry interrupt flag 14 1 RSTIF Counter reset interrupt flag 13 1 CH1ONAIF Channel 1 output inactive interrupt flag 12 1 CH1OAIF Channel 1 output active interrupt flag 11 1 CH0ONAIF Channel 0 output inactive interrupt flag 10 1 CH0OAIF Channel 0 output active interrupt flag 9 1 CAP1IF Capture 1 interrupt flag 8 1 CAP0IF Capture 0 interrupt flag 7 1 UPIF Update interrupt flag 6 1 REPIF Repetition interrupt flag 4 1 CMP3IF Compare 3 interrupt flag 3 1 CMP2IF Compare 2 interrupt flag 2 1 CMP1IF Compare 1 interrupt flag 1 1 CMP0IF Compare 0 interrupt flag 0 1 ST2INTC ST2INTC SHRTIMER Slave_TIMERx interrupt flag clear register 0x08 0x20 write-only 0x00000000 DLYIIFC Clear delayed IDLE mode entry interrupt flag 14 1 RSTIFC Clear counter reset interrupt flag 13 1 CH1ONAIFC Clear channel 1 output inactive interrupt flag 12 1 CH1OAIFC Clear channel 1 output active interrupt flag 11 1 CH0ONAIFC Clear channel 0 output inactive interrupt flag 10 1 CH0OAIFC Clear channel 0 output active interrupt flag 9 1 CAP1IFC Clear capture 1 interrupt flag 8 1 CAP0IFC Clear capture 0 interrupt flag 7 1 UPIFC Clear update interrupt flag 6 1 REPIFC Clear repetition interrupt flag 4 1 CMP3IFC Clear compare 3 interrupt flag 3 1 CMP2IFC Clear compare 2 interrupt flag 2 1 CMP1IFC Clear compare 1 interrupt flag 1 1 CMP0IFC Clear compare 0 interrupt flag 0 1 ST2DMAINTEN ST2DMAINTEN SHRTIMER Slave_TIMERx DMA and interrupt enable register 0x0C 0x20 read-write 0x00000000 DLYIDEN Delayed IDLE mode entry DMA request enable 30 1 RSTDEN Counter reset DMA request enable 29 1 CH1ONADEN Channel 1 output inactive DMA request enable 28 1 CH1OADEN Channel 1 output active DMA request enable 27 1 CH0ONADEN Channel 0 output inactive DMA request enable 26 1 CH0ADEN Channel 0 output active DMA request enable 25 1 CAP1DEN Capture 1 DMA request enable 24 1 CAP0DEN Capture 0 DMA request enable 23 1 UPDEN Update DMA request enable 22 1 REPDEN Repetition DMA request enable 20 1 CMP3DEN Compare 3 DMA request enable 19 1 CMP2DEN Compare 2 DMA request enable 18 1 CMP1DEN Compare 1 DMA request enable 17 1 CMP0DEN Compare 0 DMA request enable 16 1 DLYIIE Delayed IDLE mode entry interrupt enable 14 1 RSTIE Counter reset interrupt enable 13 1 CH1ONAIE Channel 1 output inactive interrupt enable 12 1 CH1OAIE Channel 1 output active interrupt enable 11 1 CH0ONAIE Channel 0 output inactive interrupt enable 10 1 CH0OAIE Channel 0 output active interrupt enable 9 1 CAP1IE Capture 1 interrupt enable 8 1 CAP0IE Capture 0 interrupt enable 7 1 UPIE Update interrupt enable 6 1 REPIE Repetition interrupt enable 4 1 CMP3IE Compare 3 interrupt enable 3 1 CMP2IE Compare 2 interrupt enable 2 1 CMP1IE Compare 1 interrupt enable 1 1 CMP0IE Compare 0 interrupt enable 0 1 ST2CNT ST2CNT SHRTIMER Slave_TIMERx counter register 0x10 0x20 read-write 0x00000000 CNT The current counter value 0 16 ST2CAR ST2CAR SHRTIMER Slave_TIMER2 counter auto reload register 0x14 0x20 read-write 0x00000000 CARL Counter auto reload value 0 16 ST2CREP ST2CREP SHRTIMER Slave_TIMER2 counter repetition register 0x18 0x20 read-write 0x00000000 CREP Counter repetition value 0 8 ST2CMP0V ST2CMP0V SHRTIMER Slave_TIMER2 compare 0 value register 0x1C 0x20 read-write 0x00000000 CMP0VAL Compare 0 value 0 16 ST2CMP0CP ST2CMP0CP SHRTIMER Slave_TIMERx compare 0 composite register 0x20 0x20 read-write 0x00000000 CREP Counter repetition value 16 8 CMP0VAL Compare 0 value 0 16 ST2CMP1V ST2CMP1V SHRTIMER Slave_TIMERx compare 1 value register 0x24 0x20 read-write 0x00000000 CMP1VAL Compare 1 value 0 16 ST2CMP2V ST2CMP2V SHRTIMER Slave_TIMERx compare 2 value register 0x28 0x20 read-write 0x00000000 CMP2VAL Compare 2 value 0 16 ST2CMP3V ST2CMP3V SHRTIMER Slave_TIMERx compare 3 value register 0x2C 0x20 read-write 0x00000000 CMP3VAL Compare 3 value 0 16 ST2CAP0V ST2CAP0V SHRTIMER Slave_TIMERx capture 0 value register 0x30 0x20 read-write 0x00000000 CAP0VAL Capture 0 value 0 16 ST2CAP1V ST2CAP1V SHRTIMER Slave_TIMERx capture 1 value register 0x34 0x20 read-write 0x00000000 CAP1VAL Capture 1 value 0 16 ST2DTCTL ST2DTCTL SHRTIMER Slave_TIMERx dead-time control register 0x38 0x20 read-write 0x00000000 DTFSVPROT Dead-time falling edge protection for value and sign 31 1 DTFSPROT Dead-time falling edge protection for sign 30 1 DTFS The sign of falling edge dead-time value 25 1 DTFCFG Falling edge dead-time value 16 9 DTRSVPROT Dead-time rising edge protection for value and sign 15 1 DTRSPROT Dead-time rising edge protection for sign 14 1 DTGCKDIV Dead time generator clock division 10 4 DTRS The sign of falling edge dead-time value 9 1 DTRCFG Falling edge dead-time value 0 9 ST2CH0SET ST2CH0SET SHRTIMER Slave_TIMERx channel 0 set request register 0x3C 0x20 read-write 0x00000000 CH0SUP Update event generates channel 0 31 1 CH0SEXEV9 External event 9 generates channel 0 30 1 CH0SEXEV8 External event 8 generates channel 0 29 1 CH0SEXEV7 External event 7 generates channel 0 28 1 CH0SEXEV6 External event 6 generates channel 0 27 1 CH0SEXEV5 External event 5 generates channel 0 26 1 CH0SEXEV4 External event 4 generates channel 0 25 1 CH0SEXEV3 External event 3 generates channel 0 24 1 CH0SEXEV2 External event 2 generates channel 0 23 1 CH0SEXEV1 External event 1 generates channel 0 22 1 CH0SEXEV0 External event 0 generates channel 0 21 1 CH0SSTEV8 Slave_TIMERx interconnection event 8 generates channel 0 20 1 CH0SSTEV7 Slave_TIMER1 interconnection event 7 generates channel 0 19 1 CH0SSTEV6 Slave_TIMERx interconnection event 6 generates channel 0 18 1 CH0SSTEV5 Slave_TIMERx interconnection event 5 generates channel 0 17 1 CH0SSTEV4 Slave_TIMERx interconnection event 4 generates channel 0 16 1 CH0SSTEV3 Slave_TIMERx interconnection event 3 generates channel 0 15 1 CH0SSTEV2 Slave_TIMERx interconnection event 2 generates channel 0 14 1 CH0SSTEV1 Slave_TIMERx interconnection event 1 generates channel 0 13 1 CH0SSTEV0 Slave_TIMERx interconnection event 0 generates channel 0 12 1 CH0SMTCMP3 Master_TIMER compare 3 event generates channel 0 11 1 CH0SMTCMP2 Master_TIMER compare 2 event generates channel 0 10 1 CH0SMTCMP1 Master_TIMER compare 1 event generates channel 0 9 1 CH0SMTCMP0 Master_TIMER compare 0 event generates channel 0 8 1 CH0SMTPER Master_TIMER period event generates channel 0 7 1 CH0SCMP3 Slave_TIMERx compare 3 event generates channel 0 6 1 CH0SCMP2 Slave_TIMERx compare 2 event generates channel 0 5 1 CH0SCMP1 Slave_TIMERx compare 1 event generates channel 0 4 1 CH0SCMP0 Slave_TIMERx compare 0 event generates channel 0 3 1 CH0SPER Slave_TIMERx period event generates channel 0 2 1 CH0SRST Slave_TIMERx reset event generates channel 0 1 1 CH0SSEV Software event generates channel 0 0 1 ST2CH0RST ST2CH0RST SHRTIMER Slave_TIMERx channel 0 reset request register 0x40 0x20 read-write 0x00000000 CH0RSUP Update event generates channel 0 31 1 CH0RSEXEV9 External event 9 generates channel 0 30 1 CH0RSEXEV8 External event 8 generates channel 0 29 1 CH0RSEXEV7 External event 7 generates channel 0 28 1 CH0RSEXEV6 External event 6 generates channel 0 27 1 CH0RSEXEV5 External event 5 generates channel 0 26 1 CH0RSEXEV4 External event 4 generates channel 0 25 1 CH0RSEXEV3 External event 3 generates channel 0 24 1 CH0RSEXEV2 External event 2 generates channel 0 23 1 CH0RSEXEV1 External event 1 generates channel 0 22 1 CH0RSEXEV0 External event 0 generates channel 0 21 1 CH0RSSTEV8 Slave_TIMERx interconnection event 8 generates channel 0 20 1 CH0RSSTEV7 Slave_TIMERx interconnection event 7 generates channel 0 19 1 CH0RSSTEV6 Slave_TIMERx interconnection event 6 generates channel 0 18 1 CH0RSSTEV5 Slave_TIMERx interconnection event 5 generates channel 0 17 1 CH0RSSTEV4 Slave_TIMER1 interconnection event 4 generates channel 0 16 1 CH0RSSTEV3 Slave_TIMERx interconnection event 3 generates channel 0 15 1 CH0RSSTEV2 Slave_TIMERx interconnection event 2 generates channel 0 14 1 CH0RSSTEV1 Slave_TIMERx interconnection event 1 generates channel 0 13 1 CH0RSSTEV0 Slave_TIMER1 interconnection event 0 generates channel 0 12 1 CH0RSMTCMP3 Master_TIMER compare 3 event generates channel 0 11 1 CH0RSMTCMP2 Master_TIMER compare 2 event generates channel 0 10 1 CH0RSMTCMP1 Master_TIMER compare 1 event generates channel 0 9 1 CH0RSMTCMP0 Master_TIMER compare 0 event generates channel 0 8 1 CH0RSMTPER Master_TIMER period event generates channel 0 7 1 CH0RSCMP3 Slave_TIMERx compare 3 event generates channel 0 6 1 CH0RSCMP2 Slave_TIMER1 compare 2 event generates channel 0 5 1 CH0RSCMP1 Slave_TIMERx compare 1 event generates channel 0 4 1 CH0RSCMP0 Slave_TIMERx compare 0 event generates channel 0 3 1 CH0RSPER Slave_TIMERx period event generates channel 0 2 1 CH0RSRST Slave_TIMERx reset event generates channel 0 1 1 CH0RSSEV Software event generates channel 0 0 1 ST2CH1SET ST2CH1SET SHRTIMER Slave_TIMERx channel 1 set request register 0x44 0x20 read-write 0x00000000 CH1SUP Update event generates channel 1 31 1 CH1SEXEV9 External event 9 generates channel 1 30 1 CH1SEXEV8 External event 8 generates channel 1 29 1 CH1SEXEV7 External event 7 generates channel 1 28 1 CH1SEXEV6 External event 6 generates channel 1 27 1 CH1SEXEV5 External event 5 generates channel 1 26 1 CH1SEXEV4 External event 4 generates channel 1 25 1 CH1SEXEV3 External event 3 generates channel 1 24 1 CH1SEXEV2 External event 2 generates channel 1 23 1 CH1SEXEV1 External event 1 generates channel 1 22 1 CH1SEXEV0 External event 0 generates channel 1 21 1 CH1SSTEV8 Slave_TIMERx interconnection event 8 generates channel 1 20 1 CH1SSTEV7 Slave_TIMERx interconnection event 7 generates channel 1 19 1 CH1SSTEV6 Slave_TIMERx interconnection event 6 generates channel 1 18 1 CH1SSTEV5 Slave_TIMERx interconnection event 5 generates channel 1 17 1 CH1SSTEV4 Slave_TIMERx interconnection event 4 generates channel 1 16 1 CH1SSTEV3 Slave_TIMERx interconnection event 3 generates channel 1 15 1 CH1SSTEV2 Slave_TIMERx interconnection event 2 generates channel 1 14 1 CH1SSTEV1 Slave_TIMERx interconnection event 1 generates channel 1 13 1 CH1SSTEV0 Slave_TIMERx interconnection event 0 generates channel 1 12 1 CH1SMTCMP3 Master_TIMER compare 3 event generates channel 1 11 1 CH1SMTCMP2 Master_TIMER compare 2 event generates channel 1 10 1 CH1SMTCMP1 Master_TIMER compare 1 event generates channel 1 9 1 CH1SMTCMP0 Master_TIMER compare 0 event generates channel 1 8 1 CH1SMTPER Master_TIMER period event generates channel 1 7 1 CH1SCMP3 Slave_TIMERx compare 3 event generates channel 1 6 1 CH1SCMP2 Slave_TIMERx compare 2 event generates channel 1 5 1 CH1SCMP1 Slave_TIMERx compare 1 event generates channel 1 4 1 CH1SCMP0 Slave_TIMERx compare 0 event generates channel 1 3 1 CH1SPER Slave_TIMERx period event generates channel 1 2 1 CH1SRST Slave_TIMERx reset event generates channel 1 1 1 CH1SSEV Software event generates channel 1 0 1 ST2CH1RST ST2CH1RST SHRTIMER Slave_TIMERx channel 1 reset request register 0x48 0x20 read-write 0x00000000 CH1RSUP Update event generates channel 1 31 1 CH1RSEXEV9 External event 9 generates channel 1 30 1 CH1RSEXEV8 External event 8 generates channel 1 29 1 CH1RSEXEV7 External event 7 generates channel 1 28 1 CH1RSEXEV6 External event 6 generates channel 1 27 1 CH1RSEXEV5 External event 5 generates channel 1 26 1 CH1RSEXEV4 External event 4 generates channel 1 25 1 CH1RSEXEV3 External event 3 generates channel 1 24 1 CH1RSEXEV2 External event 2 generates channel 1 23 1 CH1RSEXEV1 External event 1 generates channel 1 22 1 CH1RSEXEV0 External event 0 generates channel 1 21 1 CH1RSSTEV8 Slave_TIMERx interconnection event 8 generates channel 1 20 1 CH1RSSTEV7 Slave_TIMERx interconnection event 7 generates channel 1 19 1 CH1RSSTEV6 Slave_TIMERx interconnection event 6 generates channel 1 18 1 CH1RSSTEV5 Slave_TIMERx interconnection event 5 generates channel 1 17 1 CH1RSSTEV4 Slave_TIMERx interconnection event 4 generates channel 1 16 1 CH1RSSTEV3 Slave_TIMERx interconnection event 3 generates channel 1 15 1 CH1RSSTEV2 Slave_TIMERx interconnection event 2 generates channel 1 14 1 CH1RSSTEV1 Slave_TIMERx interconnection event 1 generates channel 1 13 1 CH1RSSTEV0 Slave_TIMERx interconnection event 0 generates channel 1 12 1 CH1RSMTCMP3 Master_TIMER compare 3 event generates channel 1 11 1 CH1RSMTCMP2 Master_TIMER compare 2 event generates channel 1 10 1 CH1RSMTCMP1 Master_TIMER compare 1 event generates channel 1 9 1 CH1RSMTCMP0 Master_TIMER compare 0 event generates channel 1 8 1 CH1RSMTPER Master_TIMER period event generates channel 1 7 1 CH1RSCMP3 Slave_TIMERx compare 3 event generates channel 1 6 1 CH1RSCMP2 Slave_TIMERx compare 2 event generates channel 1 5 1 CH1RSCMP1 Slave_TIMERx compare 1 event generates channel 1 4 1 CH1RSCMP0 Slave_TIMERx compare 0 event generates channel 1 3 1 CH1RSPER Slave_TIMERx period event generates channel 1 2 1 CH1RSRST Slave_TIMERx reset event generates channel 1 1 1 CH1RSSEV Software event generates channel 1 0 1 ST2EXEVFCFG0 ST2EXEVFCFG0 SHRTIMER Slave_TIMERx external event filter configuration register 0 0x4C 0x20 read-write 0x00000000 EXEV4FM External event 4 filter mode 25 4 EXEV4MEEN External event 4 memorized enable 24 1 EXEV3FM External event 3 filter mode 19 4 EXEV3MEEN External event 3 memorized enable 18 1 EXEV2FM External event 2 filter mode 13 4 EXEV2MEEN External event 2 memorized enable 12 1 EXEV1FM External event 1 filter mode 7 4 EXEV1MEEN External event 1 memorized enable 6 1 EXEV0FM External event 0 filter mode 1 4 EXEV0MEEN External event 0 memorized enable 0 1 ST2EXEVFCFG1 ST2EXEVFCFG1 SHRTIMER Slave_TIMERx external event filter configuration register 1 0x50 0x20 read-write 0x00000000 EXEV9FM External event 9 filter mode 25 4 EXEV9MEEN External event 9 memorized enable 24 1 EXEV8FM External event 8 filter mode 19 4 EXEV8MEEN External event 8 memorized enable 18 1 EXEV7FM External event 7 filter mode 13 4 EXEV7MEEN External event 7 memorized enable 12 1 EXEV6FM External event 6 filter mode 7 4 EXEV6MEEN External event 6 memorized enable 6 1 EXEV5FM External event 5 filter mode 1 4 EXEV5MEEN External event 5 memorized enable 0 1 ST2CNTRST ST2CNTRST SHRTIMER Slave_TIMERx counter reset register 0x54 0x20 read-write 0x00000000 ST4CMP3RST Slave_TIMER4 compare 3 event resets counter 30 1 ST4CMP1RST Slave_TIMER4 compare 1 event resets counter 29 1 ST4CMP0RST Slave_TIMER4 compare 0 event resets counter 28 1 ST3CMP3RST Slave_TIMER3 compare 3 event resets counter 27 1 ST3CMP1RST Slave_TIMER3 compare 1 event resets counter 26 1 ST3CMP0RST Slave_TIMER3 compare 0 event resets counter 25 1 ST1CMP3RST Slave_TIMER1 compare 3 event resets counter 24 1 ST1CMP1RST Slave_TIMER1 compare 1 event resets counter 23 1 ST1CMP0RST Slave_TIMER1 compare 0 event resets counter 22 1 ST0CMP3RST Slave_TIMER0 compare 3 event resets counter 21 1 ST0CMP1RST Slave_TIMER0 compare 1 event resets counter 20 1 ST0CMP0RST Slave_TIMER0 compare 0 event resets counter 19 1 EXEV9RST External event 9 resets counter 18 1 EXEV8RST External event 8 resets counter 17 1 EXEV7RST External event 7 resets counter 16 1 EXEV6RST External event 6 resets counter 15 1 EXEV5RST External event 5 resets counter 14 1 EXEV4RST External event 4 resets counter 13 1 EXEV3RST External event 3 resets counter 12 1 EXEV2RST External event 2 resets counter 11 1 EXEV1RST External event 1 resets counter 10 1 EXEV0RST External event 0 resets counter 9 1 MTCMP3RST Master_TIMER compare 3 event resets counter 8 1 MTCMP2RST Master_TIMER compare 2 event resets counter 7 1 MTCMP1RST Master_TIMER compare 1 event resets counter 6 1 MTCMP0RST Master_TIMER compare 0 event resets counter 5 1 MTPERRST Master_TIMER period event resets counter 4 1 CMP3RST Slave_TIMER2 compare 3 event resets counter 3 1 CMP1RST Slave_TIMER2 compare 1 event resets counter 2 1 UPRST Slave_TIMER2 update event resets counter 1 1 ST2CSCTL ST2CSCTL SHRTIMER Slave_TIMERx carrier-signal control register 0x58 0x20 read-write 0x00000000 CSFSTPW First carrier-signal pulse width 7 4 CSDTY Carrier signal duty cycle 4 3 CSPRD Carrier signal period 0 4 ST2CAP0TRG ST2CAP0TRG SHRTIMER Slave_TIMERx capture 0 trigger register 0x5C 0x20 read-write 0x00000000 CP0BST4CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER4 31 1 CP0BST4CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER4 30 1 CP0BST4NA Capture 0 triggered by ST4CH0_O output active to inactive transition 29 1 CP0BST4A Capture 0 triggered by ST4CH0_O output inactive to active transition 28 1 CP0BST3CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER3 27 1 CP0BST3CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER3 26 1 CP0BST3NA Capture 0 triggered by ST3CH0_O output active to inactive transition 25 1 CP0BST3A Capture 0 triggered by ST3CH0_O output inactive to active transition 24 1 CP0BST1CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER1 19 1 CP0BST1CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER1 18 1 CP0BST1NA Capture 0 triggered by ST2CH1_O output active to inactive transition 17 1 CP0BST1A Capture 0 triggered by ST2CH1_O output inactive to active transition 16 1 CP0BST0CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER0 15 1 CP0BST0CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER0 14 1 CP0BST0NA Capture 0 triggered by ST0CH0_O output active to inactive transition 13 1 CP0BST0A Capture 0 triggered by ST0CH0_O output inactive to active transition 12 1 CP0BEXEV9 Capture 0 triggered by external event 9 11 1 CP0BEXEV8 Capture 0 triggered by external event 8 10 1 CP0BEXEV7 Capture 0 triggered by external event 7 9 1 CP0BEXEV6 Capture 0 triggered by external event 6 8 1 CP0BEXEV5 Capture 0 triggered by external event 5 7 1 CP0BEXEV4 Capture 0 triggered by external event 4 6 1 CP0BEXEV3 Capture 0 triggered by external event 3 5 1 CP0BEXEV2 Capture 0 triggered by external event 2 4 1 CP0BEXEV1 Capture 0 triggered by external event 1 3 1 CP0BEXEV0 Capture 0 triggered by external event 0 2 1 CP0BUP Capture 0 triggered by update event 1 1 CP0BSW Capture 0 triggered by software 0 1 ST2CAP1TRG ST2CAP1TRG SHRTIMER Slave_TIMERx capture 1 trigger register 0x60 0x20 read-write 0x00000000 CP1BST4CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER4 31 1 CP1BST4CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER4 30 1 CP1BST4NA Capture 1 triggered by ST4CH0_O output active to inactive transition 29 1 CP1BST4A Capture 1 triggered by ST4CH0_O output inactive to active transition 28 1 CP1BST3CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER3 27 1 CP1BST3CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER3 26 1 CP1BST3NA Capture 1 triggered by ST3CH0_O output active to inactive transition 25 1 CP1BST3A Capture 1 triggered by ST3CH0_O output inactive to active transition 24 1 CP1BST1CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER1 19 1 CP1BST1CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER1 18 1 CP1BST1NA Capture 1 triggered by ST2CH1_O output active to inactive transition 17 1 CP1BST1A Capture 1 triggered by ST2CH1_O output inactive to active transition 16 1 CP1BST0CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER0 15 1 CP1BST0CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER0 14 1 CP1BST0NA Capture 1 triggered by ST0CH0_O output active to inactive transition 13 1 CP1BST0A Capture 1 triggered by ST0CH0_O output inactive to active transition 12 1 CP1BEXEV9 Capture 1 triggered by external event 9 11 1 CP1BEXEV8 Capture 1 triggered by external event 8 10 1 CP1BEXEV7 Capture 1 triggered by external event 7 9 1 CP1BEXEV6 Capture 1 triggered by external event 6 8 1 CP1BEXEV5 Capture 1 triggered by external event 5 7 1 CP1BEXEV4 Capture 1 triggered by external event 4 6 1 CP1BEXEV3 Capture 1 triggered by external event 3 5 1 CP1BEXEV2 Capture 1 triggered by external event 2 4 1 CP1BEXEV1 Capture 1 triggered by external event 1 3 1 CP1BEXEV0 Capture 1 triggered by external event 0 2 1 CP1BUP Capture 1 triggered by update event 1 1 CP1BSW Capture 1 triggered by software 0 1 ST2CHOCTL ST2CHOCTL SHRTIMER Slave_TIMERx channel output control register 0x64 0x20 read-write 0x00000000 BMCH1DTI Channel 1 dead-time insert in bunch mode 23 1 CH1CSEN Channel 1 carrier-signal mode enable 22 1 CH1FLTOS Channel 1 Fault output state 20 2 ISO1 channel 1 output idle state 19 1 BMCH1IEN Channel 1 IDLE state enable in bunch mode 18 1 CH1P Channel 1 output polarity 17 1 DLYISCH Delayed IDLE source and channel 10 3 DLYISMEN Delayed IDLE state mode enable 9 1 DTEN Dead time enable 8 1 BMCH0DTI Channel 0 dead-time insert in bunch mode 7 1 CH0CSEN Channel 0 carrier-signal mode enable 6 1 CH0FLTOS Channel 0 Fault output state 4 2 ISO0 Channel 0 output idle state 3 1 BMCH0IEN Channel 0 IDLE state enable in bunch mode 2 1 CH0P Channel 0 output polarity 1 1 ST2FLTCTL ST2FLTCTL SHRTIMER Slave_TIMERx fault control register 0x68 0x20 read-write 0x00000000 FLTENPROT Protect fault enable 31 1 FLT4EN Fault 4 enable 4 1 FLT3EN Fault 3 enable 3 1 FLT2EN Fault 2 enable 2 1 FLT1EN Fault 1 enable 1 1 FLT0EN Fault 0 enable 0 1 ST2ACTL ST2ACTL SHRTIMER Slave_TIMERx additional control register 0x7C 0x20 read-write 0x00000000 DTFCFG_15_9 Falling edge dead-time value configure 25 7 DTRCFG_15_9 Rising edge dead-time value configure 9 7 CNTCKDIV_3 Counter clock division 3 1 SLAVE_TIMER3 SHRTIMER Slave TIMER3 registers( SHRTIMER 0x40017600 0x0 0x80 registers SHRTIMER_IRQ4 71 ST3CTL0 ST3CTL0 SHRTIMER Slave_TIMERx control register 0 0x00 0x20 read-write 0x00000000 UPSEL Update event selection 28 4 SHWEN Shadow registers enable 27 1 DACTRGS Trigger source to DAC 25 2 UPBMT Update by Master_TIMER update event 24 1 UPBST4 Update by Slave_TIMER4 update event 23 1 UPBST2 Update by Slave_TIMER2 update event 21 1 UPBST1 Update by Slave_TIMER1 update event 20 1 UPBST0 Update by Slave_TIMER0 update event 19 1 UPRST Update event generated by reset event 18 1 UPREP Update event generated by repetition event 17 1 DELCMP3M Compare 3 delayed mode 14 2 DELCMP1M Compare 1 delayed mode 12 2 SYNISTRT Synchronization input start counter 11 1 SYNIRST Synchronization input reset counter 10 1 BLNMEN Balanced mode enable 6 1 HALFM Half mode 5 1 CNTRSTM Counter reset mode 4 1 CTNM Continuous mode 3 1 CNTCKDIV Counter clock division 0 3 ST3INTF ST3INTF SHRTIMER Slave_TIMERx interrupt flag register 0x04 0x20 read-only 0x00000000 CH1F Channel 1 output flag 21 1 CH0F Channel 0 output flag 20 1 BLNIF Balanced IDLE flag 17 1 CBLNF Current balanced flag 16 1 DLYIIF Delayed IDLE mode entry interrupt flag 14 1 RSTIF Counter reset interrupt flag 13 1 CH1ONAIF Channel 1 output inactive interrupt flag 12 1 CH1OAIF Channel 1 output active interrupt flag 11 1 CH0ONAIF Channel 0 output inactive interrupt flag 10 1 CH0OAIF Channel 0 output active interrupt flag 9 1 CAP1IF Capture 1 interrupt flag 8 1 CAP0IF Capture 0 interrupt flag 7 1 UPIF Update interrupt flag 6 1 REPIF Repetition interrupt flag 4 1 CMP3IF Compare 3 interrupt flag 3 1 CMP2IF Compare 2 interrupt flag 2 1 CMP1IF Compare 1 interrupt flag 1 1 CMP0IF Compare 0 interrupt flag 0 1 ST3INTC ST3INTC SHRTIMER Slave_TIMERx interrupt flag clear register 0x08 0x20 write-only 0x00000000 DLYIIFC Clear delayed IDLE mode entry interrupt flag 14 1 RSTIFC Clear counter reset interrupt flag 13 1 CH1ONAIFC Clear channel 1 output inactive interrupt flag 12 1 CH1OAIFC Clear channel 1 output active interrupt flag 11 1 CH0ONAIFC Clear channel 0 output inactive interrupt flag 10 1 CH0OAIFC Clear channel 0 output active interrupt flag 9 1 CAP1IFC Clear capture 1 interrupt flag 8 1 CAP0IFC Clear capture 0 interrupt flag 7 1 UPIFC Clear update interrupt flag 6 1 REPIFC Clear repetition interrupt flag 4 1 CMP3IFC Clear compare 3 interrupt flag 3 1 CMP2IFC Clear compare 2 interrupt flag 2 1 CMP1IFC Clear compare 1 interrupt flag 1 1 CMP0IFC Clear compare 0 interrupt flag 0 1 ST3DMAINTEN ST3DMAINTEN SHRTIMER Slave_TIMERx DMA and interrupt enable register 0x0C 0x20 read-write 0x00000000 DLYIDEN Delayed IDLE mode entry DMA request enable 30 1 RSTDEN Counter reset DMA request enable 29 1 CH1ONADEN Channel 1 output inactive DMA request enable 28 1 CH1OADEN Channel 1 output active DMA request enable 27 1 CH0ONADEN Channel 0 output inactive DMA request enable 26 1 CH0ADEN Channel 0 output active DMA request enable 25 1 CAP1DEN Capture 1 DMA request enable 24 1 CAP0DEN Capture 0 DMA request enable 23 1 UPDEN Update DMA request enable 22 1 REPDEN Repetition DMA request enable 20 1 CMP3DEN Compare 3 DMA request enable 19 1 CMP2DEN Compare 2 DMA request enable 18 1 CMP1DEN Compare 1 DMA request enable 17 1 CMP0DEN Compare 0 DMA request enable 16 1 DLYIIE Delayed IDLE mode entry interrupt enable 14 1 RSTIE Counter reset interrupt enable 13 1 CH1ONAIE Channel 1 output inactive interrupt enable 12 1 CH1OAIE Channel 1 output active interrupt enable 11 1 CH0ONAIE Channel 0 output inactive interrupt enable 10 1 CH0OAIE Channel 0 output active interrupt enable 9 1 CAP1IE Capture 1 interrupt enable 8 1 CAP0IE Capture 0 interrupt enable 7 1 UPIE Update interrupt enable 6 1 REPIE Repetition interrupt enable 4 1 CMP3IE Compare 3 interrupt enable 3 1 CMP2IE Compare 2 interrupt enable 2 1 CMP1IE Compare 1 interrupt enable 1 1 CMP0IE Compare 0 interrupt enable 0 1 ST3CNT ST3CNT SHRTIMER Slave_TIMERx counter register 0x10 0x20 read-write 0x00000000 CNT The current counter value 0 16 ST3CAR ST3CAR SHRTIMER Slave_TIMER3 counter auto reload register 0x14 0x20 read-write 0x00000000 CARL Counter auto reload value 0 16 ST3CREP ST3CREP SHRTIMER Slave_TIMER3 counter repetition register 0x18 0x20 read-write 0x00000000 CREP Counter repetition value 0 8 ST3CMP0V ST3CMP0V SHRTIMER Slave_TIMER3 compare 0 value register 0x1C 0x20 read-write 0x00000000 CMP0VAL Compare 0 value 0 16 ST3CMP0CP ST3CMP0CP SHRTIMER Slave_TIMERx compare 0 composite register 0x20 0x20 read-write 0x00000000 CREP Counter repetition value 16 8 CMP0VAL Compare 0 value 0 16 ST3CMP1V ST3CMP1V SHRTIMER Slave_TIMERx compare 1 value register 0x24 0x20 read-write 0x00000000 CMP1VAL Compare 1 value 0 16 ST3CMP2V ST3CMP2V SHRTIMER Slave_TIMERx compare 2 value register 0x28 0x20 read-write 0x00000000 CMP2VAL Compare 2 value 0 16 ST3CMP3V ST3CMP3V SHRTIMER Slave_TIMERx compare 3 value register 0x2C 0x20 read-write 0x00000000 CMP3VAL Compare 3 value 0 16 ST3CAP0V ST3CAP0V SHRTIMER Slave_TIMERx capture 0 value register 0x30 0x20 read-write 0x00000000 CAP0VAL Capture 0 value 0 16 ST3CAP1V ST3CAP1V SHRTIMER Slave_TIMERx capture 1 value register 0x34 0x20 read-write 0x00000000 CAP1VAL Capture 1 value 0 16 ST3DTCTL ST3DTCTL SHRTIMER Slave_TIMERx dead-time control register 0x38 0x20 read-write 0x00000000 DTFSVPROT Dead-time falling edge protection for value and sign 31 1 DTFSPROT Dead-time falling edge protection for sign 30 1 DTFS The sign of falling edge dead-time value 25 1 DTFCFG Falling edge dead-time value 16 9 DTRSVPROT Dead-time rising edge protection for value and sign 15 1 DTRSPROT Dead-time rising edge protection for sign 14 1 DTGCKDIV Dead time generator clock division 10 4 DTRS The sign of falling edge dead-time value 9 1 DTRCFG Falling edge dead-time value 0 9 ST3CH0SET ST3CH0SET SHRTIMER Slave_TIMERx channel 0 set request register 0x3C 0x20 read-write 0x00000000 CH0SUP Update event generates channel 0 31 1 CH0SEXEV9 External event 9 generates channel 0 30 1 CH0SEXEV8 External event 8 generates channel 0 29 1 CH0SEXEV7 External event 7 generates channel 0 28 1 CH0SEXEV6 External event 6 generates channel 0 27 1 CH0SEXEV5 External event 5 generates channel 0 26 1 CH0SEXEV4 External event 4 generates channel 0 25 1 CH0SEXEV3 External event 3 generates channel 0 24 1 CH0SEXEV2 External event 2 generates channel 0 23 1 CH0SEXEV1 External event 1 generates channel 0 22 1 CH0SEXEV0 External event 0 generates channel 0 21 1 CH0SSTEV8 Slave_TIMERx interconnection event 8 generates channel 0 20 1 CH0SSTEV7 Slave_TIMER1 interconnection event 7 generates channel 0 19 1 CH0SSTEV6 Slave_TIMERx interconnection event 6 generates channel 0 18 1 CH0SSTEV5 Slave_TIMERx interconnection event 5 generates channel 0 17 1 CH0SSTEV4 Slave_TIMERx interconnection event 4 generates channel 0 16 1 CH0SSTEV3 Slave_TIMERx interconnection event 3 generates channel 0 15 1 CH0SSTEV2 Slave_TIMERx interconnection event 2 generates channel 0 14 1 CH0SSTEV1 Slave_TIMERx interconnection event 1 generates channel 0 13 1 CH0SSTEV0 Slave_TIMERx interconnection event 0 generates channel 0 12 1 CH0SMTCMP3 Master_TIMER compare 3 event generates channel 0 11 1 CH0SMTCMP2 Master_TIMER compare 2 event generates channel 0 10 1 CH0SMTCMP1 Master_TIMER compare 1 event generates channel 0 9 1 CH0SMTCMP0 Master_TIMER compare 0 event generates channel 0 8 1 CH0SMTPER Master_TIMER period event generates channel 0 7 1 CH0SCMP3 Slave_TIMERx compare 3 event generates channel 0 6 1 CH0SCMP2 Slave_TIMERx compare 2 event generates channel 0 5 1 CH0SCMP1 Slave_TIMERx compare 1 event generates channel 0 4 1 CH0SCMP0 Slave_TIMERx compare 0 event generates channel 0 3 1 CH0SPER Slave_TIMERx period event generates channel 0 2 1 CH0SRST Slave_TIMERx reset event generates channel 0 1 1 CH0SSEV Software event generates channel 0 0 1 ST3CH0RST ST3CH0RST SHRTIMER Slave_TIMERx channel 0 reset request register 0x40 0x20 read-write 0x00000000 CH0RSUP Update event generates channel 0 31 1 CH0RSEXEV9 External event 9 generates channel 0 30 1 CH0RSEXEV8 External event 8 generates channel 0 29 1 CH0RSEXEV7 External event 7 generates channel 0 28 1 CH0RSEXEV6 External event 6 generates channel 0 27 1 CH0RSEXEV5 External event 5 generates channel 0 26 1 CH0RSEXEV4 External event 4 generates channel 0 25 1 CH0RSEXEV3 External event 3 generates channel 0 24 1 CH0RSEXEV2 External event 2 generates channel 0 23 1 CH0RSEXEV1 External event 1 generates channel 0 22 1 CH0RSEXEV0 External event 0 generates channel 0 21 1 CH0RSSTEV8 Slave_TIMERx interconnection event 8 generates channel 0 20 1 CH0RSSTEV7 Slave_TIMERx interconnection event 7 generates channel 0 19 1 CH0RSSTEV6 Slave_TIMERx interconnection event 6 generates channel 0 18 1 CH0RSSTEV5 Slave_TIMERx interconnection event 5 generates channel 0 17 1 CH0RSSTEV4 Slave_TIMER1 interconnection event 4 generates channel 0 16 1 CH0RSSTEV3 Slave_TIMERx interconnection event 3 generates channel 0 15 1 CH0RSSTEV2 Slave_TIMERx interconnection event 2 generates channel 0 14 1 CH0RSSTEV1 Slave_TIMERx interconnection event 1 generates channel 0 13 1 CH0RSSTEV0 Slave_TIMER1 interconnection event 0 generates channel 0 12 1 CH0RSMTCMP3 Master_TIMER compare 3 event generates channel 0 11 1 CH0RSMTCMP2 Master_TIMER compare 2 event generates channel 0 10 1 CH0RSMTCMP1 Master_TIMER compare 1 event generates channel 0 9 1 CH0RSMTCMP0 Master_TIMER compare 0 event generates channel 0 8 1 CH0RSMTPER Master_TIMER period event generates channel 0 7 1 CH0RSCMP3 Slave_TIMERx compare 3 event generates channel 0 6 1 CH0RSCMP2 Slave_TIMER1 compare 2 event generates channel 0 5 1 CH0RSCMP1 Slave_TIMERx compare 1 event generates channel 0 4 1 CH0RSCMP0 Slave_TIMERx compare 0 event generates channel 0 3 1 CH0RSPER Slave_TIMERx period event generates channel 0 2 1 CH0RSRST Slave_TIMERx reset event generates channel 0 1 1 CH0RSSEV Software event generates channel 0 0 1 ST3CH1SET ST3CH1SET SHRTIMER Slave_TIMERx channel 1 set request register 0x44 0x20 read-write 0x00000000 CH1SUP Update event generates channel 1 31 1 CH1SEXEV9 External event 9 generates channel 1 30 1 CH1SEXEV8 External event 8 generates channel 1 29 1 CH1SEXEV7 External event 7 generates channel 1 28 1 CH1SEXEV6 External event 6 generates channel 1 27 1 CH1SEXEV5 External event 5 generates channel 1 26 1 CH1SEXEV4 External event 4 generates channel 1 25 1 CH1SEXEV3 External event 3 generates channel 1 24 1 CH1SEXEV2 External event 2 generates channel 1 23 1 CH1SEXEV1 External event 1 generates channel 1 22 1 CH1SEXEV0 External event 0 generates channel 1 21 1 CH1SSTEV8 Slave_TIMERx interconnection event 8 generates channel 1 20 1 CH1SSTEV7 Slave_TIMERx interconnection event 7 generates channel 1 19 1 CH1SSTEV6 Slave_TIMERx interconnection event 6 generates channel 1 18 1 CH1SSTEV5 Slave_TIMERx interconnection event 5 generates channel 1 17 1 CH1SSTEV4 Slave_TIMERx interconnection event 4 generates channel 1 16 1 CH1SSTEV3 Slave_TIMERx interconnection event 3 generates channel 1 15 1 CH1SSTEV2 Slave_TIMERx interconnection event 2 generates channel 1 14 1 CH1SSTEV1 Slave_TIMERx interconnection event 1 generates channel 1 13 1 CH1SSTEV0 Slave_TIMERx interconnection event 0 generates channel 1 12 1 CH1SMTCMP3 Master_TIMER compare 3 event generates channel 1 11 1 CH1SMTCMP2 Master_TIMER compare 2 event generates channel 1 10 1 CH1SMTCMP1 Master_TIMER compare 1 event generates channel 1 9 1 CH1SMTCMP0 Master_TIMER compare 0 event generates channel 1 8 1 CH1SMTPER Master_TIMER period event generates channel 1 7 1 CH1SCMP3 Slave_TIMERx compare 3 event generates channel 1 6 1 CH1SCMP2 Slave_TIMERx compare 2 event generates channel 1 5 1 CH1SCMP1 Slave_TIMERx compare 1 event generates channel 1 4 1 CH1SCMP0 Slave_TIMERx compare 0 event generates channel 1 3 1 CH1SPER Slave_TIMERx period event generates channel 1 2 1 CH1SRST Slave_TIMERx reset event generates channel 1 1 1 CH1SSEV Software event generates channel 1 0 1 ST3CH1RST ST3CH1RST SHRTIMER Slave_TIMERx channel 1 reset request register 0x48 0x20 read-write 0x00000000 CH1RSUP Update event generates channel 1 31 1 CH1RSEXEV9 External event 9 generates channel 1 30 1 CH1RSEXEV8 External event 8 generates channel 1 29 1 CH1RSEXEV7 External event 7 generates channel 1 28 1 CH1RSEXEV6 External event 6 generates channel 1 27 1 CH1RSEXEV5 External event 5 generates channel 1 26 1 CH1RSEXEV4 External event 4 generates channel 1 25 1 CH1RSEXEV3 External event 3 generates channel 1 24 1 CH1RSEXEV2 External event 2 generates channel 1 23 1 CH1RSEXEV1 External event 1 generates channel 1 22 1 CH1RSEXEV0 External event 0 generates channel 1 21 1 CH1RSSTEV8 Slave_TIMERx interconnection event 8 generates channel 1 20 1 CH1RSSTEV7 Slave_TIMERx interconnection event 7 generates channel 1 19 1 CH1RSSTEV6 Slave_TIMERx interconnection event 6 generates channel 1 18 1 CH1RSSTEV5 Slave_TIMERx interconnection event 5 generates channel 1 17 1 CH1RSSTEV4 Slave_TIMERx interconnection event 4 generates channel 1 16 1 CH1RSSTEV3 Slave_TIMERx interconnection event 3 generates channel 1 15 1 CH1RSSTEV2 Slave_TIMERx interconnection event 2 generates channel 1 14 1 CH1RSSTEV1 Slave_TIMERx interconnection event 1 generates channel 1 13 1 CH1RSSTEV0 Slave_TIMERx interconnection event 0 generates channel 1 12 1 CH1RSMTCMP3 Master_TIMER compare 3 event generates channel 1 11 1 CH1RSMTCMP2 Master_TIMER compare 2 event generates channel 1 10 1 CH1RSMTCMP1 Master_TIMER compare 1 event generates channel 1 9 1 CH1RSMTCMP0 Master_TIMER compare 0 event generates channel 1 8 1 CH1RSMTPER Master_TIMER period event generates channel 1 7 1 CH1RSCMP3 Slave_TIMERx compare 3 event generates channel 1 6 1 CH1RSCMP2 Slave_TIMERx compare 2 event generates channel 1 5 1 CH1RSCMP1 Slave_TIMERx compare 1 event generates channel 1 4 1 CH1RSCMP0 Slave_TIMERx compare 0 event generates channel 1 3 1 CH1RSPER Slave_TIMERx period event generates channel 1 2 1 CH1RSRST Slave_TIMERx reset event generates channel 1 1 1 CH1RSSEV Software event generates channel 1 0 1 ST3EXEVFCFG0 ST3EXEVFCFG0 SHRTIMER Slave_TIMERx external event filter configuration register 0 0x4C 0x20 read-write 0x00000000 EXEV4FM External event 4 filter mode 25 4 EXEV4MEEN External event 4 memorized enable 24 1 EXEV3FM External event 3 filter mode 19 4 EXEV3MEEN External event 3 memorized enable 18 1 EXEV2FM External event 2 filter mode 13 4 EXEV2MEEN External event 2 memorized enable 12 1 EXEV1FM External event 1 filter mode 7 4 EXEV1MEEN External event 1 memorized enable 6 1 EXEV0FM External event 0 filter mode 1 4 EXEV0MEEN External event 0 memorized enable 0 1 ST3EXEVFCFG1 ST3EXEVFCFG1 SHRTIMER Slave_TIMERx external event filter configuration register 1 0x50 0x20 read-write 0x00000000 EXEV9FM External event 9 filter mode 25 4 EXEV9MEEN External event 9 memorized enable 24 1 EXEV8FM External event 8 filter mode 19 4 EXEV8MEEN External event 8 memorized enable 18 1 EXEV7FM External event 7 filter mode 13 4 EXEV7MEEN External event 7 memorized enable 12 1 EXEV6FM External event 6 filter mode 7 4 EXEV6MEEN External event 6 memorized enable 6 1 EXEV5FM External event 5 filter mode 1 4 EXEV5MEEN External event 5 memorized enable 0 1 ST3CNTRST ST3CNTRST SHRTIMER Slave_TIMERx counter reset register 0x54 0x20 read-write 0x00000000 ST4CMP3RST Slave_TIMER4 compare 3 event resets counter 30 1 ST4CMP1RST Slave_TIMER4 compare 1 event resets counter 29 1 ST4CMP0RST Slave_TIMER4 compare 0 event resets counter 28 1 ST2CMP3RST Slave_TIMER2 compare 3 event resets counter 27 1 ST2CMP1RST Slave_TIMER2 compare 1 event resets counter 26 1 ST2CMP0RST Slave_TIMER2 compare 0 event resets counter 25 1 ST1CMP3RST Slave_TIMER1 compare 3 event resets counter 24 1 ST1CMP1RST Slave_TIMER1 compare 1 event resets counter 23 1 ST1CMP0RST Slave_TIMER1 compare 0 event resets counter 22 1 ST0CMP3RST Slave_TIMER0 compare 3 event resets counter 21 1 ST0CMP1RST Slave_TIMER0 compare 1 event resets counter 20 1 ST0CMP0RST Slave_TIMER0 compare 0 event resets counter 19 1 EXEV9RST External event 9 resets counter 18 1 EXEV8RST External event 8 resets counter 17 1 EXEV7RST External event 7 resets counter 16 1 EXEV6RST External event 6 resets counter 15 1 EXEV5RST External event 5 resets counter 14 1 EXEV4RST External event 4 resets counter 13 1 EXEV3RST External event 3 resets counter 12 1 EXEV2RST External event 2 resets counter 11 1 EXEV1RST External event 1 resets counter 10 1 EXEV0RST External event 0 resets counter 9 1 MTCMP3RST Master_TIMER compare 3 event resets counter 8 1 MTCMP2RST Master_TIMER compare 2 event resets counter 7 1 MTCMP1RST Master_TIMER compare 1 event resets counter 6 1 MTCMP0RST Master_TIMER compare 0 event resets counter 5 1 MTPERRST Master_TIMER period event resets counter 4 1 CMP3RST Slave_TIMERx compare 3 event resets counter 3 1 CMP1RST Slave_TIMERx compare 1 event resets counter 2 1 UPRST Slave_TIMERx update event resets counter 1 1 ST3CSCTL ST3CSCTL SHRTIMER Slave_TIMERx carrier-signal control register 0x58 0x20 read-write 0x00000000 CSFSTPW First carrier-signal pulse width 7 4 CSDTY Carrier signal duty cycle 4 3 CSPRD Carrier signal period 0 4 ST3CAP0TRG ST3CAP0TRG SHRTIMER Slave_TIMERx capture 0 trigger register 0x5C 0x20 read-write 0x00000000 CP0BST4CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER4 31 1 CP0BST4CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER4 30 1 CP0BST4NA Capture 0 triggered by ST4CH0_O output active to inactive transition 29 1 CP0BST4A Capture 0 triggered by ST4CH0_O output inactive to active transition 28 1 CP0BST2CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER2 23 1 CP0BST2CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER2 22 1 CP0BST2NA Capture 0 triggered by ST2CH0_O output active to inactive transition 21 1 CP0BST2A Capture 0 triggered by ST2CH0_O output inactive to active transition 20 1 CP0BST1CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER1 19 1 CP0BST1CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER1 18 1 CP0BST1NA Capture 0 triggered by ST2CH1_O output active to inactive transition 17 1 CP0BST1A Capture 0 triggered by ST2CH1_O output inactive to active transition 16 1 CP0BST0CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER0 15 1 CP0BST0CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER0 14 1 CP0BST0NA Capture 0 triggered by ST0CH0_O output active to inactive transition 13 1 CP0BST0A Capture 0 triggered by ST0CH0_O output inactive to active transition 12 1 CP0BEXEV9 Capture 0 triggered by external event 9 11 1 CP0BEXEV8 Capture 0 triggered by external event 8 10 1 CP0BEXEV7 Capture 0 triggered by external event 7 9 1 CP0BEXEV6 Capture 0 triggered by external event 6 8 1 CP0BEXEV5 Capture 0 triggered by external event 5 7 1 CP0BEXEV4 Capture 0 triggered by external event 4 6 1 CP0BEXEV3 Capture 0 triggered by external event 3 5 1 CP0BEXEV2 Capture 0 triggered by external event 2 4 1 CP0BEXEV1 Capture 0 triggered by external event 1 3 1 CP0BEXEV0 Capture 0 triggered by external event 0 2 1 CP0BUP Capture 0 triggered by update event 1 1 CP0BSW Capture 0 triggered by software 0 1 ST3CAP1TRG ST3CAP1TRG SHRTIMER Slave_TIMERx capture 1 trigger register 0x60 0x20 read-write 0x00000000 CP1BST4CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER4 31 1 CP1BST4CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER4 30 1 CP1BST4NA Capture 1 triggered by ST4CH0_O output active to inactive transition 29 1 CP1BST4A Capture 1 triggered by ST4CH0_O output inactive to active transition 28 1 CP1BST2CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER2 23 1 CP1BST2CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER2 22 1 CP1BST2NA Capture 1 triggered by ST2CH0_O output active to inactive transition 21 1 CP1BST2A Capture 1 triggered by ST2CH0_O output inactive to active transition 20 1 CP1BST1CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER1 19 1 CP1BST1CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER1 18 1 CP1BST1NA Capture 1 triggered by ST2CH1_O output active to inactive transition 17 1 CP1BST1A Capture 1 triggered by ST2CH1_O output inactive to active transition 16 1 CP1BST0CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER0 15 1 CP1BST0CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER0 14 1 CP1BST0NA Capture 1 triggered by ST0CH0_O output active to inactive transition 13 1 CP1BST0A Capture 1 triggered by ST0CH0_O output inactive to active transition 12 1 CP1BEXEV9 Capture 1 triggered by external event 9 11 1 CP1BEXEV8 Capture 1 triggered by external event 8 10 1 CP1BEXEV7 Capture 1 triggered by external event 7 9 1 CP1BEXEV6 Capture 1 triggered by external event 6 8 1 CP1BEXEV5 Capture 1 triggered by external event 5 7 1 CP1BEXEV4 Capture 1 triggered by external event 4 6 1 CP1BEXEV3 Capture 1 triggered by external event 3 5 1 CP1BEXEV2 Capture 1 triggered by external event 2 4 1 CP1BEXEV1 Capture 1 triggered by external event 1 3 1 CP1BEXEV0 Capture 1 triggered by external event 0 2 1 CP1BUP Capture 1 triggered by update event 1 1 CP1BSW Capture 1 triggered by software 0 1 ST3CHOCTL ST3CHOCTL SHRTIMER Slave_TIMERx channel output control register 0x64 0x20 read-write 0x00000000 BMCH1DTI Channel 1 dead-time insert in bunch mode 23 1 CH1CSEN Channel 1 carrier-signal mode enable 22 1 CH1FLTOS Channel 1 Fault output state 20 2 ISO1 channel 1 output idle state 19 1 BMCH1IEN Channel 1 IDLE state enable in bunch mode 18 1 CH1P Channel 1 output polarity 17 1 DLYISCH Delayed IDLE source and channel 10 3 DLYISMEN Delayed IDLE state mode enable 9 1 DTEN Dead time enable 8 1 BMCH0DTI Channel 0 dead-time insert in bunch mode 7 1 CH0CSEN Channel 0 carrier-signal mode enable 6 1 CH0FLTOS Channel 0 Fault output state 4 2 ISO0 Channel 0 output idle state 3 1 BMCH0IEN Channel 0 IDLE state enable in bunch mode 2 1 CH0P Channel 0 output polarity 1 1 ST3FLTCTL ST3FLTCTL SHRTIMER Slave_TIMERx fault control register 0x68 0x20 read-write 0x00000000 FLTENPROT Protect fault enable 31 1 FLT4EN Fault 4 enable 4 1 FLT3EN Fault 3 enable 3 1 FLT2EN Fault 2 enable 2 1 FLT1EN Fault 1 enable 1 1 FLT0EN Fault 0 enable 0 1 ST3ACTL ST3ACTL SHRTIMER Slave_TIMERx additional control register 0x7C 0x20 read-write 0x00000000 DTFCFG_15_9 Falling edge dead-time value configure 25 7 DTRCFG_15_9 Rising edge dead-time value configure 9 7 CNTCKDIV_3 Counter clock division 3 1 SLAVE_TIMER4 SHRTIMER Slave TIMER4 registers( SHRTIMER 0x40017680 0x0 0x80 registers SHRTIMER_IRQ5 72 ST3CTL0 ST3CTL0 SHRTIMER Slave_TIMERx control register 0 0x00 0x20 read-write 0x00000000 UPSEL Update event selection 28 4 SHWEN Shadow registers enable 27 1 DACTRGS Trigger source to DAC 25 2 UPBMT Update by Master_TIMER update event 24 1 UPBST3 Update by Slave_TIMER3 update event 22 1 UPBST2 Update by Slave_TIMER2 update event 21 1 UPBST1 Update by Slave_TIMER1 update event 20 1 UPBST0 Update by Slave_TIMER0 update event 19 1 UPRST Update event generated by reset event 18 1 UPREP Update event generated by repetition event 17 1 DELCMP3M Compare 3 delayed mode 14 2 DELCMP1M Compare 1 delayed mode 12 2 SYNISTRT Synchronization input start counter 11 1 SYNIRST Synchronization input reset counter 10 1 BLNMEN Balanced mode enable 6 1 HALFM Half mode 5 1 CNTRSTM Counter reset mode 4 1 CTNM Continuous mode 3 1 CNTCKDIV Counter clock division 0 3 ST4INTF ST4INTF SHRTIMER Slave_TIMERx interrupt flag register 0x04 0x20 read-only 0x00000000 CH1F Channel 1 output flag 21 1 CH0F Channel 0 output flag 20 1 BLNIF Balanced IDLE flag 17 1 CBLNF Current balanced flag 16 1 DLYIIF Delayed IDLE mode entry interrupt flag 14 1 RSTIF Counter reset interrupt flag 13 1 CH1ONAIF Channel 1 output inactive interrupt flag 12 1 CH1OAIF Channel 1 output active interrupt flag 11 1 CH0ONAIF Channel 0 output inactive interrupt flag 10 1 CH0OAIF Channel 0 output active interrupt flag 9 1 CAP1IF Capture 1 interrupt flag 8 1 CAP0IF Capture 0 interrupt flag 7 1 UPIF Update interrupt flag 6 1 REPIF Repetition interrupt flag 4 1 CMP3IF Compare 3 interrupt flag 3 1 CMP2IF Compare 2 interrupt flag 2 1 CMP1IF Compare 1 interrupt flag 1 1 CMP0IF Compare 0 interrupt flag 0 1 ST4INTC ST4INTC SHRTIMER Slave_TIMERx interrupt flag clear register 0x08 0x20 write-only 0x00000000 DLYIIFC Clear delayed IDLE mode entry interrupt flag 14 1 RSTIFC Clear counter reset interrupt flag 13 1 CH1ONAIFC Clear channel 1 output inactive interrupt flag 12 1 CH1OAIFC Clear channel 1 output active interrupt flag 11 1 CH0ONAIFC Clear channel 0 output inactive interrupt flag 10 1 CH0OAIFC Clear channel 0 output active interrupt flag 9 1 CAP1IFC Clear capture 1 interrupt flag 8 1 CAP0IFC Clear capture 0 interrupt flag 7 1 UPIFC Clear update interrupt flag 6 1 REPIFC Clear repetition interrupt flag 4 1 CMP3IFC Clear compare 3 interrupt flag 3 1 CMP2IFC Clear compare 2 interrupt flag 2 1 CMP1IFC Clear compare 1 interrupt flag 1 1 CMP0IFC Clear compare 0 interrupt flag 0 1 ST4DMAINTEN ST4DMAINTEN SHRTIMER Slave_TIMERx DMA and interrupt enable register 0x0C 0x20 read-write 0x00000000 DLYIDEN Delayed IDLE mode entry DMA request enable 30 1 RSTDEN Counter reset DMA request enable 29 1 CH1ONADEN Channel 1 output inactive DMA request enable 28 1 CH1OADEN Channel 1 output active DMA request enable 27 1 CH0ONADEN Channel 0 output inactive DMA request enable 26 1 CH0ADEN Channel 0 output active DMA request enable 25 1 CAP1DEN Capture 1 DMA request enable 24 1 CAP0DEN Capture 0 DMA request enable 23 1 UPDEN Update DMA request enable 22 1 REPDEN Repetition DMA request enable 20 1 CMP3DEN Compare 3 DMA request enable 19 1 CMP2DEN Compare 2 DMA request enable 18 1 CMP1DEN Compare 1 DMA request enable 17 1 CMP0DEN Compare 0 DMA request enable 16 1 DLYIIE Delayed IDLE mode entry interrupt enable 14 1 RSTIE Counter reset interrupt enable 13 1 CH1ONAIE Channel 1 output inactive interrupt enable 12 1 CH1OAIE Channel 1 output active interrupt enable 11 1 CH0ONAIE Channel 0 output inactive interrupt enable 10 1 CH0OAIE Channel 0 output active interrupt enable 9 1 CAP1IE Capture 1 interrupt enable 8 1 CAP0IE Capture 0 interrupt enable 7 1 UPIE Update interrupt enable 6 1 REPIE Repetition interrupt enable 4 1 CMP3IE Compare 3 interrupt enable 3 1 CMP2IE Compare 2 interrupt enable 2 1 CMP1IE Compare 1 interrupt enable 1 1 CMP0IE Compare 0 interrupt enable 0 1 ST4CNT ST4CNT SHRTIMER Slave_TIMERx counter register 0x10 0x20 read-write 0x00000000 CNT The current counter value 0 16 ST4CAR ST4CAR SHRTIMER Slave_TIMER4 counter auto reload register 0x14 0x20 read-write 0x00000000 CARL Counter auto reload value 0 16 ST4CREP ST4CREP SHRTIMER Slave_TIMER4 counter repetition register 0x18 0x20 read-write 0x00000000 CREP Counter repetition value 0 8 ST4CMP0V ST4CMP0V SHRTIMER Slave_TIMER4 compare 0 value register 0x1C 0x20 read-write 0x00000000 CMP0VAL Compare 0 value 0 16 ST4CMP0CP ST4CMP0CP SHRTIMER Slave_TIMERx compare 0 composite register 0x20 0x20 read-write 0x00000000 CREP Counter repetition value 16 8 CMP0VAL Compare 0 value 0 16 ST4CMP1V ST4CMP1V SHRTIMER Slave_TIMERx compare 1 value register 0x24 0x20 read-write 0x00000000 CMP1VAL Compare 1 value 0 16 ST4CMP2V ST4CMP2V SHRTIMER Slave_TIMERx compare 2 value register 0x28 0x20 read-write 0x00000000 CMP2VAL Compare 2 value 0 16 ST4CMP3V ST4CMP3V SHRTIMER Slave_TIMERx compare 3 value register 0x2C 0x20 read-write 0x00000000 CMP3VAL Compare 3 value 0 16 ST4CAP0V ST4CAP0V SHRTIMER Slave_TIMERx capture 0 value register 0x30 0x20 read-write 0x00000000 CAP0VAL Capture 0 value 0 16 ST4CAP1V ST4CAP1V SHRTIMER Slave_TIMERx capture 1 value register 0x34 0x20 read-write 0x00000000 CAP1VAL Capture 1 value 0 16 ST4DTCTL ST4DTCTL SHRTIMER Slave_TIMERx dead-time control register 0x38 0x20 read-write 0x00000000 DTFSVPROT Dead-time falling edge protection for value and sign 31 1 DTFSPROT Dead-time falling edge protection for sign 30 1 DTFS The sign of falling edge dead-time value 25 1 DTFCFG Falling edge dead-time value 16 9 DTRSVPROT Dead-time rising edge protection for value and sign 15 1 DTRSPROT Dead-time rising edge protection for sign 14 1 DTGCKDIV Dead time generator clock division 10 4 DTRS The sign of falling edge dead-time value 9 1 DTRCFG Falling edge dead-time value 0 9 ST4CH0SET ST4CH0SET SHRTIMER Slave_TIMERx channel 0 set request register 0x3C 0x20 read-write 0x00000000 CH0SUP Update event generates channel 0 31 1 CH0SEXEV9 External event 9 generates channel 0 30 1 CH0SEXEV8 External event 8 generates channel 0 29 1 CH0SEXEV7 External event 7 generates channel 0 28 1 CH0SEXEV6 External event 6 generates channel 0 27 1 CH0SEXEV5 External event 5 generates channel 0 26 1 CH0SEXEV4 External event 4 generates channel 0 25 1 CH0SEXEV3 External event 3 generates channel 0 24 1 CH0SEXEV2 External event 2 generates channel 0 23 1 CH0SEXEV1 External event 1 generates channel 0 22 1 CH0SEXEV0 External event 0 generates channel 0 21 1 CH0SSTEV8 Slave_TIMERx interconnection event 8 generates channel 0 20 1 CH0SSTEV7 Slave_TIMER1 interconnection event 7 generates channel 0 19 1 CH0SSTEV6 Slave_TIMERx interconnection event 6 generates channel 0 18 1 CH0SSTEV5 Slave_TIMERx interconnection event 5 generates channel 0 17 1 CH0SSTEV4 Slave_TIMERx interconnection event 4 generates channel 0 16 1 CH0SSTEV3 Slave_TIMERx interconnection event 3 generates channel 0 15 1 CH0SSTEV2 Slave_TIMERx interconnection event 2 generates channel 0 14 1 CH0SSTEV1 Slave_TIMERx interconnection event 1 generates channel 0 13 1 CH0SSTEV0 Slave_TIMERx interconnection event 0 generates channel 0 12 1 CH0SMTCMP3 Master_TIMER compare 3 event generates channel 0 11 1 CH0SMTCMP2 Master_TIMER compare 2 event generates channel 0 10 1 CH0SMTCMP1 Master_TIMER compare 1 event generates channel 0 9 1 CH0SMTCMP0 Master_TIMER compare 0 event generates channel 0 8 1 CH0SMTPER Master_TIMER period event generates channel 0 7 1 CH0SCMP3 Slave_TIMERx compare 3 event generates channel 0 6 1 CH0SCMP2 Slave_TIMERx compare 2 event generates channel 0 5 1 CH0SCMP1 Slave_TIMERx compare 1 event generates channel 0 4 1 CH0SCMP0 Slave_TIMERx compare 0 event generates channel 0 3 1 CH0SPER Slave_TIMERx period event generates channel 0 2 1 CH0SRST Slave_TIMERx reset event generates channel 0 1 1 CH0SSEV Software event generates channel 0 0 1 ST4CH0RST ST4CH0RST SHRTIMER Slave_TIMERx channel 0 reset request register 0x40 0x20 read-write 0x00000000 CH0RSUP Update event generates channel 0 31 1 CH0RSEXEV9 External event 9 generates channel 0 30 1 CH0RSEXEV8 External event 8 generates channel 0 29 1 CH0RSEXEV7 External event 7 generates channel 0 28 1 CH0RSEXEV6 External event 6 generates channel 0 27 1 CH0RSEXEV5 External event 5 generates channel 0 26 1 CH0RSEXEV4 External event 4 generates channel 0 25 1 CH0RSEXEV3 External event 3 generates channel 0 24 1 CH0RSEXEV2 External event 2 generates channel 0 23 1 CH0RSEXEV1 External event 1 generates channel 0 22 1 CH0RSEXEV0 External event 0 generates channel 0 21 1 CH0RSSTEV8 Slave_TIMERx interconnection event 8 generates channel 0 20 1 CH0RSSTEV7 Slave_TIMERx interconnection event 7 generates channel 0 19 1 CH0RSSTEV6 Slave_TIMERx interconnection event 6 generates channel 0 18 1 CH0RSSTEV5 Slave_TIMERx interconnection event 5 generates channel 0 17 1 CH0RSSTEV4 Slave_TIMER1 interconnection event 4 generates channel 0 16 1 CH0RSSTEV3 Slave_TIMERx interconnection event 3 generates channel 0 15 1 CH0RSSTEV2 Slave_TIMERx interconnection event 2 generates channel 0 14 1 CH0RSSTEV1 Slave_TIMERx interconnection event 1 generates channel 0 13 1 CH0RSSTEV0 Slave_TIMER1 interconnection event 0 generates channel 0 12 1 CH0RSMTCMP3 Master_TIMER compare 3 event generates channel 0 11 1 CH0RSMTCMP2 Master_TIMER compare 2 event generates channel 0 10 1 CH0RSMTCMP1 Master_TIMER compare 1 event generates channel 0 9 1 CH0RSMTCMP0 Master_TIMER compare 0 event generates channel 0 8 1 CH0RSMTPER Master_TIMER period event generates channel 0 7 1 CH0RSCMP3 Slave_TIMERx compare 3 event generates channel 0 6 1 CH0RSCMP2 Slave_TIMER1 compare 2 event generates channel 0 5 1 CH0RSCMP1 Slave_TIMERx compare 1 event generates channel 0 4 1 CH0RSCMP0 Slave_TIMERx compare 0 event generates channel 0 3 1 CH0RSPER Slave_TIMERx period event generates channel 0 2 1 CH0RSRST Slave_TIMERx reset event generates channel 0 1 1 CH0RSSEV Software event generates channel 0 0 1 ST4CH1SET ST4CH1SET SHRTIMER Slave_TIMERx channel 1 set request register 0x44 0x20 read-write 0x00000000 CH1SUP Update event generates channel 1 31 1 CH1SEXEV9 External event 9 generates channel 1 30 1 CH1SEXEV8 External event 8 generates channel 1 29 1 CH1SEXEV7 External event 7 generates channel 1 28 1 CH1SEXEV6 External event 6 generates channel 1 27 1 CH1SEXEV5 External event 5 generates channel 1 26 1 CH1SEXEV4 External event 4 generates channel 1 25 1 CH1SEXEV3 External event 3 generates channel 1 24 1 CH1SEXEV2 External event 2 generates channel 1 23 1 CH1SEXEV1 External event 1 generates channel 1 22 1 CH1SEXEV0 External event 0 generates channel 1 21 1 CH1SSTEV8 Slave_TIMERx interconnection event 8 generates channel 1 20 1 CH1SSTEV7 Slave_TIMERx interconnection event 7 generates channel 1 19 1 CH1SSTEV6 Slave_TIMERx interconnection event 6 generates channel 1 18 1 CH1SSTEV5 Slave_TIMERx interconnection event 5 generates channel 1 17 1 CH1SSTEV4 Slave_TIMERx interconnection event 4 generates channel 1 16 1 CH1SSTEV3 Slave_TIMERx interconnection event 3 generates channel 1 15 1 CH1SSTEV2 Slave_TIMERx interconnection event 2 generates channel 1 14 1 CH1SSTEV1 Slave_TIMERx interconnection event 1 generates channel 1 13 1 CH1SSTEV0 Slave_TIMERx interconnection event 0 generates channel 1 12 1 CH1SMTCMP3 Master_TIMER compare 3 event generates channel 1 11 1 CH1SMTCMP2 Master_TIMER compare 2 event generates channel 1 10 1 CH1SMTCMP1 Master_TIMER compare 1 event generates channel 1 9 1 CH1SMTCMP0 Master_TIMER compare 0 event generates channel 1 8 1 CH1SMTPER Master_TIMER period event generates channel 1 7 1 CH1SCMP3 Slave_TIMERx compare 3 event generates channel 1 6 1 CH1SCMP2 Slave_TIMERx compare 2 event generates channel 1 5 1 CH1SCMP1 Slave_TIMERx compare 1 event generates channel 1 4 1 CH1SCMP0 Slave_TIMERx compare 0 event generates channel 1 3 1 CH1SPER Slave_TIMERx period event generates channel 1 2 1 CH1SRST Slave_TIMERx reset event generates channel 1 1 1 CH1SSEV Software event generates channel 1 0 1 ST4CH1RST ST4CH1RST SHRTIMER Slave_TIMERx channel 1 reset request register 0x48 0x20 read-write 0x00000000 CH1RSUP Update event generates channel 1 31 1 CH1RSEXEV9 External event 9 generates channel 1 30 1 CH1RSEXEV8 External event 8 generates channel 1 29 1 CH1RSEXEV7 External event 7 generates channel 1 28 1 CH1RSEXEV6 External event 6 generates channel 1 27 1 CH1RSEXEV5 External event 5 generates channel 1 26 1 CH1RSEXEV4 External event 4 generates channel 1 25 1 CH1RSEXEV3 External event 3 generates channel 1 24 1 CH1RSEXEV2 External event 2 generates channel 1 23 1 CH1RSEXEV1 External event 1 generates channel 1 22 1 CH1RSEXEV0 External event 0 generates channel 1 21 1 CH1RSSTEV8 Slave_TIMERx interconnection event 8 generates channel 1 20 1 CH1RSSTEV7 Slave_TIMERx interconnection event 7 generates channel 1 19 1 CH1RSSTEV6 Slave_TIMERx interconnection event 6 generates channel 1 18 1 CH1RSSTEV5 Slave_TIMERx interconnection event 5 generates channel 1 17 1 CH1RSSTEV4 Slave_TIMERx interconnection event 4 generates channel 1 16 1 CH1RSSTEV3 Slave_TIMERx interconnection event 3 generates channel 1 15 1 CH1RSSTEV2 Slave_TIMERx interconnection event 2 generates channel 1 14 1 CH1RSSTEV1 Slave_TIMERx interconnection event 1 generates channel 1 13 1 CH1RSSTEV0 Slave_TIMERx interconnection event 0 generates channel 1 12 1 CH1RSMTCMP3 Master_TIMER compare 3 event generates channel 1 11 1 CH1RSMTCMP2 Master_TIMER compare 2 event generates channel 1 10 1 CH1RSMTCMP1 Master_TIMER compare 1 event generates channel 1 9 1 CH1RSMTCMP0 Master_TIMER compare 0 event generates channel 1 8 1 CH1RSMTPER Master_TIMER period event generates channel 1 7 1 CH1RSCMP3 Slave_TIMERx compare 3 event generates channel 1 6 1 CH1RSCMP2 Slave_TIMERx compare 2 event generates channel 1 5 1 CH1RSCMP1 Slave_TIMERx compare 1 event generates channel 1 4 1 CH1RSCMP0 Slave_TIMERx compare 0 event generates channel 1 3 1 CH1RSPER Slave_TIMERx period event generates channel 1 2 1 CH1RSRST Slave_TIMERx reset event generates channel 1 1 1 CH1RSSEV Software event generates channel 1 0 1 ST4EXEVFCFG0 ST4EXEVFCFG0 SHRTIMER Slave_TIMERx external event filter configuration register 0 0x4C 0x20 read-write 0x00000000 EXEV4FM External event 4 filter mode 25 4 EXEV4MEEN External event 4 memorized enable 24 1 EXEV3FM External event 3 filter mode 19 4 EXEV3MEEN External event 3 memorized enable 18 1 EXEV2FM External event 2 filter mode 13 4 EXEV2MEEN External event 2 memorized enable 12 1 EXEV1FM External event 1 filter mode 7 4 EXEV1MEEN External event 1 memorized enable 6 1 EXEV0FM External event 0 filter mode 1 4 EXEV0MEEN External event 0 memorized enable 0 1 ST4EXEVFCFG1 ST4EXEVFCFG1 SHRTIMER Slave_TIMERx external event filter configuration register 1 0x50 0x20 read-write 0x00000000 EXEV9FM External event 9 filter mode 25 4 EXEV9MEEN External event 9 memorized enable 24 1 EXEV8FM External event 8 filter mode 19 4 EXEV8MEEN External event 8 memorized enable 18 1 EXEV7FM External event 7 filter mode 13 4 EXEV7MEEN External event 7 memorized enable 12 1 EXEV6FM External event 6 filter mode 7 4 EXEV6MEEN External event 6 memorized enable 6 1 EXEV5FM External event 5 filter mode 1 4 EXEV5MEEN External event 5 memorized enable 0 1 ST4CNTRST ST4CNTRST SHRTIMER Slave_TIMERx counter reset register 0x54 0x20 read-write 0x00000000 ST3CMP3RST Slave_TIMER3 compare 3 event resets counter 30 1 ST3CMP1RST Slave_TIMER3 compare 1 event resets counter 29 1 ST3CMP0RST Slave_TIMER3 compare 0 event resets counter 28 1 ST2CMP3RST Slave_TIMER2 compare 3 event resets counter 27 1 ST2CMP1RST Slave_TIMER2 compare 1 event resets counter 26 1 ST2CMP0RST Slave_TIMER2 compare 0 event resets counter 25 1 ST1CMP3RST Slave_TIMER1 compare 3 event resets counter 24 1 ST1CMP1RST Slave_TIMER1 compare 1 event resets counter 23 1 ST1CMP0RST Slave_TIMER1 compare 0 event resets counter 22 1 ST0CMP3RST Slave_TIMER0 compare 3 event resets counter 21 1 ST0CMP1RST Slave_TIMER0 compare 1 event resets counter 20 1 ST0CMP0RST Slave_TIMER0 compare 0 event resets counter 19 1 EXEV9RST External event 9 resets counter 18 1 EXEV8RST External event 8 resets counter 17 1 EXEV7RST External event 7 resets counter 16 1 EXEV6RST External event 6 resets counter 15 1 EXEV5RST External event 5 resets counter 14 1 EXEV4RST External event 4 resets counter 13 1 EXEV3RST External event 3 resets counter 12 1 EXEV2RST External event 2 resets counter 11 1 EXEV1RST External event 1 resets counter 10 1 EXEV0RST External event 0 resets counter 9 1 MTCMP3RST Master_TIMER compare 3 event resets counter 8 1 MTCMP2RST Master_TIMER compare 2 event resets counter 7 1 MTCMP1RST Master_TIMER compare 1 event resets counter 6 1 MTCMP0RST Master_TIMER compare 0 event resets counter 5 1 MTPERRST Master_TIMER period event resets counter 4 1 CMP3RST Slave_TIMERx compare 3 event resets counter 3 1 CMP1RST Slave_TIMERx compare 1 event resets counter 2 1 UPRST Slave_TIMERx update event resets counter 1 1 ST4CSCTL ST4CSCTL SHRTIMER Slave_TIMERx carrier-signal control register 0x58 0x20 read-write 0x00000000 CSFSTPW First carrier-signal pulse width 7 4 CSDTY Carrier signal duty cycle 4 3 CSPRD Carrier signal period 0 4 ST4CAP0TRG ST4CAP0TRG SHRTIMER Slave_TIMERx capture 0 trigger register 0x5C 0x20 read-write 0x00000000 CP0BST3CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER3 27 1 CP0BST3CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER3 26 1 CP0BST3NA Capture 0 triggered by ST3CH0_O output active to inactive transition 25 1 CP0BST3A Capture 0 triggered by ST3CH0_O output inactive to active transition 24 1 CP0BST2CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER2 23 1 CP0BST2CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER2 22 1 CP0BST2NA Capture 0 triggered by ST2CH0_O output active to inactive transition 21 1 CP0BST2A Capture 0 triggered by ST2CH0_O output inactive to active transition 20 1 CP0BST1CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER1 19 1 CP0BST1CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER1 18 1 CP0BST1NA Capture 0 triggered by ST2CH1_O output active to inactive transition 17 1 CP0BST1A Capture 0 triggered by ST2CH1_O output inactive to active transition 16 1 CP0BST0CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER0 15 1 CP0BST0CMP0 Capture 0 triggered by compare 0 event of Slave_TIMER0 14 1 CP0BST0NA Capture 0 triggered by ST0CH0_O output active to inactive transition 13 1 CP0BST0A Capture 0 triggered by ST0CH0_O output inactive to active transition 12 1 CP0BEXEV9 Capture 0 triggered by external event 9 11 1 CP0BEXEV8 Capture 0 triggered by external event 8 10 1 CP0BEXEV7 Capture 0 triggered by external event 7 9 1 CP0BEXEV6 Capture 0 triggered by external event 6 8 1 CP0BEXEV5 Capture 0 triggered by external event 5 7 1 CP0BEXEV4 Capture 0 triggered by external event 4 6 1 CP0BEXEV3 Capture 0 triggered by external event 3 5 1 CP0BEXEV2 Capture 0 triggered by external event 2 4 1 CP0BEXEV1 Capture 0 triggered by external event 1 3 1 CP0BEXEV0 Capture 0 triggered by external event 0 2 1 CP0BUP Capture 0 triggered by update event 1 1 CP0BSW Capture 0 triggered by software 0 1 ST4CAP1TRG ST4CAP1TRG SHRTIMER Slave_TIMERx capture 1 trigger register 0x60 0x20 read-write 0x00000000 CP0BST3CMP1 Capture 0 triggered by compare 1 event of Slave_TIMER3 27 1 CP1BST3CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER3 26 1 CP1BST3NA Capture 1 triggered by ST3CH0_O output active to inactive transition 25 1 CP1BST3A Capture 1 triggered by ST3CH0_O output inactive to active transition 24 1 CP1BST2CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER2 23 1 CP1BST2CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER2 22 1 CP1BST2NA Capture 1 triggered by ST2CH0_O output active to inactive transition 21 1 CP1BST2A Capture 1 triggered by ST2CH0_O output inactive to active transition 20 1 CP1BST1CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER1 19 1 CP1BST1CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER1 18 1 CP1BST1NA Capture 1 triggered by ST2CH1_O output active to inactive transition 17 1 CP1BST1A Capture 1 triggered by ST2CH1_O output inactive to active transition 16 1 CP1BST0CMP1 Capture 1 triggered by compare 1 event of Slave_TIMER0 15 1 CP1BST0CMP0 Capture 1 triggered by compare 0 event of Slave_TIMER0 14 1 CP1BST0NA Capture 1 triggered by ST0CH0_O output active to inactive transition 13 1 CP1BST0A Capture 1 triggered by ST0CH0_O output inactive to active transition 12 1 CP1BEXEV9 Capture 1 triggered by external event 9 11 1 CP1BEXEV8 Capture 1 triggered by external event 8 10 1 CP1BEXEV7 Capture 1 triggered by external event 7 9 1 CP1BEXEV6 Capture 1 triggered by external event 6 8 1 CP1BEXEV5 Capture 1 triggered by external event 5 7 1 CP1BEXEV4 Capture 1 triggered by external event 4 6 1 CP1BEXEV3 Capture 1 triggered by external event 3 5 1 CP1BEXEV2 Capture 1 triggered by external event 2 4 1 CP1BEXEV1 Capture 1 triggered by external event 1 3 1 CP1BEXEV0 Capture 1 triggered by external event 0 2 1 CP1BUP Capture 1 triggered by update event 1 1 CP1BSW Capture 1 triggered by software 0 1 ST4CHOCTL ST4CHOCTL SHRTIMER Slave_TIMERx channel output control register 0x64 0x20 read-write 0x00000000 BMCH1DTI Channel 1 dead-time insert in bunch mode 23 1 CH1CSEN Channel 1 carrier-signal mode enable 22 1 CH1FLTOS Channel 1 Fault output state 20 2 ISO1 channel 1 output idle state 19 1 BMCH1IEN Channel 1 IDLE state enable in bunch mode 18 1 CH1P Channel 1 output polarity 17 1 DLYISCH Delayed IDLE source and channel 10 3 DLYISMEN Delayed IDLE state mode enable 9 1 DTEN Dead time enable 8 1 BMCH0DTI Channel 0 dead-time insert in bunch mode 7 1 CH0CSEN Channel 0 carrier-signal mode enable 6 1 CH0FLTOS Channel 0 Fault output state 4 2 ISO0 Channel 0 output idle state 3 1 BMCH0IEN Channel 0 IDLE state enable in bunch mode 2 1 CH0P Channel 0 output polarity 1 1 ST4FLTCTL ST4FLTCTL SHRTIMER Slave_TIMERx fault control register 0x68 0x20 read-write 0x00000000 FLTENPROT Protect fault enable 31 1 FLT4EN Fault 4 enable 4 1 FLT3EN Fault 3 enable 3 1 FLT2EN Fault 2 enable 2 1 FLT1EN Fault 1 enable 1 1 FLT0EN Fault 0 enable 0 1 ST4ACTL ST4ACTL SHRTIMER Slave_TIMERx additional control register 0x7C 0x20 read-write 0x00000000 DTFCFG_15_9 Falling edge dead-time value configure 25 7 DTRCFG_15_9 Rising edge dead-time value configure 9 7 CNTCKDIV_3 Counter clock division 3 1 SHRTIMER_COMMON SHRTIMER Common registers SHRTIMER 0x40017780 0x0 0x80 registers SHRTIMER_IRQ6 73 CTL0 CTL0 SHRTIMER control register 0 0x00 0x20 read-write 0x00000000 ADTG3USRC SHRTIMER_ADCTRIG3 update source 25 3 ADTG2USRC SHRTIMER_ADCTRIG2 update source 22 3 ADTG1USRC SHRTIMER_ADCTRIG1 update source 19 3 ADTG0USRC SHRTIMER_ADCTRIG0 update source 16 3 ST4UPDIS Slave_TIMER4 update disable 5 1 ST3UPDIS Slave_TIMER3 update disable 4 1 ST2UPDIS Slave_TIMER2 update disable 3 1 ST0UPDIS Slave_TIMER0 update disable 1 1 MTUPDIS Master_TIMER update disable 0 1 CTL1 CTL1 SHRTIMER control register 1 0x04 0x20 read-write 0x00000000 ST4SRST Slave_TIMER4 software reset 13 1 ST3SRST Slave_TIMER3 software reset 12 1 ST2SRST Slave_TIMER2 software reset 11 1 ST1SRST Slave_TIMER1 software reset 10 1 ST0SRST Slave_TIMER0 software reset 9 1 MTSRST Master_TIMER software reset 8 1 ST4SUP Slave_TIMER4 software update 5 1 ST3SUP Slave_TIMER3 software update 4 1 ST2SUP Slave_TIMER2 software update 3 1 ST1SUP Slave_TIMER1 software update 2 1 ST0SUP Slave_TIMER0 software update 1 1 MTSUP Master_TIMER software update 0 1 INTF INTF SHRTIMER interrupt flag register 0x08 0x20 read-only 0x00000000 BMPERIF Bunch mode period interrupt flag 17 1 DLLCALIF DLL calibration completed interrupt flag 16 1 SYSFLTIF System fault interrupt flag 5 1 FLT4IF Fault 4 interrupt flag 4 1 FLT3IF Fault 3 interrupt flag 3 1 FLT2IF Fault 2 interrupt flag 2 1 FLT1IF Fault 1 interrupt flag 1 1 FLT0IF Fault 0 interrupt flag 0 1 INTC INTC SHRTIMER interrupt flag clear register 0x0C 0x20 write-only 0x00000000 BMPERIFC Clear bunch mode period interrupt flag 17 1 DLLCALIF Clear DLL calibration completed interrupt flag 16 1 SYSFLTIFC Clear system fault interrupt flag 5 1 FLT4IFC Clear fault 4 interrupt flag 4 1 FLT3IFC Clear fault 3 interrupt flag 3 1 FLT2IFC Clear fault 2 interrupt flag 2 1 FLT1IF Fault 1 interrupt flag 1 1 FLT0IFC Fault 0 interrupt flag 0 1 INTEN INTEN SHRTIMER interrupt enable register 0x10 0x20 read-write 0x00000000 BMPERIE Bunch mode period interrupt enable 17 1 DLLCALIE DLL calibration completed interrupt enable 16 1 SYSFLTIE System fault interrupt enable 5 1 CHOUTEN CHOUTEN SHRTIMER channel output enable register 0x14 0x20 read-write 0x00000000 ST4CH1EN Slave_TIMER4 channel 1 output (ST4CH1_O) enable 9 1 ST4CH0EN Slave_TIMER4 channel 0 output (ST4CH0_O) enable 8 1 ST3CH1EN Slave_TIMER3 channel 1 output (ST3CH1_O) enable 7 1 ST3CH0EN Slave_TIMER3 channel 0 output (ST3CH0_O) enable 6 1 ST2CH1EN Slave_TIMER2 channel 1 output (ST2CH1_O) enable 5 1 ST2CH0EN Slave_TIMER2 channel 0 output (ST2CH0_O) enable 4 1 ST1CH1EN Slave_TIMER1 channel 1 output (ST1CH1_O) enable 3 1 ST1CH0EN Slave_TIMER1 channel 0 output (ST1CH0_O) enable 2 1 ST0CH1EN Slave_TIMER0 channel 1 output (ST0CH1_O) enable 1 1 ST0CH0EN Slave_TIMER0 channel 0 output (ST0CH0_O) enable 0 1 CHOUTDIS CHOUTDIS SHRTIMER channel output disable register 0x18 0x20 write-only 0x00000000 ST4CH1DIS Slave_TIMER4 channel 1 output (ST4CH1_O) disable 9 1 ST4CH0DIS Slave_TIMER4 channel 0 output (ST4CH0_O) disable 8 1 ST3CH1DIS Slave_TIMER3 channel 1 output (ST3CH1_O) disable 7 1 ST3CH0DIS Slave_TIMER3 channel 0 output (ST3CH0_O) disable 6 1 ST2CH1DIS Slave_TIMER2 channel 1 output (ST2CH1_O) disable 5 1 ST2CH0DIS Slave_TIMER2 channel 0 output (ST2CH0_O) disable 4 1 ST1CH1DIS Slave_TIMER1 channel 1 output (ST1CH1_O) disable 3 1 ST1CH0DIS Slave_TIMER1 channel 0 output (ST1CH0_O) disable 2 1 ST0CH1DIS Slave_TIMER0 channel 1 output (ST4CH0_O) disable 1 1 ST0CH0DIS Slave_TIMER0 channel 0 output (ST0CH0_O) disable 0 1 CHOUTDISF CHOUTDISF SHRTIMER channel output disable flag register 0x1C 0x20 read-only 0x00000000 ST4CH1DISF Slave_TIMER4 channel 1 output (ST4CH1_O) disable flag 9 1 ST4CH0DISF Slave_TIMER4 channel 0 output (ST4CH0_O) disable flag 8 1 ST3CH1DISF Slave_TIMER3 channel 1 output (ST3CH1_O) disable flag 7 1 ST3CH0DISF Slave_TIMER3 channel 0 output (ST3CH0_O) disable flag 6 1 ST2CH1DISF Slave_TIMER2 channel 1 output (ST2CH1_O) disable flag 5 1 ST2CH0DISF Slave_TIMER2 channel 0 output (ST2CH0_O) disable flag 4 1 ST1CH1DISF Slave_TIMER1 channel 1 output (ST1CH1_O) disable flag 3 1 ST1CH0DISF Slave_TIMER1 channel 0 output (ST1CH0_O) disable flag 2 1 ST0CH1DISF Slave_TIMER0 channel 1 output (ST0CH1_O) disable flag 1 1 ST0CH0DISF Slave_TIMER0 channel 0 output (ST0CH0_O) disable flag 0 1 BMCTL BMCTL SHRTIMER bunch mode control register 0x20 0x20 read-write 0x00000000 BMOPTF Bunch mode operating flag 31 1 BMST4 Slave_TIMER4 bunch mode 21 1 BMST3 Slave_TIMER3 bunch mode 20 1 BMST2 Slave_TIMER2 bunch mode 19 1 BMST1 Slave_TIMER1 bunch mode 18 1 BMST0 Slave_TIMER0 bunch mode 17 1 BMMT Master_TIMER bunch mode 16 1 BMSE Bunch mode shadow enable 10 1 BMPSC Bunch mode clock division 6 4 BMCLKS Bunch mode clock source 2 4 BMCTN Continuous mode in bunch mode 1 1 BMEN Bunch mode enable 0 1 BMSTRG BMSTRG SHRTIMER bunch mode start trigger register 0x24 0x20 read-write 0x00000000 CISGN Chip internal signal triggers bunch mode operation 31 1 EXEV7 External event 7 triggers bunch mode operation 30 1 EXEV6 External event 6 triggers bunch mode operation 29 1 ST3EXEV7 Slave_TIMER3 period event following external event 7 triggers bunch mode operation 28 1 ST0EXEV6 Slave_TIMER0 period event following external event 6 triggers bunch mode operation 27 1 ST4CMP1 Slave_TIMER4 compare 1 event triggers bunch mode operation 26 1 ST4CMP0 Slave_TIMER4 compare 0 event triggers bunch mode operation 25 1 ST4REP Slave_TIMER4 repetition event triggers bunch mode operation 24 1 ST4RST Slave_TIMER4 reset event triggers bunch mode operation 23 1 ST3CMP1 Slave_TIMER3 compare 1 event triggers bunch mode operation 22 1 ST3CMP0 Slave_TIMER3 compare 0 event triggers bunch mode operation 21 1 ST3REP Slave_TIMER3 repetition event triggers bunch mode operation 20 1 ST3RST Slave_TIMER3 reset event triggers bunch mode operation 19 1 ST2CMP1 Slave_TIMER2 compare 1 event triggers bunch mode operation 18 1 ST2CMP0 Slave_TIMER2 compare 0 event triggers bunch mode operation 17 1 ST2REP Slave_TIMER1 repetition event triggers bunch mode operation 16 1 ST2RST Slave_TIMER2 reset event triggers bunch mode operation 15 1 ST1CMP1 Slave_TIMER1 compare 1 event triggers bunch mode operation 14 1 ST1CMP0 Slave_TIMER1 compare 0 event triggers bunch mode operation 13 1 ST1REP Slave_TIMER1 repetition event triggers bunch mode operation 12 1 ST1RST Slave_TIMER1 reset event triggers bunch mode operation 11 1 ST0CMP1 Slave_TIMER0 compare 1 event triggers bunch mode operation 10 1 ST0CMP0 Slave_TIMER0 compare 0 event triggers bunch mode operation 9 1 ST0REP Slave_TIMER0 repetition event triggers bunch mode operation 8 1 ST0RST Slave_TIMER0 reset event triggers bunch mode operation 7 1 MTCMP3 Master_TIMER compare 3 event triggers bunch mode operation 6 1 MTCMP2 Master_TIMER compare 2 event triggers bunch mode operation 5 1 MTCMP1 Master_TIMER compare 1 event triggers bunch mode operation 4 1 MTCMP0 Master_TIMER compare 0 event triggers bunch mode operation 3 1 MTREP Master_TIMER repetition event triggers bunch mode operation 2 1 MTRST Master_TIMER reset event triggers bunch mode operation 1 1 SWTRG Software triggers bunch mode operation 0 1 BMCMPV BMCMPV SHRTIMER bunch mode compare value register 0x28 0x20 read-write 0x00000000 BMCMPVAL Bunch mode compare value 0 16 BMCAR BMCAR SHRTIMER bunch mode counter auto reload register 0x2C 0x20 read-write 0x00000000 BMCARL Bunch mode counter auto reload value 0 16 EXEVCFG0 EXEVCFG0 SHRTIMER external event configuration register 0 0x30 0x20 read-write 0x00000000 EXEV4EG External event 4 edge sensitivity 27 2 EXEV4P External event 4 polarity 26 1 EXEV4SRC External event 4 source 24 2 EXEV3EG External event 3 edge sensitivity 21 2 EXEV3P External event 3 polarity 20 1 EXEV3SRC External event 3 source 18 2 EXEV2EG External event 2 edge sensitivity 15 2 EXEV2P External event 2 polarity 14 1 EXEV2SRC External event 2 source 12 2 EXEV1EG External event 1 edge sensitivity 9 2 EXEV1P External event 1 polarity 8 1 EXEV1SRC External event 1 source 6 2 EXEV0EG External event 0 edge sensitivity 3 2 EXEV0P External event 0 polarity 2 1 EXEV0SRC External event 0 source 0 2 EXEVCFG1 EXEVCFG1 SHRTIMER external event configuration register 1 0x34 0x20 read-write 0x00000000 EXEV9EG External event 9 edge sensitivity 27 2 EXEV9P External event 9 polarity 26 1 EXEV9SRC External event 9 source 24 2 EXEV8EG External event 8 edge sensitivity 21 2 EXEV8P External event 8 polarity 20 1 EXEV8SRC External event 8 source 18 2 EXEV7EG External event 7 edge sensitivity 15 2 EXEV7P External event 7polarity 14 1 EXEV7SRC External event 7 source 12 2 EXEV6EG External event 6 edge sensitivity 9 2 EXEV6P External event 1 polarity 8 1 EXEV6SRC External event 1 source 6 2 EXEV5EG External event 0 edge sensitivity 3 2 EXEV5P External event 0 polarity 2 1 EXEV5SRC External event 0 source 0 2 EXEVDFCTL EXEVDFCTL SHRTIMER external event digital filter control register 0x38 0x20 read-write 0x00000000 EXEVFDIV External event digital filter clock division 30 2 EXEV9FC External event 9 filter control 24 4 EXEV8FC External event 8 filter control 18 4 EXEV7FC External event 7 filter control 12 4 EXEV6FC External event 6 filter control 6 4 EXEV5FC External event 5 filter control 0 4 ADCTRIGS0 ADCTRIGS0 SHRTIMER trigger source 0 to ADC register 0x3C 0x20 read-write 0x00000000 TRG0ST4PER SHRTIMER_ADCTRIG0 on Slave_TIMER4 period event 31 1 TRG0ST4C3 SHRTIMER_ADCTRIG0 on Slave_TIMER4 compare 3 event 30 1 TRG0ST4C2 SHRTIMER_ADCTRIG0 on Slave_TIMER4 compare 2 event 29 1 TRG0ST4C1 SHRTIMER_ADCTRIG0 on Slave_TIMER4 compare 1 event 28 1 TRG0ST3PER SHRTIMER_ADCTRIG0 on Slave_TIMER3 period event 27 1 TRG0ST3C3 SHRTIMER_ADCTRIG0 on Slave_TIMER3 compare 3 event 26 1 TRG0ST3C2 SHRTIMER_ADCTRIG0 on Slave_TIMER3 compare 2 event 25 1 TRG0ST3C1 SHRTIMER_ADCTRIG0 on Slave_TIMER3 compare 1 event 24 1 TRG0ST2PER SHRTIMER_ADCTRIG0 on Slave_TIMER2 period event 23 1 TRG0ST2C3 SHRTIMER_ADCTRIG0 on Slave_TIMER2 compare 3 event 22 1 TRG0ST2C2 SHRTIMER_ADCTRIG0 on Slave_TIMER2 compare 2 event 21 1 TRG0ST2C1 SHRTIMER_ADCTRIG0 on Slave_TIMER2 compare 1 event 20 1 TRG0ST1RST SHRTIMER_ADCTRIG0 on Slave_TIMER1 reset 19 1 TRG0ST1PER SHRTIMER_ADCTRIG0 on Slave_TIMER1 period event 18 1 TRG0ST1C3 SHRTIMER_ADCTRIG0 on Slave_TIMER1 compare 3 event 17 1 TRG0ST1C2 SHRTIMER_ADCTRIG0 on Slave_TIMER1 compare 2 event 16 1 TRG0ST1C1 SHRTIMER_ADCTRIG0 on Slave_TIMER1 compare 1 event 15 1 TRG0ST0RST SHRTIMER_ADCTRIG0 on Slave_TIMER0 reset 14 1 TRG0ST0PER SHRTIMER_ADCTRIG0 on Slave_TIMER0 period event 13 1 TRG0ST0C3 SHRTIMER_ADCTRIG0 on Slave_TIMER0 compare 3 event 12 1 TRG0ST0C2 SHRTIMER_ADCTRIG0 on Slave_TIMER0 compare 2 event 11 1 TRG0ST0C1 SHRTIMER_ADCTRIG0 on Slave_TIMER0 compare 1 event 10 1 TRG0EXEV4 SHRTIMER_ADCTRIG0 on external event 4 9 1 TRG0EXEV3 SHRTIMER_ADCTRIG0 on external event 3 8 1 TRG0EXEV2 SHRTIMER_ADCTRIG0 on external event 2 7 1 TRG0EXEV1 SHRTIMER_ADCTRIG0 on external event 1 6 1 TRG0EXEV0 SHRTIMER_ADCTRIG0 on external event 0 5 1 TRG0MTPER SHRTIMER_ADCTRIG0 on Master_TIMER period event 4 1 TRG0MTC3 SHRTIMER_ADCTRIG0 on Master_TIMER compare 3 event 3 1 TRG0MTC2 SHRTIMER_ADCTRIG0 on Master_TIMER compare 2 event 2 1 TRG0MTC1 SHRTIMER_ADCTRIG0 on Master_TIMER compare 1 event 1 1 TRG0MTC0 SHRTIMER_ADCTRIG0 on Master_TIMER compare 0 event 0 1 ADCTRIGS1 ADCTRIGS1 SHRTIMER trigger source 1 to ADC register 0x40 0x20 read-write 0x00000000 TRG1ST4RST SHRTIMER_ADCTRIG1 on Slave_TIMER4 reset 31 1 TRG1ST4C3 SHRTIMER_ADCTRIG1 on Slave_TIMER4 compare 3 event 30 1 TRG1ST4C2 SHRTIMER_ADCTRIG1 on Slave_TIMER4 compare 2 event 29 1 TRG1ST4C1 SHRTIMER_ADCTRIG1 on Slave_TIMER4 compare 1 event 28 1 TRG1ST3RST SHRTIMER_ADCTRIG1 on Slave_TIMER3 reset 27 1 TRG1ST3PER SHRTIMER_ADCTRIG1 on Slave_TIMER3 period event 26 1 TRG1ST3C3 SHRTIMER_ADCTRIG1 on Slave_TIMER3 compare 3 event 25 1 TRG1ST3C2 SHRTIMER_ADCTRIG1 on Slave_TIMER3 compare 2 event 24 1 TRG1ST3C1 SHRTIMER_ADCTRIG1 on Slave_TIMER3 compare 1 event 23 1 TRG1ST2RST SHRTIMER_ADCTRIG1 on Slave_TIMER2 reset 22 1 TRG1ST2PER SHRTIMER_ADCTRIG1 on Slave_TIMER2 period event 21 1 TRG1ST2C3 SHRTIMER_ADCTRIG1 on Slave_TIMER2 compare 3 event 20 1 TRG1ST2C2 SHRTIMER_ADCTRIG1 on Slave_TIMER2 compare 2 event 19 1 TRG1ST2C1 SHRTIMER_ADCTRIG1 on Slave_TIMER2 compare 1 event 18 1 TRG1ST1PER SHRTIMER_ADCTRIG1 on Slave_TIMER1 period event 17 1 TRG1ST1C3 SHRTIMER_ADCTRIG1 on Slave_TIMER1 compare 3 event 16 1 TRG1ST1C2 SHRTIMER_ADCTRIG1 on Slave_TIMER1 compare 2 event 15 1 TRG1ST1C1 SHRTIMER_ADCTRIG1 on Slave_TIMER1 compare 1 event 14 1 TRG1ST0PER SHRTIMER_ADCTRIG1 on Slave_TIMER0 period event 13 1 TRG1ST0C3 SHRTIMER_ADCTRIG1 on Slave_TIMER0 compare 3 event 12 1 TRG1ST0C2 SHRTIMER_ADCTRIG1 on Slave_TIMER0 compare 2 event 11 1 TRG1ST0C1 SHRTIMER_ADCTRIG1 on Slave_TIMER0 compare 1 event 10 1 TRG1EXEV9 SHRTIMER_ADCTRIG1 on external event 9 9 1 TRG1EXEV8 SHRTIMER_ADCTRIG1 on external event 8 8 1 TRG1EXEV7 SHRTIMER_ADCTRIG1 on external event 7 7 1 TRG1EXEV6 SHRTIMER_ADCTRIG1 on external event 6 6 1 TRG1EXEV5 SHRTIMER_ADCTRIG1 on external event 5 5 1 TRG1MTPER SHRTIMER_ADCTRIG1 on Master_TIMER period event 4 1 TRG1MTC3 SHRTIMER_ADCTRIG1 on Master_TIMER compare 3 event 3 1 TRG1MTC2 SHRTIMER_ADCTRIG1 on Master_TIMER compare 2 event 2 1 TRG1MTC1 SHRTIMER_ADCTRIG1 on Master_TIMER compare 1 event 1 1 TRG1MTC0 SHRTIMER_ADCTRIG1 on Master_TIMER compare 0 event 0 1 ADCTRIGS2 ADCTRIGS2 SHRTIMER trigger source 2 to ADC register 0x44 0x20 read-write 0x00000000 TRG2ST4PER SHRTIMER_ADCTRIG2 on Slave_TIMER4 period event 31 1 TRG2ST4C3 SHRTIMER_ADCTRIG2 on Slave_TIMER4 compare 3 event 30 1 TRG2ST4C2 SHRTIMER_ADCTRIG2 on Slave_TIMER4 compare 2 event 29 1 TRG2ST4C1 SHRTIMER_ADCTRIG2 on Slave_TIMER4 compare 1 event 28 1 TRG2ST3PER SHRTIMER_ADCTRIG2 on Slave_TIMER3 period event 27 1 TRG2ST3C3 SHRTIMER_ADCTRIG2 on Slave_TIMER3 compare 3 event 26 1 TRG2ST3C2 SHRTIMER_ADCTRIG2 on Slave_TIMER3 compare 2 event 25 1 TRG2ST3C1 SHRTIMER_ADCTRIG2 on Slave_TIMER3 compare 1 event 24 1 TRG2ST2PER SHRTIMER_ADCTRIG2 on Slave_TIMER2 period event 23 1 TRG2ST2C3 SHRTIMER_ADCTRIG2 on Slave_TIMER2 compare 3 event 22 1 TRG2ST2C2 SHRTIMER_ADCTRIG2 on Slave_TIMER2 compare 2 event 21 1 TRG2ST2C1 SHRTIMER_ADCTRIG2 on Slave_TIMER2 compare 1 event 20 1 TRG2ST1RST SHRTIMER_ADCTRIG2 on Slave_TIMER1 reset 19 1 TRG2ST1PER SHRTIMER_ADCTRIG2 on Slave_TIMER1 period event 18 1 TRG2ST1C3 SHRTIMER_ADCTRIG2 on Slave_TIMER1 compare 3 event 17 1 TRG2ST1C2 SHRTIMER_ADCTRIG2 on Slave_TIMER1 compare 2 event 16 1 TRG2ST1C1 SHRTIMER_ADCTRIG2 on Slave_TIMER1 compare 1 event 15 1 TRG2ST0RST SHRTIMER_ADCTRIG2 on Slave_TIMER0 reset 14 1 TRG2ST0PER SHRTIMER_ADCTRIG2 on Slave_TIMER0 period event 13 1 TRG2ST0C3 SHRTIMER_ADCTRIG2 on Slave_TIMER0 compare 3 event 12 1 TRG2ST0C2 SHRTIMER_ADCTRIG2 on Slave_TIMER0 compare 2 event 11 1 TRG2ST0C1 SHRTIMER_ADCTRIG2 on Slave_TIMER0 compare 1 event 10 1 TRG2EXEV4 SHRTIMER_ADCTRIG2 on external event 4 9 1 TRG2EXEV3 SHRTIMER_ADCTRIG2 on external event 3 8 1 TRG2EXEV2 SHRTIMER_ADCTRIG2 on external event 2 7 1 TRG2EXEV1 SHRTIMER_ADCTRIG2 on external event 1 6 1 TRG2EXEV0 SHRTIMER_ADCTRIG2 on external event 0 5 1 TRG2MTPER SHRTIMER_ADCTRIG2 on Master_TIMER period event 4 1 TRG2MTC3 SHRTIMER_ADCTRIG2 on Master_TIMER compare 3 event 3 1 TRG2MTC2 SHRTIMER_ADCTRIG2 on Master_TIMER compare 2 event 2 1 TRG2MTC1 SHRTIMER_ADCTRIG2 on Master_TIMER compare 1 event 1 1 TRG2MTC0 SHRTIMER_ADCTRIG2 on Master_TIMER compare 0 event 0 1 ADCTRIGS3 ADCTRIGS3 SHRTIMER trigger source 3 to ADC register 0x48 0x20 read-write 0x00000000 TRG3ST4RST SHRTIMER_ADCTRIG3 on Slave_TIMER4 reset 31 1 TRG3ST4C3 SHRTIMER_ADCTRIG3 on Slave_TIMER4 compare 3 event 30 1 TRG3ST4C2 SHRTIMER_ADCTRIG3 on Slave_TIMER4 compare 2 event 29 1 TRG3ST4C1 SHRTIMER_ADCTRIG3 on Slave_TIMER4 compare 1 event 28 1 TRG3ST3RST SHRTIMER_ADCTRIG3 on Slave_TIMER3 reset 27 1 TRG3ST3PER SHRTIMER_ADCTRIG3 on Slave_TIMER3 period event 26 1 TRG3ST3C3 SHRTIMER_ADCTRIG3 on Slave_TIMER3 compare 3 event 25 1 TRG3ST3C2 SHRTIMER_ADCTRIG3 on Slave_TIMER3 compare 2 event 24 1 TRG3ST3C1 SHRTIMER_ADCTRIG3 on Slave_TIMER3 compare 1 event 23 1 TRG3ST2RST SHRTIMER_ADCTRIG3 on Slave_TIMER2 reset 22 1 TRG3ST2PER SHRTIMER_ADCTRIG3 on Slave_TIMER2 period event 21 1 TRG3ST2C3 SHRTIMER_ADCTRIG3 on Slave_TIMER2 compare 3 event 20 1 TRG3ST2C2 SHRTIMER_ADCTRIG3 on Slave_TIMER2 compare 2 event 19 1 TRG3ST2C1 SHRTIMER_ADCTRIG3 on Slave_TIMER2 compare 1 event 18 1 TRG1ST3PER SHRTIMER_ADCTRIG3 on Slave_TIMER1 period event 17 1 TRG3ST1C3 SHRTIMER_ADCTRIG3 on Slave_TIMER1 compare 3 event 16 1 TRG3ST1C2 SHRTIMER_ADCTRIG3 on Slave_TIMER1 compare 2 event 15 1 TRG3ST1C1 SHRTIMER_ADCTRIG3 on Slave_TIMER1 compare 1 event 14 1 TRG3ST0PER SHRTIMER_ADCTRIG3 on Slave_TIMER0 period event 13 1 TRG3ST0C3 SHRTIMER_ADCTRIG3 on Slave_TIMER0 compare 3 event 12 1 TRG3ST0C2 SHRTIMER_ADCTRIG3 on Slave_TIMER0 compare 2 event 11 1 TRG3ST0C1 SHRTIMER_ADCTRIG3 on Slave_TIMER0 compare 1 event 10 1 TRG3EXEV9 SHRTIMER_ADCTRIG3 on external event 9 9 1 TRG3EXEV8 SHRTIMER_ADCTRIG3 on external event 8 8 1 TRG3EXEV7 SHRTIMER_ADCTRIG3 on external event 7 7 1 TRG3EXEV6 SHRTIMER_ADCTRIG3 on external event 6 6 1 TRG3EXEV5 SHRTIMER_ADCTRIG3 on external event 5 5 1 TRG3MTPER SHRTIMER_ADCTRIG3 on Master_TIMER period event 4 1 TRG3MTC3 SHRTIMER_ADCTRIG3 on Master_TIMER compare 3 event 3 1 TRG3MTC2 SHRTIMER_ADCTRIG3 on Master_TIMER compare 2 event 2 1 TRG1MTC3 SHRTIMER_ADCTRIG3 on Master_TIMER compare 1 event 1 1 TRG3MTC0 SHRTIMER_ADCTRIG3 on Master_TIMER compare 0 event 0 1 DLLCCTL DLLCCTL SHRTIMER DLL calibration control register 0x4C 0x20 read-write 0x00000000 CLBPER DLL calibration period 2 2 CLBPEREN DLL periodic calibration enable 1 1 CLBSTRT DLL calibration start once 0 1 FLTINCFG0 FLTINCFG0 SHRTIMER fault input configuration register 0 0x50 0x20 read-write 0x00000000 FLT3INPROT Protect fault 3 input configuration 31 1 FLT3INFC Fault 3 input filter control 27 4 FLT3INSRC Fault 3 input source 26 1 FLT3INP Fault 3 input polarity 25 1 FLT3INEN Fault 3 input enable 24 1 FLT2INPROT Protect fault 2 input configuration 23 1 FLT2INFC Fault 2 input filter control 19 4 FLT2INSRC Fault 2 input source 18 1 FLT2INP Fault 2 input polarity 17 1 FLT2INEN Fault 2 input enable 16 1 FLT1INPROT Protect fault 1 input configuration 15 1 FLT1INFC Fault 1 input filter control 11 4 FLT1INSRC Fault 2 input source 10 1 FLT1INP Fault 1 input polarity 9 1 FLT1INEN Fault 1 input enable 8 1 FLT0INPROT Protect fault 0 input configuration 7 1 FLT0INFC Fault 0 input filter control 3 4 FLT0INSRC Fault 0 input source 2 1 FLT0INP Fault 0 input polarity 1 1 FLT0INEN Fault 0 input enable 0 1 FLTINCFG1 FLTINCFG1 SHRTIMER fault input configuration register 1 0x54 0x20 read-write 0x00000000 FLTFDIV Fault input digital filter clock division 24 2 FLT4INPROT Protect fault 4 input configuration 7 1 FLT4INFC Fault 4 input filter control 3 4 FLT4INSRC Fault 4 input source 2 1 FLT4INP Fault 4 input polarity 1 1 FLT4INEN Fault 4 input enable 0 1 DMAUPMTR DMAUPMTR SHRTIMER DMA update Master_TIMER register 0x58 0x20 read-write 0x00000000 MTACTL SHRTIMER_MTACTL update by DMA mode 31 1 MTCMP3V SHRTIMER_MTCMP3V update by DMA mode 9 1 MTCMP2V SHRTIMER_MTCMP2V update by DMA mode 8 1 MTCMP1V SHRTIMER_MTCMP1V update by DMA mode 7 1 MTCMP0V SHRTIMER_MTCMP0V update by DMA mode 6 1 MTCREP SHRTIMER_MTCAR update by DMA mode 5 1 MTCAR SHRTIMER_MTCAR update by DMA mode 4 1 MTCNT SHRTIMER_MTCNT update by DMA mode 3 1 MTDMAINTEN SHRTIMER_MTDMAINTEN update by DMA mode 2 1 MTINTC SHRTIMER_MTINTC update by DMA mode 1 1 MTCTL0 SHRTIMER_MTCTL0 update by DMA mode 0 1 DMAUPST0R DMAUPST0R SHRTIMER DMA update Slave_TIMER0 register 0x5C 0x20 read-write 0x00000000 ST0ACTL SHRTIMER_ST0ACTL update by DMA mode 31 1 ST0FLTCTL SHRTIMER_ST0FLTCTL update by DMA mode 20 1 ST0CHOCTL SHRTIMER_ST0CHOCTL update by DMA mode 19 1 ST0CSCTL SHRTIMER_ST0CSCTL update by DMA mode 18 1 ST0CNTRST SHRTIMER_ST0CNTRST update by DMA mode 17 1 ST0EXEVFCFG1 SHRTIMER_ST0EXEVFCFG1update by DMA mode 16 1 ST0EXEVFCFG0 SHRTIMER_ST0EXEVFCFG0update by DMA mode 15 1 ST0CH1RST SHRTIMER_ST0CH1RST update by DMA mode 14 1 ST0CH1SET SHRTIMER_ST0CH1SET update by DMA mode 13 1 ST0CH0RST SHRTIMER_ST0CH0RST update by DMA mode 12 1 ST0CH0SET SHRTIMER_ST0CH0SET update by DMA mode 11 1 ST0DTCTL SHRTIMER_ST0DTCTL update by DMA mode 10 1 ST0CMP3V SHRTIMER_ST0CMP3V update by DMA mode 9 1 ST0CMP2V SHRTIMER_ST0CMP2V update by DMA mode 8 1 ST0CMP1V SHRTIMER_ST0CMP1V update by DMA mode 7 1 ST0CMP0V SHRTIMER_ST0CMP0V update by DMA mode 6 1 ST0CREP SHRTIMER_ST0CREP update by DMA mode 5 1 ST0CAR SHRTIMER_ST0CAR update by DMA mode 4 1 ST0CNT SHRTIMER_ST0CNT update by DMA mode 3 1 ST0DMAINTEN SHRTIMER_ST0DMAINTEN update by DMA mode 2 1 ST0INTC SHRTIMER_ST0INTC update by DMA mode 1 1 ST0CTL0 SHRTIMER_ST0CTL0 update by DMA mode 0 1 DMAUPST1R DMAUPST1R SHRTIMER DMA update Slave_TIMER1 register 0x60 0x20 read-write 0x00000000 ST1ACTL SHRTIMER_ST1ACTL update by DMA mode 31 1 ST1FLTCTL SHRTIMER_ST1FLTCTL update by DMA mode 20 1 ST1CHOCTL SHRTIMER_ST1CHOCTL update by DMA mode 19 1 ST1CSCTL SHRTIMER_ST1CSCTL update by DMA mode 18 1 ST1CNTRST SHRTIMER_ST1CNTRST update by DMA mode 17 1 ST1EXEVFCFG1 SHRTIMER_ST1EXEVFCFG1update by DMA mode 16 1 ST1EXEVFCFG0 SHRTIMER_ST1EXEVFCFG0update by DMA mode 15 1 ST1CH1RST SHRTIMER_ST1CH1RST update by DMA mode 14 1 ST1CH1SET SHRTIMER_ST1CH1SET update by DMA mode 13 1 ST1CH0RST SHRTIMER_ST1CH0RST update by DMA mode 12 1 ST1CH0SET SHRTIMER_ST1CH0SET update by DMA mode 11 1 ST1DTCTL SHRTIMER_ST1DTCTL update by DMA mode 10 1 ST1CMP3V SHRTIMER_ST1CMP3V update by DMA mode 9 1 ST1CMP2V SHRTIMER_ST1CMP2V update by DMA mode 8 1 ST1CMP1V SHRTIMER_ST1CMP1V update by DMA mode 7 1 ST1CMP0V SHRTIMER_ST1CMP0V update by DMA mode 6 1 ST1CREP SHRTIMER_ST1CREP update by DMA mode 5 1 ST1CAR SHRTIMER_ST1CAR update by DMA mode 4 1 ST1CNT SHRTIMER_ST1CNT update by DMA mode 3 1 ST1DMAINTEN SHRTIMER_ST1DMAINTEN update by DMA mode 2 1 ST1INTC SHRTIMER_ST1INTC update by DMA mode 1 1 ST1CTL0 SHRTIMER_ST1CTL0 update by DMA mode 0 1 DMAUPST2R DMAUPST2R SHRTIMER DMA update Slave_TIMER2 register 0x64 0x20 read-write 0x00000000 ST2ACTL SHRTIMER_ST2ACTL update by DMA mode 31 1 ST2FLTCTL SHRTIMER_ST2FLTCTL update by DMA mode 20 1 ST2CHOCTL SHRTIMER_ST2CHOCTL update by DMA mode 19 1 ST2CSCTL SHRTIMER_ST2CSCTL update by DMA mode 18 1 ST2CNTRST SHRTIMER_ST2CNTRST update by DMA mode 17 1 ST2EXEVFCFG1 SHRTIMER_ST2EXEVFCFG1update by DMA mode 16 1 ST2EXEVFCFG0 SHRTIMER_ST2EXEVFCFG0update by DMA mode 15 1 ST2CH1RST SHRTIMER_ST2CH1RST update by DMA mode 14 1 ST2CH1SET SHRTIMER_ST2CH1SET update by DMA mode 13 1 ST2CH0RST SHRTIMER_ST2CH0RST update by DMA mode 12 1 ST2CH0SET SHRTIMER_ST2CH0SET update by DMA mode 11 1 ST2DTCTL SHRTIMER_ST2DTCTL update by DMA mode 10 1 ST2CMP3V SHRTIMER_ST2CMP3V update by DMA mode 9 1 ST2CMP2V SHRTIMER_ST2CMP2V update by DMA mode 8 1 ST2CMP1V SHRTIMER_ST2CMP1V update by DMA mode 7 1 ST2CMP0V SHRTIMER_ST2CMP0V update by DMA mode 6 1 ST2CREP SHRTIMER_ST2CREP update by DMA mode 5 1 ST2CAR SHRTIMER_ST2CAR update by DMA mode 4 1 ST2CNT SHRTIMER_ST2CNT update by DMA mode 3 1 ST2DMAINTEN SHRTIMER_ST2DMAINTEN update by DMA mode 2 1 ST2INTC SHRTIMER_ST2INTC update by DMA mode 1 1 ST2CTL0 SHRTIMER_ST2CTL0 update by DMA mode 0 1 DMAUPST3R DMAUPST3R SHRTIMER DMA update Slave_TIMER3 register 0x68 0x20 read-write 0x00000000 ST3ACTL SHRTIMER_ST3ACTL update by DMA mode 31 1 ST3FLTCTL SHRTIMER_ST3FLTCTL update by DMA mode 20 1 ST3CHOCTL SHRTIMER_ST3CHOCTL update by DMA mode 19 1 ST3CSCTL SHRTIMER_ST3CSCTL update by DMA mode 18 1 ST3CNTRST SHRTIMER_ST3CNTRST update by DMA mode 17 1 ST3EXEVFCFG1 SHRTIMER_ST3EXEVFCFG1update by DMA mode 16 1 ST3EXEVFCFG0 SHRTIMER_ST3EXEVFCFG0update by DMA mode 15 1 ST3CH1RST SHRTIMER_ST3CH1RST update by DMA mode 14 1 ST3CH1SET SHRTIMER_ST3CH1SET update by DMA mode 13 1 ST3CH0RST SHRTIMER_ST3CH0RST update by DMA mode 12 1 ST3CH0SET SHRTIMER_ST3CH0SET update by DMA mode 11 1 ST3DTCTL SHRTIMER_ST3DTCTL update by DMA mode 10 1 ST3CMP3V SHRTIMER_ST3CMP3V update by DMA mode 9 1 ST3CMP2V SHRTIMER_ST3CMP2V update by DMA mode 8 1 ST3CMP1V SHRTIMER_ST3CMP1V update by DMA mode 7 1 ST3CMP0V SHRTIMER_ST3CMP0V update by DMA mode 6 1 ST3CREP SHRTIMER_ST3CREP update by DMA mode 5 1 ST3CAR SHRTIMER_ST3CAR update by DMA mode 4 1 ST3CNT SHRTIMER_ST3CNT update by DMA mode 3 1 ST3DMAINTEN SHRTIMER_ST3DMAINTEN update by DMA mode 2 1 ST3INTC SHRTIMER_ST3INTC update by DMA mode 1 1 ST3CTL0 SHRTIMER_ST3CTL0 update by DMA mode 0 1 DMAUPST4R DMAUPST4R SHRTIMER DMA update Slave_TIMER4 register 0x6C 0x20 read-write 0x00000000 ST4ACTL SHRTIMER_ST4ACTL update by DMA mode 31 1 ST4FLTCTL SHRTIMER_ST4FLTCTL update by DMA mode 20 1 ST4CHOCTL SHRTIMER_ST4CHOCTL update by DMA mode 19 1 ST4CSCTL SHRTIMER_ST4CSCTL update by DMA mode 18 1 ST4CNTRST SHRTIMER_ST4CNTRST update by DMA mode 17 1 ST4EXEVFCFG1 SHRTIMER_ST4EXEVFCFG1update by DMA mode 16 1 ST4EXEVFCFG0 SHRTIMER_ST4EXEVFCFG0update by DMA mode 15 1 ST4CH1RST SHRTIMER_ST4CH1RST update by DMA mode 14 1 ST4CH1SET SHRTIMER_ST4CH1SET update by DMA mode 13 1 ST4CH0RST SHRTIMER_ST4CH0RST update by DMA mode 12 1 ST4CH0SET SHRTIMER_ST4CH0SET update by DMA mode 11 1 ST4DTCTL SHRTIMER_ST4DTCTL update by DMA mode 10 1 ST4CMP3V SHRTIMER_ST4CMP3V update by DMA mode 9 1 ST4CMP2V SHRTIMER_ST4CMP2V update by DMA mode 8 1 ST4CMP1V SHRTIMER_ST4CMP1V update by DMA mode 7 1 ST4CMP0V SHRTIMER_ST4CMP0V update by DMA mode 6 1 ST4CREP SHRTIMER_ST4CREP update by DMA mode 5 1 ST4CAR SHRTIMER_ST4CAR update by DMA mode 4 1 ST4CNT SHRTIMER_ST4CNT update by DMA mode 3 1 ST4DMAINTEN SHRTIMER_ST4DMAINTEN update by DMA mode 2 1 ST4INTC SHRTIMER_ST4INTC update by DMA mode 1 1 ST4CTL0 SHRTIMER_ST4CTL0 update by DMA mode 0 1 DMATB DMATB SHRTIMER DMA transfer buffer register 0x70 0x20 write-only 0x00000000 DMATB DMA transfer buffer 0 32 I2C0 Inter integrated circuit I2C 0x40005400 0x0 0x400 registers I2C0_EV 31 I2C0_ER 32 CTL0 CTL0 Control register 0 0x0 0x20 read-write 0x00000000 SRESET Software reset 15 1 SALT SMBus alert 13 1 PECTRANS PEC Transfer 12 1 POAP Position of ACK and PEC when receiving 11 1 ACKEN Whether or not to send an ACK 10 1 STOP Generate a STOP condition on I2C bus 9 1 START Generate a START condition on I2C bus 8 1 SS Whether to stretch SCL low when data is not ready in slave mode 7 1 GCEN Whether or not to response to a General Call (0x00) 6 1 PECEN PEC Calculation Switch 5 1 ARPEN ARP protocol in SMBus switch 4 1 SMBSEL SMBusType Selection 3 1 SMBEN SMBus/I2C mode switch 1 1 I2CEN I2C peripheral enable 0 1 CTL1 CTL1 Control register 1 0x04 0x20 read-write 0x00000000 DMALST Flag indicating DMA last transfer 12 1 DMAON DMA mode switch 11 1 BUFIE Buffer interrupt enable 10 1 EVIE Event interrupt enable 9 1 ERRIE Error interrupt enable 8 1 I2CCLK I2C Peripheral clock frequency 0 7 SADDR0 SADDR0 Slave address register 0 0x08 0x20 read-write 0x00000000 ADDFORMAT Address mode for the I2C slave 15 1 ADDRESS9_8 Highest two bits of a 10-bit address 8 2 ADDRESS7_1 7-bit address or bits 7:1 of a 10-bit address 1 7 ADDRESS0 Bit 0 of a 10-bit address 0 1 SADDR1 SADDR1 Slave address register 1 0x0C 0x20 read-write 0x00000000 ADDRESS2 Second I2C address for the slave in Dual-Address mode 1 7 DUADEN Dual-Address mode switch 0 1 DATA DATA Transfer buffer register 0x10 0x20 read-write 0x00000000 TRB Transmission or reception data buffer register 0 8 STAT0 STAT0 Transfer status register 0 0x14 0x20 0x00000000 SMBALT SMBus Alert status 15 1 read-write SMBTO Timeout signal in SMBus mode 14 1 read-write PECERR PEC error when receiving data 12 1 read-write OUERR Over-run or under-run situation occurs in slave mode 11 1 read-write AERR Acknowledge error 10 1 read-write LOSTARB Arbitration Lost in master mode 9 1 read-write BERR A bus error occurs indication a unexpected START or STOP condition on I2C bus 8 1 read-write TBE I2C_DATA is Empty during transmitting 7 1 read-only RBNE I2C_DATA is not Empty during receiving 6 1 read-only STPDET STOP condition detected in slave mode 4 1 read-only ADD10SEND Header of 10-bit address is sent in master mode 3 1 read-only BTC Byte transmission completed 2 1 read-only ADDSEND Address is sent in master mode or received and matches in slave mode 1 1 read-only SBSEND START condition sent out in master mode 0 1 read-only STAT1 STAT1 Transfer status register 1 0x18 0x20 read-only 0x00000000 PECV Packet Error Checking Value that calculated by hardware when PEC is enabled 8 8 DUMODF Dual Flag in slave mode 7 1 HSTSMB SMBus Host Header detected in slave mode 6 1 DEFSMB Default address of SMBusDevice 5 1 RXGC General call address (00h) received 4 1 TR Whether the I2C is a transmitter or a receiver 2 1 I2CBSY Busy flag 1 1 MASTER A flag indicating whether I2C block is in master or slave mode 0 1 CKCFG CKCFG Clock configure register 0x1C 0x20 read-write 0x00000000 FAST I2C speed selection in master mode 15 1 DTCY Duty cycle in fast mode 14 1 CLKC I2C Clock control in master mode 0 12 RT RT Rise time register 0x20 0x20 read-write 0x00000002 RISETIME Maximum rise time in master mode 0 7 SAMCS SAMCS SAM control and status register 0x80 0x20 read-write 0x00000000 RFR Rxframe rise flag 15 1 RFF Rxframe fall flag 14 1 TFR Txframe rise flag 13 1 TFF Txframe fall flag 12 1 RXF level of rx frame signal 9 1 TXF level of tx frame signal 8 1 RFRIE Rx frame rise interrupt enable 7 1 RFFIE Rx frame fall interrupt enable 6 1 TFRIE Tx frame rise interrupt enable 5 1 TFFIE Tx frame fall interrupt enable 4 1 STOEN SAM_V interface timeout detect enable 1 1 SAMEN SAM_V interface enable 0 1 CTL2 CTL2 Control register 2 0x90 0x20 read-write 0x0000FE00 ADDM ingnore specify bits 9 7 RADD slave address recorde enable 8 1 TOEN Timeout calculation enable 4 1 SETM Start Early Termination Mode 1 1 FMPEN Fast mode plus enable 0 1 CS CS Control and status register 0x94 0x20 read-write 0x00000000 STPSENDIE Interrupt enable for stop condition sent 9 1 STLOIE Interrupt enable for start lost 8 1 STPSEND Stop condition sent out in master mode 1 1 STLO Start lost flag 0 1 STATC STATC Status clear register 0x98 0x20 read-write 0x0000 SRCEN Status register clear enable 15 1 STOPFC STOPF status clear 4 1 ADD10SENDC ADD10SEND status clear 3 1 BTCC BTC status clear 2 1 ADDSENDC ADDSEND status clear 1 1 SBSENDC Start send status clear 0 1 I2C1 Inter integrated circuit I2C 0x40005800 0x0 0x400 registers I2C1_EV 33 I2C1_ER 34 CTL0 CTL0 Control register 0 0x0 0x20 read-write 0x00000000 SRESET Software reset 15 1 SALT SMBus alert 13 1 PECTRANS PEC Transfer 12 1 POAP Position of ACK and PEC when receiving 11 1 ACKEN Whether or not to send an ACK 10 1 STOP Generate a STOP condition on I2C bus 9 1 START Generate a START condition on I2C bus 8 1 SS Whether to stretch SCL low when data is not ready in slave mode 7 1 GCEN Whether or not to response to a General Call (0x00) 6 1 PECEN PEC Calculation Switch 5 1 ARPEN ARP protocol in SMBus switch 4 1 SMBSEL SMBusType Selection 3 1 SMBEN SMBus/I2C mode switch 1 1 I2CEN I2C peripheral enable 0 1 CTL1 CTL1 Control register 1 0x04 0x20 read-write 0x00000000 DMALST Flag indicating DMA last transfer 12 1 DMAON DMA mode switch 11 1 BUFIE Buffer interrupt enable 10 1 EVIE Event interrupt enable 9 1 ERRIE Error interrupt enable 8 1 I2CCLK I2C Peripheral clock frequency 0 7 SADDR0 SADDR0 Slave address register 0 0x08 0x20 read-write 0x00000000 ADDFORMAT Address mode for the I2C slave 15 1 ADDRESS9_8 Highest two bits of a 10-bit address 8 2 ADDRESS7_1 7-bit address or bits 7:1 of a 10-bit address 1 7 ADDRESS0 Bit 0 of a 10-bit address 0 1 SADDR1 SADDR1 Slave address register 1 0x0C 0x20 read-write 0x00000000 ADDRESS2 Second I2C address for the slave in Dual-Address mode 1 7 DUADEN Dual-Address mode switch 0 1 DATA DATA Transfer buffer register 0x10 0x20 read-write 0x00000000 TRB Transmission or reception data buffer register 0 8 STAT0 STAT0 Transfer status register 0 0x14 0x20 0x00000000 SMBALT SMBus Alert status 15 1 read-write SMBTO Timeout signal in SMBus mode 14 1 read-write PECERR PEC error when receiving data 12 1 read-write OUERR Over-run or under-run situation occurs in slave mode 11 1 read-write AERR Acknowledge error 10 1 read-write LOSTARB Arbitration Lost in master mode 9 1 read-write BERR A bus error occurs indication a unexpected START or STOP condition on I2C bus 8 1 read-write TBE I2C_DATA is Empty during transmitting 7 1 read-only RBNE I2C_DATA is not Empty during receiving 6 1 read-only STPDET STOP condition detected in slave mode 4 1 read-only ADD10SEND Header of 10-bit address is sent in master mode 3 1 read-only BTC Byte transmission completed 2 1 read-only ADDSEND Address is sent in master mode or received and matches in slave mode 1 1 read-only SBSEND START condition sent out in master mode 0 1 read-only STAT1 STAT1 Transfer status register 1 0x18 0x20 read-only 0x00000000 PECV Packet Error Checking Value that calculated by hardware when PEC is enabled 8 8 DUMODF Dual Flag in slave mode 7 1 HSTSMB SMBus Host Header detected in slave mode 6 1 DEFSMB Default address of SMBusDevice 5 1 RXGC General call address (00h) received 4 1 TR Whether the I2C is a transmitter or a receiver 2 1 I2CBSY Busy flag 1 1 MASTER A flag indicating whether I2C block is in master or slave mode 0 1 CKCFG CKCFG Clock configure register 0x1C 0x20 read-write 0x00000000 FAST I2C speed selection in master mode 15 1 DTCY Duty cycle in fast mode 14 1 CLKC I2C Clock control in master mode 0 12 RT RT Rise time register 0x20 0x20 read-write 0x00000002 RISETIME Maximum rise time in master mode 0 7 SAMCS SAMCS SAM control and status register 0x80 0x20 read-write 0x00000000 RFR Rxframe rise flag 15 1 RFF Rxframe fall flag 14 1 TFR Txframe rise flag 13 1 TFF Txframe fall flag 12 1 RXF level of rx frame signal 9 1 TXF level of tx frame signal 8 1 RFRIE Rx frame rise interrupt enable 7 1 RFFIE Rx frame fall interrupt enable 6 1 TFRIE Tx frame rise interrupt enable 5 1 TFFIE Tx frame fall interrupt enable 4 1 STOEN SAM_V interface timeout detect enable 1 1 SAMEN SAM_V interface enable 0 1 CTL2 CTL2 Control register 2 0x90 0x20 read-write 0x0000FE00 ADDM ingnore specify bits 9 7 RADD slave address recorde enable 8 1 TOEN Timeout calculation enable 4 1 SETM Start Early Termination Mode 1 1 FMPEN Fast mode plus enable 0 1 CS CS Control and status register 0x94 0x20 read-write 0x00000000 STPSENDIE Interrupt enable for stop condition sent 9 1 STLOIE Interrupt enable for start lost 8 1 STPSEND Stop condition sent out in master mode 1 1 STLO Start lost flag 0 1 STATC STATC Status clear register 0x98 0x20 read-write 0x0000 SRCEN Status register clear enable 15 1 STOPFC STOPF status clear 4 1 ADD10SENDC ADD10SEND status clear 3 1 BTCC BTC status clear 2 1 ADDSENDC ADDSEND status clear 1 1 SBSENDC Start send status clear 0 1 I2C2 Inter integrated circuit I2C 0x4000C000 0x0 0x400 registers I2C2_EV 82 I2C2_ER 83 CTL0 CTL0 Control register 0 0x0 0x20 read-write 0x00000000 PECEN PEC Calculation Switch 23 1 SMBALTEN SMBus Alert enable 22 1 SMBDAEN SMBus device default address enable 21 1 SMBHAEN SMBus Host address enable 20 1 GCEN Whether or not to response to a General Call 19 1 WUEN Wakeup from Deep-sleep mode enable 18 1 SS Whether to stretch SCL low when data is not ready in slave mode 17 1 SBCTL Slave byte control 16 1 DENR DMA enable for reception 15 1 DENT DMA enable for transmission 14 1 ANOFF Analog noise filter disable 12 1 DNF Digital noise filter 8 4 ERRIE Error interrupt enable 7 1 TCIE Transfer complete interrupt enable 6 1 STPDETIE Stop detection interrupt enable 5 1 NACKIE Not acknowledge received interrupt enable 4 1 ADDMIE Address match interrupt enable in slave mode 3 1 RBNEIE Receive interrupt enable 2 1 TIE Receive interrupt enable 1 1 I2CEN I2C peripheral enable 0 1 CTL1 CTL1 Control register 1 0x04 0x20 read-write 0x00000000 PECTRANS PEC Transfer 26 1 AUTOEND Automatic end mode in master mode 25 1 RELOAD Reload mode 24 1 BYTENUM Number of bytes to be transferred 16 8 NACKEN Generate NACK in slave mode 15 1 STOP Generate a STOP condition on I2C bus 14 1 START Generate a START condition on I2C bus 13 1 HEAD10R 10-bit address header executes read direction only in master receive mode 12 1 ADD10EN 10-bit addressing mode enable in master mode 11 1 TRDIR Transfer direction in master mode 10 1 SADDRESS Slave address to be sent 0 10 SADDR0 SADDR0 Slave address register 0 0x08 0x20 read-write 0x00000000 ADDRESSEN I2C address enable 15 1 ADDFORMAT Address mode for the I2C slave 10 1 ADDRESS_8_9 7-bit address or bits 7:1 of a 10-bit address 8 2 ADDRESS_1_7 Highest two bits of a 10-bit address 1 7 ADDRESS_0 Bit 0 of a 10-bit address 0 1 SADDR1 SADDR1 Slave address register 1 0x0C 0x20 read-write 0x00000000 ADDRESS2EN Second I2C address enable 15 1 ADDMSK2 ADDRESS2[7:1] mask 8 3 ADDRESS2 Second I2C address for the slave 1 7 TIMING TIMING Timing register 0x10 0x20 read-write 0x00000000 PSC Timing prescaler 28 4 SCLDELY Data setup time 20 4 SDADELY Data hold time 16 4 SCLH SCL high period 8 8 SCLL SCL low period 0 8 TIMEOUT TIMEOUT timeout register 0x14 0x20 0x00000000 EXTOEN Extended clock timeout detection enable 31 1 read-write BUSTOB Bus timeout B 16 12 read-write TOEN Clock timeout detection enable 15 1 read-write TOIDLE Idle clock timeout detection 12 1 read-write BUSTOA Bus timeout A 0 12 read-write STAT STAT Transfer status register 0x18 0x20 0x00000001 READDR Received match address in slave mode 17 7 read-only TR Whether the I2C is a transmitter or a receiver in slave mode 16 1 read-only I2CBSY Busy flag 15 1 read-only SMBALT SMBus Alert 13 1 read-only TIMEOUT TIMEOUT flag 12 1 read-only PECERR PEC error 11 1 read-only OUERR Overrun/Underrun error in slave mode 10 1 read-only LOSTARB Arbitration Lost 9 1 read-only BERR Bus error 8 1 read-only TCR Transfer complete reload 7 1 read-only TC Transfer complete in master mode 6 1 read-only STPDET STOP condition is detected on the bus 5 1 read-only NACK Not Acknowledge flag 4 1 read-only ADDSEND Address received matches in slave mode 3 1 read-only RBNE I2C_RDATA is not empty during receiving 2 1 read-only TI Transmit interrupt 1 1 read-write TBE I2C_TDATA is empty during transmitting 0 1 read-write STATC STATC Status clear register 0x1C 0x20 write-only 0x00000000 SMBALTC SMBus Alert flag clear 13 1 TIMEOUTC TIMEOUT flag clear 12 1 PECERRC PEC error flag clear 11 1 OUERRC Overrun/Underrun flag clear 10 1 LOSTARBC Arbitration Lost flag clear 9 1 BERRC Bus error flag clear 8 1 STPDETC STPDET flag clear 5 1 NACKC Not Acknowledge flag clear 4 1 ADDSENDC ADDSEND flag clear 3 1 PEC PEC Packet Error Checking 0x20 0x20 read-only 0x00000000 PECV Packet Error Checking Value 0 8 RDATA RDATA receive data register 0x24 0x20 read-only 0x00000000 RDATA Receive data value 0 8 TDATA TDATA Transmit data register 0x28 0x20 read-write 0x00000000 TDATA Transmit data value 0 8 NVIC Nested Vectored Interrupt Controller NVIC 0xE000E100 0x0 0xF00 registers 0x33D 0xC3 reserved ISER ISER Interrupt Set Enable Register 0x0 0x20 read-write 0x00000000 SETENA SETENA 0 32 ICER ICER Interrupt Clear Enable Register 0x80 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ISPR ISPR Interrupt Set-Pending Register 0x100 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ICPR ICPR Interrupt Clear-Pending Register 0x180 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 IABR IABR Interrupt Active bit Register 0x200 0x20 read-write 0x00000000 IABR IABR 0 32 IPR0 IPR0 Interrupt Priority Register 0 0x300 0x08 read-write 0x00 PRI_00 PRI_00 0 8 IPR1 IPR1 Interrupt Priority Register 1 0x301 0x08 read-write 0x00 PRI_01 PRI_01 0 8 IPR2 IPR2 Interrupt Priority Register 2 0x302 0x08 read-write 0x00 PRI_02 PRI_02 0 8 IPR3 IPR3 Interrupt Priority Register 3 0x303 0x08 read-write 0x00 PRI_03 PRI_03 0 8 IPR4 IPR4 Interrupt Priority Register 4 0x304 0x08 read-write 0x00 PRI_04 PRI_04 0 8 IPR5 IPR5 Interrupt Priority Register 5 0x305 0x08 read-write 0x00 PRI_05 PRI_05 0 8 IPR6 IPR6 Interrupt Priority Register 6 0x306 0x08 read-write 0x00 PRI_06 PRI_06 0 8 IPR7 IPR7 Interrupt Priority Register 7 0x307 0x08 read-write 0x00 PRI_07 PRI_07 0 8 IPR8 IPR8 Interrupt Priority Register 8 0x308 0x08 read-write 0x00 PRI_08 PRI_08 0 8 IPR9 IPR9 Interrupt Priority Register 9 0x309 0x08 read-write 0x00 PRI_09 PRI_09 0 8 IPR10 IPR10 Interrupt Priority Register 10 0x30A 0x08 read-write 0x00 PRI_10 PRI_10 0 8 IPR11 IPR11 Interrupt Priority Register 11 0x30B 0x08 read-write 0x00 PRI_11 PRI_11 0 8 IPR12 IPR12 Interrupt Priority Register 12 0x30C 0x08 read-write 0x00 PRI_12 PRI_12 0 8 IPR13 IPR13 Interrupt Priority Register 13 0x30D 0x08 read-write 0x00 PRI_13 PRI_13 0 8 IPR14 IPR14 Interrupt Priority Register 14 0x30E 0x08 read-write 0x00 PRI_14 PRI_14 0 8 IPR15 IPR15 Interrupt Priority Register 15 0x30F 0x08 read-write 0x00 PRI_15 PRI_15 0 8 IPR16 IPR16 Interrupt Priority Register 16 0x310 0x08 read-write 0x00 PRI_16 PRI_16 0 8 IPR17 IPR17 Interrupt Priority Register 17 0x311 0x08 read-write 0x00 PRI_17 PRI_17 0 8 IPR18 IPR18 Interrupt Priority Register 18 0x312 0x08 read-write 0x00 PRI_18 PRI_18 0 8 IPR19 IPR19 Interrupt Priority Register 19 0x313 0x08 read-write 0x00 PRI_19 PRI_19 0 8 IPR20 IPR20 Interrupt Priority Register 20 0x314 0x08 read-write 0x00 PRI_20 PRI_20 0 8 IPR21 IPR21 Interrupt Priority Register 21 0x315 0x08 read-write 0x00 PRI_21 PRI_21 0 8 IPR22 IPR22 Interrupt Priority Register 22 0x316 0x08 read-write 0x00 PRI_22 PRI_22 0 8 IPR23 IPR23 Interrupt Priority Register 23 0x317 0x08 read-write 0x00 PRI_23 PRI_23 0 8 IPR24 IPR24 Interrupt Priority Register 24 0x318 0x08 read-write 0x00 PRI_24 PRI_24 0 8 IPR25 IPR25 Interrupt Priority Register 25 0x319 0x08 read-write 0x00 PRI_25 PRI_25 0 8 IPR26 IPR26 Interrupt Priority Register 26 0x31A 0x08 read-write 0x00 PRI_26 PRI_26 0 8 IPR27 IPR27 Interrupt Priority Register 27 0x31B 0x08 read-write 0x00 PRI_27 PRI_27 0 8 IPR28 IPR28 Interrupt Priority Register 28 0x31C 0x08 read-write 0x00 PRI_28 PRI_28 0 8 IPR29 IPR29 Interrupt Priority Register 29 0x31D 0x08 read-write 0x00 PRI_29 PRI_29 0 8 IPR30 IPR30 Interrupt Priority Register 30 0x31E 0x08 read-write 0x00 PRI_30 PRI_30 0 8 IPR31 IPR31 Interrupt Priority Register 31 0x31F 0x08 read-write 0x00 PRI_31 PRI_31 0 8 IPR32 IPR32 Interrupt Priority Register 32 0x320 0x08 read-write 0x00 PRI_32 PRI_32 0 8 IPR33 IPR33 Interrupt Priority Register 33 0x321 0x08 read-write 0x00 PRI_33 PRI_33 0 8 IPR34 IPR34 Interrupt Priority Register 34 0x322 0x08 read-write 0x00 PRI_34 PRI_34 0 8 IPR35 IPR35 Interrupt Priority Register 35 0x323 0x08 read-write 0x00 PRI_35 PRI_35 0 8 IPR36 IPR36 Interrupt Priority Register 36 0x324 0x08 read-write 0x00 PRI_36 PRI_36 0 8 IPR37 IPR37 Interrupt Priority Register 37 0x325 0x08 read-write 0x00 PRI_37 PRI_37 0 8 IPR38 IPR38 Interrupt Priority Register 38 0x326 0x08 read-write 0x00 PRI_38 PRI_38 0 8 IPR39 IPR39 Interrupt Priority Register 39 0x327 0x08 read-write 0x00 PRI_39 PRI_39 0 8 IPR40 IPR40 Interrupt Priority Register 40 0x328 0x08 read-write 0x00 PRI_40 PRI_40 0 8 IPR41 IPR41 Interrupt Priority Register 41 0x329 0x08 read-write 0x00 PRI_41 PRI_41 0 8 IPR42 IPR42 Interrupt Priority Register 42 0x32A 0x08 read-write 0x00 PRI_42 PRI_42 0 8 IPR43 IPR43 Interrupt Priority Register 43 0x32B 0x08 read-write 0x00 PRI_43 PRI_43 0 8 IPR44 IPR44 Interrupt Priority Register 44 0x32C 0x08 read-write 0x00 PRI_44 PRI_44 0 8 IPR45 IPR45 Interrupt Priority Register 45 0x32D 0x08 read-write 0x00 PRI_45 PRI_45 0 8 IPR46 IPR46 Interrupt Priority Register 46 0x32E 0x08 read-write 0x00 PRI_46 PRI_46 0 8 IPR47 IPR47 Interrupt Priority Register 47 0x32F 0x08 read-write 0x00 PRI_47 PRI_47 0 8 IPR48 IPR48 Interrupt Priority Register 48 0x330 0x08 read-write 0x00 PRI_48 PRI_48 0 8 IPR49 IPR49 Interrupt Priority Register 49 0x331 0x08 read-write 0x00 PRI_49 PRI_49 0 8 IPR50 IPR50 Interrupt Priority Register 50 0x332 0x08 read-write 0x00 PRI_50 PRI_50 0 8 IPR51 IPR51 Interrupt Priority Register 51 0x333 0x08 read-write 0x00 PRI_51 PRI_51 0 8 IPR52 IPR52 Interrupt Priority Register 52 0x334 0x08 read-write 0x00 PRI_52 PRI_52 0 8 IPR53 IPR53 Interrupt Priority Register 53 0x335 0x08 read-write 0x00 PRI_53 PRI_53 0 8 IPR54 IPR54 Interrupt Priority Register 54 0x336 0x08 read-write 0x00 PRI_54 PRI_54 0 8 IPR55 IPR55 Interrupt Priority Register 55 0x337 0x08 read-write 0x00 PRI_55 PRI_55 0 8 IPR56 IPR56 Interrupt Priority Register 56 0x338 0x08 read-write 0x00 PRI_56 PRI_56 0 8 IPR57 IPR57 Interrupt Priority Register 57 0x339 0x08 read-write 0x00 PRI_57 PRI_57 0 8 IPR58 IPR58 Interrupt Priority Register 58 0x33A 0x08 read-write 0x00 PRI_58 PRI_58 0 8 IPR59 IPR59 Interrupt Priority Register 59 0x33B 0x08 read-write 0x00 PRI_59 PRI_59 0 8 IPR60 IPR60 Interrupt Priority Register 60 0x33C 0x08 read-write 0x00 PRI_60 PRI_60 0 8 IPR61 IPR61 Interrupt Priority Register 61 0x33D 0x08 read-write 0x00 PRI_61 PRI_61 0 8 IPR62 IPR62 Interrupt Priority Register 62 0x33E 0x08 read-write 0x00 PRI_62 PRI_62 0 8 IPR63 IPR63 Interrupt Priority Register 63 0x33F 0x08 read-write 0x00 PRI_63 PRI_63 0 8 IPR64 IPR64 Interrupt Priority Register 64 0x340 0x08 read-write 0x00 PRI_64 PRI_64 0 8 IPR65 IPR65 Interrupt Priority Register 65 0x341 0x08 read-write 0x00 PRI_65 PRI_65 0 8 IPR66 IPR66 Interrupt Priority Register 66 0x342 0x08 read-write 0x00 PRI_66 PRI_66 0 8 IPR67 IPR67 Interrupt Priority Register 67 0x343 0x08 read-write 0x00 PRI_67 PRI_67 0 8 STIR STIR Software Trigger Interrupt Register 0xE00 0x20 write-only 0x00000000 STIR STIR 0 32 PMU Power management unit PMU 0x40007000 0x0 0x400 registers CTL0 CTL0 power control register 0 0x00 0x20 read-write 0x0000C000 LDEN Low-driver mode enable in Deep-sleep mode 18 2 HDS High-driver mode switch 17 1 HDEN High-driver mode enable 16 1 LDNP Low-driver mode when use normal power LDO 11 1 LDLP Low-driver mode when use low power LDO. 10 1 BKPWEN Backup Domain Write Enable 8 1 LVDT Low Voltage Detector Threshold 5 3 LVDEN Low Voltage Detector Enable 4 1 STBRST Standby Flag Reset 3 1 WURST Wakeup Flag Reset 2 1 STBMOD Standby Mode 1 1 LDOLP LDO Low Power Mode 0 1 CS0 CS0 power control/status register 0 0x04 0x20 0x00000000 LDRF Low-driver mode ready flag 18 2 read-write HDSRF High-driver switch ready flag 17 1 read-only HDRF High-driver ready flag 16 1 read-only WUPEN7 Enable WKUP Pin7(PF8) 15 1 read-write WUPEN5 Enable WKUP pin5 13 1 read-write WUPEN4 Enable WKUP pin4 12 1 read-write WUPEN3 Enable WKUP pin3 11 1 read-write WUPEN2 Enable WKUP pin2 10 1 read-write WUPEN1 Enable WKUP pin1 9 1 read-write WUPEN0 Enable WKUP pin0 8 1 read-write WUPEN6 Enable WKUP pin6 7 1 read-write LVDF Low Voltage Detector Status Flag 2 1 read-only STBF Standby flag 1 1 read-only WUF Wakeup flag 0 1 read-only CTL1 CTL1 power control register 1 0x08 0x20 read-write 0x00000000 DPMOD2 Enable deep-sleep 2 mode 1 1 DPMOD1 Enable deep-sleep 1 mode 0 1 CS1 CS1 power control and status register 1 0x0C 0x20 read-write 0x00000000 DPF2 Deep-sleep 2 mode status flag 1 1 DPF1 Deep-sleep1 mode status flag 0 1 RCU Reset and clock unit RCU 0x40021000 0x0 0x400 registers RCU_CTC 5 CTL CTL Control register 0x0 0x20 0x00000083 IRC8MEN Internal 8MHz RC oscillator Enable 0 1 read-write IRC8MSTB IRC8M Internal 8MHz RC Oscillator stabilization Flag 1 1 read-only IRC8MADJ Internal 8MHz RC Oscillator clock trim adjust value 3 5 read-write IRC8MCALIB Internal 8MHz RC Oscillator calibration value register 8 8 read-only HXTALEN External High Speed oscillator Enable 16 1 read-write HXTALSTB External crystal oscillator (HXTAL) clock stabilization flag 17 1 read-only HXTALBPS External crystal oscillator (HXTAL) clock bypass mode enable 18 1 read-write CKMEN HXTAL Clock Monitor Enable 19 1 read-write PLLEN PLL enable 24 1 read-write PLLSTB PLL Clock Stabilization Flag 25 1 read-only PLL1EN PLL1 enable 26 1 read-write PLL1STB PLL1 Clock Stabilization Flag 27 1 read-only PLL2EN PLL2 enable 28 1 read-write PLL2STB PLL2 Clock Stabilization Flag 29 1 read-only CFG0 CFG0 Clock configuration register 0 (RCU_CFG0) 0x04 0x20 0x00000000 SCS System clock switch 0 2 read-write SCSS System clock switch status 2 2 read-only AHBPSC AHB prescaler selection 4 4 read-write APB1PSC APB1 prescaler selection 8 3 read-write APB2PSC APB2 prescaler selection 11 3 read-write ADCPSC_1_0 ADC clock prescaler selection 14 2 read-write PLLSEL PLL Clock Source Selection 16 1 read-write PREDV0_LSB The LSB of PREDV0 division factor 17 1 read-write PLLMF_3_0 The PLL clock multiplication factor 18 4 read-write USBHSPSC_1_0 USBHS clock prescaler selection 22 2 read-write CKOUT0SEL CKOUT0 Clock Source Selection 24 4 read-write ADCPSC_2 Bit 2 of ADCPSC 28 1 read-write PLLMF_5_4 Bit 5 and Bit 4 of PLLMF 29 2 read-write USBHSPSC Bit 2 of USBHSPSC 31 1 read-write INT INT Clock interrupt register (RCU_INT) 0x08 0x20 0x00000000 IRC40KSTBIF IRC40K stabilization interrupt flag 0 1 read-only LXTALSTBIF LXTAL stabilization interrupt flag 1 1 read-only IRC8MSTBIF IRC8M stabilization interrupt flag 2 1 read-only HXTALSTBIF HXTAL stabilization interrupt flag 3 1 read-only PLLSTBIF PLL stabilization interrupt flag 4 1 read-only PLL1STBIF PLL1 stabilization interrupt flag 5 1 read-only PLL2STBIF PLL2 stabilization interrupt flag 6 1 read-only CKMIF HXTAL Clock Stuck Interrupt Flag 7 1 read-only IRC40KSTBIE IRC40K Stabilization interrupt enable 8 1 read-write LXTALSTBIE LXTAL Stabilization Interrupt Enable 9 1 read-write IRC8MSTBIE IRC8M Stabilization Interrupt Enable 10 1 read-write HXTALSTBIE HXTAL Stabilization Interrupt Enable 11 1 read-write PLLSTBIE PLL Stabilization Interrupt Enable 12 1 read-write PLL1STBIE PLL1 Stabilization Interrupt Enable 13 1 read-write PLL2STBIE PLL2 Stabilization Interrupt Enable 14 1 read-write IRC40KSTBIC IRC40K Stabilization Interrupt Clear 16 1 write-only LXTALSTBIC LXTAL Stabilization Interrupt Clear 17 1 write-only IRC8MSTBIC IRC8M Stabilization Interrupt Clear 18 1 write-only HXTALSTBIC HXTAL Stabilization Interrupt Clear 19 1 write-only PLLSTBIC PLL stabilization Interrupt Clear 20 1 write-only PLL1STBIC PLL1 stabilization Interrupt Clear 21 1 write-only PLL2STBIC PLL2 stabilization Interrupt Clear 22 1 write-only CKMIC HXTAL Clock Stuck Interrupt Clear 23 1 write-only APB2RST APB2RST APB2 reset register (RCU_APB2RST) 0x0C 0x20 read-write 0x00000000 AFRST Alternate function I/O reset 0 1 PARST GPIO port A reset 2 1 PBRST GPIO port B reset 3 1 PCRST GPIO port C reset 4 1 PDRST GPIO port D reset 5 1 PERST GPIO port E reset 6 1 PFRST GPIO portF reset 7 1 PGRST GPIO port G reset 8 1 ADC0RST ADC0 reset 9 1 ADC1RST ADC1 reset 10 1 TIMER0RST Timer 0 reset 11 1 SPI0RST SPI0 reset 12 1 TIMER7RST Timer 7 reset 13 1 USART0RST USART0 Reset 14 1 ADC2RST ADC2 reset 15 1 TIMER8RST Timer 8 reset 19 1 TIMER9RST Timer 9 reset 20 1 TIMER10RST Timer 10 reset 21 1 USART5RST USART5 reset 28 1 SHRTIMERRST SHRTIMER reset 29 1 CMPRST CMP reset 31 1 APB1RST APB1RST APB1 reset register (RCU_APB1RST) 0x10 0x20 read-write 0x00000000 TIMER1RST TIMER1 timer reset 0 1 TIMER2RST TIMER2 timer reset 1 1 TIMER3RST TIMER3 timer reset 2 1 TIMER4RST TIMER4 timer reset 3 1 TIMER5RST TIMER5 timer reset 4 1 TIMER6RST TIMER6 timer reset 5 1 TIMER11RST TIMER11 timer reset 6 1 TIMER12RST TIMER12 timer reset 7 1 TIMER13RST TIMER13 timer reset 8 1 WWDGTRST Window watchdog timer reset 11 1 SPI1RST SPI1 reset 14 1 SPI2RST SPI2 reset 15 1 USART1RST USART1 reset 17 1 USART2RST USART2 reset 18 1 UART3RST UART3 reset 19 1 UART4RST UART4 reset 20 1 I2C0RST I2C0 reset 21 1 I2C1RST I2C1 reset 22 1 I2C2RST I2C2 reset 24 1 CAN0RST CAN0 reset 25 1 CAN1RST CAN1 reset 26 1 BKPIRST Backup interface reset 27 1 PMURST Power control reset 28 1 DACRST DAC reset 29 1 AHBEN AHBEN AHB enable register 0x14 0x20 read-write 0x00000014 DMA0EN DMA0 clock enable 0 1 DMA1EN DMA1 clock enable 1 1 SRAMSPEN SRAM interface clock enable when sleep mode 2 1 FMCSPEN FMC clock enable when sleep mode 4 1 CRCEN CRC clock enable 6 1 EXMCEN EXMC clock enable 8 1 USBHSEN USBFS clock enable 12 1 ULPIEN ULPI clock enable 13 1 ENETEN Ethernet clock enable 14 1 ENETTXEN Ethernet TX clock enable 15 1 ENETRXEN Ethernet RX clock enable 16 1 TMUEN TMU clock enable 30 1 SQPIEN SQPI clock enable 31 1 APB2EN APB2EN APB2 clock enable register (RCU_APB2EN) 0x18 0x20 read-write 0x00000000 AFEN Alternate function IO clock enable 0 1 PAEN GPIO port A clock enable 2 1 PBEN GPIO port B clock enable 3 1 PCEN GPIO port C clock enable 4 1 PDEN GPIO port D clock enable 5 1 PEEN GPIO port E clock enable 6 1 PFEN GPIO port F clock enable 7 1 PGEN GPIO port G clock enable 8 1 ADC0EN ADC0 clock enable 9 1 ADC1EN ADC1 clock enable 10 1 TIMER0EN TIMER0 clock enable 11 1 SPI0EN SPI0 clock enable 12 1 TIMER7EN TIMER7 clock enable 13 1 USART0EN USART0 clock enable 14 1 ADC2EN ADC2 clock enable 15 1 TIMER8EN TIMER8 clock enable 19 1 TIMER9EN TIMER9 clock enable 20 1 TIMER10EN TIMER10 clock enable 21 1 USART5EN USART5 clock enable 28 1 SHRTIMEREN SHRTIMER clock enable 29 1 CMPEN CMP clock enable 31 1 APB1EN APB1EN APB1 clock enable register (RCU_APB1EN) 0x1C 0x20 read-write 0x00000000 TIMER1EN TIMER1 timer clock enable 0 1 TIMER2EN TIMER2 timer clock enable 1 1 TIMER3EN TIMER3 timer clock enable 2 1 TIMER4EN TIMER4 timer clock enable 3 1 TIMER5EN TIMER5 timer clock enable 4 1 TIMER6EN TIMER6 timer clock enable 5 1 TIMER11EN TIMER11 timer clock enable 6 1 TIMER12EN TIMER12 timer clock enable 7 1 TIMER13EN TIMER13 timer clock enable 8 1 WWDGTEN Window watchdog timer clock enable 11 1 SPI1EN SPI1 clock enable 14 1 SPI2EN SPI2 clock enable 15 1 USART1EN USART1 clock enable 17 1 USART2EN USART2 clock enable 18 1 UART3EN UART3 clock enable 19 1 UART4EN UART4 clock enable 20 1 I2C0EN I2C0 clock enable 21 1 I2C1EN I2C1 clock enable 22 1 I2C2EN I2C2 clock enable 24 1 CAN0EN CAN0 clock enable 25 1 CAN1EN CAN1 clock enable 26 1 BKPIEN Backup interface clock enable 27 1 PMUEN Power control clock enable 28 1 DACEN DAC clock enable 29 1 BDCTL BDCTL Backup domain control register (RCU_BDCTL) 0x20 0x20 0x00000018 LXTALEN LXTAL enable 0 1 read-write LXTALSTB External low-speed oscillator stabilization 1 1 read-only LXTALBPS LXTAL bypass mode enable 2 1 read-write LXTALDRI LXTAL drive capability 3 2 read-write RTCSRC RTC clock entry selection 8 2 read-write RTCEN RTC clock enable 15 1 read-write BKPRST Backup domain reset 16 1 read-write RSTSCK RSTSCK Reset source /clock register (RCU_RSTSCK) 0x24 0x20 0x0C000000 IRC40KEN IRC40K enable 0 1 read-write IRC40KSTB IRC40K stabilization 1 1 read-only RSTFC Reset flag clear 24 1 read-write BORRSTF BORt flag clear 25 1 read-write EPRSTF External PIN reset flag 26 1 read-only PORRSTF Power reset flag 27 1 read-only SWRSTF Software reset flag 28 1 read-only FWDGTRSTF Free Watchdog timer reset flag 29 1 read-only WWDGTRSTF Window watchdog timer reset flag 30 1 read-only LPRSTF Low-power reset flag 31 1 read-only AHBRST AHBRST AHB reset register 0x28 0x20 read-write 0x00000000 USBHSRST USBHS reset 12 1 ENETRST ENET reset 14 1 TMURST TMU reset 30 1 SQPIRST SQPI reset 31 1 CFG1 CFG1 Clock Configuration register 1 0x2C 0x20 read-write 0x00000000 PREDV0 PREDV0 division factor 0 4 PREDV1 PREDV1 division factor 4 4 PLL1MF The PLL1 clock multiplication factor 8 4 PLL2MF The PLL2 clock multiplication factor 12 4 PREDV0SEL PREDV0 input Clock Source Selection 16 1 I2S1SEL I2S1 Clock Source Selection 17 1 I2S2SEL I2S2 Clock Source Selection 18 1 SHRTIMERSEL SHRTIMER Clock Source Selection 19 1 PLL2MF_5 Bit 5 of PLL2MF 28 1 ADCPSC_3 Bit 3 of ADCPSC 29 1 PLLPRESEL PLL Clock Source Selection 30 1 PLL2MF_4 Bit 4 of PLL2MF 31 1 DSV DSV Deep sleep mode Voltage register 0x34 0x20 0x00000000 DSLPVS Deep-sleep mode voltage select 0 3 read-write ADDCTL ADDCTL Additional clock control register 0xC0 0x20 0x80000000 CK48MSEL 48MHz clock selection 0 2 read-write USBHSSEL USBHS clock divider factor 2 1 read-write USBHSDV USBHS clock selection 3 3 read-write USBSWEN USB clock source selection enable 6 1 read-write PLLUSBEN PLLUSB enable 14 1 read-write PLLUSBSTB PLLUSB clock stabilization flag 15 1 read-write IRC48MEN Internal 48MHz RC oscillator enable 16 1 read-write IRC48MSTB Internal 48MHz RC oscillator clock stabilization Flag 17 1 read-only IRC48MCALIB Internal 48MHz RC oscillator calibration value register 24 8 read-only ADDCFG ADDCFG Additional clock configuration register 0xC4 0x20 read-write 0x00000000 PLLUSBPREDV PLLUSBPREDV division factor 0 4 PLLUSBPRESEL PLLUSB clock source preselection 16 1 PLLUSBPREDVSEL PLLUSBPREDV input Clock Source Selection 17 1 PLLUSBMF The PLLUSB clock multiplication factor 18 7 ADDINT ADDINT Additional clock interrupt register 0xCC 0x20 0x00000000 IRC48MSTBIF IRC48M stabilization interrupt flag 6 1 read-only PLLUSBSTBIF PLLUSB stabilization interrupt flag 7 1 read-only IRC48MSTBIE Internal 48 MHz RC oscillator Stabilization Interrupt Enable 14 1 read-write PLLUSBSTBIE PLLUSB stabilization interrupt enable 15 1 read-write IRC48MSTBIC Internal 48 MHz RC oscillator Stabilization Interrupt Clear 22 1 write-only PLLUSBSTBIC PLLUSB stabilization interrupt clear 23 1 write-only PLLSSCTL PLLSSCTL PLL clock spread spectrum control register 0xD0 0x20 read-write 0x00000000 MODCNT Configure PLL spread spectrum modulation profile amplitude and frequency 0 13 MODSTEP Configure PLL spread spectrum modulation profile amplitude and frequency 13 15 SS_TYPE PLL spread spectrum modulation type select 30 1 SSCGON PLL spread spectrum modulation enable 31 1 CFG2 CFG2 Clock configuration register 2 0xD4 0x20 read-write 0x00000000 USART5SEL USART5 Clock Source Selection 0 2 I2C2SEL I2C2 Clock Source Selection 4 2 ADDAPB1RST ADDAPB1RST APB1 additional reset register 0xE0 0x20 0x00000000 CTCRST CTC reset 27 1 read-write CAN2RST CAN2 reset 31 1 read-write ADDAPB1EN ADDAPB1EN APB1 additional enable register 0xE4 0x20 0x00000000 CTCEN CTC clock enable 27 1 read-write CAN2EN CNA2 clock enable 31 1 read-write RTC Real-time clock RTC 0x40002800 0x0 0x400 registers RTC 3 RTC_Alarm 41 INTEN INTEN RTC interrupt enable register 0x0 0x20 read-write 0x00000000 OVIE Overflow interrupt enable 2 1 ALRMIE Alarm interrupt enable 1 1 SCIE Second interrupt 0 1 CTL CTL control register 0x04 0x20 0x00000020 LWOFF Last write operation finished flag 5 1 read-only CMF Configuration mode flag 4 1 read-write RSYNF Registers synchronized flag 3 1 read-write OVIF Overflow interrupt flag 2 1 read-write ALRMIF Alarm interrupt flag 1 1 read-write SCIF Sencond interrupt flag 0 1 read-write PSCH PSCH RTC prescaler high register 0x08 0x20 0x00000000 PSC RTC prescaler value high 0 4 write-only PSCL PSCL RTC prescaler low register 0x0C 0x20 0x00008000 PSC RTC prescaler value low 0 16 write-only DIVH DIVH RTC divider high register 0x10 0x20 read-only 0x00000000 DIV RTC divider value high 0 4 DIVL DIVL RTC divider low register 0x14 0x20 read-only 0x00008000 DIV RTC divider value low 0 16 CNTH CNTH RTC counter high register 0x18 0x20 read-write 0x00000000 CNT RTC counter value high 0 16 CNTL CNTL RTC counter low register 0x1C 0x20 read-write 0x00000000 CNT RTC conuter value low 0 16 ALRMH ALRMH Alarm high register 0x20 0x20 write-only 0x0000FFFF ALRM Alarm value high 0 16 ALRML ALRML RTC alarm low register 0x24 0x20 write-only 0x0000FFFF ALRM alarm value low 0 16 SPI0 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI0 35 CTL0 CTL0 control register 0 0x0 0x20 read-write 0x00000000 BDEN Bidirectional enable 15 1 BDENread-writeUnidirectional2-line unidirectional data mode selected0Bidirectional1-line bidirectional data mode selected1 BDOEN Bidirectional Transmit output enable 14 1 BDOENread-writeReceiveOnlyReceive-only mode0TransmitOnlyTransmit-only mode1 CRCEN CRC Calculation Enable 13 1 CRCENread-writeDisabledCRC calculation disabled0EnabledCRC calculation enabled1 CRCNT CRC Next Transfer 12 1 CRCNTread-writeDataNext transmit value is data from Tx buffer0CRCNext transmit value is CRC value from TCRC1 FF16 Data frame format 11 1 FF16read-writeEightBit8-bit data frame format is selected for transmission/reception0SixteenBit16-bit data frame format is selected for transmission/reception1 RO Receive only 10 1 ROread-writeFullDuplexFull duplex (Transmit and receive)0ReceiveOnlyOutput disabled (Receive-only mode)1 SWNSSEN NSS Software Mode Selection 9 1 SWNSSENread-writeHardwareSoftware slave management disabled0SoftwareSoftware slave management enabled1 SWNSS NSS Pin Selection In NSS Software Mode 8 1 SWNSSread-writeSlaveSelectedNSS is pulled low0SlaveNotSelectedNSS is pulled high1 LF LSB First Mode 7 1 LFread-writeMSBFirstData is transmitted/received with the MSB first0LSBFirstData is transmitted/received with the LSB first1 SPIEN SPI enable 6 1 SPIENread-writeDisabledPeripheral disabled0EnabledPeripheral enabled1 PSC Master Clock Prescaler Selection 3 3 PSCread-writeDiv2PCLK / 20Div4PCLK / 41Div8PCLK / 82Div16PCLK / 163Div32PCLK / 324Div64PCLK / 645Div128PCLK / 1286Div256PCLK / 2567 MSTMOD Master Mode Enable 2 1 MSTMODread-writeSlaveSlave configuration0MasterMaster configuration1 CKPL Clock polarity Selection 1 1 CKPLread-writeIdleLowCLK pulled low when idle0IdleHighCLK pulled high when idle1 CKPH Clock Phase Selection 0 1 CKPHread-writeFirstEdgeThe first clock transition is the first data capture edge0SecondEdgeThe second clock transition is the first data capture edge1 CTL1 CTL1 control register 1 0x04 0x20 read-write 0x00000000 TBEIE Tx buffer empty interrupt enable 7 1 TBEIEread-writeDisabledTBE interrupt disabled0EnabledTBE interrupt enabled1 RBNEIE RX buffer not empty interrupt enable 6 1 RBNEIEread-writeDisabledRBNE interrupt disabled0EnabledRBNE interrupt enabled1 ERRIE Error interrupt enable 5 1 ERRIEread-writeDisabledError interrupt disabled0EnabledError interrupt enabled1 TMOD SPI TI Mode Enable 4 1 NSSP SPI NSS pulse mode Enable 3 1 NSSDRV Drive NSS Output 2 1 NSSDRVread-writeDisabledNSS output is disabled in master mode0EnabledNSS output is enabled in master mode1 DMATEN Transmit Buffer DMA Enable 1 1 DMATENread-writeDisabledTx buffer DMA disabled0EnabledTx buffer DMA enabled1 DMAREN Rx buffer DMA enable 0 1 DMARENread-writeDisabledRx buffer DMA disabled0EnabledRx buffer DMA enabled1 STAT STAT status register 0x08 0x20 0x00000002 FERR Format Error 8 1 read-write TRANS Transmitting On-going Bit 7 1 read-only TRANSread-writeIdleSPI or I2S is idle0BusySPI or I2S is currently transmitting or receiving1 RXORERR Reception Overrun Error Bit 6 1 read-only RXORERRread-writeNoOverrunNo overrun occurred0OverrunOverrun occurred1 CONFERR SPI Configuration error 5 1 read-only CONFERRread-writeNoFaultNo configuration fault occurred0FaultConfiguration fault occurred1 CRCERR SPI CRC Error Bit 4 1 read-write CRCERRRreadMatchCRC value received matches the SPIx_RXCRCR value0NoMatchCRC value received does not match the SPIx_RXCRCR value1 CRCERRWwriteClearClear CRC error0 TXURERR Transmission underrun error bit 3 1 read-only TXURERRread-writeNoUnderrunNo underrun occurred0UnderrunUnderrun occurred1 I2SCH I2S channel side 2 1 read-only I2SCHread-writeLeftChannel left has to be transmitted or has been received0RightChannel right has to be transmitted or has been received1 TBE Transmit Buffer Empty 1 1 read-only TBEread-writeNotEmptyTx buffer not empty0EmptyTx buffer empty1 RBNE Receive Buffer Not Empty 0 1 read-only RBNEread-writeEmptyRx buffer empty0NotEmptyRx buffer not empty1 DATA DATA data register 0x0C 0x20 read-write 0x00000000 DATA Data transfer register 0 16 065535 CRCPOLY CRCPOLY CRC polynomial register 0x10 0x20 read-write 0x00000007 CRCPOLY CRC polynomial register 0 16 065535 RCRC RCRC RX CRC register 0x14 0x20 read-only 0x00000000 RCRC RX CRC register 0 16 065535 TCRC TCRC TX CRC register 0x18 0x20 read-only 0x00000000 TCRC Tx CRC register 0 16 065535 I2SCTL I2SCTL I2S control register 0x1C 0x20 read-write 0x00000000 I2SSEL I2S mode selection 11 1 I2SSELread-writeSPIModeSPI mode is selected0I2SModeI2S mode is selected1 I2SEN I2S Enable 10 1 I2SENread-writeDisabledI2S peripheral is disabled0EnabledI2S peripheral is enabled1 I2SOPMOD I2S operation mode 8 2 I2SOPMODread-writeSlaveTxSlave - transmit0SlaveRxSlave - receive1MasterTxMaster - transmit2MasterRxMaster - receive3 PCMSMOD PCM frame synchronization mode 7 1 PCMSMODread-writeShortShort frame synchronisation0LongLong frame synchronisation1 I2SSTD I2S standard selection 4 2 I2SSTDread-writePhilipsI2S Philips standard0MSBMSB justified standard1LSBLSB justified standard2PCMPCM standard3 CKPL Idle state clock polarity 3 1 CKPLread-writeIdleLowI2S clock inactive state is low level0IdleHighI2S clock inactive state is high level1 DTLEN Data length 1 2 DTLENread-writeSixteenBit16-bit data length0TwentyFourBit24-bit data length1ThirtyTwoBit32-bit data length2 CHLEN Channel length (number of bits per audio channel) 0 1 CHLENread-writeSixteenBit16-bit wide0ThirtyTwoBit32-bit wide1 I2SPSC I2SPSC I2S prescaler register 0x20 0x20 read-write 0x00000002 MCKOEN I2S_MCK output enable 9 1 MCKOENread-writeDisabledMaster clock output is disabled0EnabledMaster clock output is enabled1 OF Odd factor for the prescaler 8 1 OFread-writeEvenReal divider value is DIV * 20OddReal divider value is (DIV * 2) + 11 DIV Dividing factor for the prescaler 0 8 1255 SPI1 Serial peripheral interface SPI 0x40003800 0x0 0x400 registers SPI1 36 CTL0 CTL0 control register 0 0x0 0x20 read-write 0x00000000 BDEN Bidirectional enable 15 1 BDENread-writeUnidirectional2-line unidirectional data mode selected0Bidirectional1-line bidirectional data mode selected1 BDOEN Bidirectional Transmit output enable 14 1 BDOENread-writeReceiveOnlyReceive-only mode0TransmitOnlyTransmit-only mode1 CRCEN CRC Calculation Enable 13 1 CRCENread-writeDisabledCRC calculation disabled0EnabledCRC calculation enabled1 CRCNT CRC Next Transfer 12 1 CRCNTread-writeDataNext transmit value is data from Tx buffer0CRCNext transmit value is CRC value from TCRC1 FF16 Data frame format 11 1 FF16read-writeEightBit8-bit data frame format is selected for transmission/reception0SixteenBit16-bit data frame format is selected for transmission/reception1 RO Receive only 10 1 ROread-writeFullDuplexFull duplex (Transmit and receive)0ReceiveOnlyOutput disabled (Receive-only mode)1 SWNSSEN NSS Software Mode Selection 9 1 SWNSSENread-writeHardwareSoftware slave management disabled0SoftwareSoftware slave management enabled1 SWNSS NSS Pin Selection In NSS Software Mode 8 1 SWNSSread-writeSlaveSelectedNSS is pulled low0SlaveNotSelectedNSS is pulled high1 LF LSB First Mode 7 1 LFread-writeMSBFirstData is transmitted/received with the MSB first0LSBFirstData is transmitted/received with the LSB first1 SPIEN SPI enable 6 1 SPIENread-writeDisabledPeripheral disabled0EnabledPeripheral enabled1 PSC Master Clock Prescaler Selection 3 3 PSCread-writeDiv2PCLK / 20Div4PCLK / 41Div8PCLK / 82Div16PCLK / 163Div32PCLK / 324Div64PCLK / 645Div128PCLK / 1286Div256PCLK / 2567 MSTMOD Master Mode Enable 2 1 MSTMODread-writeSlaveSlave configuration0MasterMaster configuration1 CKPL Clock polarity Selection 1 1 CKPLread-writeIdleLowCLK pulled low when idle0IdleHighCLK pulled high when idle1 CKPH Clock Phase Selection 0 1 CKPHread-writeFirstEdgeThe first clock transition is the first data capture edge0SecondEdgeThe second clock transition is the first data capture edge1 CTL1 CTL1 control register 1 0x04 0x20 read-write 0x00000000 TBEIE Tx buffer empty interrupt enable 7 1 TBEIEread-writeDisabledTBE interrupt disabled0EnabledTBE interrupt enabled1 RBNEIE RX buffer not empty interrupt enable 6 1 RBNEIEread-writeDisabledRBNE interrupt disabled0EnabledRBNE interrupt enabled1 ERRIE Error interrupt enable 5 1 ERRIEread-writeDisabledError interrupt disabled0EnabledError interrupt enabled1 TMOD SPI TI Mode Enable 4 1 NSSP SPI NSS pulse mode Enable 3 1 NSSDRV Drive NSS Output 2 1 NSSDRVread-writeDisabledNSS output is disabled in master mode0EnabledNSS output is enabled in master mode1 DMATEN Transmit Buffer DMA Enable 1 1 DMATENread-writeDisabledTx buffer DMA disabled0EnabledTx buffer DMA enabled1 DMAREN Rx buffer DMA enable 0 1 DMARENread-writeDisabledRx buffer DMA disabled0EnabledRx buffer DMA enabled1 STAT STAT status register 0x08 0x20 0x00000002 FERR Format Error 8 1 read-write TRANS Transmitting On-going Bit 7 1 read-only TRANSread-writeIdleSPI or I2S is idle0BusySPI or I2S is currently transmitting or receiving1 RXORERR Reception Overrun Error Bit 6 1 read-only RXORERRread-writeNoOverrunNo overrun occurred0OverrunOverrun occurred1 CONFERR SPI Configuration error 5 1 read-only CONFERRread-writeNoFaultNo configuration fault occurred0FaultConfiguration fault occurred1 CRCERR SPI CRC Error Bit 4 1 read-write CRCERRRreadMatchCRC value received matches the SPIx_RXCRCR value0NoMatchCRC value received does not match the SPIx_RXCRCR value1 CRCERRWwriteClearClear CRC error0 TXURERR Transmission underrun error bit 3 1 read-only TXURERRread-writeNoUnderrunNo underrun occurred0UnderrunUnderrun occurred1 I2SCH I2S channel side 2 1 read-only I2SCHread-writeLeftChannel left has to be transmitted or has been received0RightChannel right has to be transmitted or has been received1 TBE Transmit Buffer Empty 1 1 read-only TBEread-writeNotEmptyTx buffer not empty0EmptyTx buffer empty1 RBNE Receive Buffer Not Empty 0 1 read-only RBNEread-writeEmptyRx buffer empty0NotEmptyRx buffer not empty1 DATA DATA data register 0x0C 0x20 read-write 0x00000000 DATA Data transfer register 0 16 065535 CRCPOLY CRCPOLY CRC polynomial register 0x10 0x20 read-write 0x00000007 CRCPOLY CRC polynomial register 0 16 065535 RCRC RCRC RX CRC register 0x14 0x20 read-only 0x00000000 RCRC RX CRC register 0 16 065535 TCRC TCRC TX CRC register 0x18 0x20 read-only 0x00000000 TCRC Tx CRC register 0 16 065535 I2SCTL I2SCTL I2S control register 0x1C 0x20 read-write 0x00000000 I2SSEL I2S mode selection 11 1 I2SSELread-writeSPIModeSPI mode is selected0I2SModeI2S mode is selected1 I2SEN I2S Enable 10 1 I2SENread-writeDisabledI2S peripheral is disabled0EnabledI2S peripheral is enabled1 I2SOPMOD I2S operation mode 8 2 I2SOPMODread-writeSlaveTxSlave - transmit0SlaveRxSlave - receive1MasterTxMaster - transmit2MasterRxMaster - receive3 PCMSMOD PCM frame synchronization mode 7 1 PCMSMODread-writeShortShort frame synchronisation0LongLong frame synchronisation1 I2SSTD I2S standard selection 4 2 I2SSTDread-writePhilipsI2S Philips standard0MSBMSB justified standard1LSBLSB justified standard2PCMPCM standard3 CKPL Idle state clock polarity 3 1 CKPLread-writeIdleLowI2S clock inactive state is low level0IdleHighI2S clock inactive state is high level1 DTLEN Data length 1 2 DTLENread-writeSixteenBit16-bit data length0TwentyFourBit24-bit data length1ThirtyTwoBit32-bit data length2 CHLEN Channel length (number of bits per audio channel) 0 1 CHLENread-writeSixteenBit16-bit wide0ThirtyTwoBit32-bit wide1 I2SPSC I2SPSC I2S prescaler register 0x20 0x20 read-write 0x00000002 MCKOEN I2S_MCK output enable 9 1 MCKOENread-writeDisabledMaster clock output is disabled0EnabledMaster clock output is enabled1 OF Odd factor for the prescaler 8 1 OFread-writeEvenReal divider value is DIV * 20OddReal divider value is (DIV * 2) + 11 DIV Dividing factor for the prescaler 0 8 1255 SPI2 Serial peripheral interface SPI 0x40003C00 0x0 0x400 registers SPI2 51 CTL0 CTL0 control register 0 0x0 0x20 read-write 0x00000000 BDEN Bidirectional enable 15 1 BDENread-writeUnidirectional2-line unidirectional data mode selected0Bidirectional1-line bidirectional data mode selected1 BDOEN Bidirectional Transmit output enable 14 1 BDOENread-writeReceiveOnlyReceive-only mode0TransmitOnlyTransmit-only mode1 CRCEN CRC Calculation Enable 13 1 CRCENread-writeDisabledCRC calculation disabled0EnabledCRC calculation enabled1 CRCNT CRC Next Transfer 12 1 CRCNTread-writeDataNext transmit value is data from Tx buffer0CRCNext transmit value is CRC value from TCRC1 FF16 Data frame format 11 1 FF16read-writeEightBit8-bit data frame format is selected for transmission/reception0SixteenBit16-bit data frame format is selected for transmission/reception1 RO Receive only 10 1 ROread-writeFullDuplexFull duplex (Transmit and receive)0ReceiveOnlyOutput disabled (Receive-only mode)1 SWNSSEN NSS Software Mode Selection 9 1 SWNSSENread-writeHardwareSoftware slave management disabled0SoftwareSoftware slave management enabled1 SWNSS NSS Pin Selection In NSS Software Mode 8 1 SWNSSread-writeSlaveSelectedNSS is pulled low0SlaveNotSelectedNSS is pulled high1 LF LSB First Mode 7 1 LFread-writeMSBFirstData is transmitted/received with the MSB first0LSBFirstData is transmitted/received with the LSB first1 SPIEN SPI enable 6 1 SPIENread-writeDisabledPeripheral disabled0EnabledPeripheral enabled1 PSC Master Clock Prescaler Selection 3 3 PSCread-writeDiv2PCLK / 20Div4PCLK / 41Div8PCLK / 82Div16PCLK / 163Div32PCLK / 324Div64PCLK / 645Div128PCLK / 1286Div256PCLK / 2567 MSTMOD Master Mode Enable 2 1 MSTMODread-writeSlaveSlave configuration0MasterMaster configuration1 CKPL Clock polarity Selection 1 1 CKPLread-writeIdleLowCLK pulled low when idle0IdleHighCLK pulled high when idle1 CKPH Clock Phase Selection 0 1 CKPHread-writeFirstEdgeThe first clock transition is the first data capture edge0SecondEdgeThe second clock transition is the first data capture edge1 CTL1 CTL1 control register 1 0x04 0x20 read-write 0x00000000 TBEIE Tx buffer empty interrupt enable 7 1 TBEIEread-writeDisabledTBE interrupt disabled0EnabledTBE interrupt enabled1 RBNEIE RX buffer not empty interrupt enable 6 1 RBNEIEread-writeDisabledRBNE interrupt disabled0EnabledRBNE interrupt enabled1 ERRIE Error interrupt enable 5 1 ERRIEread-writeDisabledError interrupt disabled0EnabledError interrupt enabled1 TMOD SPI TI Mode Enable 4 1 NSSP SPI NSS pulse mode Enable 3 1 NSSDRV Drive NSS Output 2 1 NSSDRVread-writeDisabledNSS output is disabled in master mode0EnabledNSS output is enabled in master mode1 DMATEN Transmit Buffer DMA Enable 1 1 DMATENread-writeDisabledTx buffer DMA disabled0EnabledTx buffer DMA enabled1 DMAREN Rx buffer DMA enable 0 1 DMARENread-writeDisabledRx buffer DMA disabled0EnabledRx buffer DMA enabled1 STAT STAT status register 0x08 0x20 0x00000002 FERR Format Error 8 1 read-write TRANS Transmitting On-going Bit 7 1 read-only TRANSread-writeIdleSPI or I2S is idle0BusySPI or I2S is currently transmitting or receiving1 RXORERR Reception Overrun Error Bit 6 1 read-only RXORERRread-writeNoOverrunNo overrun occurred0OverrunOverrun occurred1 CONFERR SPI Configuration error 5 1 read-only CONFERRread-writeNoFaultNo configuration fault occurred0FaultConfiguration fault occurred1 CRCERR SPI CRC Error Bit 4 1 read-write CRCERRRreadMatchCRC value received matches the SPIx_RXCRCR value0NoMatchCRC value received does not match the SPIx_RXCRCR value1 CRCERRWwriteClearClear CRC error0 TXURERR Transmission underrun error bit 3 1 read-only TXURERRread-writeNoUnderrunNo underrun occurred0UnderrunUnderrun occurred1 I2SCH I2S channel side 2 1 read-only I2SCHread-writeLeftChannel left has to be transmitted or has been received0RightChannel right has to be transmitted or has been received1 TBE Transmit Buffer Empty 1 1 read-only TBEread-writeNotEmptyTx buffer not empty0EmptyTx buffer empty1 RBNE Receive Buffer Not Empty 0 1 read-only RBNEread-writeEmptyRx buffer empty0NotEmptyRx buffer not empty1 DATA DATA data register 0x0C 0x20 read-write 0x00000000 DATA Data transfer register 0 16 065535 CRCPOLY CRCPOLY CRC polynomial register 0x10 0x20 read-write 0x00000007 CRCPOLY CRC polynomial register 0 16 065535 RCRC RCRC RX CRC register 0x14 0x20 read-only 0x00000000 RCRC RX CRC register 0 16 065535 TCRC TCRC TX CRC register 0x18 0x20 read-only 0x00000000 TCRC Tx CRC register 0 16 065535 I2SCTL I2SCTL I2S control register 0x1C 0x20 read-write 0x00000000 I2SSEL I2S mode selection 11 1 I2SSELread-writeSPIModeSPI mode is selected0I2SModeI2S mode is selected1 I2SEN I2S Enable 10 1 I2SENread-writeDisabledI2S peripheral is disabled0EnabledI2S peripheral is enabled1 I2SOPMOD I2S operation mode 8 2 I2SOPMODread-writeSlaveTxSlave - transmit0SlaveRxSlave - receive1MasterTxMaster - transmit2MasterRxMaster - receive3 PCMSMOD PCM frame synchronization mode 7 1 PCMSMODread-writeShortShort frame synchronisation0LongLong frame synchronisation1 I2SSTD I2S standard selection 4 2 I2SSTDread-writePhilipsI2S Philips standard0MSBMSB justified standard1LSBLSB justified standard2PCMPCM standard3 CKPL Idle state clock polarity 3 1 CKPLread-writeIdleLowI2S clock inactive state is low level0IdleHighI2S clock inactive state is high level1 DTLEN Data length 1 2 DTLENread-writeSixteenBit16-bit data length0TwentyFourBit24-bit data length1ThirtyTwoBit32-bit data length2 CHLEN Channel length (number of bits per audio channel) 0 1 CHLENread-writeSixteenBit16-bit wide0ThirtyTwoBit32-bit wide1 I2SPSC I2SPSC I2S prescaler register 0x20 0x20 read-write 0x00000002 MCKOEN I2S_MCK output enable 9 1 MCKOENread-writeDisabledMaster clock output is disabled0EnabledMaster clock output is enabled1 OF Odd factor for the prescaler 8 1 OFread-writeEvenReal divider value is DIV * 20OddReal divider value is (DIV * 2) + 11 DIV Dividing factor for the prescaler 0 8 1255 QCTL QCTL Quad-SPI mode control register 0x80 0x20 read-write 0x00000000 IO23_DRV Drive IO2 and IO3 enable 2 1 QRD Quad-SPI mode read select 1 1 QMOD Quad-SPI mode enable 0 1 SQPI Serial/Quad Parallel Interface SQPI 0xA0001000 0x0 0x400 registers INIT INIT SQPI Initial Register 0x0 0x20 read-write 0x18010004 SQPI_PL Read data sample polarity. 31 1 SQPI_IDLEN SQPI controller external memory ID length 29 2 SQPI_ADDRBIT Bit number of SPI PSRAM address phase. 24 5 SQPI_CLKDIV Clock divider for SQPI output clock 18 6 SQPI_CMDBIT Bit number of SQPI controller command phase 16 2 RCMD RCMD SQPI Read Command Register 0x04 0x20 read-write 0x00100000 SQPI_RID Send read ID command 31 1 SQPI_RMODE SQPI controller read command mode 20 3 SQPI_RWAITCYCLE SQPI read command waitcycle number after address phase 16 4 SQPI_RCMD SQPI read command for AHB read transfer 0 16 WCMD WCMD Write Command Register 0x08 0x20 read-write 0x00010000 SQPI_SC Send special command 31 1 SQPI_WMODE SQPI controller write command mode 20 3 SQPI_WWAITCYCLE SQPI write command waitcycle number after address phase 16 4 SPI_WCMD SQPI write command for AHB write transfer 0 16 IDL IDL ID Low Register 0x0C 0x20 read-only 0x00000000 SQPI_IDL ID Low Data saved for SQPI Read ID Command 0 32 IDH IDH ID High Register 0x10 0x20 read-only 0x00000000 SQPI_IDH ID High Data saved for SQPI read ID command 0 32 TIMER0 Advanced-timers TIMER 0x40012C00 0x0 0x400 registers TIMER0_BRK_TIMER8 24 TIMER0_UP_TIMER9 25 TIMER0_TRG_CMT_TIMER10 26 TIMER0_CC 27 CTL0 CTL0 control register 0 0x0 0x20 read-write 0x00000000 CKDIV Clock division 8 2 CKDIVread-writeDiv1t_DTS = t_CK_INT0Div2t_DTS = 2 × t_CK_INT1Div4t_DTS = 4 × t_CK_INT2 ARSE Auto-reload shadow enable 7 1 ARSEread-writeDisabledThe shadow register for CAR is disabled0EnabledThe shadow register for CAR is enabled1 CAM Counter aligns mode selection 5 2 CAMread-writeEdgeAlignedThe counter counts up or down depending on the direction bit0CenterAlignedCountingDownThe counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.1CenterAlignedCountingUpThe counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.2CenterAlignedCountingUpDownThe counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.3 DIR Direction 4 1 DIRread-writeUpCounter used as upcounter0DownCounter used as downcounter1 SPM Single pulse mode 3 1 SPMread-writeDisabledCounter is not stopped at update event0EnabledCounter stops counting at the next update event (clearing the CEN bit)1 UPS Update source 2 1 UPSread-writeAnyEventAny of counter overflow/underflow, setting UPG, or update through slave mode, generates an update interrupt or DMA request0CounterOnlyOnly counter overflow/underflow generates an update interrupt or DMA request1 UPDIS Update disable 1 1 UPDISread-writeEnabledUpdate event enabled0DisabledUpdate event disabled1 CEN Counter enable 0 1 CENread-writeDisabledCounter disabled0EnabledCounter enabled1 CTL1 CTL1 control register 1 0x04 0x20 read-write 0x00000000 ISO3 Idle state of channel 3 output 14 1 ISO2N Idle state of channel 2 complementary output 13 1 ISO2 Idle state of channel 2 output 12 1 ISO1N Idle state of channel 1 complementary output 11 1 ISO1 Idle state of channel 1 output 10 1 ISO0N Idle state of channel 0 complementary output 9 1 ISO0Nread-writeLowCHn_ON=0 when POEN=00HighCHn_ON=1 when POEN=01 ISO0 Idle state of channel 0 output 8 1 ISO0read-writeLowCHn_O=0 (after a dead-time if CHn_ON is implemented) when POEN=00HighCHn_O=1 (after a dead-time if CHn_ON is implemented) when POEN=01 TI0S Channel 0 trigger input selection 7 1 TI0Sread-writeNormalThe CH0 pin input is selected as channel 0 trigger input0XORThe XOR of CH0, CH1 and CH2 pins are selected as channel 0 trigger input1 MMC Master mode control 4 3 MMCread-writeResetUse UPG bit from SWEVG register0EnableUse CEN bit from CTL0 register1UpdateUse the update event2CaptureComparePulseThe trigger output send a positive pulse when a capture or a compare match occurred in channel 03CompareO0CO0CPRE signal is used as trigger output4CompareO1CO1CPRE signal is used as trigger output5CompareO2CO2CPRE signal is used as trigger output6CompareO3CO3CPRE signal is used as trigger output7 DMAS DMA request source selection 3 1 DMASread-writeOnCompareCCx DMA request sent when CCx event occurs0OnUpdateCCx DMA request sent when update event occurs1 CCUC Commutation control shadow register update control 2 1 CCUCread-writeDefaultCapture/compare are updated only by setting the CMTG bit0WithRisingEdgeCapture/compare are updated by setting the CMTG bit or when an rising edge occurs on TRGI1 CCSE Commutation control shadow enable 0 1 CCSEread-writeNotPreloadedThe shadow registers for CHxEN, CHxNEN and CHxCOMCTL bits are disabled0PreloadedThe shadow registers for CHxEN, CHxNEN and CHxCOMCTL bits are enabled1 SMCFG SMCFG slave mode configuration register 0x08 0x20 read-write 0x00000000 ETP External trigger polarity 15 1 ETPread-writeNotInvertedETI is noninverted, active at high level or rising edge0InvertedETI is inverted, active at low level or falling edge1 SMC1 Part of SMC for enable External clock mode1 14 1 SMC1read-writeDisabledExternal clock mode 1 disabled0EnabledExternal clock mode 1 enabled. The counter is clocked by any active edge on the ETIF signal.1 ETPSC External trigger prescaler 12 2 ETPSCread-writeDiv1External trigger prescaler disabled0Div2ETI frequency divided by 21Div4ETI frequency divided by 42Div8ETI frequency divided by 83 ETFC External trigger filter control 8 4 ETFCread-writeNoFilterFilter disabled. fSAMP=fDTS, N=10TimerCk_N2fSAMP=fTIMER_CK, N=21TimerCk_N4fSAMP=fTIMER_CK, N=42TimerCk_N8fSAMP=fTIMER_CK, N=83FDTS_Div2_N6fSAMP=fDTS/2, N=64FDTS_Div2_N8fSAMP=fDTS/2, N=85FDTS_Div4_N6fSAMP=fDTS/4, N=66FDTS_Div4_N8fSAMP=fDTS/4, N=87FDTS_Div8_N6fSAMP=fDTS/8, N=68FDTS_Div8_N8fSAMP=fDTS/8, N=89FDTS_Div16_N5fSAMP=fDTS/16, N=510FDTS_Div16_N6fSAMP=fDTS/16, N=611FDTS_Div16_N8fSAMP=fDTS/16, N=812FDTS_Div32_N5fSAMP=fDTS/32, N=513FDTS_Div32_N6fSAMP=fDTS/32, N=614FDTS_Div32_N8fSAMP=fDTS/32, N=815 MSM Master/Slave mode 7 1 MSMread-writeNoSyncNo action0SyncThe effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.1 TRGS Trigger selection 4 3 TRGSread-writeITI0Internal Trigger 0 (ITI0)0ITI1Internal Trigger 1 (ITI1)1ITI2Internal Trigger 2 (ITI2)2CI0F_EDCI0 Edge Detector (CI0F_ED)4CI0FE0Filtered Timer Input 0 (CI0FE0)5CI1FE1Filtered Timer Input 1 (CI1FE1)6ETIFPExternal Trigger input (ETIFP)7 SMC Slave mode selection 0 3 SMCread-writeDisabledSlave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.0QuadratureDecoderMode0Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.1QuadratureDecoderMode1Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.2QuadratureDecoderMode2Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.3RestartModeRestart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.4PauseModePause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.5EventModeEvent Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.6ExternalClockModeExternal Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.7 DMAINTEN DMAINTEN DMA/Interrupt enable register 0x0C 0x20 read-write 0x00000000 TRGDEN Trigger DMA request enable 14 1 TRGDENread-writeDisabledTrigger DMA request disabled0EnabledTrigger DMA request enabled1 CMTDEN Commutation DMA request enable 13 1 CMTDENread-writeDisabledCommutation DMA request disabled0EnabledCommutation DMA request enabled1 CH3DEN Channel 3 capture/compare DMA request enable 12 1 CH2DEN Channel 2 capture/compare DMA request enable 11 1 CH1DEN Channel 1 capture/compare DMA request enable 10 1 CH0DEN Channel 0 capture/compare DMA request enable 9 1 CH0DENread-writeDisabledCapture/compare DMA request disabled0EnabledCapture/compare DMA request enabled1 UPDEN Update DMA request enable 8 1 UPDENread-writeDisabledUpdate DMA request disabled0EnabledUpdate DMA request enabled1 BRKIE Break interrupt enable 7 1 BRKIEread-writeDisabledBreak interrupt disabled0EnabledBreak interrupt enabled1 TRGIE Trigger interrupt enable 6 1 TRGIEread-writeDisabledTrigger interrupt disabled0EnabledTrigger interrupt enabled1 CMTIE commutation interrupt enable 5 1 CMTIEread-writeDisabledCommutation interrupt disabled0EnabledCommutation interrupt enabled1 CH3IE Channel 3 capture/compare interrupt enable 4 1 CH2IE Channel 2 capture/compare interrupt enable 3 1 CH1IE Channel 1 capture/compare interrupt enable 2 1 CH0IE Channel 0 capture/compare interrupt enable 1 1 CH0IEread-writeDisabledCapture/compare interrupt disabled0EnabledCapture/compare interrupt enabled1 UPIE Update interrupt enable 0 1 UPIEread-writeDisabledUpdate interrupt disabled0EnabledUpdate interrupt enabled1 INTF INTF Interrupt flag register 0x10 0x20 read-write 0x00000000 CH3OF Channel 3 over capture flag 12 1 CH2OF Channel 2 over capture flag 11 1 CH1OF Channel 1 over capture flag 10 1 CH0OF Channel 0 over capture flag 9 1 CH0OFread-writeClearNo over capture occurred0OverCaptureA capture event occured while CHnIF was already set1 BRKIF Break interrupt flag 7 1 BRKIFread-writeClearNo active level break detected0BreakActive level detected1 TRGIF Trigger interrupt flag 6 1 TRGIFread-writeClearNo trigger event occured0TriggeredTrigger event occurred1 CMTIF Channel commutation interrupt flag 5 1 CMTIFread-writeClearNo channel commutation event occured0CommutationChannel commutation event occurred1 CH3IF Channel 3 capture/compare interrupt flag 4 1 CH2IF Channel 2 capture/compare interrupt flag 3 1 CH1IF Channel 1 capture/compare interrupt flag 2 1 CH0IF Channel 0 capture/compare interrupt flag 1 1 CH0IFread-writeClearNo capture or compare interrupt occurred0CaptureCompareA capture or compare event occurred1 UPIF Update interrupt flag 0 1 UPIFread-writeClearNo update interrupt occurred0UpdatePendingUpdate interrupt pending.1 SWEVG SWEVG Software event generation register 0x14 0x20 write-only 0x00000000 BRKG Break event generation 7 1 BRKGread-writeBreakGenerate a break event1 TRGG Trigger event generation 6 1 TRGGread-writeTriggerGenerate a trigger event1 CMTG Channel commutation event generation 5 1 CMTGread-writeUpdateGenerate a channel commutation event, updating capture/compare control registers based on the value of CCSE1 CH3G Channel 3 capture or compare event generation 4 1 CH2G Channel 2 capture or compare event generation 3 1 CH1G Channel 1 capture or compare event generation 2 1 CH0G Channel 0 capture or compare event generation 1 1 CH0Gread-writeCaptureCompareGenerate a capture or compare event1 UPG Update event generation 0 1 UPGread-writeUpdateRe-initializes the timer counter and generates an update of the registers.1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x20 read-write 0x00000000 CH1COMCEN Channel 1 output compare clear enable 15 1 CH1COMCTL Channel 1 compare output control 12 3 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1MS Channel 1 mode selection 8 2 CH0COMCEN Channel 0 output compare clear enable 7 1 CH0COMCENread-writeDisabledOutput compare clear disabled0EnabledOutput compare clear enabled1 CH0COMCTL Channel 0 compare output control 4 3 CH0COMCTLread-writeFrozenThe comparison between the output compare register CHyCV and the counter CNT has no effect on the outputs0ActiveOnMatchSet channel to active level on match. OxCPRE signal is forced high when the counter matches the capture/compare register CHyCV1InactiveOnMatchSet channel to inactive level on match. OxCPRE signal is forced low when the counter matches the capture/compare register CHyCV2ToggleOxCPRE toggles when CNT=CHyCV3ForceInactiveOxCPRE is forced low4ForceActiveOxCPRE is forced high5PwmMode0In upcounting, channel is active as long as CNT<CHyCV else inactive. In downcounting, channel is inactive as long as CNT>CHyCV else active6PwmMode1Inversely to PwmMode07 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0COMSENread-writeDisabledPreload register on CHyCV disabled. New values written to CHyCV are taken into account immediately0EnabledPreload register on CHyCV enabled. Preload value is loaded into active register on each update event1 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0COMFENread-writeSlowThe minimum delay from an edge is 5 clock cycles0FastThe minimum delay from an edge is 3 clock cycles1 CH0MS Channel 0 I/O mode selection 0 2 CH0MSread-writeOutputChannel is configured as output0CI0Channel is configured as input, ISx is connected to CI0FE01CI1Channel is configured as input, ISx is connected to CI1FE02ITSChannel is configured as input, ISx is connected to ITS3 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 0x20 read-write 0x00000000 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPFLTread-writeNoFilterFilter disabled. fSAMP=fDTS, N=10TimerCk_N2fSAMP=fTIMER_CK, N=21TimerCk_N4fSAMP=fTIMER_CK, N=42TimerCk_N8fSAMP=fTIMER_CK, N=83FDTS_Div2_N6fSAMP=fDTS/2, N=64FDTS_Div2_N8fSAMP=fDTS/2, N=85FDTS_Div4_N6fSAMP=fDTS/4, N=66FDTS_Div4_N8fSAMP=fDTS/4, N=87FDTS_Div8_N6fSAMP=fDTS/8, N=68FDTS_Div8_N8fSAMP=fDTS/8, N=89FDTS_Div16_N5fSAMP=fDTS/16, N=510FDTS_Div16_N6fSAMP=fDTS/16, N=611FDTS_Div16_N8fSAMP=fDTS/16, N=812FDTS_Div32_N5fSAMP=fDTS/32, N=513FDTS_Div32_N6fSAMP=fDTS/32, N=614FDTS_Div32_N8fSAMP=fDTS/32, N=815 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0CAPPSCread-writeDiv1Prescaler disabled, capture on every edge0Div2Capture every 2 edges1Div4Capture every 4 edges2Div8Capture every 8 edges3 CH0MS Channel 0 mode selection 0 2 CH0MSread-writeOutputChannel is configured as output0CI0Channel is configured as input, ISx is connected to CI0FEx1CI1Channel is configured as input, ISx is connected to CI1FEx2ITSChannel is configured as input, ISx is connected to ITS3 CHCTL1_Output CHCTL1_Output Channel control register 1 (output mode) 0x1C 0x20 read-write 0x00000000 CH3COMCEN Channel 3 output compare clear enable 15 1 CH3COMCTL Channel 3 compare output control 12 3 CH3COMSEN Channel 3 output compare shadow enable 11 1 CH3COMFEN Channel 3 output compare fast enable 10 1 CH3MS Channel 3 mode selection 8 2 CH2COMCEN Channel 2 output compare clear enable 7 1 CH2COMCTL Channel 2 compare output control 4 3 CH2COMSEN Channel 2 compare output shadow enable 3 1 CH2COMFEN Channel 2 output compare fast enable 2 1 CH2MS Channel 2 I/O mode selection 0 2 CHCTL1_Input CHCTL1_Input Channel control register 1 (input mode) CHCTL1_Output 0x1C 0x20 read-write 0x00000000 CH3CAPFLT Channel 3 input capture filter control 12 4 CH3CAPPSC Channel 3 input capture prescaler 10 2 CH3MS Channel 3 mode selection 8 2 CH2CAPFLT Channel 2 input capture filter control 4 4 CH2CAPPSC Channel 2 input capture prescaler 2 2 CH2MS Channel 2 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x20 read-write 0x00000000 CH3P Channel 3 capture/compare function polarity 13 1 CH3EN Channel 3 capture/compare function enable 12 1 CH2NP Channel 2 complementary output polarity 11 1 CH2NEN Channel 2 complementary output enable 10 1 CH2P Channel 2 capture/compare function polarity 9 1 CH2EN Channel 2 capture/compare function enable 8 1 CH1NP Channel 1 complementary output polarity 7 1 CH1NEN Channel 1 complementary output enable 6 1 CH1P Channel 1 capture/compare function polarity 5 1 CH1EN Channel 1 capture/compare function enable 4 1 CH0NP Channel 0 complementary output polarity 3 1 CH0NEN Channel 0 complementary output enable 2 1 CH0P Channel 0 capture/compare function polarity 1 1 CH0Pread-writeNotInvertedActive high0InvertedActive low1 CH0EN Channel 0 capture/compare function enable 0 1 CH0ENread-writeDisabledChannel output is disabled0EnabledChannel output is enabled1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT current counter value 0 16 065535 PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value of the counter clock 0 16 065535 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x00000000 CAR Counter auto reload value 0 16 065535 CREP CREP Counter repetition register 0x30 0x20 read-write 0x00000000 CREP Counter repetition value 0 8 0255 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x20 read-write 0x00000000 CH0VAL Capture or compare value of channel0 0 16 065535 CH1CV CH1CV Channel 1 capture/compare value register 0x38 0x20 read-write 0x00000000 CH1VAL Capture or compare value of channel1 0 16 065535 CH2CV CH2CV Channel 2 capture/compare value register 0x3C 0x20 read-write 0x00000000 CH2VAL Capture or compare value of channel 2 0 16 065535 CH3CV CH3CV Channel 3 capture/compare value register 0x40 0x20 read-write 0x00000000 CH3VAL Capture or compare value of channel 3 0 16 065535 CCHP CCHP channel complementary protection register 0x44 0x20 read-write 0x00000000 POEN Primary output enable 15 1 POENread-writeDisabledChannel outputs are disabled0EnabledChannel outputs are enabled1 OAEN Output automatic enable 14 1 OAENread-writeManualPOEN cannot be set by hardware0AutomaticPOEN can be set by hardware automatically at the next update event1 BRKP Break polarity 13 1 BRKPread-writeInvertedBRKIN is active low0NotInvertedBRKIN is active high1 BRKEN Break enable 12 1 BRKENread-writeDisabledBreak inputs disabled0EnabledBreak inputs enabled1 ROS Run mode off-state configure 11 1 ROSread-writeDisabledWhen POEN is set, the channel output signals are disabled0EnabledWhen POEN is set, the channel output signals are enabled1 IOS Idle mode off-state configure 10 1 IOSread-writeDisabledWhen POEN is reset, the channel output signals are disabled0EnabledWhen POEN is reset, the channel output signals are enabled1 PROT Complementary register protect control 8 2 PROTread-writeDisabledWrite protection disabled0Mode0Protection mode 01Mode1Protection mode 12Mode2Protection mode 23 DTCFG Dead time configure 0 8 0255 DMACFG DMACFG DMA configuration register 0x48 0x20 read-write 0x00000000 DMATC DMA transfer count 8 5 031 DMATA DMA transfer access start address 0 5 031 DMATB DMATB DMA transfer buffer register 0x4C 0x20 read-write 0x00000000 DMATB DMA transfer buffer 0 16 065535 CFG CFG Configuration register 0xFC 0x20 read-write 0x00000000 OUTSEL The output value selection 0 1 CHVSEL Write CHxVAL register selection 1 1 TIMER1 General-purpose-timers TIMER 0x40000000 0x0 0x400 registers TIMER1 28 CTL0 CTL0 control register 0 0x0 0x20 read-write 0x00000000 CKDIV Clock division 8 2 ARSE Auto-reload shadow enable 7 1 CAM Counter aligns mode selection 5 2 DIR Direction 4 1 SPM Single pulse mode 3 1 SPMread-writeDisabledCounter is not stopped at update event0EnabledCounter stops counting at the next update event (clearing the CEN bit)1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 CTL1 CTL1 control register 1 0x04 0x20 read-write 0x00000000 TI0S Channel 0 trigger input selection 7 1 TI0Sread-writeNormalThe CH0 pin input is selected as channel 0 trigger input0XORThe XOR of CH0, CH1 and CH2 pins are selected as channel 0 trigger input1 MMC Master mode control 4 3 MMCread-writeResetUse UPG bit from SWEVG register0EnableUse CEN bit from CTL0 register1UpdateUse the update event2 DMAS DMA request source selection 3 1 DMASread-writeOnCompareCCx DMA request sent when CCx event occurs0OnUpdateCCx DMA request sent when update event occurs1 SMCFG SMCFG slave mode control register 0x08 0x20 read-write 0x00000000 ETP External trigger polarity 15 1 ETPread-writeNotInvertedETI is noninverted, active at high level or rising edge0InvertedETI is inverted, active at low level or falling edge1 SMC1 Part of SMC for enable External clock mode1 14 1 SMC1read-writeDisabledExternal clock mode 1 disabled0EnabledExternal clock mode 1 enabled. The counter is clocked by any active edge on the ETIF signal.1 ETPSC External trigger prescaler 12 2 ETPSCread-writeDiv1External trigger prescaler disabled0Div2ETI frequency divided by 21Div4ETI frequency divided by 42Div8ETI frequency divided by 83 ETFC External trigger filter control 8 4 ETFCread-writeNoFilterFilter disabled. fSAMP=fDTS, N=10TimerCk_N2fSAMP=fTIMER_CK, N=21TimerCk_N4fSAMP=fTIMER_CK, N=42TimerCk_N8fSAMP=fTIMER_CK, N=83FDTS_Div2_N6fSAMP=fDTS/2, N=64FDTS_Div2_N8fSAMP=fDTS/2, N=85FDTS_Div4_N6fSAMP=fDTS/4, N=66FDTS_Div4_N8fSAMP=fDTS/4, N=87FDTS_Div8_N6fSAMP=fDTS/8, N=68FDTS_Div8_N8fSAMP=fDTS/8, N=89FDTS_Div16_N5fSAMP=fDTS/16, N=510FDTS_Div16_N6fSAMP=fDTS/16, N=611FDTS_Div16_N8fSAMP=fDTS/16, N=812FDTS_Div32_N5fSAMP=fDTS/32, N=513FDTS_Div32_N6fSAMP=fDTS/32, N=614FDTS_Div32_N8fSAMP=fDTS/32, N=815 MSM Master-slave mode 7 1 MSMread-writeNoSyncNo action0SyncThe effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.1 TRGS Trigger selection 4 3 TRGSread-writeITI0Internal Trigger 0 (ITI0)0ITI1Internal Trigger 1 (ITI1)1ITI2Internal Trigger 2 (ITI2)2CI0F_EDCI0 Edge Detector (CI0F_ED)4CI0FE0Filtered Timer Input 0 (CI0FE0)5CI1FE1Filtered Timer Input 1 (CI1FE1)6ETIFPExternal Trigger input (ETIFP)7 SMC Slave mode control 0 3 SMCread-writeDisabledSlave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.0QuadratureDecoderMode0Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.1QuadratureDecoderMode1Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.2QuadratureDecoderMode2Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.3RestartModeRestart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.4PauseModePause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.5EventModeEvent Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.6ExternalClockModeExternal Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.7 DMAINTEN DMAINTEN DMA/Interrupt enable register 0x0C 0x20 read-write 0x00000000 TRGDEN Trigger DMA request enable 14 1 TRGDENread-writeDisabledTrigger DMA request disabled0EnabledTrigger DMA request enabled1 CH3DEN Channel 3 capture/compare DMA request enable 12 1 CH2DEN Channel 2 capture/compare DMA request enable 11 1 CH1DEN Channel 1 capture/compare DMA request enable 10 1 CH0DEN Channel 0 capture/compare DMA request enable 9 1 CH0DENread-writeDisabledCapture/compare DMA request disabled0EnabledCapture/compare DMA request enabled1 UPDEN Update DMA request enable 8 1 UPDENread-writeDisabledUpdate DMA request disabled0EnabledUpdate DMA request enabled1 TRGIE Trigger interrupt enable 6 1 TRGIEread-writeDisabledTrigger interrupt disabled0EnabledTrigger interrupt enabled1 CH3IE Channel 3 capture/compare interrupt enable 4 1 CH2IE Channel 2 capture/compare interrupt enable 3 1 CH1IE Channel 1 capture/compare interrupt enable 2 1 CH0IE Channel 0 capture/compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 0x20 read-write 0x00000000 CH3OF Channel 3 over capture flag 12 1 CH2OF Channel 2 over capture flag 11 1 CH1OF Channel 1 over capture flag 10 1 CH0OF Channel 0 over capture flag 9 1 TRGIF Trigger interrupt flag 6 1 TRGIFread-writeClearNo trigger event occured0TriggeredTrigger event occurred1 CH3IF Channel 3 capture/compare interrupt enable 4 1 CH2IF Channel 2 capture/compare interrupt enable 3 1 CH1IF Channel 1 capture/compare interrupt flag 2 1 CH0IF Channel 0 capture/compare interrupt flag 1 1 UPIF Update interrupt flag 0 1 SWEVG SWEVG event generation register 0x14 0x20 write-only 0x00000000 TRGG Trigger event generation 6 1 TRGGread-writeTriggerGenerate a trigger event1 CH3G Channel 3 capture or compare event generation 4 1 CH2G Channel 2 capture or compare event generation 3 1 CH1G Channel 1 capture or compare event generation 2 1 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x20 read-write 0x00000000 CH1COMCEN Channel 1 output compare clear enable 15 1 CH1COMCTL Channel 1 compare output control 12 3 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1MS Channel 1 mode selection 8 2 CH0COMCEN Channel 0 output compare clear enable 7 1 CH0COMCTL Channel 0 compare output control 4 3 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0MS Channel 0 I/O mode selection 0 2 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 0x20 read-write 0x00000000 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL1_Output CHCTL1_Output Channel control register 1 (output mode) 0x1C 0x20 read-write 0x00000000 CH3COMCEN Channel 3 output compare clear enable 15 1 CH3COMCTL Channel 3 compare output control 12 3 CH3COMSEN Channel 3 output compare shadow enable 11 1 CH3COMFEN Channel 3 output compare fast enable 10 1 CH3MS Channel 3 mode selection 8 2 CH2COMCEN Channel 2 output compare clear enable 7 1 CH2COMCTL Channel 2 compare output control 4 3 CH2COMSEN Channel 2 compare output shadow enable 3 1 CH2COMFEN Channel 2 output compare fast enable 2 1 CH2MS Channel 2 I/O mode selection 0 2 CHCTL1_Input CHCTL1_Input Channel control register 1 (input mode) CHCTL1_Output 0x1C 0x20 read-write 0x00000000 CH3CAPFLT Channel 3 input capture filter control 12 4 CH3CAPPSC Channel 3 input capture prescaler 10 2 CH3MS Channel 3 mode selection 8 2 CH2CAPFLT Channel 2 input capture filter control 4 4 CH2CAPPSC Channel 2 input capture prescaler 2 2 CH2MS Channel 2 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x20 read-write 0x00000000 CH3NP Channel 3 complementary output polarity 15 1 CH3P Channel 3 capture/compare function polarity 13 1 CH3EN Channel 3 capture/compare function enable 12 1 CH2NP Channel 2 complementary output polarity 11 1 CH2P Channel 2 capture/compare function polarity 9 1 CH2EN Channel 2 capture/compare function enable 8 1 CH1NP Channel 1 complementary output polarity 7 1 CH1P Channel 1 capture/compare function polarity 5 1 CH1EN Channel 1 capture/compare function enable 4 1 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare function polarity 1 1 CH0EN Channel 0 capture/compare function enable 0 1 CNT CNT Counter register 0x24 0x20 read-write 0x00000000 CNT counter value 0 32 065535 PSC PSC Prescaler register 0x28 0x20 read-write 0x00000000 PSC Prescaler value of the counter clock 0 16 065535 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x00000000 CAR Counter auto reload value 0 32 065535 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x20 read-write 0x00000000 CH0VAL Capture or compare value of channel 0 0 32 065535 CH1CV CH1CV Channel 1 capture/compare value register 0x38 0x20 read-write 0x00000000 CH1VAL Capture or compare value of channel1 0 32 065535 CH2CV CH2CV Channel 2 capture/compare value register 0x3C 0x20 read-write 0x00000000 CH2VAL Capture or compare value of channel 2 0 32 065535 CH3CV CH3CV Channel 3 capture/compare value register 0x40 0x20 read-write 0x00000000 CH3VAL Capture or compare value of channel 3 0 32 065535 DMACFG DMACFG DMA configuration register 0x48 0x20 read-write 0x00000000 DMATC DMA transfer count 8 5 031 DMATA DMA transfer access start address 0 5 031 DMATB DMATB DMA transfer buffer register 0x4C 0x20 read-write 0x00000000 DMATB DMA transfer buffer 0 16 065535 CFG CFG Configuration 0xFC 0x20 read-write 0x00000000 CHVSEL Write CHxVAL register selection 1 1 TIMER2 General-purpose-timers TIMER 0x40000400 0x0 0x400 registers TIMER2 29 CTL0 CTL0 control register 0 0x0 0x20 read-write 0x00000000 CKDIV Clock division 8 2 ARSE Auto-reload shadow enable 7 1 CAM Counter aligns mode selection 5 2 DIR Direction 4 1 SPM Single pulse mode 3 1 SPMread-writeDisabledCounter is not stopped at update event0EnabledCounter stops counting at the next update event (clearing the CEN bit)1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 CTL1 CTL1 control register 1 0x04 0x20 read-write 0x00000000 TI0S Channel 0 trigger input selection 7 1 TI0Sread-writeNormalThe CH0 pin input is selected as channel 0 trigger input0XORThe XOR of CH0, CH1 and CH2 pins are selected as channel 0 trigger input1 MMC Master mode control 4 3 MMCread-writeResetUse UPG bit from SWEVG register0EnableUse CEN bit from CTL0 register1UpdateUse the update event2 DMAS DMA request source selection 3 1 DMASread-writeOnCompareCCx DMA request sent when CCx event occurs0OnUpdateCCx DMA request sent when update event occurs1 SMCFG SMCFG slave mode control register 0x08 0x20 read-write 0x00000000 ETP External trigger polarity 15 1 ETPread-writeNotInvertedETI is noninverted, active at high level or rising edge0InvertedETI is inverted, active at low level or falling edge1 SMC1 Part of SMC for enable External clock mode1 14 1 SMC1read-writeDisabledExternal clock mode 1 disabled0EnabledExternal clock mode 1 enabled. The counter is clocked by any active edge on the ETIF signal.1 ETPSC External trigger prescaler 12 2 ETPSCread-writeDiv1External trigger prescaler disabled0Div2ETI frequency divided by 21Div4ETI frequency divided by 42Div8ETI frequency divided by 83 ETFC External trigger filter control 8 4 ETFCread-writeNoFilterFilter disabled. fSAMP=fDTS, N=10TimerCk_N2fSAMP=fTIMER_CK, N=21TimerCk_N4fSAMP=fTIMER_CK, N=42TimerCk_N8fSAMP=fTIMER_CK, N=83FDTS_Div2_N6fSAMP=fDTS/2, N=64FDTS_Div2_N8fSAMP=fDTS/2, N=85FDTS_Div4_N6fSAMP=fDTS/4, N=66FDTS_Div4_N8fSAMP=fDTS/4, N=87FDTS_Div8_N6fSAMP=fDTS/8, N=68FDTS_Div8_N8fSAMP=fDTS/8, N=89FDTS_Div16_N5fSAMP=fDTS/16, N=510FDTS_Div16_N6fSAMP=fDTS/16, N=611FDTS_Div16_N8fSAMP=fDTS/16, N=812FDTS_Div32_N5fSAMP=fDTS/32, N=513FDTS_Div32_N6fSAMP=fDTS/32, N=614FDTS_Div32_N8fSAMP=fDTS/32, N=815 MSM Master-slave mode 7 1 MSMread-writeNoSyncNo action0SyncThe effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.1 TRGS Trigger selection 4 3 TRGSread-writeITI0Internal Trigger 0 (ITI0)0ITI1Internal Trigger 1 (ITI1)1ITI2Internal Trigger 2 (ITI2)2CI0F_EDCI0 Edge Detector (CI0F_ED)4CI0FE0Filtered Timer Input 0 (CI0FE0)5CI1FE1Filtered Timer Input 1 (CI1FE1)6ETIFPExternal Trigger input (ETIFP)7 SMC Slave mode control 0 3 SMCread-writeDisabledSlave mode disabled - if CEN=1 then the prescaler is clocked directly by the internal clock.0QuadratureDecoderMode0Quadrature decoder mode 0 - Counter counts up/down on CI1FE1 edge depending on CI0FE0 level.1QuadratureDecoderMode1Quadrature decoder mode 1 - Counter counts up/down on CI0FE0 edge depending on CI1FE1 level.2QuadratureDecoderMode2Quadrature decoder mode 2 - Counter counts up/down on both CI0FE0 and CI1FE1 edges depending on the level of the other input.3RestartModeRestart Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.4PauseModePause Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.5EventModeEvent Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.6ExternalClockModeExternal Clock Mode 0 - Rising edges of the selected trigger (TRGI) clock the counter.7 DMAINTEN DMAINTEN DMA/Interrupt enable register 0x0C 0x20 read-write 0x00000000 TRGDEN Trigger DMA request enable 14 1 TRGDENread-writeDisabledTrigger DMA request disabled0EnabledTrigger DMA request enabled1 CH3DEN Channel 3 capture/compare DMA request enable 12 1 CH2DEN Channel 2 capture/compare DMA request enable 11 1 CH1DEN Channel 1 capture/compare DMA request enable 10 1 CH0DEN Channel 0 capture/compare DMA request enable 9 1 CH0DENread-writeDisabledCapture/compare DMA request disabled0EnabledCapture/compare DMA request enabled1 UPDEN Update DMA request enable 8 1 UPDENread-writeDisabledUpdate DMA request disabled0EnabledUpdate DMA request enabled1 TRGIE Trigger interrupt enable 6 1 TRGIEread-writeDisabledTrigger interrupt disabled0EnabledTrigger interrupt enabled1 CH3IE Channel 3 capture/compare interrupt enable 4 1 CH2IE Channel 2 capture/compare interrupt enable 3 1 CH1IE Channel 1 capture/compare interrupt enable 2 1 CH0IE Channel 0 capture/compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 0x20 read-write 0x00000000 CH3OF Channel 3 over capture flag 12 1 CH2OF Channel 2 over capture flag 11 1 CH1OF Channel 1 over capture flag 10 1 CH0OF Channel 0 over capture flag 9 1 TRGIF Trigger interrupt flag 6 1 TRGIFread-writeClearNo trigger event occured0TriggeredTrigger event occurred1 CH3IF Channel 3 capture/compare interrupt enable 4 1 CH2IF Channel 2 capture/compare interrupt enable 3 1 CH1IF Channel 1 capture/compare interrupt flag 2 1 CH0IF Channel 0 capture/compare interrupt flag 1 1 UPIF Update interrupt flag 0 1 SWEVG SWEVG event generation register 0x14 0x20 write-only 0x00000000 TRGG Trigger event generation 6 1 TRGGread-writeTriggerGenerate a trigger event1 CH3G Channel 3 capture or compare event generation 4 1 CH2G Channel 2 capture or compare event generation 3 1 CH1G Channel 1 capture or compare event generation 2 1 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x20 read-write 0x00000000 CH1COMCEN Channel 1 output compare clear enable 15 1 CH1COMCTL Channel 1 compare output control 12 3 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1MS Channel 1 mode selection 8 2 CH0COMCEN Channel 0 output compare clear enable 7 1 CH0COMCTL Channel 0 compare output control 4 3 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0MS Channel 0 I/O mode selection 0 2 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 0x20 read-write 0x00000000 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL1_Output CHCTL1_Output Channel control register 1 (output mode) 0x1C 0x20 read-write 0x00000000 CH3COMCEN Channel 3 output compare clear enable 15 1 CH3COMCTL Channel 3 compare output control 12 3 CH3COMSEN Channel 3 output compare shadow enable 11 1 CH3COMFEN Channel 3 output compare fast enable 10 1 CH3MS Channel 3 mode selection 8 2 CH2COMCEN Channel 2 output compare clear enable 7 1 CH2COMCTL Channel 2 compare output control 4 3 CH2COMSEN Channel 2 compare output shadow enable 3 1 CH2COMFEN Channel 2 output compare fast enable 2 1 CH2MS Channel 2 I/O mode selection 0 2 CHCTL1_Input CHCTL1_Input Channel control register 1 (input mode) CHCTL1_Output 0x1C 0x20 read-write 0x00000000 CH3CAPFLT Channel 3 input capture filter control 12 4 CH3CAPPSC Channel 3 input capture prescaler 10 2 CH3MS Channel 3 mode selection 8 2 CH2CAPFLT Channel 2 input capture filter control 4 4 CH2CAPPSC Channel 2 input capture prescaler 2 2 CH2MS Channel 2 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x20 read-write 0x00000000 CH3NP Channel 3 complementary output polarity 15 1 CH3P Channel 3 capture/compare function polarity 13 1 CH3EN Channel 3 capture/compare function enable 12 1 CH2NP Channel 2 complementary output polarity 11 1 CH2P Channel 2 capture/compare function polarity 9 1 CH2EN Channel 2 capture/compare function enable 8 1 CH1NP Channel 1 complementary output polarity 7 1 CH1P Channel 1 capture/compare function polarity 5 1 CH1EN Channel 1 capture/compare function enable 4 1 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare function polarity 1 1 CH0EN Channel 0 capture/compare function enable 0 1 CNT CNT Counter register 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 065535 PSC PSC Prescaler register 0x28 0x20 read-write 0x00000000 PSC Prescaler value of the counter clock 0 16 065535 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x00000000 CAR Counter auto reload value 0 16 065535 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x20 read-write 0x00000000 CH0VAL Capture or compare value of channel 0 0 16 065535 CH1CV CH1CV Channel 1 capture/compare value register 0x38 0x20 read-write 0x00000000 CH1VAL Capture or compare value of channel1 0 16 065535 CH2CV CH2CV Channel 2 capture/compare value register 0x3C 0x20 read-write 0x00000000 CH2VAL Capture or compare value of channel 2 0 16 065535 CH3CV CH3CV Channel 3 capture/compare value register 0x40 0x20 read-write 0x00000000 CH3VAL Capture or compare value of channel 3 0 16 065535 DMACFG DMACFG DMA configuration register 0x48 0x20 read-write 0x00000000 DMATC DMA transfer count 8 5 031 DMATA DMA transfer access start address 0 5 031 DMATB DMATB DMA transfer buffer register 0x4C 0x20 read-write 0x00000000 DMATB DMA transfer buffer 0 16 065535 CFG CFG Configuration 0xFC 0x20 read-write 0x00000000 CHVSEL Write CHxVAL register selection 1 1 TIMER3 General-purpose-timers TIMER 0x40000800 0x0 0x400 registers TIMER3 30 CTL0 CTL0 control register 0 0x0 0x20 read-write 0x00000000 CKDIV Clock division 8 2 ARSE Auto-reload shadow enable 7 1 CAM Counter aligns mode selection 5 2 DIR Direction 4 1 SPM Single pulse mode 3 1 SPMread-writeDisabledCounter is not stopped at update event0EnabledCounter stops counting at the next update event (clearing the CEN bit)1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 CTL1 CTL1 control register 1 0x04 0x20 read-write 0x00000000 TI0S Channel 0 trigger input selection 7 1 MMC Master mode control 4 3 MMCread-writeResetUse UPG bit from SWEVG register0EnableUse CEN bit from CTL0 register1UpdateUse the update event2 DMAS DMA request source selection 3 1 DMASread-writeOnCompareCCx DMA request sent when CCx event occurs0OnUpdateCCx DMA request sent when update event occurs1 SMCFG SMCFG slave mode control register 0x08 0x20 read-write 0x00000000 ETP External trigger polarity 15 1 SMC1 Part of SMC for enable External clock mode1 14 1 ETPSC External trigger prescaler 12 2 ETFC External trigger filter control 8 4 MSM Master-slave mode 7 1 TRGS Trigger selection 4 3 SMC Slave mode control 0 3 DMAINTEN DMAINTEN DMA/Interrupt enable register 0x0C 0x20 read-write 0x00000000 TRGDEN Trigger DMA request enable 14 1 CH3DEN Channel 3 capture/compare DMA request enable 12 1 CH2DEN Channel 2 capture/compare DMA request enable 11 1 CH1DEN Channel 1 capture/compare DMA request enable 10 1 CH0DEN Channel 0 capture/compare DMA request enable 9 1 CH0DENread-writeDisabledCapture/compare DMA request disabled0EnabledCapture/compare DMA request enabled1 UPDEN Update DMA request enable 8 1 UPDENread-writeDisabledUpdate DMA request disabled0EnabledUpdate DMA request enabled1 TRGIE Trigger interrupt enable 6 1 CH3IE Channel 3 capture/compare interrupt enable 4 1 CH2IE Channel 2 capture/compare interrupt enable 3 1 CH1IE Channel 1 capture/compare interrupt enable 2 1 CH0IE Channel 0 capture/compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 0x20 read-write 0x00000000 CH3OF Channel 3 over capture flag 12 1 CH2OF Channel 2 over capture flag 11 1 CH1OF Channel 1 over capture flag 10 1 CH0OF Channel 0 over capture flag 9 1 TRGIF Trigger interrupt flag 6 1 CH3IF Channel 3 capture/compare interrupt enable 4 1 CH2IF Channel 2 capture/compare interrupt enable 3 1 CH1IF Channel 1 capture/compare interrupt flag 2 1 CH0IF Channel 0 capture/compare interrupt flag 1 1 UPIF Update interrupt flag 0 1 SWEVG SWEVG event generation register 0x14 0x20 write-only 0x00000000 TRGG Trigger event generation 6 1 CH3G Channel 3 capture or compare event generation 4 1 CH2G Channel 2 capture or compare event generation 3 1 CH1G Channel 1 capture or compare event generation 2 1 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x20 read-write 0x00000000 CH1COMCEN Channel 1 output compare clear enable 15 1 CH1COMCTL Channel 1 compare output control 12 3 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1MS Channel 1 mode selection 8 2 CH0COMCEN Channel 0 output compare clear enable 7 1 CH0COMCTL Channel 0 compare output control 4 3 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0MS Channel 0 I/O mode selection 0 2 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 0x20 read-write 0x00000000 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL1_Output CHCTL1_Output Channel control register 1 (output mode) 0x1C 0x20 read-write 0x00000000 CH3COMCEN Channel 3 output compare clear enable 15 1 CH3COMCTL Channel 3 compare output control 12 3 CH3COMSEN Channel 3 output compare shadow enable 11 1 CH3COMFEN Channel 3 output compare fast enable 10 1 CH3MS Channel 3 mode selection 8 2 CH2COMCEN Channel 2 output compare clear enable 7 1 CH2COMCTL Channel 2 compare output control 4 3 CH2COMSEN Channel 2 compare output shadow enable 3 1 CH2COMFEN Channel 2 output compare fast enable 2 1 CH2MS Channel 2 I/O mode selection 0 2 CHCTL1_Input CHCTL1_Input Channel control register 1 (input mode) CHCTL1_Output 0x1C 0x20 read-write 0x00000000 CH3CAPFLT Channel 3 input capture filter control 12 4 CH3CAPPSC Channel 3 input capture prescaler 10 2 CH3MS Channel 3 mode selection 8 2 CH2CAPFLT Channel 2 input capture filter control 4 4 CH2CAPPSC Channel 2 input capture prescaler 2 2 CH2MS Channel 2 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x20 read-write 0x00000000 CH3NP Channel 3 complementary output polarity 15 1 CH3P Channel 3 capture/compare function polarity 13 1 CH3EN Channel 3 capture/compare function enable 12 1 CH2NP Channel 2 complementary output polarity 11 1 CH2P Channel 2 capture/compare function polarity 9 1 CH2EN Channel 2 capture/compare function enable 8 1 CH1NP Channel 1 complementary output polarity 7 1 CH1P Channel 1 capture/compare function polarity 5 1 CH1EN Channel 1 capture/compare function enable 4 1 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare function polarity 1 1 CH0EN Channel 0 capture/compare function enable 0 1 CNT CNT Counter register 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 065535 PSC PSC Prescaler register 0x28 0x20 read-write 0x00000000 PSC Prescaler value of the counter clock 0 16 065535 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x00000000 CAR Counter auto reload value 0 16 065535 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x20 read-write 0x00000000 CH0VAL Capture or compare value of channel 0 0 16 065535 CH1CV CH1CV Channel 1 capture/compare value register 0x38 0x20 read-write 0x00000000 CH1VAL Capture or compare value of channel1 0 16 065535 CH2CV CH2CV Channel 2 capture/compare value register 0x3C 0x20 read-write 0x00000000 CH2VAL Capture or compare value of channel 2 0 16 065535 CH3CV CH3CV Channel 3 capture/compare value register 0x40 0x20 read-write 0x00000000 CH3VAL Capture or compare value of channel 3 0 16 065535 DMACFG DMACFG DMA configuration register 0x48 0x20 read-write 0x00000000 DMATC DMA transfer count 8 5 031 DMATA DMA transfer access start address 0 5 031 DMATB DMATB DMA transfer buffer register 0x4C 0x20 read-write 0x00000000 DMATB DMA transfer buffer 0 16 065535 CFG CFG Configuration 0xFC 0x20 read-write 0x00000000 CHVSEL Write CHxVAL register selection 1 1 TIMER4 General-purpose-timers TIMER 0x40000C00 0x0 0x400 registers TIMER4 50 CTL0 CTL0 control register 0 0x0 0x20 read-write 0x00000000 CKDIV Clock division 8 2 ARSE Auto-reload shadow enable 7 1 CAM Counter aligns mode selection 5 2 DIR Direction 4 1 SPM Single pulse mode 3 1 SPMread-writeDisabledCounter is not stopped at update event0EnabledCounter stops counting at the next update event (clearing the CEN bit)1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 CTL1 CTL1 control register 1 0x04 0x20 read-write 0x00000000 TI0S Channel 0 trigger input selection 7 1 MMC Master mode control 4 3 MMCread-writeResetUse UPG bit from SWEVG register0EnableUse CEN bit from CTL0 register1UpdateUse the update event2 DMAS DMA request source selection 3 1 DMASread-writeOnCompareCCx DMA request sent when CCx event occurs0OnUpdateCCx DMA request sent when update event occurs1 SMCFG SMCFG slave mode control register 0x08 0x20 read-write 0x00000000 ETP External trigger polarity 15 1 SMC1 Part of SMC for enable External clock mode1 14 1 ETPSC External trigger prescaler 12 2 ETFC External trigger filter control 8 4 MSM Master-slave mode 7 1 TRGS Trigger selection 4 3 SMC Slave mode control 0 3 DMAINTEN DMAINTEN DMA/Interrupt enable register 0x0C 0x20 read-write 0x00000000 TRGDEN Trigger DMA request enable 14 1 CH3DEN Channel 3 capture/compare DMA request enable 12 1 CH2DEN Channel 2 capture/compare DMA request enable 11 1 CH1DEN Channel 1 capture/compare DMA request enable 10 1 CH0DEN Channel 0 capture/compare DMA request enable 9 1 CH0DENread-writeDisabledCapture/compare DMA request disabled0EnabledCapture/compare DMA request enabled1 UPDEN Update DMA request enable 8 1 UPDENread-writeDisabledUpdate DMA request disabled0EnabledUpdate DMA request enabled1 TRGIE Trigger interrupt enable 6 1 CH3IE Channel 3 capture/compare interrupt enable 4 1 CH2IE Channel 2 capture/compare interrupt enable 3 1 CH1IE Channel 1 capture/compare interrupt enable 2 1 CH0IE Channel 0 capture/compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 0x20 read-write 0x00000000 CH3OF Channel 3 over capture flag 12 1 CH2OF Channel 2 over capture flag 11 1 CH1OF Channel 1 over capture flag 10 1 CH0OF Channel 0 over capture flag 9 1 TRGIF Trigger interrupt flag 6 1 CH3IF Channel 3 capture/compare interrupt enable 4 1 CH2IF Channel 2 capture/compare interrupt enable 3 1 CH1IF Channel 1 capture/compare interrupt flag 2 1 CH0IF Channel 0 capture/compare interrupt flag 1 1 UPIF Update interrupt flag 0 1 SWEVG SWEVG event generation register 0x14 0x20 write-only 0x00000000 TRGG Trigger event generation 6 1 CH3G Channel 3 capture or compare event generation 4 1 CH2G Channel 2 capture or compare event generation 3 1 CH1G Channel 1 capture or compare event generation 2 1 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x20 read-write 0x00000000 CH1COMCEN Channel 1 output compare clear enable 15 1 CH1COMCTL Channel 1 compare output control 12 3 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1MS Channel 1 mode selection 8 2 CH0COMCEN Channel 0 output compare clear enable 7 1 CH0COMCTL Channel 0 compare output control 4 3 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0MS Channel 0 I/O mode selection 0 2 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 0x20 read-write 0x00000000 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL1_Output CHCTL1_Output Channel control register 1 (output mode) 0x1C 0x20 read-write 0x00000000 CH3COMCEN Channel 3 output compare clear enable 15 1 CH3COMCTL Channel 3 compare output control 12 3 CH3COMSEN Channel 3 output compare shadow enable 11 1 CH3COMFEN Channel 3 output compare fast enable 10 1 CH3MS Channel 3 mode selection 8 2 CH2COMCEN Channel 2 output compare clear enable 7 1 CH2COMCTL Channel 2 compare output control 4 3 CH2COMSEN Channel 2 compare output shadow enable 3 1 CH2COMFEN Channel 2 output compare fast enable 2 1 CH2MS Channel 2 I/O mode selection 0 2 CHCTL1_Input CHCTL1_Input Channel control register 1 (input mode) CHCTL1_Output 0x1C 0x20 read-write 0x00000000 CH3CAPFLT Channel 3 input capture filter control 12 4 CH3CAPPSC Channel 3 input capture prescaler 10 2 CH3MS Channel 3 mode selection 8 2 CH2CAPFLT Channel 2 input capture filter control 4 4 CH2CAPPSC Channel 2 input capture prescaler 2 2 CH2MS Channel 2 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x20 read-write 0x00000000 CH3NP Channel 3 complementary output polarity 15 1 CH3P Channel 3 capture/compare function polarity 13 1 CH3EN Channel 3 capture/compare function enable 12 1 CH2NP Channel 2 complementary output polarity 11 1 CH2P Channel 2 capture/compare function polarity 9 1 CH2EN Channel 2 capture/compare function enable 8 1 CH1NP Channel 1 complementary output polarity 7 1 CH1P Channel 1 capture/compare function polarity 5 1 CH1EN Channel 1 capture/compare function enable 4 1 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare function polarity 1 1 CH0EN Channel 0 capture/compare function enable 0 1 CNT CNT Counter register 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 065535 PSC PSC Prescaler register 0x28 0x20 read-write 0x00000000 PSC Prescaler value of the counter clock 0 16 065535 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x00000000 CAR Counter auto reload value 0 16 065535 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x20 read-write 0x00000000 CH0VAL Capture or compare value of channel 0 0 16 065535 CH1CV CH1CV Channel 1 capture/compare value register 0x38 0x20 read-write 0x00000000 CH1VAL Capture or compare value of channel1 0 16 065535 CH2CV CH2CV Channel 2 capture/compare value register 0x3C 0x20 read-write 0x00000000 CH2VAL Capture or compare value of channel 2 0 16 065535 CH3CV CH3CV Channel 3 capture/compare value register 0x40 0x20 read-write 0x00000000 CH3VAL Capture or compare value of channel 3 0 16 065535 DMACFG DMACFG DMA configuration register 0x48 0x20 read-write 0x00000000 DMATC DMA transfer count 8 5 031 DMATA DMA transfer access start address 0 5 031 DMATB DMATB DMA transfer buffer register 0x4C 0x20 read-write 0x00000000 DMATB DMA transfer buffer 0 16 065535 CFG CFG Configuration 0xFC 0x20 read-write 0x00000000 CHVSEL Write CHxVAL register selection 1 1 TIMER5 Basic-timers TIMER 0x40001000 0x0 0x400 registers TIMER5 54 CTL0 CTL0 control register 0 0x0 0x20 read-write 0x00000000 ARSE Auto-reload shadow enable 7 1 SPM Single pulse mode 3 1 SPMread-writeDisabledCounter is not stopped at update event0EnabledCounter stops counting at the next update event (clearing the CEN bit)1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 CTL1 CTL1 control register 1 0x04 0x20 read-write 0x00000000 MMC Master mode control 4 3 MMCread-writeResetUse UPG bit from SWEVG register0EnableUse CEN bit from CTL0 register1UpdateUse the update event2 DMAINTEN DMAINTEN DMA/Interrupt enable register 0x0C 0x20 read-write 0x00000000 UPDEN Update DMA request enable 8 1 UPDENread-writeDisabledUpdate DMA request disabled0EnabledUpdate DMA request enabled1 UPIE Update interrupt enable 0 1 INTF INTF Interrupt flag register 0x10 0x20 read-write 0x00000000 UPIF Update interrupt flag 0 1 SWEVG SWEVG event generation register 0x14 0x20 write-only 0x00000000 UPG Update generation 0 1 CNT CNT Counter register 0x24 0x20 read-write 0x00000000 CNT Low counter value 0 16 065535 PSC PSC Prescaler register 0x28 0x20 read-write 0x00000000 PSC Prescaler value of the counter clock 0 16 065535 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x00000000 CAR Counter auto reload value 0 16 065535 TIMER6 Basic-timers TIMER 0x40001400 0x0 0x400 registers TIMER6 55 CTL0 CTL0 control register 0 0x0 0x20 read-write 0x00000000 ARSE Auto-reload shadow enable 7 1 SPM Single pulse mode 3 1 SPMread-writeDisabledCounter is not stopped at update event0EnabledCounter stops counting at the next update event (clearing the CEN bit)1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 CTL1 CTL1 control register 1 0x04 0x20 read-write 0x00000000 MMC Master mode control 4 3 DMAINTEN DMAINTEN DMA/Interrupt enable register 0x0C 0x20 read-write 0x00000000 UPDEN Update DMA request enable 8 1 UPDENread-writeDisabledUpdate DMA request disabled0EnabledUpdate DMA request enabled1 UPIE Update interrupt enable 0 1 INTF INTF Interrupt flag register 0x10 0x20 read-write 0x00000000 UPIF Update interrupt flag 0 1 SWEVG SWEVG event generation register 0x14 0x20 write-only 0x00000000 UPG Update generation 0 1 CNT CNT Counter register 0x24 0x20 read-write 0x00000000 CNT Low counter value 0 16 065535 PSC PSC Prescaler register 0x28 0x20 read-write 0x00000000 PSC Prescaler value of the counter clock 0 16 065535 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x00000000 CAR Counter auto reload value 0 16 065535 TIMER7 Advanced-timers TIMER 0x40013400 0x0 0x400 registers TIMER7_BRK_TIMER11 43 TIMER7_UP_TIMER12 44 TIMER7_TRG_CMT_TIMER13 45 TIMER7_CC 46 CTL0 CTL0 control register 0 0x0 0x20 read-write 0x00000000 CKDIV Clock division 8 2 ARSE Auto-reload shadow enable 7 1 CAM Counter aligns mode selection 5 2 DIR Direction 4 1 SPM Single pulse mode 3 1 SPMread-writeDisabledCounter is not stopped at update event0EnabledCounter stops counting at the next update event (clearing the CEN bit)1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 CTL1 CTL1 control register 1 0x04 0x20 read-write 0x00000000 ISO3 Idle state of channel 3 output 14 1 ISO2N Idle state of channel 2 complementary output 13 1 ISO2 Idle state of channel 2 output 12 1 ISO1N Idle state of channel 1 complementary output 11 1 ISO1 Idle state of channel 1 output 10 1 ISO0N Idle state of channel 0 complementary output 9 1 ISO0 Idle state of channel 0 output 8 1 TI0S Channel 0 trigger input selection 7 1 MMC Master mode control 4 3 DMAS DMA request source selection 3 1 DMASread-writeOnCompareCCx DMA request sent when CCx event occurs0OnUpdateCCx DMA request sent when update event occurs1 CCUC Commutation control shadow register update control 2 1 CCSE Commutation control shadow enable 0 1 SMCFG SMCFG slave mode configuration register 0x08 0x20 read-write 0x00000000 ETP External trigger polarity 15 1 SMC1 Part of SMC for enable External clock mode1 14 1 ETPSC External trigger prescaler 12 2 ETFC External trigger filter control 8 4 MSM Master/Slave mode 7 1 TRGS Trigger selection 4 3 SMC Slave mode selection 0 3 DMAINTEN DMAINTEN DMA/Interrupt enable register 0x0C 0x20 read-write 0x00000000 TRGDEN Trigger DMA request enable 14 1 CMTDEN Commutation DMA request enable 13 1 CH3DEN Channel 3 capture/compare DMA request enable 12 1 CH2DEN Channel 2 capture/compare DMA request enable 11 1 CH1DEN Channel 1 capture/compare DMA request enable 10 1 CH0DEN Channel 0 capture/compare DMA request enable 9 1 CH0DENread-writeDisabledCapture/compare DMA request disabled0EnabledCapture/compare DMA request enabled1 UPDEN Update DMA request enable 8 1 UPDENread-writeDisabledUpdate DMA request disabled0EnabledUpdate DMA request enabled1 BRKIE Break interrupt enable 7 1 TRGIE Trigger interrupt enable 6 1 CMTIE commutation interrupt enable 5 1 CH3IE Channel 3 capture/compare interrupt enable 4 1 CH2IE Channel 2 capture/compare interrupt enable 3 1 CH1IE Channel 1 capture/compare interrupt enable 2 1 CH0IE Channel 0 capture/compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF Interrupt flag register 0x10 0x20 read-write 0x00000000 CH3OF Channel 3 over capture flag 12 1 CH2OF Channel 2 over capture flag 11 1 CH1OF Channel 1 over capture flag 10 1 CH0OF Channel 0 over capture flag 9 1 BRKIF Break interrupt flag 7 1 TRGIF Trigger interrupt flag 6 1 CMTIF Channel commutation interrupt flag 5 1 CH3IF Channel 3 capture/compare interrupt flag 4 1 CH2IF Channel 2 capture/compare interrupt flag 3 1 CH1IF Channel 1 capture/compare interrupt flag 2 1 CH0IF Channel 0 capture/compare interrupt flag 1 1 UPIF Update interrupt flag 0 1 SWEVG SWEVG Software event generation register 0x14 0x20 write-only 0x00000000 BRKG Break event generation 7 1 TRGG Trigger event generation 6 1 CMTG Channel commutation event generation 5 1 CH3G Channel 3 capture or compare event generation 4 1 CH2G Channel 2 capture or compare event generation 3 1 CH1G Channel 1 capture or compare event generation 2 1 CH0G Channel 0 capture or compare event generation 1 1 UPG Update event generation 0 1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x20 read-write 0x00000000 CH1COMCEN Channel 1 output compare clear enable 15 1 CH1COMCTL Channel 1 compare output control 12 3 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1MS Channel 1 mode selection 8 2 CH0COMCEN Channel 0 output compare clear enable 7 1 CH0COMCTL Channel 0 compare output control 4 3 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0MS Channel 0 I/O mode selection 0 2 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 0x20 read-write 0x00000000 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL1_Output CHCTL1_Output Channel control register 1 (output mode) 0x1C 0x20 read-write 0x00000000 CH3COMCEN Channel 3 output compare clear enable 15 1 CH3COMCTL Channel 3 compare output control 12 3 CH3COMSEN Channel 3 output compare shadow enable 11 1 CH3COMFEN Channel 3 output compare fast enable 10 1 CH3MS Channel 3 mode selection 8 2 CH2COMCEN Channel 2 output compare clear enable 7 1 CH2COMCTL Channel 2 compare output control 4 3 CH2COMSEN Channel 2 compare output shadow enable 3 1 CH2COMFEN Channel 2 output compare fast enable 2 1 CH2MS Channel 2 I/O mode selection 0 2 CHCTL1_Input CHCTL1_Input Channel control register 1 (input mode) CHCTL1_Output 0x1C 0x20 read-write 0x00000000 CH3CAPFLT Channel 3 input capture filter control 12 4 CH3CAPPSC Channel 3 input capture prescaler 10 2 CH3MS Channel 3 mode selection 8 2 CH2CAPFLT Channel 2 input capture filter control 4 4 CH2CAPPSC Channel 2 input capture prescaler 2 2 CH2MS Channel 2 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x20 read-write 0x00000000 CH3P Channel 3 capture/compare function polarity 13 1 CH3EN Channel 3 capture/compare function enable 12 1 CH2NP Channel 2 complementary output polarity 11 1 CH2NEN Channel 2 complementary output enable 10 1 CH2P Channel 2 capture/compare function polarity 9 1 CH2EN Channel 2 capture/compare function enable 8 1 CH1NP Channel 1 complementary output polarity 7 1 CH1NEN Channel 1 complementary output enable 6 1 CH1P Channel 1 capture/compare function polarity 5 1 CH1EN Channel 1 capture/compare function enable 4 1 CH0NP Channel 0 complementary output polarity 3 1 CH0NEN Channel 0 complementary output enable 2 1 CH0P Channel 0 capture/compare function polarity 1 1 CH0EN Channel 0 capture/compare function enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT current counter value 0 16 065535 PSC PSC prescaler 0x28 0x20 read-write 0x00000000 PSC Prescaler value of the counter clock 0 16 065535 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x00000000 CAR Counter auto reload value 0 16 065535 CREP CREP Counter repetition register 0x30 0x20 read-write 0x00000000 CREP Counter repetition value 0 8 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x20 read-write 0x00000000 CH0VAL Capture or compare value of channel0 0 16 065535 CH1CV CH1CV Channel 1 capture/compare value register 0x38 0x20 read-write 0x00000000 CH1VAL Capture or compare value of channel1 0 16 065535 CH2CV CH2CV Channel 2 capture/compare value register 0x3C 0x20 read-write 0x00000000 CH2VAL Capture or compare value of channel 2 0 16 065535 CH3CV CH3CV Channel 3 capture/compare value register 0x40 0x20 read-write 0x00000000 CH3VAL Capture or compare value of channel 3 0 16 065535 CCHP CCHP channel complementary protection register 0x44 0x20 read-write 0x00000000 POEN Primary output enable 15 1 OAEN Output automatic enable 14 1 BRKP Break polarity 13 1 BRKEN Break enable 12 1 ROS Run mode off-state configure 11 1 IOS Idle mode off-state configure 10 1 PROT Complementary register protect control 8 2 DTCFG Dead time configure 0 8 DMACFG DMACFG DMA configuration register 0x48 0x20 read-write 0x00000000 DMATC DMA transfer count 8 5 031 DMATA DMA transfer access start address 0 5 031 DMATB DMATB DMA transfer buffer register 0x4C 0x20 read-write 0x00000000 DMATB DMA transfer buffer 0 16 065535 CFG CFG Configuration register 0xFC 0x20 read-write 0x00000000 OUTSEL The output value selection 0 1 CHVSEL Write CHxVAL register selection 1 1 TIMER8 General-purpose-timers TIMER 0x40014c00 0x0 0x400 registers TIMER0_BRK_TIMER8 24 CTL0 CTL0 control register 0 0x0 0x20 read-write 0x00000000 CKDIV Clock division 8 2 ARSE Auto-reload shadow enable 7 1 SPM Single pulse mode 3 1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 SMCFG SMCFG slave mode configuration register 0x08 0x20 read-write 0x00000000 MSM Master-slave mode 7 1 TRGS Trigger selection 4 3 SMC Slave mode control 0 3 DMAINTEN DMAINTEN DMA and interrupt enable register 0x0C 0x20 read-write 0x00000000 TRGIE Trigger interrupt enable 6 1 CH1IE Channel 1 capture/compare interrupt enable 2 1 CH0IE Channel 0 capture/compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 0x20 read-write 0x00000000 CH1OF Channel 1 over capture flag 10 1 CH0OF Channel 0 over capture flag 9 1 TRGIF Trigger interrupt flag 6 1 CH1IF Channel 1 capture/compare interrupt flag 2 1 CH0IF Channel 0 capture/compare interrupt flag 1 1 UPIF Update interrupt flag 0 1 SWEVG SWEVG event generation register 0x14 0x20 write-only 0x00000000 TRGG Trigger event generation 6 1 CH1G Channel 1 capture or compare event generation 2 1 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x20 read-write 0x00000000 CH1COMCTL Channel 1 compare output control 12 3 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1MS Channel 1 mode selection 8 2 CH0COMCTL Channel 0 compare output control 4 3 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0MS Channel 0 I/O mode selection 0 2 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 0x20 read-write 0x00000000 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x20 read-write 0x00000000 CH1NP Channel 1 complementary output polarity 7 1 CH1P Channel 1 capture/compare function polarity 5 1 CH1EN Channel 1 capture/compare function enable 4 1 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare function polarity 1 1 CH0EN Channel 0 capture/compare function enable 0 1 CNT CNT Counter register 0x24 0x20 read-write 0x00000000 CNT current counter value 0 16 065535 PSC PSC Prescaler register 0x28 0x20 read-write 0x00000000 PSC Prescaler value of the counter clock 0 16 065535 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x00000000 CAR Counter auto reload value 0 16 065535 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x20 read-write 0x00000000 CH0VAL Capture or compare value of channel0 0 16 065535 CH1CV CH1CV Channel 1 capture/compare value register 0x38 0x20 read-write 0x00000000 CH1VAL Capture or compare value of channel1 0 16 065535 CFG CFG configuration register 0xFC 0x20 read-write 0x00000000 CHVSEL Write CHxVAL register selection 1 1 TIMER9 General-purpose-timers TIMER 0x40015000 0x0 0x400 registers TIMER0_UP_TIMER9 25 CTL0 CTL0 control register 0 0x00 0x20 read-write 0x00000000 CKDIV Clock division 8 2 ARSE Auto-reload shadow enable 7 1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 CTL1 CTL1 control register 1 0x04 0x20 read-write 0x00000000 MMC Master mode control 4 3 DMAINTEN DMAINTEN DMA/Interrupt enable register 0x0C 0x20 read-write 0x00000000 CH0IE Channel 0 capture/compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 0x20 read-write 0x00000000 CH0OF Channel 0 over capture flag 9 1 CH0IF Channel 0 capture/compare interrupt flag 1 1 UPIF Update interrupt flag 0 1 SWEVG SWEVG event generation register 0x14 0x20 write-only 0x00000000 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x20 read-write 0x00000000 CH0MS Channel 0 I/O mode selection 0 2 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0COMCTL Channel 0 compare output control 4 3 CHCTL0_Input CHCTL0_Input Channel control register 0 ( (input mode) CHCTL0_Output 0x18 0x20 read-write 0x00000000 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x20 read-write 0x00000000 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare polarity 1 1 CH0EN Channel 0 capture/compare function enable 0 1 CNT CNT Counter register 0x24 0x20 read-write 0x00000000 CNT current counter value 0 16 065535 PSC PSC Prescaler register 0x28 0x20 read-write 0x00000000 PSC Prescaler value of the counter clock 0 16 065535 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x00000000 CAR Counter auto reload value 0 16 065535 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x20 read-write 0x00000000 CH0VAL Capture or compare value of channel 0 0 16 065535 CFG CFG configuration register 0xFC 0x20 read-write 0x00000000 CHVSEL Write CHxVAL register selection 1 1 TIMER10 General-purpose-timers TIMER 0x40015400 0x0 0x400 registers TIMER0_TRG_CMT_TIMER10 26 CTL0 CTL0 control register 0 0x00 0x20 read-write 0x00000000 CKDIV Clock division 8 2 ARSE Auto-reload shadow enable 7 1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 CTL1 CTL1 control register 1 0x04 0x20 read-write 0x00000000 MMC Master mode control 4 3 DMAINTEN DMAINTEN DMA/Interrupt enable register 0x0C 0x20 read-write 0x00000000 CH0IE Channel 0 capture/compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 0x20 read-write 0x00000000 CH0OF Channel 0 over capture flag 9 1 CH0IF Channel 0 capture/compare interrupt flag 1 1 UPIF Update interrupt flag 0 1 SWEVG SWEVG event generation register 0x14 0x20 write-only 0x00000000 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x20 read-write 0x00000000 CH0MS Channel 0 I/O mode selection 0 2 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0COMCTL Channel 0 compare output control 4 3 CHCTL0_Input CHCTL0_Input Channel control register 0 ( (input mode) CHCTL0_Output 0x18 0x20 read-write 0x00000000 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x20 read-write 0x00000000 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare polarity 1 1 CH0EN Channel 0 capture/compare function enable 0 1 CNT CNT Counter register 0x24 0x20 read-write 0x00000000 CNT current counter value 0 16 065535 PSC PSC Prescaler register 0x28 0x20 read-write 0x00000000 PSC Prescaler value of the counter clock 0 16 065535 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x00000000 CAR Counter auto reload value 0 16 065535 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x20 read-write 0x00000000 CH0VAL Capture or compare value of channel 0 0 16 065535 CFG CFG configuration register 0xFC 0x20 read-write 0x00000000 CHVSEL Write CHxVAL register selection 1 1 TIMER11 General-purpose-timers TIMER 0x40001800 0x0 0x400 registers TIMER7_BRK_TIMER11 43 CTL0 CTL0 control register 0 0x0 0x20 read-write 0x00000000 CKDIV Clock division 8 2 ARSE Auto-reload shadow enable 7 1 SPM Single pulse mode 3 1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 SMCFG SMCFG slave mode configuration register 0x08 0x20 read-write 0x00000000 MSM Master-slave mode 7 1 TRGS Trigger selection 4 3 SMC Slave mode control 0 3 DMAINTEN DMAINTEN DMA and interrupt enable register 0x0C 0x20 read-write 0x00000000 TRGIE Trigger interrupt enable 6 1 CH1IE Channel 1 capture/compare interrupt enable 2 1 CH0IE Channel 0 capture/compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 0x20 read-write 0x00000000 CH1OF Channel 1 over capture flag 10 1 CH0OF Channel 0 over capture flag 9 1 TRGIF Trigger interrupt flag 6 1 CH1IF Channel 1 capture/compare interrupt flag 2 1 CH0IF Channel 0 capture/compare interrupt flag 1 1 UPIF Update interrupt flag 0 1 SWEVG SWEVG event generation register 0x14 0x20 write-only 0x00000000 TRGG Trigger event generation 6 1 CH1G Channel 1 capture or compare event generation 2 1 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x20 read-write 0x00000000 CH1COMCTL Channel 1 compare output control 12 3 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1MS Channel 1 mode selection 8 2 CH0COMCTL Channel 0 compare output control 4 3 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0MS Channel 0 I/O mode selection 0 2 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 0x20 read-write 0x00000000 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x20 read-write 0x00000000 CH1NP Channel 1 complementary output polarity 7 1 CH1P Channel 1 capture/compare function polarity 5 1 CH1EN Channel 1 capture/compare function enable 4 1 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare function polarity 1 1 CH0EN Channel 0 capture/compare function enable 0 1 CNT CNT Counter register 0x24 0x20 read-write 0x00000000 CNT current counter value 0 16 065535 PSC PSC Prescaler register 0x28 0x20 read-write 0x00000000 PSC Prescaler value of the counter clock 0 16 065535 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x00000000 CAR Counter auto reload value 0 16 065535 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x20 read-write 0x00000000 CH0VAL Capture or compare value of channel0 0 16 065535 CH1CV CH1CV Channel 1 capture/compare value register 0x38 0x20 read-write 0x00000000 CH1VAL Capture or compare value of channel1 0 16 065535 CFG CFG configuration register 0xFC 0x20 read-write 0x00000000 CHVSEL Write CHxVAL register selection 1 1 TIMER12 General-purpose-timers TIMER 0x40001C00 0x0 0x400 registers TIMER7_UP_TIMER12 44 CTL0 CTL0 control register 0 0x00 0x20 read-write 0x00000000 CKDIV Clock division 8 2 ARSE Auto-reload shadow enable 7 1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 CTL1 CTL1 control register 1 0x04 0x20 read-write 0x00000000 MMC Master mode control 4 3 DMAINTEN DMAINTEN DMA/Interrupt enable register 0x0C 0x20 read-write 0x00000000 CH0IE Channel 0 capture/compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 0x20 read-write 0x00000000 CH0OF Channel 0 over capture flag 9 1 CH0IF Channel 0 capture/compare interrupt flag 1 1 UPIF Update interrupt flag 0 1 SWEVG SWEVG event generation register 0x14 0x20 write-only 0x00000000 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x20 read-write 0x00000000 CH0MS Channel 0 I/O mode selection 0 2 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0COMCTL Channel 0 compare output control 4 3 CHCTL0_Input CHCTL0_Input Channel control register 0 ( (input mode) CHCTL0_Output 0x18 0x20 read-write 0x00000000 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x20 read-write 0x00000000 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare polarity 1 1 CH0EN Channel 0 capture/compare function enable 0 1 CNT CNT Counter register 0x24 0x20 read-write 0x00000000 CNT current counter value 0 16 065535 PSC PSC Prescaler register 0x28 0x20 read-write 0x00000000 PSC Prescaler value of the counter clock 0 16 065535 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x00000000 CAR Counter auto reload value 0 16 065535 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x20 read-write 0x00000000 CH0VAL Capture or compare value of channel 0 0 16 065535 CFG CFG configuration register 0xFC 0x20 read-write 0x00000000 CHVSEL Write CHxVAL register selection 1 1 TIMER13 General-purpose-timers TIMER 0x40002000 0x0 0x400 registers TIMER7_TRG_CMT_TIMER13 45 CTL0 CTL0 control register 0 0x00 0x20 read-write 0x00000000 CKDIV Clock division 8 2 ARSE Auto-reload shadow enable 7 1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 CTL1 CTL1 control register 1 0x04 0x20 read-write 0x00000000 MMC Master mode control 4 3 DMAINTEN DMAINTEN DMA/Interrupt enable register 0x0C 0x20 read-write 0x00000000 CH0IE Channel 0 capture/compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 0x20 read-write 0x00000000 CH0OF Channel 0 over capture flag 9 1 CH0IF Channel 0 capture/compare interrupt flag 1 1 UPIF Update interrupt flag 0 1 SWEVG SWEVG event generation register 0x14 0x20 write-only 0x00000000 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x20 read-write 0x00000000 CH0MS Channel 0 I/O mode selection 0 2 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0COMCTL Channel 0 compare output control 4 3 CHCTL0_Input CHCTL0_Input Channel control register 0 ( (input mode) CHCTL0_Output 0x18 0x20 read-write 0x00000000 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x20 read-write 0x00000000 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare polarity 1 1 CH0EN Channel 0 capture/compare function enable 0 1 CNT CNT Counter register 0x24 0x20 read-write 0x00000000 CNT current counter value 0 16 065535 PSC PSC Prescaler register 0x28 0x20 read-write 0x00000000 PSC Prescaler value of the counter clock 0 16 065535 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x00000000 CAR Counter auto reload value 0 16 065535 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x20 read-write 0x00000000 CH0VAL Capture or compare value of channel 0 0 16 065535 CFG CFG configuration register 0xFC 0x20 read-write 0x00000000 CHVSEL Write CHxVAL register selection 1 1 TMU TMU TMU 0x40080000 0x0 0x400 registers TMU 103 IDATA0 IDATA0 Input data0 register 0x00 0x20 read-write 0x3F800000 IDATA0 IDATA0 0 32 IDATA1 IDATA1 Input data1 register 0x04 0x20 read-write 0x3F800000 IDATA1 IDATA1 0 32 CTL CTL Control register 0x08 0x20 0x00000000 CFIF CFIF 6 1 read-only CFIE CFIE 5 1 read-write MODE Set the mode of TMU 1 4 read-write TMUEN start TMU module calculation 0 1 read-write DATA0 DATA0 data0 register 0x0C 0x20 read-write 0x34000000 DATA0 DATA0 0 32 DATA1 DATA1 data1 register 0x10 0x20 read-write 0x00000000 DATA1 DATA1 0 32 STAT STAT Status register 0x14 0x20 read-only 0x00000000 UDRF The flag of underflow 1 1 OVRF The flag of overflow 0 1 USART0 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART0 37 STAT0 STAT0 Status register 0 0x00 0x20 read-only 0x000000C0 CTSF CTS change flag 9 1 LBDF LIN break detection flag 8 1 TBE Transmit data buffer empty 7 1 TC Transmission complete 6 1 RBNE Read data buffer not empty 5 1 IDLEF IDLE frame detected flag 4 1 ORERR Overrun error 3 1 NERR Noise error flag 2 1 FERR Frame error flag 1 1 PERR Parity error flag 0 1 DATA DATA Data register 0x04 0x20 read-write 0x00000000 DATA Transmit or read data value 0 9 BAUD BAUD Baud rate register 0x08 0x20 read-write 0x00000000 INTDIV Integer part of baud-rate divider 4 12 FRADIV Fraction part of baud-rate divider 0 4 CTL0 CTL0 Control register 0 0x0C 0x20 read-write 0x00000000 OVSMOD Oversampe mode 15 1 UEN USART enable 13 1 WL Word length 12 1 WM Wakeup method in mute mode 11 1 PCEN Parity check function enable 10 1 PM Parity mode 9 1 PERRIE Parity error interrupt enable 8 1 TBEIE Transmitter buffer empty interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable 5 1 IDLEIE IDLE line detected interrupt enable 4 1 TEN Transmitter enable 3 1 REN Receiver enable 2 1 RWU Receiver wakeup from mute mode 1 1 SBKCMD Send break command 0 1 CTL1 CTL1 Control register 1 0x10 0x20 read-write 0x00000000 LMEN LIN mode enable 14 1 STB STOP bits length 12 2 CKEN CK pin enable 11 1 CPL Clock polarity 10 1 CPH Clock phase 9 1 CLEN CK Length 8 1 LBDIE LIN break detection interrupt enable 6 1 LBLEN LIN break frame length 5 1 ADDR Address of the USART 0 4 CTL2 CTL2 Control register 2 0x14 0x20 read-write 0x00000000 OSB One sample bit method 11 1 CTSIE CTS interrupt enable 10 1 CTSEN CTS enable 9 1 RTSEN RTS enable 8 1 DENT DMA request enable for transmission 7 1 DENR DMA request enable for reception 6 1 SCEN Smartcard mode enable 5 1 NKEN Smartcard NACK enable 4 1 HDEN Half-duplex selection 3 1 IRLP IrDA low-power 2 1 IREN IrDA mode enable 1 1 ERRIE Error interrupt enable 0 1 GP GP Guard time and prescaler register 0x18 0x20 read-write 0x00000000 GUAT Guard time value in Smartcard mode 8 8 PSC Prescaler value 0 8 CTL3 CTL3 Control register 3 0x80 0x20 read-write 0x00000000 MSBF Most significant bit first 11 1 DINV Data bit level inversion 10 1 TINV TX pin level inversion 9 1 RINV RX pin level inversion 8 1 EBIE Interrupt enable bit of end of block event 5 1 RTIE Interrupt enable bit of receive timeout event 4 1 SCRTNUM Smartcard auto-retry number 1 3 RTEN Receiver timeout enable 0 1 RT RT Receiver timeout register 0x84 0x20 read-write 0x00000000 BL Block Length 24 8 RT Receiver timeout threshold 0 24 STAT1 STAT1 Status register 1 0x88 0x20 0x00000000 BSY Busy flag 16 1 read-only EBF End of block flag 12 1 write-only RTF Receiver timeout flag 11 1 write-only GDCTL GDCTL GD control register 0xD0 0x20 0x00000000 CDIE Collision detected interrupt enable 16 1 read-write CD Collision detected status 8 1 write-only CDEN Collision detection enable 1 1 read-write USART1 Universal synchronous asynchronous receiver transmitter USART 0x40004400 0x0 0x400 registers USART1 38 STAT0 STAT0 Status register 0 0x00 0x20 read-only 0x000000C0 CTSF CTS change flag 9 1 LBDF LIN break detection flag 8 1 TBE Transmit data buffer empty 7 1 TC Transmission complete 6 1 RBNE Read data buffer not empty 5 1 IDLEF IDLE frame detected flag 4 1 ORERR Overrun error 3 1 NERR Noise error flag 2 1 FERR Frame error flag 1 1 PERR Parity error flag 0 1 DATA DATA Data register 0x04 0x20 read-write 0x00000000 DATA Transmit or read data value 0 9 BAUD BAUD Baud rate register 0x08 0x20 read-write 0x00000000 INTDIV Integer part of baud-rate divider 4 12 FRADIV Fraction part of baud-rate divider 0 4 CTL0 CTL0 Control register 0 0x0C 0x20 read-write 0x00000000 OVSMOD Oversampe mode 15 1 UEN USART enable 13 1 WL Word length 12 1 WM Wakeup method in mute mode 11 1 PCEN Parity check function enable 10 1 PM Parity mode 9 1 PERRIE Parity error interrupt enable 8 1 TBEIE Transmitter buffer empty interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable 5 1 IDLEIE IDLE line detected interrupt enable 4 1 TEN Transmitter enable 3 1 REN Receiver enable 2 1 RWU Receiver wakeup from mute mode 1 1 SBKCMD Send break command 0 1 CTL1 CTL1 Control register 1 0x10 0x20 read-write 0x00000000 LMEN LIN mode enable 14 1 STB STOP bits length 12 2 CKEN CK pin enable 11 1 CPL Clock polarity 10 1 CPH Clock phase 9 1 CLEN CK Length 8 1 LBDIE LIN break detection interrupt enable 6 1 LBLEN LIN break frame length 5 1 ADDR Address of the USART 0 4 CTL2 CTL2 Control register 2 0x14 0x20 read-write 0x00000000 OSB One sample bit method 11 1 CTSIE CTS interrupt enable 10 1 CTSEN CTS enable 9 1 RTSEN RTS enable 8 1 DENT DMA request enable for transmission 7 1 DENR DMA request enable for reception 6 1 SCEN Smartcard mode enable 5 1 NKEN Smartcard NACK enable 4 1 HDEN Half-duplex selection 3 1 IRLP IrDA low-power 2 1 IREN IrDA mode enable 1 1 ERRIE Error interrupt enable 0 1 GP GP Guard time and prescaler register 0x18 0x20 read-write 0x00000000 GUAT Guard time value in Smartcard mode 8 8 PSC Prescaler value 0 8 CTL3 CTL3 Control register 3 0x80 0x20 read-write 0x00000000 MSBF Most significant bit first 11 1 DINV Data bit level inversion 10 1 TINV TX pin level inversion 9 1 RINV RX pin level inversion 8 1 EBIE Interrupt enable bit of end of block event 5 1 RTIE Interrupt enable bit of receive timeout event 4 1 SCRTNUM Smartcard auto-retry number 1 3 RTEN Receiver timeout enable 0 1 RT RT Receiver timeout register 0x84 0x20 read-write 0x00000000 BL Block Length 24 8 RT Receiver timeout threshold 0 24 STAT1 STAT1 Status register 1 0x88 0x20 0x00000000 BSY Busy flag 16 1 read-only EBF End of block flag 12 1 write-only RTF Receiver timeout flag 11 1 write-only GDCTL GDCTL GD control register 0xD0 0x20 0x00000000 CDIE Collision detected interrupt enable 16 1 read-write CD Collision detected status 8 1 write-only CDEN Collision detection enable 1 1 read-write USART2 Universal synchronous asynchronous receiver transmitter USART 0x40004800 0x0 0x400 registers USART2 39 STAT0 STAT0 Status register 0 0x00 0x20 read-only 0x000000C0 CTSF CTS change flag 9 1 LBDF LIN break detection flag 8 1 TBE Transmit data buffer empty 7 1 TC Transmission complete 6 1 RBNE Read data buffer not empty 5 1 IDLEF IDLE frame detected flag 4 1 ORERR Overrun error 3 1 NERR Noise error flag 2 1 FERR Frame error flag 1 1 PERR Parity error flag 0 1 DATA DATA Data register 0x04 0x20 read-write 0x00000000 DATA Transmit or read data value 0 9 BAUD BAUD Baud rate register 0x08 0x20 read-write 0x00000000 INTDIV Integer part of baud-rate divider 4 12 FRADIV Fraction part of baud-rate divider 0 4 CTL0 CTL0 Control register 0 0x0C 0x20 read-write 0x00000000 OVSMOD Oversampe mode 15 1 UEN USART enable 13 1 WL Word length 12 1 WM Wakeup method in mute mode 11 1 PCEN Parity check function enable 10 1 PM Parity mode 9 1 PERRIE Parity error interrupt enable 8 1 TBEIE Transmitter buffer empty interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable 5 1 IDLEIE IDLE line detected interrupt enable 4 1 TEN Transmitter enable 3 1 REN Receiver enable 2 1 RWU Receiver wakeup from mute mode 1 1 SBKCMD Send break command 0 1 CTL1 CTL1 Control register 1 0x10 0x20 read-write 0x00000000 LMEN LIN mode enable 14 1 STB STOP bits length 12 2 CKEN CK pin enable 11 1 CPL Clock polarity 10 1 CPH Clock phase 9 1 CLEN CK Length 8 1 LBDIE LIN break detection interrupt enable 6 1 LBLEN LIN break frame length 5 1 ADDR Address of the USART 0 4 CTL2 CTL2 Control register 2 0x14 0x20 read-write 0x00000000 OSB One sample bit method 11 1 CTSIE CTS interrupt enable 10 1 CTSEN CTS enable 9 1 RTSEN RTS enable 8 1 DENT DMA request enable for transmission 7 1 DENR DMA request enable for reception 6 1 SCEN Smartcard mode enable 5 1 NKEN Smartcard NACK enable 4 1 HDEN Half-duplex selection 3 1 IRLP IrDA low-power 2 1 IREN IrDA mode enable 1 1 ERRIE Error interrupt enable 0 1 GP GP Guard time and prescaler register 0x18 0x20 read-write 0x00000000 GUAT Guard time value in Smartcard mode 8 8 PSC Prescaler value 0 8 CTL3 CTL3 Control register 3 0x80 0x20 read-write 0x00000000 MSBF Most significant bit first 11 1 DINV Data bit level inversion 10 1 TINV TX pin level inversion 9 1 RINV RX pin level inversion 8 1 EBIE Interrupt enable bit of end of block event 5 1 RTIE Interrupt enable bit of receive timeout event 4 1 SCRTNUM Smartcard auto-retry number 1 3 RTEN Receiver timeout enable 0 1 RT RT Receiver timeout register 0x84 0x20 read-write 0x00000000 BL Block Length 24 8 RT Receiver timeout threshold 0 24 STAT1 STAT1 Status register 1 0x88 0x20 0x00000000 BSY Busy flag 16 1 read-only EBF End of block flag 12 1 write-only RTF Receiver timeout flag 11 1 write-only GDCTL GDCTL GD control register 0xD0 0x20 0x00000000 CDIE Collision detected interrupt enable 16 1 read-write CD Collision detected status 8 1 write-only CDEN Collision detection enable 1 1 read-write UART3 Universal asynchronous receiver transmitter UART 0x40004C00 0x0 0x400 registers UART3 52 STAT0 STAT0 Status register 0 0x00 0x20 read-only 0x000000C0 LBDF LIN break detection flag 8 1 TBE Transmit data buffer empty 7 1 TC Transmission complete 6 1 RBNE Read data buffer not empty 5 1 IDLEF IDLE frame detected flag 4 1 ORERR Overrun error 3 1 NERR Noise error flag 2 1 FERR Frame error flag 1 1 PERR Parity error flag 0 1 DATA DATA Data register 0x04 0x20 read-write 0x00000000 DATA Transmit or read data value 0 9 BAUD BAUD Baud rate register 0x08 0x20 read-write 0x00000000 INTDIV Integer part of baud-rate divider 4 12 FRADIV Fraction part of baud-rate divider 0 4 CTL0 CTL0 Control register 0 0x0C 0x20 read-write 0x00000000 OVSMOD Oversampe mode 15 1 UEN USART enable 13 1 WL Word length 12 1 WM Wakeup method in mute mode 11 1 PCEN Parity check function enable 10 1 PM Parity mode 9 1 PERRIE Parity error interrupt enable 8 1 TBEIE Transmitter buffer empty interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable 5 1 IDLEIE IDLE line detected interrupt enable 4 1 TEN Transmitter enable 3 1 REN Receiver enable 2 1 RWU Receiver wakeup from mute mode 1 1 SBKCMD Send break command 0 1 CTL1 CTL1 Control register 1 0x10 0x20 read-write 0x00000000 LMEN LIN mode enable 14 1 STB STOP bits length 12 2 LBDIE LIN break detection interrupt enable 6 1 LBLEN LIN break frame length 5 1 ADDR Address of the USART 0 4 CTL2 CTL2 Control register 2 0x14 0x20 read-write 0x00000000 OSB One sample bit method enable 11 1 DENT DMA request enable for transmission 7 1 DENR DMA request enable for reception 6 1 HDEN Half-duplex selection 3 1 IRLP IrDA low-power 2 1 IREN IrDA mode enable 1 1 ERRIE Error interrupt enable 0 1 GP GP Guard time and prescaler register 0x18 0x20 read-write 0x00000000 GUAT Guard time value in Smartcard mode 8 8 PSC Prescaler value 0 8 GDCTL GDCTL GD control register 0xD0 0x20 0x00000000 CDIE Collision detected interrupt enable 16 1 read-write CD Collision detected status 8 1 write-only CDEN Collision detection enable 1 1 read-write UART4 Universal asynchronous receiver transmitter UART 0x40005000 0x0 0x400 registers UART4 53 STAT0 STAT0 Status register 0 0x00 0x20 read-only 0x000000C0 LBDF LIN break detection flag 8 1 TBE Transmit data buffer empty 7 1 TC Transmission complete 6 1 RBNE Read data buffer not empty 5 1 IDLEF IDLE frame detected flag 4 1 ORERR Overrun error 3 1 NERR Noise error flag 2 1 FERR Frame error flag 1 1 PERR Parity error flag 0 1 DATA DATA Data register 0x04 0x20 read-write 0x00000000 DATA Transmit or read data value 0 9 BAUD BAUD Baud rate register 0x08 0x20 read-write 0x00000000 INTDIV Integer part of baud-rate divider 4 12 FRADIV Fraction part of baud-rate divider 0 4 CTL0 CTL0 Control register 0 0x0C 0x20 read-write 0x00000000 OVSMOD Oversampe mode 15 1 UEN USART enable 13 1 WL Word length 12 1 WM Wakeup method in mute mode 11 1 PCEN Parity check function enable 10 1 PM Parity mode 9 1 PERRIE Parity error interrupt enable 8 1 TBEIE Transmitter buffer empty interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable 5 1 IDLEIE IDLE line detected interrupt enable 4 1 TEN Transmitter enable 3 1 REN Receiver enable 2 1 RWU Receiver wakeup from mute mode 1 1 SBKCMD Send break command 0 1 CTL1 CTL1 Control register 1 0x10 0x20 read-write 0x00000000 LMEN LIN mode enable 14 1 STB STOP bits length 12 2 LBDIE LIN break detection interrupt enable 6 1 LBLEN LIN break frame length 5 1 ADDR Address of the USART 0 4 CTL2 CTL2 Control register 2 0x14 0x20 read-write 0x00000000 OSB One sample bit method enable 11 1 DENT DMA request enable for transmission 7 1 DENR DMA request enable for reception 6 1 HDEN Half-duplex selection 3 1 IRLP IrDA low-power 2 1 IREN IrDA mode enable 1 1 ERRIE Error interrupt enable 0 1 GP GP Guard time and prescaler register 0x18 0x20 read-write 0x00000000 GUAT Guard time value in Smartcard mode 8 8 PSC Prescaler value 0 8 GDCTL GDCTL GD control register 0xD0 0x20 0x00000000 CDIE Collision detected interrupt enable 16 1 read-write CD Collision detected status 8 1 write-only CDEN Collision detection enable 1 1 read-write USART5 Universal asynchronous receiver transmitter USART 0x40017000 0x0 0x400 registers USART5 84 USART5_WKUP 102 CTL0 CTL0 Control register 0 0x00 0x20 read-write 0x00000000 EBIE End of Block interrupt enable 27 1 RTIE Receiver timeout interrupt enable 26 1 OVSMOD Oversample mode 15 1 AMIE ADDR match interrupt enable 14 1 MEN Mute mode enable 13 1 WL Word length 12 1 WM Wakeup method in mute mode 11 1 PCEN Parity control enable 10 1 PM Parity mode 9 1 PERRIE Parity error interrupt enable 8 1 TBEIE Transmitter register empty interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable 5 1 IDLEIE IDLE line detected interrupt enable 4 1 TEN Transmitter enable 3 1 REN Receiver enable 2 1 UESM USART enable in Deep-sleep mode 1 1 UEN USART enable 0 1 CTL1 CTL1 Control register 1 0x04 0x20 read-write 0x00000000 ADDR Address of the USART terminal 24 8 RTEN Receiver timeout enable 23 1 ABDM Auto baud rate mode 21 2 ABDEN Auto baud rate enable 20 1 MSBF Most significant bit first 19 1 DINV Data bit level inversion 18 1 TINV TX pin level inversion 17 1 RINV RX pin level inversion 16 1 STRP Swap TX/RX pins 15 1 LMEN LIN mode enable 14 1 STB STOP bits length 12 2 CKEN CK pin enable 11 1 CPL Clock polarity 10 1 CPH Clock phase 9 1 CLEN CK length 8 1 LBDIE LIN break detection interrupt enable 6 1 LBLEN LIN break frame length 5 1 ADDM Address detection mode 4 1 CTL2 CTL2 Control register 2 0x08 0x20 read-write 0x00000000 WUIE Wakeup from Deep-sleep mode interrupt enable 22 1 WUM Wakeup mode from Deep-sleep mode 20 2 SCRTNUM Smartcard auto-retry number 17 3 DDRE Disable DMA on reception error 13 1 OVRD Overrun disable 12 1 OSB One sample bit method 11 1 DENT DMA enable for transmission 7 1 DENR DMA enable for reception 6 1 SCEN Smartcard mode enable 5 1 NKEN NACK enable in Smartcard mode 4 1 HDEN Half-duplex enable 3 1 IRLP IrDA low-power 2 1 IREN IrDA mode enable 1 1 ERRIE Error interrupt enable 0 1 BAUD BAUD Baud rate generator register 0x0C 0x20 read-write 0x00000000 BRR_4_15 Integer of baud-rate divider 4 12 BRR_0_3 Fraction of baud-rate divider 0 4 GP GP Prescaler and guard time configuration register 0x10 0x20 read-write 0x00000000 GUAT Guard time value in smartcard mode 8 8 PSC Prescaler value for dividing the system clock 0 8 RT RT Receiver timeout register 0x14 0x20 read-write 0x00000000 BL Block Length 24 8 RT Receiver timeout threshold 0 24 CMD CMD Command register (USART_CMD) 0x18 0x20 write-only 0x00000000 TXFCMD Transmit data flush request 4 1 RXFCMD Receive data flush command 3 1 MMCMD Mute mode command 2 1 SBKCMD Send break command 1 1 ABDCMD Auto baudrate detection command 0 1 STAT STAT Status register 0x1C 0x20 read-only 0x000000C0 REA Receive enable acknowledge flag 22 1 TEA Transmit enable acknowledge flag 21 1 WUF Wakeup from Deep-sleep mode flag 20 1 RWU Receiver wakeup from mute mode 19 1 SBF Send break flag 18 1 AMF ADDR match flag 17 1 BSY Busy flag 16 1 ABDF Auto baudrate detection flag 15 1 ABDE Auto baudrate detection error 14 1 EBF End of block flag 12 1 RTF Receiver timeout flag 11 1 LBDF LIN break detected flag 8 1 TBE Transmit data register empty 7 1 TC Transmission completed 6 1 RBNE Read data buffer not empty 5 1 IDLEF IDLE line detected flag 4 1 ORERR Overrun error 3 1 NERR Noise error flag 2 1 FERR Frame error flag 1 1 PERR Parity error flag 0 1 INTC INTC Interrupt status clear register 0x20 0x20 write-only 0x00000000 WUC Wakeup from Deep-sleep mode clear 20 1 AMC ADDR match clear 17 1 EBC End of block clear 12 1 RTC Receiver timeout clear 11 1 LBDC LIN break detected clear 8 1 TCC Transmission complete clear 6 1 IDLEC Idle line detected clear 4 1 OREC Overrun error clear 3 1 NEC Noise detected clear 2 1 FEC Frame error flag clear 1 1 PEC Parity error clear 0 1 RDATA RDATA Receive data register ( 0x24 0x20 read-only 0x00000000 RDATA Receive Data value 0 9 TDATA TDATA Transmit data register 0x28 0x20 read-write 0x00000000 TDATA Transmit Data value 0 9 CHC CHC USART coherence control register 0xC0 0x20 read-write 0x00000000 EPERR Early parity error flag 8 1 HCM Hardware flow control coherence mode 0 1 RFCS RFCS receive FIFO control and status register 0xD0 0x20 0x00000400 RFFINT Receive FIFO full interrupt flag 15 1 read-write RFCNT Receive FIFO counter number 12 3 read-only RFF Receive FIFO full flag 11 1 read-only RFE Receive FIFO empty flag 10 1 read-only RFFIE Receive FIFO full interrupt enable 9 1 read-write RFEN Receive FIFO enable 8 1 read-write ELNACK Early NACK when smartcard mode is selected 0 1 read-write USBHS_GLOBAL USB high speed global registers USBHS 0x50000000 0x0 0x400 registers USBHS_WKUP 42 USBHS 67 GOTGCS GOTGCS Global OTG control and status register (USBFS_GOTGCS) 0x0 0x20 0x00000800 SRPS SRP success 0 1 read-only SRPREQ SRP request 1 1 read-write VOE Override enable of VBUS valid 2 1 read-write VOV Override value of VBUS valid 3 1 read-write AVOE Override enable of A-peripheral session valid 4 1 read-write AVOV Override value of A-peripheral session valid 5 1 read-write BVOE Override enable of B-peripheral session valid 6 1 read-write BVOV Override value of B-peripheral session valid 7 1 read-write HNPS HNP success 8 1 read-only HNPREQ HNP request 9 1 read-write HHNPEN Host HNP enable 10 1 read-write DHNPEN Device HNP enabled 11 1 read-write EHE Embedded host enable 12 1 read-write IDPS ID pin status 16 1 read-only DI Debounce interval 17 1 read-only ASV A-session valid 18 1 read-only BSV B-session valid 19 1 read-only OV Select OTG version 20 1 read-write GOTGINTF GOTGINTF Global OTG interrupt flag register (USBHS_GOTGINTF) 0x04 0x20 read-write 0x00000000 SESEND Session end 2 1 SRPEND Session request success status change 8 1 HNPEND HNP end 9 1 HNPDET Host negotiation request detected 17 1 ADTO A-device timeout 18 1 DF Debounce finish 19 1 IDCHG There is a change in the value of ID input 20 1 GAHBCS GAHBCS Global AHB control and status register (USBHS_GAHBCS) 0x08 0x20 read-write 0x00000000 GINTEN Global interrupt enable 0 1 BURST The AHB burst type used by DMA 1 4 DMAEN DMA function Enable 5 1 TXFTH Tx FIFO threshold 7 1 PTXFTH Periodic Tx FIFO threshold 8 1 GUSBCS GUSBCS Global USB control and status register (USBHS_GUSBCSR) 0x0C 0x20 0x00000A00 TOC Timeout calibration 0 3 read-write HS_CUR_FE HS current software enable 4 1 read-write EMBPHY_HS Embedded HS PHY selected 5 1 read-write EMBPHY_FS Embedded FS PHY selected 6 1 read-write SRPCEN SRP capability enable 8 1 read-write HNPCEN HNP capability enable 9 1 read-write UTT USB turnaround time 10 4 read-write ULPIEVD ULPI external VBUS driver 20 1 read-write ULPIEOI ULPI external over-current indicator 21 1 read-write FHM Force host mode 29 1 read-write FDM Force device mode 30 1 read-write GRSTCTL GRSTCTL Global reset control register (USBHS_GRSTCTL) 0x10 0x20 0x80000000 CSRST Core soft reset 0 1 read-write HCSRST HCLK soft reset 1 1 read-write HFCRST Host frame counter reset 2 1 read-write RXFF RxFIFO flush 4 1 read-write TXFF TxFIFO flush 5 1 read-write TXFNUM TxFIFO number 6 5 read-write DMABSY DMA Busy 30 1 read-only DMAIDL DMA Idle state 31 1 read-only GINTF GINTF Global interrupt flag register (USBFS_GINTF) 0x14 0x20 0x04000021 COPM Current operation mode 0 1 read-only MFIF Mode fault interrupt flag 1 1 read-write OTGIF OTG interrupt flag 2 1 read-only SOF Start of frame 3 1 read-write RXFNEIF RxFIFO non-empty interrupt flag 4 1 read-only NPTXFEIF Non-periodic TxFIFO empty interrupt flag 5 1 read-only GNPINAK Global Non-Periodic IN NAK effective 6 1 read-only GONAK Global OUT NAK effective 7 1 read-only ESP Early suspend 10 1 read-write SP USB suspend 11 1 read-write RST USB reset 12 1 read-write ENUMF Enumeration finished 13 1 read-write ISOOPDIF Isochronous OUT packet dropped interrupt 14 1 read-write EOPFIF End of periodic frame interrupt flag 15 1 read-write IEPIF IN endpoint interrupt flag 18 1 read-only OEPIF OUT endpoint interrupt flag 19 1 read-only ISOINCIF Isochronous IN transfer Not Complete Interrupt Flag 20 1 read-write PXNCIF_ISOONCIF periodic transfer not complete interrupt flag(Host mode)/isochronous OUT transfer not complete interrupt flag(Device mode) 21 1 read-write HPIF Host port interrupt flag 24 1 read-only HCIF Host channels interrupt flag 25 1 read-only PTXFEIF Periodic TxFIFO empty interrupt flag 26 1 read-only LPMIF LPM interrupt flag 27 1 read-write IDPSC ID pin status change 28 1 read-write DISCIF Disconnect interrupt flag 29 1 read-write SESIF Session interrupt flag 30 1 read-write WKUPIF Wakeup interrupt flag 31 1 read-write GINTEN GINTEN Global interrupt enable register (USBHS_GINTEN) 0x18 0x20 0x00000000 MFIE Mode fault interrupt enable 1 1 read-write OTGIE OTG interrupt enable 2 1 read-write SOFIE Start of frame interrupt enable 3 1 read-write RXFNEIE Receive FIFO non-empty interrupt enable 4 1 read-write NPTXFEIE Non-periodic TxFIFO empty interrupt enable 5 1 read-write GNPINAKIE Global non-periodic IN NAK effective interrupt enable 6 1 read-write GONAKIE Global OUT NAK effective interrupt enable 7 1 read-write ESPIE Early suspend interrupt enable 10 1 read-write SPIE USB suspend interrupt enable 11 1 read-write RSTIE USB reset interrupt enable 12 1 read-write ENUMFIE Enumeration finish interrupt enable 13 1 read-write ISOOPDIE Isochronous OUT packet dropped interrupt enable 14 1 read-write EOPFIE End of periodic frame interrupt enable 15 1 read-write IEPIE IN endpoints interrupt enable 18 1 read-write OEPIE OUT endpoints interrupt enable 19 1 read-write ISOINCIE isochronous IN transfer not complete interrupt enable 20 1 read-write PXNCIE_ISOONCIE periodic transfer not compelete Interrupt enable(Host mode)/isochronous OUT transfer not complete interrupt enable(Device mode) 21 1 read-write HPIE Host port interrupt enable 24 1 read-only HCIE Host channels interrupt enable 25 1 read-write PTXFEIE Periodic TxFIFO empty interrupt enable 26 1 read-write LPMIE LPM interrupt enable 27 1 read-write IDPSCIE ID pin status change interrupt enable 28 1 read-write DISCIE Disconnect interrupt enable 29 1 read-write SESIE Session interrupt enable 30 1 read-write WKUPIE Wakeup interrupt enable 31 1 read-write GRSTATR_Device GRSTATR_Device Global Receive status read(Device mode) 0x1C 0x20 read-only 0x00000000 EPNUM Endpoint number 0 4 BCOUNT Byte count 4 11 DPID Data PID 15 2 RPCKST Recieve packet status 17 4 GRSTATR_Host GRSTATR_Host Global Receive status read(Host mode) GRSTATR_Device 0x1C 0x20 read-only 0x00000000 CNUM Channel number 0 4 BCOUNT Byte count 4 11 DPID Data PID 15 2 RPCKST Reivece packet status 17 4 GRSTATP_Device GRSTATP_Device Global Receive status pop(Device mode) 0x20 0x20 read-only 0x00000000 EPNUM Endpoint number 0 4 BCOUNT Byte count 4 11 DPID Data PID 15 2 RPCKST Recieve packet status 17 4 GRSTATP_Host GRSTATP_Host Global Receive status pop(Host mode) GRSTATP_Device 0x20 0x20 read-only 0x00000000 CNUM Channel number 0 4 BCOUNT Byte count 4 11 DPID Data PID 15 2 RPCKST Reivece packet status 17 4 GRFLEN GRFLEN Global Receive FIFO size register (USBHS_GRFLEN) 0x24 0x20 read-write 0x00000200 RXFD Rx FIFO depth 0 16 HNPTFLEN HNPTFLEN Host non-periodic transmit FIFO length register (Host mode) 0x28 0x20 read-write 0x02000200 HNPTXRSAR host non-periodic transmit Tx RAM start address 0 16 HNPTXFD host non-periodic TxFIFO depth 16 16 DIEP0TFLEN DIEP0TFLEN Device IN endpoint 0 transmit FIFO length (Device mode) HNPTFLEN 0x28 0x20 read-write 0x02000200 IEP0TXFD in endpoint 0 Tx FIFO depth 16 16 IEP0TXRSAR in endpoint 0 Tx RAM start address 0 16 HNPTFQSTAT HNPTFQSTAT Host non-periodic transmit FIFO/queue status register (HNPTFQSTAT) 0x2C 0x20 read-only 0x00080200 NPTXFS Non-periodic TxFIFO space 0 16 NPTXRQS Non-periodic transmit request queue space 16 8 NPTXRQTOP Top of the non-periodic transmit request queue 24 7 GCCFG GCCFG Global core configuration register (USBFS_GCCFG) 0x38 0x20 read-write 0x00000000 DCDF Data connect detection status 0 1 PDF Primary detection status 1 1 SDF Secondary detection status 2 1 PS2F PS2 detection status 3 1 BCDEN Battery charging detection enable 12 1 DCDMEN Data connect detection mode enable 13 1 PDMEN Primary detection mode enable 14 1 SDMEN Secondary detection mode enable 15 1 PWRON Power on 16 1 SOFOEN SOF output enable 20 1 VDEN Enable of VBUS sensing comparator to detect VBUS valid 21 1 CID CID core ID register 0x3C 0x20 read-write 0x00001000 CID Core ID 0 32 GLPMCFG GLPMCFG Global core LPM configuration register 0x54 0x20 read-write 0x00000000 LPMEN LPM enable 0 1 ACKLPM ACK in LPM transaction enable 1 1 BESL Best effort service latency 2 4 REW RemoteWake value 6 1 SSEN Shallow sleep enable 7 1 BESLTH BESL threshold 8 4 DSEN Deep sleep enable 12 1 LPMRSP Response of LPM 13 2 LPMSLPS Sleep status 15 1 RSOK Resume can be sent after sleep state 16 1 LPMCHI Channel number index when send LPM transaction 17 4 LPMRC LPM retry count 21 3 LPMSND Send LPM transaction 24 1 LPMRCS LPM retry count status 25 3 BESLEN LPM Errata selection enable 28 1 PWRD PWRD Power down register (USBHS_PWRD) 0x58 0x20 read-write 0x00000000 ADPMEN ADP module enable 0 1 ADPF ADP event interrupt flag 23 1 ADPCTL ADPCTL ADP control andstatus register 0x60 0x20 0x00001000 DSCHGPR Time of probe discharge 0 2 read-write RESOPR The resolution of CHGT value 2 2 read-write PERPR Period of probe 4 2 read-write CHGT The latest time that VBUS ramps from VADPSINK to VADPPRB 6 11 read-only PREN ADP probe enable 17 1 read-write SNEN ADP sense enable 18 1 read-write ADPRST ADP reset 19 1 read-only ADPEN ADP enable 20 1 read-write ADPPRF ADP probe interrupt flag 21 1 read-write ADPSNF ADP sense interrupt flag 22 1 read-write ADPTF ADP timeout interrupt flag 23 1 read-write ADPPRFM The mask of ADP probe interrupt flag 24 1 read-write ADPSNFM The mask of ADP sense interrupt flag 25 1 read-write ADPTFM The mask of ADP timeout interrupt flag 26 1 read-write RWR Read and write request 27 2 read-write HPTFLEN HPTFLEN Host periodic transmit FIFO length register (HPTFLEN) 0x100 0x20 read-write 0x02000600 HPTXFSAR Host periodic TxFIFO start address 0 16 HPTXFD Host periodic TxFIFO depth 16 16 DIEP1TFLEN DIEP1TFLEN device IN endpoint transmit FIFO size register 0x104 0x20 read-write 0x02000400 IEPTXRSAR IN endpoint FIFO transmit RAM start address 0 16 IEPTXFD IN endpoint TxFIFO depth 16 16 DIEP2TFLEN DIEP2TFLEN device IN endpoint transmit FIFO size register 0x108 0x20 read-write 0x02000400 IEPTXRSAR IN endpoint FIFO transmit RAM start address 0 16 IEPTXFD IN endpoint TxFIFO depth 16 16 DIEP3TFLEN DIEP3TFLEN device IN endpoint transmit FIFO size register 0x10C 0x20 read-write 0x02000400 IEPTXRSAR IN endpoint FIFO4 transmit RAM start address 0 16 IEPTXFD IN endpoint TxFIFO depth 16 16 DIEP4TFLEN DIEP4TFLEN device IN endpoint transmit FIFO size register 0x110 0x20 read-write 0x02000400 IEPTXRSAR IN endpoint FIFO4 transmit RAM start address 0 16 IEPTXFD IN endpoint TxFIFO depth 16 16 DIEP5TFLEN DIEP5TFLEN device IN endpoint transmit FIFO size register (FS_DIEP5TXFLEN) 0x114 0x20 read-write 0x02000400 IEPTXRSAR IN endpoint FIFO4 transmit RAM start address 0 16 IEPTXFD IN endpoint TxFIFO depth 16 16 USBGS_HOST USB on the go high speed host USBHS 0x50000400 0x0 0x400 registers HCTL HCTL host configuration register (HCTL) 0x00 0x20 0x00000000 SPDFSLS Speed limited to FS and LS 2 1 read-write HFT HFT Host frame interval register 0x04 0x20 read-write 0x0000BB80 FRI Frame interval 0 16 HFINFR HFINFR OTG_FS host frame number/frame time remaining register (HFINFR) 0x08 0x20 read-only 0xBB800000 FRNUM Frame number 0 16 FRT Frame remaining time 16 16 HPTFQSTAT HPTFQSTAT Host periodic transmit FIFO/queue status register (HPTFQSTAT) 0x10 0x20 0x00080200 PTXFS Periodic transmit data FIFO space available 0 16 read-only PTXREQS Periodic transmit request queue space available 16 8 read-only PTXREQT Top of the periodic transmit request queue 24 8 read-only HACHINT HACHINT Host all channels interrupt register 0x14 0x20 read-only 0x00000000 HACHINT Host all channel interrupts 0 12 HACHINTEN HACHINTEN host all channels interrupt mask register 0x18 0x20 read-write 0x00000000 CINTEN Channel interrupt enable 0 12 HPCS HPCS Host port control and status register (USBFS_HPCS) 0x40 0x20 0x00000000 PCST Port connect status 0 1 read-only PCD Port connect detected 1 1 read-write PE Port enable 2 1 read-write PEDC Port enable/disable change 3 1 read-write PREM Port resume 6 1 read-write PSP Port suspend 7 1 read-write PRST Port reset 8 1 read-write PLST Port line status 10 2 read-only PP Port power 12 1 read-write PTEST Port Test control 13 4 read-write PS Port speed 17 2 read-only HCH0CTL HCH0CTL host channel-0 characteristics register (HCH0CTL) 0x100 0x20 read-write 0x00000000 MPL Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSD Low-speed device 17 1 EPTYPE Endpoint type 18 2 MPC Multiple Packet Count 20 2 DAR Device address 22 7 ODDFRM Odd frame 29 1 CDIS Channel disable 30 1 CEN Channel enable 31 1 HCH1CTL HCH1CTL host channel-1 characteristics register (HCH1CTL) 0x120 0x20 read-write 0x00000000 MPL Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSD Low-speed device 17 1 EPTYPE Endpoint type 18 2 MPC Multiple Packet Count 20 2 DAR Device address 22 7 ODDFRM Odd frame 29 1 CDIS Channel disable 30 1 CEN Channel enable 31 1 HCH2CTL HCH2CTL host channel-2 characteristics register (HCH2CTL) 0x140 0x20 read-write 0x00000000 MPL Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSD Low-speed device 17 1 EPTYPE Endpoint type 18 2 MPC Multiple Packet Count 20 2 DAR Device address 22 7 ODDFRM Odd frame 29 1 CDIS Channel disable 30 1 CEN Channel enable 31 1 HCH3CTL HCH3CTL host channel-3 characteristics register (HCH3CTL) 0x160 0x20 read-write 0x00000000 MPL Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSD Low-speed device 17 1 EPTYPE Endpoint type 18 2 MPC Multiple Packet Count 20 2 DAR Device address 22 7 ODDFRM Odd frame 29 1 CDIS Channel disable 30 1 CEN Channel enable 31 1 HCH4CTL HCH4CTL host channel-4 characteristics register (HCH4CTL) 0x180 0x20 read-write 0x00000000 MPL Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSD Low-speed device 17 1 EPTYPE Endpoint type 18 2 MPC Multiple Packet Count 20 2 DAR Device address 22 7 ODDFRM Odd frame 29 1 CDIS Channel disable 30 1 CEN Channel enable 31 1 HCH5CTL HCH5CTL host channel-5 characteristics register (HCH5CTL) 0x1A0 0x20 read-write 0x00000000 MPL Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSD Low-speed device 17 1 EPTYPE Endpoint type 18 2 MPC Multiple Packet Count 20 2 DAR Device address 22 7 ODDFRM Odd frame 29 1 CDIS Channel disable 30 1 CEN Channel enable 31 1 HCH6CTL HCH6CTL host channel-6 characteristics register (HCH6CTL) 0x1C0 0x20 read-write 0x00000000 MPL Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSD Low-speed device 17 1 EPTYPE Endpoint type 18 2 MPC Multiple Packet Count 20 2 DAR Device address 22 7 ODDFRM Odd frame 29 1 CDIS Channel disable 30 1 CEN Channel enable 31 1 HCH7CTL HCH7CTL host channel-7 characteristics register (HCH7CTL) 0x1E0 0x20 read-write 0x00000000 MPL Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSD Low-speed device 17 1 EPTYPE Endpoint type 18 2 MPC Multiple Packet Count 20 2 DAR Device address 22 7 ODDFRM Odd frame 29 1 CDIS Channel disable 30 1 CEN Channel enable 31 1 HCH8CTL HCH8CTL host channel-8 characteristics register (HCH8CTL) 0x200 0x20 read-write 0x00000000 MPL Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSD Low-speed device 17 1 EPTYPE Endpoint type 18 2 MPC Multiple Packet Count 20 2 DAR Device address 22 7 ODDFRM Odd frame 29 1 CDIS Channel disable 30 1 CEN Channel enable 31 1 HCH9CTL HCH9CTL host channel-9 characteristics register (HCH9CTL) 0x220 0x20 read-write 0x00000000 MPL Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSD Low-speed device 17 1 EPTYPE Endpoint type 18 2 MPC Multiple Packet Count 20 2 DAR Device address 22 7 ODDFRM Odd frame 29 1 CDIS Channel disable 30 1 CEN Channel enable 31 1 HCH10CTL HCH10CTL host channel-10 characteristics register (HCH10CTL) 0x240 0x20 read-write 0x00000000 MPL Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSD Low-speed device 17 1 EPTYPE Endpoint type 18 2 MPC Multiple Packet Count 20 2 DAR Device address 22 7 ODDFRM Odd frame 29 1 CDIS Channel disable 30 1 CEN Channel enable 31 1 HCH11CTL HCH11CTL host channel-11 characteristics register (HCH11CTL) 0x260 0x20 read-write 0x00000000 MPL Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSD Low-speed device 17 1 EPTYPE Endpoint type 18 2 MPC Multiple Packet Count 20 2 DAR Device address 22 7 ODDFRM Odd frame 29 1 CDIS Channel disable 30 1 CEN Channel enable 31 1 HCH0INTF HCH0INTF host channel-0 interrupt register (USBHS_HCHxINTF) 0x108 0x20 read-write 0x00000000 TF Transfer finished 0 1 CH Channel halted 1 1 DMAER DMA Error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET NYET 6 1 USBER USB bus error 7 1 BBER Babble error 8 1 REQOVR Request queue overrun 9 1 DTER Data toggle error 10 1 HCH1INTF HCH1INTF host channel-1 interrupt register (HCH1INTF) 0x128 0x20 read-write 0x00000000 TF Transfer finished 0 1 CH Channel halted 1 1 DMAER DMA Error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET NYET 6 1 USBER USB bus error 7 1 BBER Babble error 8 1 REQOVR Request queue overrun 9 1 DTER Data toggle error 10 1 HCH2INTF HCH2INTF host channel-2 interrupt register (HCH2INTF) 0x148 0x20 read-write 0x00000000 TF Transfer finished 0 1 CH Channel halted 1 1 DMAER DMA Error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET NYET 6 1 USBER USB bus error 7 1 BBER Babble error 8 1 REQOVR Request queue overrun 9 1 DTER Data toggle error 10 1 HCH3INTF HCH3INTF host channel-3 interrupt register (HCH3INTF) 0x168 0x20 read-write 0x00000000 TF Transfer finished 0 1 CH Channel halted 1 1 DMAER DMA Error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET NYET 6 1 USBER USB bus error 7 1 BBER Babble error 8 1 REQOVR Request queue overrun 9 1 DTER Data toggle error 10 1 HCH4INTF HCH4INTF host channel-4 interrupt register (HCH4INTF) 0x188 0x20 read-write 0x00000000 TF Transfer finished 0 1 CH Channel halted 1 1 DMAER DMA Error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET NYET 6 1 USBER USB bus error 7 1 BBER Babble error 8 1 REQOVR Request queue overrun 9 1 DTER Data toggle error 10 1 HCH5INTF HCH5INTF host channel-5 interrupt register (HCH5INTF) 0x1A8 0x20 read-write 0x00000000 TF Transfer finished 0 1 CH Channel halted 1 1 DMAER DMA Error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET NYET 6 1 USBER USB bus error 7 1 BBER Babble error 8 1 REQOVR Request queue overrun 9 1 DTER Data toggle error 10 1 HCH6INTF HCH6INTF host channel-6 interrupt register (HCH6INTF) 0x1C8 0x20 read-write 0x00000000 TF Transfer finished 0 1 CH Channel halted 1 1 DMAER DMA Error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET NYET 6 1 USBER USB bus error 7 1 BBER Babble error 8 1 REQOVR Request queue overrun 9 1 DTER Data toggle error 10 1 HCH7INTF HCH7INTF host channel-7 interrupt register (HCH7INTF) 0x1E8 0x20 read-write 0x00000000 TF Transfer finished 0 1 CH Channel halted 1 1 DMAER DMA Error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET NYET 6 1 USBER USB bus error 7 1 BBER Babble error 8 1 REQOVR Request queue overrun 9 1 DTER Data toggle error 10 1 HCH8INTF HCH8INTF host channel-8 interrupt register (HCH8INTF) 0x208 0x20 read-write 0x00000000 TF Transfer finished 0 1 CH Channel halted 1 1 DMAER DMA Error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET NYET 6 1 USBER USB bus error 7 1 BBER Babble error 8 1 REQOVR Request queue overrun 9 1 DTER Data toggle error 10 1 HCH9INTF HCH9INTF host channel-9 interrupt register (HCH9INTF) 0x228 0x20 read-write 0x00000000 TF Transfer finished 0 1 CH Channel halted 1 1 DMAER DMA Error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET NYET 6 1 USBER USB bus error 7 1 BBER Babble error 8 1 REQOVR Request queue overrun 9 1 DTER Data toggle error 10 1 HCH10INTF HCH10INTF host channel-10 interrupt register (HCH10INTF) 0x248 0x20 read-write 0x00000000 TF Transfer finished 0 1 CH Channel halted 1 1 DMAER DMA Error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET NYET 6 1 USBER USB bus error 7 1 BBER Babble error 8 1 REQOVR Request queue overrun 9 1 DTER Data toggle error 10 1 HCH11INTF HCH11INTF host channel-11 interrupt register (HCH11INTF) 0x268 0x20 read-write 0x00000000 TF Transfer finished 0 1 CH Channel halted 1 1 DMAER DMA Error 2 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 NYET NYET 6 1 USBER USB bus error 7 1 BBER Babble error 8 1 REQOVR Request queue overrun 9 1 DTER Data toggle error 10 1 HCH0INTEN HCH0INTEN host channel-0 interrupt enable register (HCH0INTEN) 0x10C 0x20 read-write 0x00000000 TFIE Transfer completed interrupt enable 0 1 CHIE Channel halted interrupt enable 1 1 DMAERIE DMA Error interrupt enable 2 1 STALLIE STALL interrupt enable 3 1 NAKIE NAK interrupt enable 4 1 ACKIE ACK interrupt enable 5 1 NYETIE NYET interrupt enable 6 1 USBERIE USB bus error interrupt enable 7 1 BBERIE Babble error interrupt enable 8 1 REQOVRIE request queue overrun interrupt enable 9 1 DTERIE Data toggle error interrupt enable 10 1 HCH1INTEN HCH1INTEN host channel-1 interrupt enable register (HCH1INTEN) 0x12C 0x20 read-write 0x00000000 TFIE Transfer completed interrupt enable 0 1 CHIE Channel halted interrupt enable 1 1 STALLIE STALL interrupt enable 3 1 NAKIE NAK interrupt enable 4 1 ACKIE ACK interrupt enable 5 1 USBERIE USB bus error interrupt enable 7 1 BBERIE Babble error interrupt enable 8 1 REQOVRIE request queue overrun interrupt enable 9 1 DTERIE Data toggle error interrupt enable 10 1 HCH2INTEN HCH2INTEN host channel-2 interrupt enable register (HCH2INTEN) 0x14C 0x20 read-write 0x00000000 TFIE Transfer completed interrupt enable 0 1 CHIE Channel halted interrupt enable 1 1 STALLIE STALL interrupt enable 3 1 NAKIE NAK interrupt enable 4 1 ACKIE ACK interrupt enable 5 1 USBERIE USB bus error interrupt enable 7 1 BBERIE Babble error interrupt enable 8 1 REQOVRIE request queue overrun interrupt enable 9 1 DTERIE Data toggle error interrupt enable 10 1 HCH3INTEN HCH3INTEN host channel-3 interrupt enable register (HCH3INTEN) 0x16C 0x20 read-write 0x00000000 TFIE Transfer completed interrupt enable 0 1 CHIE Channel halted interrupt enable 1 1 STALLIE STALL interrupt enable 3 1 NAKIE NAK interrupt enable 4 1 ACKIE ACK interrupt enable 5 1 USBERIE USB bus error interrupt enable 7 1 BBERIE Babble error interrupt enable 8 1 REQOVRIE request queue overrun interrupt enable 9 1 DTERIE Data toggle error interrupt enable 10 1 HCH4INTEN HCH4INTEN host channel-4 interrupt enable register (HCH4INTEN) 0x18C 0x20 read-write 0x00000000 TFIE Transfer completed interrupt enable 0 1 CHIE Channel halted interrupt enable 1 1 STALLIE STALL interrupt enable 3 1 NAKIE NAK interrupt enable 4 1 ACKIE ACK interrupt enable 5 1 USBERIE USB bus error interrupt enable 7 1 BBERIE Babble error interrupt enable 8 1 REQOVRIE request queue overrun interrupt enable 9 1 DTERIE Data toggle error interrupt enable 10 1 HCH5INTEN HCH5INTEN host channel-5 interrupt enable register (HCH5INTEN) 0x1AC 0x20 read-write 0x00000000 TFIE Transfer completed interrupt enable 0 1 CHIE Channel halted interrupt enable 1 1 STALLIE STALL interrupt enable 3 1 NAKIE NAK interrupt enable 4 1 ACKIE ACK interrupt enable 5 1 USBERIE USB bus error interrupt enable 7 1 BBERIE Babble error interrupt enable 8 1 REQOVRIE request queue overrun interrupt enable 9 1 DTERIE Data toggle error interrupt enable 10 1 HCH6INTEN HCH6INTEN host channel-6 interrupt enable register (HCH6INTEN) 0x1CC 0x20 read-write 0x00000000 TFIE Transfer completed interrupt enable 0 1 CHIE Channel halted interrupt enable 1 1 STALLIE STALL interrupt enable 3 1 NAKIE NAK interrupt enable 4 1 ACKIE ACK interrupt enable 5 1 USBERIE USB bus error interrupt enable 7 1 BBERIE Babble error interrupt enable 8 1 REQOVRIE request queue overrun interrupt enable 9 1 DTERIE Data toggle error interrupt enable 10 1 HCH7INTEN HCH7INTEN host channel-7 interrupt enable register (HCH7INTEN) 0x1EC 0x20 read-write 0x00000000 TFIE Transfer completed interrupt enable 0 1 CHIE Channel halted interrupt enable 1 1 STALLIE STALL interrupt enable 3 1 NAKIE NAK interrupt enable 4 1 ACKIE ACK interrupt enable 5 1 USBERIE USB bus error interrupt enable 7 1 BBERIE Babble error interrupt enable 8 1 REQOVRIE request queue overrun interrupt enable 9 1 DTERIE Data toggle error interrupt enable 10 1 HCH8INTEN HCH8INTEN host channel-8 interrupt enable register (HCH7INTEN) 0x20C 0x20 read-write 0x00000000 TFIE Transfer completed interrupt enable 0 1 CHIE Channel halted interrupt enable 1 1 STALLIE STALL interrupt enable 3 1 NAKIE NAK interrupt enable 4 1 ACKIE ACK interrupt enable 5 1 USBERIE USB bus error interrupt enable 7 1 BBERIE Babble error interrupt enable 8 1 REQOVRIE request queue overrun interrupt enable 9 1 DTERIE Data toggle error interrupt enable 10 1 HCH9INTEN HCH9INTEN host channel-9 interrupt enable register (HCH9INTEN) 0x22C 0x20 read-write 0x00000000 TFIE Transfer completed interrupt enable 0 1 CHIE Channel halted interrupt enable 1 1 STALLIE STALL interrupt enable 3 1 NAKIE NAK interrupt enable 4 1 ACKIE ACK interrupt enable 5 1 USBERIE USB bus error interrupt enable 7 1 BBERIE Babble error interrupt enable 8 1 REQOVRIE request queue overrun interrupt enable 9 1 DTERIE Data toggle error interrupt enable 10 1 HCH10INTEN HCH10INTEN host channel-10 interrupt enable register (HCH10INTEN) 0x24C 0x20 read-write 0x00000000 TFIE Transfer completed interrupt enable 0 1 CHIE Channel halted interrupt enable 1 1 STALLIE STALL interrupt enable 3 1 NAKIE NAK interrupt enable 4 1 ACKIE ACK interrupt enable 5 1 USBERIE USB bus error interrupt enable 7 1 BBERIE Babble error interrupt enable 8 1 REQOVRIE request queue overrun interrupt enable 9 1 DTERIE Data toggle error interrupt enable 10 1 HCH11INTEN HCH11INTEN host channel-11 interrupt enable register (HCH11INTEN) 0x26C 0x20 read-write 0x00000000 TFIE Transfer completed interrupt enable 0 1 CHIE Channel halted interrupt enable 1 1 STALLIE STALL interrupt enable 3 1 NAKIE NAK interrupt enable 4 1 ACKIE ACK interrupt enable 5 1 USBERIE USB bus error interrupt enable 7 1 BBERIE Babble error interrupt enable 8 1 REQOVRIE request queue overrun interrupt enable 9 1 DTERIE Data toggle error interrupt enable 10 1 HCH0LEN HCH0LEN host channel-0 transfer length register 0x110 0x20 read-write 0x00000000 TLEN Transfer length 0 19 PCNT Packet count 19 10 DPID Data PID 29 2 PING PING token request 31 1 HCH1LEN HCH1LEN host channel-1 transfer length register 0x130 0x20 read-write 0x00000000 TLEN Transfer length 0 19 PCNT Packet count 19 10 DPID Data PID 29 2 PING PING token request 31 1 HCH2LEN HCH2LEN host channel-2 transfer length register 0x150 0x20 read-write 0x00000000 TLEN Transfer length 0 19 PCNT Packet count 19 10 DPID Data PID 29 2 PING PING token request 31 1 HCH3LEN HCH3LEN host channel-3 transfer length register 0x170 0x20 read-write 0x00000000 TLEN Transfer length 0 19 PCNT Packet count 19 10 DPID Data PID 29 2 PING PING token request 31 1 HCH4LEN HCH4LEN host channel-4 transfer length register 0x190 0x20 read-write 0x00000000 TLEN Transfer length 0 19 PCNT Packet count 19 10 DPID Data PID 29 2 PING PING token request 31 1 HCH5LEN HCH5LEN host channel-5 transfer length register 0x1B0 0x20 read-write 0x00000000 TLEN Transfer length 0 19 PCNT Packet count 19 10 DPID Data PID 29 2 PING PING token request 31 1 HCH6LEN HCH6LEN host channel-6 transfer length register 0x1D0 0x20 read-write 0x00000000 TLEN Transfer length 0 19 PCNT Packet count 19 10 DPID Data PID 29 2 PING PING token request 31 1 HCH7LEN HCH7LEN host channel-7 transfer length register 0x1F0 0x20 read-write 0x00000000 TLEN Transfer length 0 19 PCNT Packet count 19 10 DPID Data PID 29 2 PING PING token request 31 1 HCH8LEN HCH8LEN host channel-8 transfer length register 0x210 0x20 read-write 0x00000000 TLEN Transfer length 0 19 PCNT Packet count 19 10 DPID Data PID 29 2 PING PING token request 31 1 HCH9LEN HCH9LEN host channel-9 transfer length register 0x230 0x20 read-write 0x00000000 TLEN Transfer length 0 19 PCNT Packet count 19 10 DPID Data PID 29 2 PING PING token request 31 1 HCH10LEN HCH10LEN host channel-10 transfer length register 0x250 0x20 read-write 0x00000000 TLEN Transfer length 0 19 PCNT Packet count 19 10 DPID Data PID 29 2 PING PING token request 31 1 HCH11LEN HCH11LEN host channel-11 transfer length register 0x270 0x20 read-write 0x00000000 TLEN Transfer length 0 19 PCNT Packet count 19 10 DPID Data PID 29 2 PING PING token request 31 1 HCH0DMAADDR HCH0DMAADDR Host channel 0 DMA address register 0x114 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 HCH1DMAADDR HCH1DMAADDR Host channel 1 DMA address register 0x134 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 HCH2DMAADDR HCH2DMAADDR Host channel 2 DMA address register 0x154 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 HCH3DMAADDR HCH3DMAADDR Host channel 3 DMA address register 0x174 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 HCH4DMAADDR HCH4DMAADDR Host channel 4 DMA address register 0x194 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 HCH5DMAADDR HCH5DMAADDR Host channel 5 DMA address register 0x1B4 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 HCH6DMAADDR HCH6DMAADDR Host channel 6 DMA address register 0x1D4 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 HCH7DMAADDR HCH7DMAADDR Host channel 7 DMA address register 0x1F4 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 HCH8DMAADDR HCH8DMAADDR Host channel 8 DMA address register 0x214 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 HCH9DMAADDR HCH9DMAADDR Host channel 9 DMA address register 0x234 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 HCH10DMAADDR HCH10DMAADDR Host channel 10 DMA address register 0x254 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 HCH11DMAADDR HCH11DMAADDR Host channel 11 DMA address register 0x274 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 USBHS_DEVICE USB on the go high speed device USBHS 0x50000800 0x00 0x400 registers DCFG DCFG device configuration register (DCFG) 0x0 0x20 read-write 0x00000000 DS Device speed 0 2 NZLSOH Non-zero-length status OUT handshake 2 1 DAR Device address 4 7 EOPFT end of periodic frame time 11 2 DCTL DCTL device control register (DCTL) 0x04 0x20 0x00000000 RWKUP Remote wakeup 0 1 read-write SD Soft disconnect 1 1 read-write GINS Global IN NAK status 2 1 read-only GONS Global OUT NAK status 3 1 read-only DTEST Device Test control 4 3 read-write SGINAK Set global IN NAK 7 1 write-only CGINAK Clear global IN NAK 8 1 write-only SGONAK Set global OUT NAK 9 1 write-only CGONAK Clear global OUT NAK 10 1 write-only POIF Power-on initialization flag 11 1 read-write L1RJCT Deep sleep reject 18 1 read-write DSTAT DSTAT device status register (DSTAT) 0x08 0x20 read-only 0x00000000 SPST Suspend status 0 1 ES Enumerated speed 1 2 FNRSOF Frame number of the received SOF 8 14 DIEPINTEN DIEPINTEN device IN endpoint common interrupt mask register (DIEPINTEN) 0x10 0x20 read-write 0x00000000 TFEN Transfer finished interrupt enable 0 1 EPDISEN Endpoint disabled interrupt enable 1 1 CITOEN Control IN timeout condition interrupt enable (Non-isochronous endpoints) 3 1 EPTXFUDEN Endpoint Tx FIFO underrun interrupt enable bit 4 1 IEPNEEN IN endpoint NAK effective interrupt enable 6 1 NAKEN NAK handshake sent by USBHS interrupt enable bit 13 1 DOEPINTEN DOEPINTEN device OUT endpoint common interrupt enable register (DOEPINTEN) 0x14 0x20 read-write 0x00000000 TFEN Transfer finished interrupt enable 0 1 EPDISEN Endpoint disabled interrupt enable 1 1 STPFEN SETUP phase finished interrupt enable 3 1 EPRXFOVREN Endpoint Rx FIFO overrun interrupt enable 4 1 BTBSTPEN Back-to-back SETUP packets interrupt enable 6 1 NYETEN Send NYET handshake interrupt enable bit 14 1 DAEPINT DAEPINT device all endpoints interrupt register (DAEPINT) 0x18 0x20 read-only 0x00000000 IEPITB Device all IN endpoint interrupt bits 0 6 OEPITB Device all OUT endpoint interrupt bits 16 6 DAEPINTEN DAEPINTEN Device all endpoints interrupt enable register (DAEPINTEN) 0x1C 0x20 read-write 0x00000000 IEPIE IN EP interrupt interrupt enable bits 0 6 OEPIE OUT endpoint interrupt enable bits 16 6 DVBUSDT DVBUSDT device VBUS discharge time register 0x28 0x20 read-write 0x000017D7 DVBUSDT Device VBUS discharge time 0 16 DVBUSPT DVBUSPT device VBUS pulsing time register 0x2C 0x20 read-write 0x000005B8 DVBUSPT Device VBUS pulsing time 0 12 DIEPFEINTEN DIEPFEINTEN device IN endpoint FIFO empty interrupt enable register 0x34 0x20 read-write 0x00000000 IEPTXFEIE IN EP Tx FIFO empty interrupt enable bits 0 6 DEP1INT DEP1INT Device endpoint 1 interrupt register 0x38 0x20 read-only 0x00000000 IEP1INT IN Endpoint 1 interrupt 1 1 OEP1INT OUT Endpoint 1 interrupt 17 1 DEP1INTEN DEP1INTEN Device endpoint 1 interrupt register 0x3C 0x20 read-only 0x00000000 IEP1INTEN IN Endpoint 1 interrupt enable 1 1 OEP1INTEN OUT Endpoint 1 interrupt enable 17 1 DIEP1INTEN DIEP1INTEN Device IN endpoint 1 interrupt enable register 0x44 0x20 read-write 0x00000000 TFEN Transfer finished interrupt enable bit 0 1 EPDISEN Endpoint disabled interrupt enable bit 1 1 CITOEN Control In Timeout interrupt enable bit 3 1 EPTXFUDEN Endpoint Tx FIFO underrun interrupt enable bit 4 1 IEPNEEN IN endpoint NAK effective interrupt enable bit 6 1 NAKEN Interrupt enable bit of NAK handshake sent by USBHS 13 1 DOEP1INTEN DOEP1INTEN Device OUT endpoint 1 interrupt enable register 0x84 0x20 read-write 0x00000000 TFEN Transfer finished interrupt enable bit 0 1 EPDISEN Endpoint disabled interrupt enable bit 1 1 STPFEN SETUP phase finished interrupt enable bit 3 1 EPRXFOVREN Endpoint Rx FIFO over run interrupt enable bit 4 1 BTBSTPEN Back-to-back SETUP packets interrupt enable bit 6 1 NYETEN Send NYET handshake interrupt enable bit 13 1 DIEP0CTL DIEP0CTL device IN endpoint 0 control register (DIEP0CTL) 0x100 0x20 0x00008000 MPL Maximum packet length 0 2 read-write EPACT endpoint active 15 1 read-only NAKS NAK status 17 1 read-only EPTYPE Endpoint type 18 2 read-only STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only EPD Endpoint disable 30 1 read-write EPEN Endpoint enable 31 1 read-write DIEP1CTL DIEP1CTL device in endpoint-1 control register 0x120 0x20 0x00000000 EPEN Endpoint enable 31 1 read-write EPD Endpoint disable 30 1 read-write SD1PID_SODDFRM Set DATA1 PID/Set odd frame 29 1 write-only SD0PID_SEVENFRM SD0PID/SEVNFRM 28 1 write-only SNAK Set NAK 27 1 write-only CNAK Clear NAK 26 1 write-only TXFNUM Tx FIFO number 22 4 read-write STALL STALL handshake 21 1 read-write EPTYPE Endpoint type 18 2 read-write NAKS NAK status 17 1 read-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write MPL maximum packet length 0 11 read-write DIEP2CTL DIEP2CTL device endpoint-2 control register 0x140 0x20 0x00000000 EPEN Endpoint enable 31 1 read-write EPD Endpoint disable 30 1 read-write SD1PID_SODDFRM Set DATA1 PID/Set odd frame 29 1 write-only SD0PID_SEVENFRM SD0PID/SEVNFRM 28 1 write-only SNAK Set NAK 27 1 write-only CNAK Clear NAK 26 1 write-only TXFNUM Tx FIFO number 22 4 read-write STALL STALL handshake 21 1 read-write EPTYPE Endpoint type 18 2 read-write NAKS NAK status 17 1 read-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write MPL maximum packet length 0 11 read-write DIEP3CTL DIEP3CTL device endpoint-3 control register 0x160 0x20 0x00000000 EPEN Endpoint enable 31 1 read-write EPD Endpoint disable 30 1 read-write SD1PID_SODDFRM Set DATA1 PID/Set odd frame 29 1 write-only SD0PID_SEVENFRM SD0PID/SEVNFRM 28 1 write-only SNAK Set NAK 27 1 write-only CNAK Clear NAK 26 1 write-only TXFNUM Tx FIFO number 22 4 read-write STALL STALL handshake 21 1 read-write EPTYPE Endpoint type 18 2 read-write NAKS NAK status 17 1 read-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write MPL maximum packet length 0 11 read-write DIEP4CTL DIEP4CTL device endpoint-4 control register 0x180 0x20 0x00000000 EPEN Endpoint enable 31 1 read-write EPD Endpoint disable 30 1 read-write SD1PID_SODDFRM Set DATA1 PID/Set odd frame 29 1 write-only SD0PID_SEVENFRM SD0PID/SEVNFRM 28 1 write-only SNAK Set NAK 27 1 write-only CNAK Clear NAK 26 1 write-only TXFNUM Tx FIFO number 22 4 read-write STALL STALL handshake 21 1 read-write EPTYPE Endpoint type 18 2 read-write NAKS NAK status 17 1 read-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write MPL maximum packet length 0 11 read-write DIEP5CTL DIEP5CTL device endpoint-5 control register 0x1A0 0x20 0x00000000 EPEN Endpoint enable 31 1 read-write EPD Endpoint disable 30 1 read-write SD1PID_SODDFRM Set DATA1 PID/Set odd frame 29 1 write-only SD0PID_SEVENFRM SD0PID/SEVNFRM 28 1 write-only SNAK Set NAK 27 1 write-only CNAK Clear NAK 26 1 write-only TXFNUM Tx FIFO number 22 4 read-write STALL STALL handshake 21 1 read-write EPTYPE Endpoint type 18 2 read-write NAKS NAK status 17 1 read-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write MPL maximum packet length 0 11 read-write DOEP0CTL DOEP0CTL device endpoint-0 control register 0x300 0x20 0x00008000 EPEN Endpoint enable 31 1 write-only EPD Endpoint disable 30 1 read-only SNAK Set NAK 27 1 write-only CNAK Clear NAK 26 1 write-only STALL STALL handshake 21 1 read-write SNOOP Snoop mode 20 1 read-write EPTYPE Endpoint type 18 2 read-only NAKS NAK status 17 1 read-only EPACT Endpoint active 15 1 read-only MPL Maximum packet length 0 2 read-only DOEP1CTL DOEP1CTL device endpoint-1 control register 0x320 0x20 0x00000000 EPEN Endpoint enable 31 1 read-write EPD Endpoint disable 30 1 read-write SD1PID_SODDFRM SD1PID/SODDFRM 29 1 write-only SD0PID_SEVENFRM SD0PID/SEVENFRM 28 1 write-only SNAK Set NAK 27 1 write-only CNAK Clear NAK 26 1 write-only STALL STALL handshake 21 1 read-write SNOOP Snoop mode 20 1 read-write EPTYPE Endpoint type 18 2 read-write NAKS NAK status 17 1 read-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write MPL maximum packet length 0 11 read-write DOEP2CTL DOEP2CTL device endpoint-2 control register 0x340 0x20 0x00000000 EPEN Endpoint enable 31 1 read-write EPD Endpoint disable 30 1 read-write SD1PID_SODDFRM SD1PID/SODDFRM 29 1 write-only SD0PID_SEVENFRM SD0PID/SEVENFRM 28 1 write-only SNAK Set NAK 27 1 write-only CNAK Clear NAK 26 1 write-only STALL STALL handshake 21 1 read-write SNOOP Snoop mode 20 1 read-write EPTYPE Endpoint type 18 2 read-write NAKS NAK status 17 1 read-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write MPL maximum packet length 0 11 read-write DOEP3CTL DOEP3CTL device endpoint-3 control register 0x360 0x20 0x00000000 EPEN Endpoint enable 31 1 read-write EPD Endpoint disable 30 1 read-write SD1PID_SODDFRM SD1PID/SODDFRM 29 1 write-only SD0PID_SEVENFRM SD0PID/SEVENFRM 28 1 write-only SNAK Set NAK 27 1 write-only CNAK Clear NAK 26 1 write-only STALL STALL handshake 21 1 read-write SNOOP Snoop mode 20 1 read-write EPTYPE Endpoint type 18 2 read-write NAKS NAK status 17 1 read-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write MPL maximum packet length 0 11 read-write DOEP4CTL DOEP4CTL device endpoint-4 control register 0x380 0x20 0x00000000 EPEN Endpoint enable 31 1 read-write EPD Endpoint disable 30 1 read-write SD1PID_SODDFRM SD1PID/SODDFRM 29 1 write-only SD0PID_SEVENFRM SD0PID/SEVENFRM 28 1 write-only SNAK Set NAK 27 1 write-only CNAK Clear NAK 26 1 write-only STALL STALL handshake 21 1 read-write SNOOP Snoop mode 20 1 read-write EPTYPE Endpoint type 18 2 read-write NAKS NAK status 17 1 read-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write MPL maximum packet length 0 11 read-write DOEP5CTL DOEP5CTL device endpoint-5 control register 0x3A0 0x20 0x00000000 EPEN Endpoint enable 31 1 read-write EPD Endpoint disable 30 1 read-write SD1PID_SODDFRM SD1PID/SODDFRM 29 1 write-only SD0PID_SEVENFRM SD0PID/SEVENFRM 28 1 write-only SNAK Set NAK 27 1 write-only CNAK Clear NAK 26 1 write-only STALL STALL handshake 21 1 read-write SNOOP Snoop mode 20 1 read-write EPTYPE Endpoint type 18 2 read-write NAKS NAK status 17 1 read-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write MPL maximum packet length 0 11 read-write DIEP0INTF DIEP0INTF device endpoint-0 interrupt register 0x108 0x20 0x00000080 NAK NAK handshake sent by USBHS 13 1 read-write TXFE Transmit FIFO empty 7 1 read-only IEPNE IN endpoint NAK effective 6 1 read-write EPTXFUD Endpoint Tx FIFO underrun 4 1 read-write CITO Control in timeout interrupt 3 1 read-write EPDIS Endpoint finished 1 1 read-write TF Transfer finished 0 1 read-write DIEP1INTF DIEP1INTF device endpoint-1 interrupt register 0x128 0x20 0x00000080 NAK NAK handshake sent by USBHS 13 1 read-write TXFE Transmit FIFO empty 7 1 read-only IEPNE IN endpoint NAK effective 6 1 read-write EPTXFUD Endpoint Tx FIFO underrun 4 1 read-write CITO Control in timeout interrupt 3 1 read-write EPDIS Endpoint finished 1 1 read-write TF Transfer finished 0 1 read-write DIEP2INTF DIEP2INTF device endpoint-2 interrupt register 0x148 0x20 0x00000080 NAK NAK handshake sent by USBHS 13 1 read-write TXFE Transmit FIFO empty 7 1 read-only IEPNE IN endpoint NAK effective 6 1 read-write EPTXFUD Endpoint Tx FIFO underrun 4 1 read-write CITO Control in timeout interrupt 3 1 read-write EPDIS Endpoint finished 1 1 read-write TF Transfer finished 0 1 read-write DIEP3INTF DIEP3INTF device endpoint-3 interrupt register 0x168 0x20 0x00000080 NAK NAK handshake sent by USBHS 13 1 read-write TXFE Transmit FIFO empty 7 1 read-only IEPNE IN endpoint NAK effective 6 1 read-write EPTXFUD Endpoint Tx FIFO underrun 4 1 read-write CITO Control in timeout interrupt 3 1 read-write EPDIS Endpoint finished 1 1 read-write TF Transfer finished 0 1 read-write DIEP4INTF DIEP4INTF device endpoint-4 interrupt register 0x188 0x20 0x00000080 NAK NAK handshake sent by USBHS 13 1 read-write TXFE Transmit FIFO empty 7 1 read-only IEPNE IN endpoint NAK effective 6 1 read-write EPTXFUD Endpoint Tx FIFO underrun 4 1 read-write CITO Control in timeout interrupt 3 1 read-write EPDIS Endpoint finished 1 1 read-write TF Transfer finished 0 1 read-write DIEP5INTF DIEP5INTF device endpoint-5 interrupt register 0x1A8 0x20 0x00000080 NAK NAK handshake sent by USBHS 13 1 read-write TXFE Transmit FIFO empty 7 1 read-only IEPNE IN endpoint NAK effective 6 1 read-write EPTXFUD Endpoint Tx FIFO underrun 4 1 read-write CITO Control in timeout interrupt 3 1 read-write EPDIS Endpoint finished 1 1 read-write TF Transfer finished 0 1 read-write DOEP0INTF DOEP0INTF device out endpoint-0 interrupt flag register 0x308 0x20 read-write 0x00000000 NYET NYET handshake is sent 14 1 BTBSTP Back-to-back SETUP packets 6 1 EPRXFOVR Endpoint Rx FIFO overrun 4 1 STPF Setup phase finished 3 1 EPDIS Endpoint disabled 1 1 TF Transfer finished 0 1 DOEP1INTF DOEP1INTF device out endpoint-1 interrupt flag register 0x328 0x20 read-write 0x00000000 NYET NYET handshake is sent 14 1 BTBSTP Back-to-back SETUP packets 6 1 EPRXFOVR Endpoint Rx FIFO overrun 4 1 STPF Setup phase finished 3 1 EPDIS Endpoint disabled 1 1 TF Transfer finished 0 1 DOEP2INTF DOEP2INTF device out endpoint-2 interrupt flag register 0x348 0x20 read-write 0x00000000 NYET NYET handshake is sent 14 1 BTBSTP Back-to-back SETUP packets 6 1 EPRXFOVR Endpoint Rx FIFO overrun 4 1 STPF Setup phase finished 3 1 EPDIS Endpoint disabled 1 1 TF Transfer finished 0 1 DOEP3INTF DOEP3INTF device out endpoint-3 interrupt flag register 0x368 0x20 read-write 0x00000000 NYET NYET handshake is sent 14 1 BTBSTP Back-to-back SETUP packets 6 1 EPRXFOVR Endpoint Rx FIFO overrun 4 1 STPF Setup phase finished 3 1 EPDIS Endpoint disabled 1 1 TF Transfer finished 0 1 DOEP4INTF DOEP4INTF device out endpoint-4 interrupt flag register 0x388 0x20 read-write 0x00000000 NYET NYET handshake is sent 14 1 BTBSTP Back-to-back SETUP packets 6 1 EPRXFOVR Endpoint Rx FIFO overrun 4 1 STPF Setup phase finished 3 1 EPDIS Endpoint disabled 1 1 TF Transfer finished 0 1 DOEP5INTF DOEP5INTF device out endpoint-5 interrupt flag register 0x3A8 0x20 read-write 0x00000000 NYET NYET handshake is sent 14 1 BTBSTP Back-to-back SETUP packets 6 1 EPRXFOVR Endpoint Rx FIFO overrun 4 1 STPF Setup phase finished 3 1 EPDIS Endpoint disabled 1 1 TF Transfer finished 0 1 DIEP0LEN DIEP0LEN device IN endpoint-0 transfer length register 0x110 0x20 read-write 0x00000000 PCNT Packet count 19 2 TLEN Transfer length 0 7 DOEP0LEN DOEP0LEN device OUT endpoint-0 transfer length register 0x310 0x20 read-write 0x00000000 STPCNT SETUP packet count 29 2 PCNT Packet count 19 1 TLEN Transfer length 0 7 DIEP1LEN DIEP1LEN device IN endpoint-1 transfer length register 0x130 0x20 read-write 0x00000000 MCNT Multi count 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 DIEP2LEN DIEP2LEN device IN endpoint-2 transfer length register 0x150 0x20 read-write 0x00000000 MCNT Multi count 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 DIEP3LEN DIEP3LEN device IN endpoint-3 transfer length register 0x170 0x20 read-write 0x00000000 MCNT Multi count 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 DIEP4LEN DIEP4LEN device IN endpoint-4 transfer length register 0x190 0x20 read-write 0x00000000 MCNT Multi count 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 DIEP5LEN DIEP5LEN device IN endpoint-5 transfer length register 0x1B0 0x20 read-write 0x00000000 MCNT Multi count 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 DOEP1LEN DOEP1LEN device OUT endpoint-1 transfer length register 0x330 0x20 read-write 0x00000000 STPCNT_RXDPID SETUP packet count/Received data PID 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 DOEP2LEN DOEP2LEN device OUT endpoint-2 transfer length register 0x350 0x20 read-write 0x00000000 STPCNT_RXDPID SETUP packet count/Received data PID 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 DOEP3LEN DOEP3LEN device OUT endpoint-3 transfer length register 0x370 0x20 read-write 0x00000000 STPCNT_RXDPID SETUP packet count/Received data PID 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 DOEP4LEN DOEP4LEN device OUT endpoint-4 transfer length register 0x390 0x20 read-write 0x00000000 STPCNT_RXDPID SETUP packet count/Received data PID 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 DOEP5LEN DOEP5LEN device OUT endpoint-5 transfer length register 0x3B0 0x20 read-write 0x00000000 STPCNT_RXDPID SETUP packet count/Received data PID 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 DIEP0DMAADDR DIEP0DMAADDR Device IN endpoint 0 DMA address register 0x114 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 DIEP1DMAADDR DIEP1DMAADDR Device IN endpoint 1 DMA address register 0x134 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 DIEP2DMAADDR DIEP2DMAADDR Device IN endpoint 2 DMA address register 0x154 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 DIEP3DMAADDR DIEP3DMAADDR Device IN endpoint 3 DMA address register 0x174 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 DIEP4DMAADDR DIEP4DMAADDR Device IN endpoint 4 DMA address register 0x194 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 DIEP5DMAADDR DIEP5DMAADDR Device IN endpoint 5 DMA address register 0x1B4 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 DOEP0DMAADDR DOEP0DMAADDR Device OUT endpoint 0 DMA address register 0x314 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 DOEP1DMAADDR DOEP1DMAADDR Device OUT endpoint 1 DMA address register 0x334 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 DOEP2DMAADDR DOEP2DMAADDR Device OUT endpoint 2 DMA address register 0x354 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 DOEP3DMAADDR DOEP3DMAADDR Device OUT endpoint 3 DMA address register 0x374 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 DOEP4DMAADDR DOEP4DMAADDR Device OUT endpoint 4 DMA address register 0x394 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 DOEP5DMAADDR DOEP5DMAADDR Device OUT endpoint 5 DMA address register 0x3B4 0x20 read-write 0x00000000 DMAADDR DMA address 0 32 DIEP0TFSTAT DIEP0TFSTAT device IN endpoint 0 transmit FIFO status register 0x118 0x20 read-only 0x00000200 IEPTFS IN endpoint TxFIFO space remaining 0 16 DIEP1TFSTAT DIEP1TFSTAT device IN endpoint 1 transmit FIFO status register 0x138 0x20 read-only 0x00000200 IEPTFS IN endpoint TxFIFO space remaining 0 16 DIEP2TFSTAT DIEP2TFSTAT device IN endpoint 2 transmit FIFO status register 0x158 0x20 read-only 0x00000200 IEPTFS IN endpoint TxFIFO space remaining 0 16 DIEP3TFSTAT DIEP3TFSTAT device IN endpoint 3 transmit FIFO status register 0x178 0x20 read-only 0x00000200 IEPTFS IN endpoint TxFIFO space remaining 0 16 DIEP4TFSTAT DIEP4TFSTAT device IN endpoint 4 transmit FIFO status register 0x198 0x20 read-only 0x00000200 IEPTFS IN endpoint TxFIFO space remaining 0 16 DIEP5TFSTAT DIEP5TFSTAT device IN endpoint 5 transmit FIFO status register 0x1B8 0x20 read-only 0x00000200 IEPTFS IN endpoint TxFIFO space remaining 0 16 USBHS_PWRCLK USB on the go high speed USBHS 0x50000E00 0x0 0x100 registers PWRCLKCTL PWRCLKCTL power and clock gating control register (PWRCLKCTL) 0x00 0x20 0x00000000 SUCLK Stop the USB clock 0 1 read-write SHCLK Stop HCLK 1 1 read-write SUSP PHY is in suspend status 4 1 read-only SCGEN internal clock gating enable 5 1 read-only SSLEEP PHY is in shallow sleep status 6 1 read-only DSLEEP PHY is in deep sleep status 7 1 read-only WWDGT Window watchdog timer WWDGT 0x40002C00 0x0 0x400 registers WWDGT 0 CTL CTL Control register 0x0 0x20 read-write 0x0000007F WDGTEN Activation bit 7 1 WDGTENread-writeDisabledWatchdog disabled0EnabledWatchdog enabled1 CNT 7-bit counter 0 7 0127 CFG CFG Configuration register 0x04 0x20 read-write 0x0000007F EWIE Early wakeup interrupt 9 1 EWIEWwriteEnableinterrupt occurs whenever the counter reaches the value 0x401 PSC Prescaler 7 2 PSCread-writeDiv1Counter clock (PCLK1 div 4096) div 10Div2Counter clock (PCLK1 div 4096) div 21Div4Counter clock (PCLK1 div 4096) div 42Div8Counter clock (PCLK1 div 4096) div 83 WIN 7-bit window value 0 7 0127 STAT STAT Status register 0x08 0x20 read-write 0x00000000 EWIF Early wakeup interrupt flag 0 1 EWIFRreadPendingThe EWI Interrupt Service Routine has been triggered1FinishedThe EWI Interrupt Service Routine has been serviced0 EWIFWwriteFinishedThe EWI Interrupt Service Routine has been serviced0