GD32F307 1.0 GD32F30x ARM 32-bit Cortex-M4 Microcontroller based device CM4 r2p1 little 1 1 4 0 8 32 0x20 0x0 0xFFFFFFFF ADC0 Analog to digital converter ADC 0x40012400 0x0 0x400 registers ADC0_1 18 STAT STAT status register 0x0 0x20 read-write 0x00000000 STRC Start flag of regular channel group 4 1 STRCRreadNotStartedNo regular channel conversion started0StartedRegular channel conversion has started1 STRCWwriteClearClear the regular channel start flag0 STIC Start flag of inserted channel group 3 1 STICRreadNotStartedNo inserted channel group conversion started0StartedInserted channel group conversion has started1 STICWwriteClearClear the inserted channel group start flag0 EOIC End of inserted group conversion flag 2 1 EOICRreadNotCompleteConversion is not complete0CompleteConversion complete1 EOICWwriteClearClear end of inserted group conversion flag0 EOC End of group conversion flag 1 1 EOCRreadNotCompleteConversion is not complete0CompleteConversion complete1 EOCWwriteClearClear end of group conversion flag0 WDE Analog watchdog event flag 0 1 WDERreadNoEventNo analog watchdog event occurred0EventAnalog watchdog event occurred1 WDEWwriteClearClear the analog watchdog event flag0 CTL0 CTL0 control register 0 0x4 0x20 read-write 0x00000000 RWDEN Regular channel analog watchdog enable 23 1 RWDENread-writeDisabledAnalog watchdog disabled on regular channels0EnabledAnalog watchdog enabled on regular channels1 IWDEN Inserted channel analog watchdog enable 22 1 IWDENread-writeDisabledAnalog watchdog disabled on inserted channels0EnabledAnalog watchdog enabled on inserted channels1 SYNCM sync mode selection 16 3 DISNUM Number of conversions in discontinuous mode 13 3 07 DISIC Discontinuous mode on inserted channels 12 1 DISICread-writeDisabledDiscontinuous mode on inserted channels disabled0EnabledDiscontinuous mode on inserted channels enabled1 DISRC Discontinuous mode on regular channels 11 1 DISRCread-writeDisabledDiscontinuous mode on regular channels disabled0EnabledDiscontinuous mode on regular channels enabled1 ICA Inserted channel group convert automatically 10 1 ICAread-writeDisabledAutomatic inserted group conversion disabled0EnabledAutomatic inserted group conversion enabled1 WDSC When in scan mode, analog watchdog is effective on a single channel 9 1 WDSCread-writeAllAnalog watchdog enabled on all channels0SingleAnalog watchdog enabled on a single channel1 SM Scan mode 8 1 SMread-writeDisabledScan mode disabled0EnabledScan mode enabled1 EOICIE Interrupt enable for EOIC 7 1 EOICIEread-writeDisabledEOIC interrupt disabled0EnabledEOIC interrupt enabled. An interrupt is generated when the EOIC bit is set1 WDEIE Interrupt enable for WDE 6 1 WDEIEread-writeDisabledWDE interrupt disabled0EnabledWDE interrupt enabled. An interrupt is generated when the WDE bit is set1 EOCIE Interrupt enable for EOC 5 1 EOCIEread-writeDisabledEOC interrupt disabled0EnabledEOC interrupt enabled. An interrupt is generated when the EOC bit is set1 WDCHSEL Analog watchdog channel select 0 5 018 CTL1 CTL1 control register 1 0x08 0x20 read-write 0x00000000 TSVREN Channel 16 and 17 enable of ADC0 23 1 TSVRENread-writeDisabledChannel 16 and 17 disabled0EnabledChannel 16 and 17 enabled1 SWRCST Start on regular channel 22 1 SWRCSTRreadStartedReset state0NotStartedStarting conversion of regular channels1 SWRCSTWwriteStartStart conversion of regular channels1 SWICST Start on inserted channel 21 1 SWICSTRreadStartedReset state0NotStartedStarting conversion of inserted channels1 SWICSTWwriteStartStart conversion of inserted channels1 ETERC External trigger enable for regular channel 20 1 ETERCread-writeDisabledConversion on external event disabled0EnabledConversion on external event enabled1 ETSRC External trigger select for regular channel 17 3 ETSRCread-writeTimer0Ch0Timer 0 channel 0 event0Timer0Ch1Timer 0 channel 1 event1Timer0Ch2Timer 0 channel 2 event2Timer1Ch1Timer 1 channel 1 event3Timer2TrgoTimer 2 TRGO event4Timer14Ch0Timer 14 channel 0 event5Exti11EXTI line 116SwrcstSWRCST7 ETSIC External trigger select for inserted channel 12 3 ETSICread-writeTimer0TrgoTimer 0 TRGO event0Timer0Ch3Timer 0 channel 3 event1Timer1TrgoTimer 1 TRGO event2Timer1Ch0Timer 1 channel 0 event3Timer2Ch2Timer 2 channel 3 event4Timer14TrgoTimer 14 TRGO event5Exti15EXTI line 156SwicstSWICST7 DAL Data alignment 11 1 DALread-writeRightRight alignment0LeftLeft alignment1 DMA DMA request enable 8 1 DMAread-writeDisabledDMA mode disabled0EnabledDMA mode enabled1 RSTCLB Reset calibration 3 1 RSTCLBRreadCompleteCalibration completed0NotCompleteCalibrating1 RSTCLBWwriteStartEnable calibration1 CLB ADC calibration 2 1 CLBRreadCompleteCalibration completed0NotCompleteCalibrating1 CLBWwriteStartEnable calibration1 CTN Continuous mode 1 1 CTNread-writeSingleSingle conversion mode0ContinuousContinuous conversion mode1 ADCON ADC on 0 1 ADCONread-writeDisabledDisable ADC conversion/calibration and go to power down mode0EnabledEnable ADC and to start conversion1 SAMPT0 SAMPT0 Sample time register 0 0x0C 0x20 read-write 0x00000000 SPT10 Channel 10 sample time selection 0 3 SPT10read-writeCycles1_51.5 ADC clock cycles0Cycles7_57.5 ADC clock cycles1Cycles13_513.5 ADC clock cycles2Cycles28_528.5 ADC clock cycles3Cycles41_541.5 ADC clock cycles4Cycles55_555.5 ADC clock cycles5Cycles71_571.5 ADC clock cycles6Cycles239_5239.5 ADC clock cycles7 SPT11 Channel 11 sample time selection 3 3 SPT12 Channel 12 sample time selection 6 3 SPT13 Channel 13 sample time selection 9 3 SPT14 Channel 14 sample time selection 12 3 SPT15 Channel 15 sample time selection 15 3 SPT16 Channel 16 sample time selection 18 3 SPT17 Channel 17 sample time selection 21 3 SAMPT1 SAMPT1 Sample time register 1 0x10 0x20 read-write 0x00000000 SPT0 Channel 0 sample time selection 0 3 SPT0read-writeCycles1_51.5 ADC clock cycles0Cycles7_57.5 ADC clock cycles1Cycles13_513.5 ADC clock cycles2Cycles28_528.5 ADC clock cycles3Cycles41_541.5 ADC clock cycles4Cycles55_555.5 ADC clock cycles5Cycles71_571.5 ADC clock cycles6Cycles239_5239.5 ADC clock cycles7 SPT1 Channel 1 sample time selection 3 3 SPT2 Channel 2 sample time selection 6 3 SPT3 Channel 3 sample time selection 9 3 SPT4 Channel 4 sample time selection 12 3 SPT5 Channel 5 sample time selection 15 3 SPT6 Channel 6 sample time selection 18 3 SPT7 Channel 7 sample time selection 21 3 SPT8 Channel 8 sample time selection 24 3 SPT9 Channel 9 sample time selection 27 3 IOFF0 IOFF0 Inserted channel data offset register 0 0x14 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 0 0 12 04095 IOFF1 IOFF1 Inserted channel data offset register 1 0x18 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 1 0 12 04095 IOFF2 IOFF2 Inserted channel data offset register 2 0x1C 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 2 0 12 04095 IOFF3 IOFF3 Inserted channel data offset register 3 0x20 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 3 0 12 04095 WDHT WDHT watchdog higher threshold register 0x24 0x20 read-write 0x00000FFF WDHT Analog watchdog higher threshold 0 12 04095 WDLT WDLT watchdog lower threshold register 0x28 0x20 read-write 0x00000000 WDLT Analog watchdog lower threshold 0 12 04095 RSQ0 RSQ0 regular sequence register 0 0x2C 0x20 read-write 0x00000000 RL Regular channel group length 20 4 015 RSQ15 16th conversion in regular sequence 15 5 018 RSQ14 15th conversion in regular sequence 10 5 018 RSQ13 14th conversion in regular sequence 5 5 018 RSQ12 13th conversion in regular sequence 0 5 018 RSQ1 RSQ1 regular sequence register 1 0x30 0x20 read-write 0x00000000 RSQ11 12th conversion in regular sequence 25 5 018 RSQ10 11th conversion in regular sequence 20 5 018 RSQ9 10th conversion in regular sequence 15 5 018 RSQ8 9th conversion in regular sequence 10 5 018 RSQ7 8th conversion in regular sequence 5 5 018 RSQ6 7th conversion in regular sequence 0 5 018 RSQ2 RSQ2 regular sequence register 2 0x34 0x20 read-write 0x00000000 RSQ5 6th conversion in regular sequence 25 5 018 RSQ4 5th conversion in regular sequence 20 5 018 RSQ3 4th conversion in regular sequence 15 5 018 RSQ2 3rd conversion in regular sequence 10 5 018 RSQ1 2nd conversion in regular sequence 5 5 018 RSQ0 1st conversion in regular sequence 0 5 018 ISQ ISQ Inserted sequence register 0x38 0x20 read-write 0x00000000 IL Inserted channel group length 20 2 03 ISQ3 4th conversion in inserted sequence 15 5 018 ISQ2 3rd conversion in inserted sequence 10 5 018 ISQ1 2nd conversion in inserted sequence 5 5 018 ISQ0 1st conversion in inserted sequence 0 5 018 IDATA0 IDATA0 Inserted data register 0 0x3C 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 065535 IDATA1 IDATA1 Inserted data register 1 0x40 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 065535 IDATA2 IDATA2 Inserted data register 2 0x44 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 065535 IDATA3 IDATA3 Inserted data register 3 0x48 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 065535 RDATA RDATA regular data register 0x4C 0x20 read-only 0x00000000 ADC1RDTR ADCegular channel data 16 16 RDATA Regular channel data 0 16 065535 OVSAMPCTL OVSAMPCTL Oversample control register 0x80 0x20 read-write 0x00000000 DRES ADC resolution 12 2 DRESread-writeBits1212 bit resolution0Bits1010 bit resolution1Bits88 bit resolution2Bits66 bit resolution3 TOVS Triggered Oversampling 9 1 TOVSread-writeConsecutiveAll oversampled conversions are done consecutively0IndividualEach oversampled conversion needs a trigger1 OVSS Oversampling shift 5 4 08 OVSR Oversampling ratio 2 3 OVSRread-writeTimes22x0Times44x1Times88x2Times1616x3Times3232x4Times6464x5Times128128x6Times256256x7 OVSEN Oversampling Enable 0 1 OVSENread-writeDisabledOversampling disabled0EnabledOversampling enabled1 ADC1 Analog to digital converter ADC 0x40012800 0x0 0x400 registers ADC0_1 18 STAT STAT status register 0x0 0x20 read-write 0x00000000 STRC Start flag of regular channel group 4 1 STRCRreadNotStartedNo regular channel conversion started0StartedRegular channel conversion has started1 STRCWwriteClearClear the regular channel start flag0 STIC Start flag of inserted channel group 3 1 STICRreadNotStartedNo inserted channel group conversion started0StartedInserted channel group conversion has started1 STICWwriteClearClear the inserted channel group start flag0 EOIC End of inserted group conversion flag 2 1 EOICRreadNotCompleteConversion is not complete0CompleteConversion complete1 EOICWwriteClearClear end of inserted group conversion flag0 EOC End of group conversion flag 1 1 EOCRreadNotCompleteConversion is not complete0CompleteConversion complete1 EOCWwriteClearClear end of group conversion flag0 WDE Analog watchdog event flag 0 1 WDERreadNoEventNo analog watchdog event occurred0EventAnalog watchdog event occurred1 WDEWwriteClearClear the analog watchdog event flag0 CTL0 CTL0 control register 0 0x4 0x20 read-write 0x00000000 RWDEN Regular channel analog watchdog enable 23 1 RWDENread-writeDisabledAnalog watchdog disabled on regular channels0EnabledAnalog watchdog enabled on regular channels1 IWDEN Inserted channel analog watchdog enable 22 1 IWDENread-writeDisabledAnalog watchdog disabled on inserted channels0EnabledAnalog watchdog enabled on inserted channels1 SYNCM sync mode selection 16 3 DISNUM Number of conversions in discontinuous mode 13 3 07 DISIC Discontinuous mode on inserted channels 12 1 DISICread-writeDisabledDiscontinuous mode on inserted channels disabled0EnabledDiscontinuous mode on inserted channels enabled1 DISRC Discontinuous mode on regular channels 11 1 DISRCread-writeDisabledDiscontinuous mode on regular channels disabled0EnabledDiscontinuous mode on regular channels enabled1 ICA Inserted channel group convert automatically 10 1 ICAread-writeDisabledAutomatic inserted group conversion disabled0EnabledAutomatic inserted group conversion enabled1 WDSC When in scan mode, analog watchdog is effective on a single channel 9 1 WDSCread-writeAllAnalog watchdog enabled on all channels0SingleAnalog watchdog enabled on a single channel1 SM Scan mode 8 1 SMread-writeDisabledScan mode disabled0EnabledScan mode enabled1 EOICIE Interrupt enable for EOIC 7 1 EOICIEread-writeDisabledEOIC interrupt disabled0EnabledEOIC interrupt enabled. An interrupt is generated when the EOIC bit is set1 WDEIE Interrupt enable for WDE 6 1 WDEIEread-writeDisabledWDE interrupt disabled0EnabledWDE interrupt enabled. An interrupt is generated when the WDE bit is set1 EOCIE Interrupt enable for EOC 5 1 EOCIEread-writeDisabledEOC interrupt disabled0EnabledEOC interrupt enabled. An interrupt is generated when the EOC bit is set1 WDCHSEL Analog watchdog channel select 0 5 018 CTL1 CTL1 control register 1 0x08 0x20 read-write 0x00000000 TSVREN Channel 16 and 17 enable of ADC0 23 1 TSVRENread-writeDisabledChannel 16 and 17 disabled0EnabledChannel 16 and 17 enabled1 SWRCST Start on regular channel 22 1 SWRCSTRreadStartedReset state0NotStartedStarting conversion of regular channels1 SWRCSTWwriteStartStart conversion of regular channels1 SWICST Start on inserted channel 21 1 SWICSTRreadStartedReset state0NotStartedStarting conversion of inserted channels1 SWICSTWwriteStartStart conversion of inserted channels1 ETERC External trigger enable for regular channel 20 1 ETERCread-writeDisabledConversion on external event disabled0EnabledConversion on external event enabled1 ETSRC External trigger select for regular channel 17 3 ETSRCread-writeTimer0Ch0Timer 0 channel 0 event0Timer0Ch1Timer 0 channel 1 event1Timer0Ch2Timer 0 channel 2 event2Timer1Ch1Timer 1 channel 1 event3Timer2TrgoTimer 2 TRGO event4Timer14Ch0Timer 14 channel 0 event5Exti11EXTI line 116SwrcstSWRCST7 ETSIC External trigger select for inserted channel 12 3 ETSICread-writeTimer0TrgoTimer 0 TRGO event0Timer0Ch3Timer 0 channel 3 event1Timer1TrgoTimer 1 TRGO event2Timer1Ch0Timer 1 channel 0 event3Timer2Ch2Timer 2 channel 3 event4Timer14TrgoTimer 14 TRGO event5Exti15EXTI line 156SwicstSWICST7 DAL Data alignment 11 1 DALread-writeRightRight alignment0LeftLeft alignment1 DMA DMA request enable 8 1 DMAread-writeDisabledDMA mode disabled0EnabledDMA mode enabled1 RSTCLB Reset calibration 3 1 RSTCLBRreadCompleteCalibration completed0NotCompleteCalibrating1 RSTCLBWwriteStartEnable calibration1 CLB ADC calibration 2 1 CLBRreadCompleteCalibration completed0NotCompleteCalibrating1 CLBWwriteStartEnable calibration1 CTN Continuous mode 1 1 CTNread-writeSingleSingle conversion mode0ContinuousContinuous conversion mode1 ADCON ADC on 0 1 ADCONread-writeDisabledDisable ADC conversion/calibration and go to power down mode0EnabledEnable ADC and to start conversion1 SAMPT0 SAMPT0 Sample time register 0 0x0C 0x20 read-write 0x00000000 SPT10 Channel 10 sample time selection 0 3 SPT10read-writeCycles1_51.5 ADC clock cycles0Cycles7_57.5 ADC clock cycles1Cycles13_513.5 ADC clock cycles2Cycles28_528.5 ADC clock cycles3Cycles41_541.5 ADC clock cycles4Cycles55_555.5 ADC clock cycles5Cycles71_571.5 ADC clock cycles6Cycles239_5239.5 ADC clock cycles7 SPT11 Channel 11 sample time selection 3 3 SPT12 Channel 12 sample time selection 6 3 SPT13 Channel 13 sample time selection 9 3 SPT14 Channel 14 sample time selection 12 3 SPT15 Channel 15 sample time selection 15 3 SPT16 Channel 16 sample time selection 18 3 SPT17 Channel 17 sample time selection 21 3 SAMPT1 SAMPT1 Sample time register 1 0x10 0x20 read-write 0x00000000 SPT0 Channel 0 sample time selection 0 3 SPT0read-writeCycles1_51.5 ADC clock cycles0Cycles7_57.5 ADC clock cycles1Cycles13_513.5 ADC clock cycles2Cycles28_528.5 ADC clock cycles3Cycles41_541.5 ADC clock cycles4Cycles55_555.5 ADC clock cycles5Cycles71_571.5 ADC clock cycles6Cycles239_5239.5 ADC clock cycles7 SPT1 Channel 1 sample time selection 3 3 SPT2 Channel 2 sample time selection 6 3 SPT3 Channel 3 sample time selection 9 3 SPT4 Channel 4 sample time selection 12 3 SPT5 Channel 5 sample time selection 15 3 SPT6 Channel 6 sample time selection 18 3 SPT7 Channel 7 sample time selection 21 3 SPT8 Channel 8 sample time selection 24 3 SPT9 Channel 9 sample time selection 27 3 IOFF0 IOFF0 Inserted channel data offset register 0 0x14 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 0 0 12 04095 IOFF1 IOFF1 Inserted channel data offset register 1 0x18 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 1 0 12 04095 IOFF2 IOFF2 Inserted channel data offset register 2 0x1C 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 2 0 12 04095 IOFF3 IOFF3 Inserted channel data offset register 3 0x20 0x20 read-write 0x00000000 IOFF Data offset for inserted channel 3 0 12 04095 WDHT WDHT watchdog higher threshold register 0x24 0x20 read-write 0x00000FFF WDHT Analog watchdog higher threshold 0 12 04095 WDLT WDLT watchdog lower threshold register 0x28 0x20 read-write 0x00000000 WDLT Analog watchdog lower threshold 0 12 04095 RSQ0 RSQ0 regular sequence register 0 0x2C 0x20 read-write 0x00000000 RL Regular channel group length 20 4 015 RSQ15 16th conversion in regular sequence 15 5 018 RSQ14 15th conversion in regular sequence 10 5 018 RSQ13 14th conversion in regular sequence 5 5 018 RSQ12 13th conversion in regular sequence 0 5 018 RSQ1 RSQ1 regular sequence register 1 0x30 0x20 read-write 0x00000000 RSQ11 12th conversion in regular sequence 25 5 018 RSQ10 11th conversion in regular sequence 20 5 018 RSQ9 10th conversion in regular sequence 15 5 018 RSQ8 9th conversion in regular sequence 10 5 018 RSQ7 8th conversion in regular sequence 5 5 018 RSQ6 7th conversion in regular sequence 0 5 018 RSQ2 RSQ2 regular sequence register 2 0x34 0x20 read-write 0x00000000 RSQ5 6th conversion in regular sequence 25 5 018 RSQ4 5th conversion in regular sequence 20 5 018 RSQ3 4th conversion in regular sequence 15 5 018 RSQ2 3rd conversion in regular sequence 10 5 018 RSQ1 2nd conversion in regular sequence 5 5 018 RSQ0 1st conversion in regular sequence 0 5 018 ISQ ISQ Inserted sequence register 0x38 0x20 read-write 0x00000000 IL Inserted channel group length 20 2 03 ISQ3 4th conversion in inserted sequence 15 5 018 ISQ2 3rd conversion in inserted sequence 10 5 018 ISQ1 2nd conversion in inserted sequence 5 5 018 ISQ0 1st conversion in inserted sequence 0 5 018 IDATA0 IDATA0 Inserted data register 0 0x3C 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 065535 IDATA1 IDATA1 Inserted data register 1 0x40 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 065535 IDATA2 IDATA2 Inserted data register 2 0x44 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 065535 IDATA3 IDATA3 Inserted data register 3 0x48 0x20 read-only 0x00000000 IDATAn Inserted number n conversion data 0 16 065535 RDATA RDATA regular data register 0x4C 0x20 read-only 0x00000000 RDATA Regular channel data 0 16 065535 OVSAMPCTL OVSAMPCTL Oversample control register 0x80 0x20 read-write 0x00000000 DRES ADC resolution 12 2 DRESread-writeBits1212 bit resolution0Bits1010 bit resolution1Bits88 bit resolution2Bits66 bit resolution3 TOVS Triggered Oversampling 9 1 TOVSread-writeConsecutiveAll oversampled conversions are done consecutively0IndividualEach oversampled conversion needs a trigger1 OVSS Oversampling shift 5 4 08 OVSR Oversampling ratio 2 3 OVSRread-writeTimes22x0Times44x1Times88x2Times1616x3Times3232x4Times6464x5Times128128x6Times256256x7 OVSEN Oversampling Enable 0 1 OVSENread-writeDisabledOversampling disabled0EnabledOversampling enabled1 ADC2 0x40013C00 ADC2 47 AFIO Alternate-function I/Os AFIO 0x40010000 0x0 0x400 registers EC EC Event control register 0x0 0x20 read-write 0x00000000 EOE Event output enable 7 1 PORT Event output port selection 4 3 PIN Event output pin selection 0 4 PCF0 PCF0 AFIO port configuration register 0 0x4 0x20 read-write 0x00000000 PTP_PPS_REMAP Ethernet PTP PPS remapping 30 1 TIMER1ITR0_REMAP TIMER1 internal trigger 0 remapping 29 1 SPI2_REMAP SPI2/I2S2 remapping 28 1 SWJ_CFG Serial wire JTAG configuration 24 3 ENET_PHY_SEL Ethernet MII or RMII PHY selection 23 1 CAN1_REMAP CAN1 I/O remapping 22 1 ENET_REMAP Ethernet MAC I/O remapping 21 1 TIMER4CH3_IREMAP TIMER4 channel3 internal remapping 16 1 PD01_REMAP Port D0/Port D1 mapping on OSC_IN/OSC_OUT 15 1 CAN0_REMAP CAN0 alternate interface remapping 13 2 TIMER3_REMAP TIMER3 remapping 12 1 TIMER2_REMAP TIMER2 remapping 10 2 TIMER1_REMAP TIMER1 remapping 8 2 TIMER0_REMAP TIMER0 remapping 6 2 USART2_REMAP USART2 remapping 4 2 USART1_REMAP USART1 remapping 3 1 USART0_REMAP USART0 remapping 2 1 I2C0_REMAP I2C0 remapping 1 1 SPI0_REMAP SPI0 remapping 0 1 EXTISS0 EXTISS0 EXTI sources selection register 0 0x08 0x20 read-write 0x00000000 EXTI3_SS EXTI 3 sources selection 12 4 EXTI2_SS EXTI 2 sources selection 8 4 EXTI1_SS EXTI 1 sources selection 4 4 EXTI0_SS EXTI 0 sources selection 0 4 EXTISS1 EXTISS1 EXTI sources selection register 1 0x0C 0x20 read-write 0x00000000 EXTI7_SS EXTI 7 sources selection 12 4 EXTI6_SS EXTI 6 sources selection 8 4 EXTI5_SS EXTI 5 sources selection 4 4 EXTI4_SS EXTI 4 sources selection 0 4 EXTISS2 EXTISS2 EXTI sources selection register 2 0x10 0x20 read-write 0x00000000 EXTI11_SS EXTI 11 sources selection 12 4 EXTI10_SS EXTI 10 sources selection 8 4 EXTI9_SS EXTI 9 sources selection 4 4 EXTI8_SS EXTI 8 sources selection 0 4 EXTISS3 EXTISS3 EXTI sources selection register 3 0x14 0x20 read-write 0x00000000 EXTI15_SS EXTI 15 sources selection 12 4 EXTI14_SS EXTI 14 sources selection 8 4 EXTI13_SS EXTI 13 sources selection 4 4 EXTI12_SS EXTI 12 sources selection 0 4 PCF1 PCF1 AFIO port configuration register 1 0x1C 0x20 read-write 0x00000000 CTC_REMAP CTC remapping 11 2 FSMC_NADV FSMC_NADV connect/disconnect 10 1 TIMER13_REMAP TIMER13 remapping 9 1 TIMER12_REMAP TIMER12 remapping 8 1 TIMER10_REMAP TIMER10 remapping 7 1 TIMER9_REMAP TIMER9 remapping 6 1 TIMER8_REMAP TIMER8 remapping 5 1 CPSCTL CPSCTL IO compensation control register 0x20 0x20 read-write 0x00000000 CPS_RDY I/O compensation cell is really or not 8 1 CPS_EN I/O compensation cell enable 0 1 BKP Backup registers BKP 0x40006C00 0x0 0x400 registers Tamper 2 DATA0 DATA0 Backup data register 0 0x4 0x20 read-write 0x0000 DATA Backup data 0 16 DATA1 DATA1 Backup data register 1 0x8 0x20 read-write 0x0000 DATA Backup data 0 16 DATA2 DATA2 Backup data register 2 0xC 0x20 read-write 0x0000 DATA Backup data 0 16 DATA3 DATA3 Backup data register 3 0x10 0x20 read-write 0x0000 DATA Backup data 0 16 DATA4 DATA4 Backup data register 4 0x14 0x20 read-write 0x0000 DATA Backup data 0 16 DATA5 DATA5 Backup data register 5 0x18 0x20 read-write 0x0000 DATA Backup data 0 16 DATA6 DATA6 Backup data register 6 0x1C 0x20 read-write 0x0000 DATA Backup data 0 16 DATA7 DATA7 Backup data register 7 0x20 0x20 read-write 0x0000 DATA Backup data 0 16 DATA8 DATA8 Backup data register 8 0x24 0x20 read-write 0x0000 DATA Backup data 0 16 DATA9 DATA9 Backup data register 9 0x28 0x20 read-write 0x0000 DATA Backup data 0 16 DATA10 DATA10 Backup data register 10 0x40 0x20 read-write 0x0000 DATA Backup data 0 16 DATA11 DATA11 Backup data register 11 0x44 0x20 read-write 0x0000 DATA Backup data 0 16 DATA12 DATA12 Backup data register 12 0x48 0x20 read-write 0x0000 DATA Backup data 0 16 DATA13 DATA13 Backup data register 13 0x4C 0x20 read-write 0x0000 DATA Backup data 0 16 DATA14 DATA14 Backup data register 14 0x50 0x20 read-write 0x0000 DATA Backup data 0 16 DATA15 DATA15 Backup data register 15 0x54 0x20 read-write 0x0000 DATA Backup data 0 16 DATA16 DATA16 Backup data register 16 0x58 0x20 read-write 0x0000 DATA Backup data 0 16 DATA17 DATA17 Backup data register 17 0x5C 0x20 read-write 0x0000 DATA Backup data 0 16 DATA18 DATA18 Backup data register 18 0x60 0x20 read-write 0x0000 DATA Backup data 0 16 DATA19 DATA19 Backup data register 19 0x64 0x20 read-write 0x0000 DATA Backup data 0 16 DATA20 DATA20 Backup data register 20 0x68 0x20 read-write 0x0000 DATA Backup data 0 16 DATA21 DATA21 Backup data register 21 0x6C 0x20 read-write 0x0000 DATA Backup data 0 16 DATA22 DATA22 Backup data register 22 0x70 0x20 read-write 0x0000 DATA Backup data 0 16 DATA23 DATA23 Backup data register 23 0x74 0x20 read-write 0x0000 DATA Backup data 0 16 DATA24 DATA24 Backup data register 24 0x78 0x20 read-write 0x0000 DATA Backup data 0 16 DATA25 DATA25 Backup data register 25 0x7C 0x20 read-write 0x0000 DATA Backup data 0 16 DATA26 DATA26 Backup data register 26 0x80 0x20 read-write 0x0000 DATA Backup data 0 16 DATA27 DATA27 Backup data register 27 0x84 0x20 read-write 0x0000 DATA Backup data 0 16 DATA28 DATA28 Backup data register 28 0x88 0x20 read-write 0x0000 DATA Backup data 0 16 DATA29 DATA29 Backup data register 29 0x8C 0x20 read-write 0x0000 DATA Backup data 0 16 DATA30 DATA30 Backup data register 30 0x90 0x20 read-write 0x0000 DATA Backup data 0 16 DATA31 DATA31 Backup data register 31 0x94 0x20 read-write 0x0000 DATA Backup data 0 16 DATA32 DATA32 Backup data register 32 0x98 0x20 read-write 0x0000 DATA Backup data 0 16 DATA33 DATA33 Backup data register 33 0x9C 0x20 read-write 0x0000 DATA Backup data 0 16 DATA34 DATA34 Backup data register 34 0xA0 0x20 read-write 0x0000 DATA Backup data 0 16 DATA35 DATA35 Backup data register 35 0xA4 0x20 read-write 0x0000 DATA Backup data 0 16 DATA36 DATA36 Backup data register 36 0xA8 0x20 read-write 0x0000 DATA Backup data 0 16 DATA37 DATA37 Backup data register 37 0xAC 0x20 read-write 0x0000 DATA Backup data 0 16 DATA38 DATA38 Backup data register 38 0xB0 0x20 read-write 0x0000 DATA Backup data 0 16 DATA39 DATA39 Backup data register 39 0xB4 0x20 read-write 0x0000 DATA Backup data 0 16 DATA40 DATA40 Backup data register 40 0xB8 0x20 read-write 0x0000 DATA Backup data 0 16 DATA41 DATA41 Backup data register 41 0xBC 0x20 read-write 0x0000 DATA Backup data 0 16 OCTL OCTL RTC signal output control register 0x2C 0x20 read-write 0x0000 CALDIR RTC clock calibration direction 15 1 CCOSEL RTC clock output selection 14 1 ROSEL RTC output selection 9 1 ASOEN RTC alarm or second signal output enable 8 1 COEN RTC clock calibration output enable 7 1 RCCV RTC clock calibration value 0 7 TPCTL TPCTL Tamper pin control register 0x30 0x20 read-write 0x0000 TPAL TAMPER pin active level 1 1 TPEN TAMPER detection enable 0 1 TPCS TPCS Tamper control and status register 0x34 0x20 read-write 0x0000 TIF Tamper interrupt flag 9 1 TEF Tamper event flag 8 1 TPIE Tamper interrupt enable 2 1 TIR Tamper interrupt reset 1 1 TER Tamper event reset 0 1 CAN0 Controller area network CAN 0x40006400 0x0 0x400 registers CAN0_TX 19 CAN0_RX0 20 CAN0_RX1 21 CAN0_EWMC 22 CTL CTL Control register 0x0 0x20 read-write 0x00010002 DFZ Debug freeze 16 1 DFZread-writeContinueContinue running CAN during debug0StopStop CAN reception and transmission during debug hold1 SWRST Software reset 15 1 SWRSTRreadNotResettingFinished resetting0ResettingReset in progress1 SWRSTWwriteResetReset CAN1 TTC Time-triggered communication 7 1 TTCread-writeDisabledDisable time-triggered communication0EnabledEnable time-triggered communication1 ABOR Automatic bus-off recovery 6 1 ABORread-writeManualBus off state is set by software0AutomaticBus off state is set automatically by hardware1 AWU Automatic wakeup 5 1 AWUread-writeManualSleep state is set by software0AutomaticSleep state is set automatically by hardware1 ARD Automatic retransmission disable 4 1 ARDread-writeEnabledEnable automatic retransmission0DisabledDisable automatic retransmission1 RFOD Receive FIFO overwrite disable 3 1 RFODread-writeOverwriteOverwrite full receive FIFO with incoming frame0DiscardDiscard incoming frame when receive FIFO is full1 TFO Transmit FIFO order 2 1 TFOread-writeIdentifierOrder by identifier of the frame0FIFOFirst in first out order1 SLPWMOD Sleep working mode 1 1 SLPWMODread-writeActiveDisable sleep mode, bus activity detected0SleepEnable sleep mode1 IWMOD Initial working mode 0 1 IWMODread-writeDisabledDisable initial working mode0EnabledEnable initial working mode1 STAT STAT Status register 0x04 0x20 0x00000C02 RXL RX level 11 1 read-only LASTRX Last sample value of RX pin 10 1 read-only RS Receiving state 9 1 read-only RSread-writeNotWorkingCAN is not working in receiving state0WorkingCAN is working in receiving state1 TS Transmitting state 8 1 read-only TSread-writeNotWorkingCAN is not working in transmitting state0WorkingCAN is working in transmitting state1 SLPIF Status change interrupt flag of sleep working mode entering 4 1 read-write SLPIFRreadAwakeCAN is not entering sleep working mode0SleepingCAN is entering sleep working mode1 SLPIFWwriteClearClears flag1 WUIF Status change interrupt flag of wakeup from sleep working mode 3 1 read-write WUIFRreadNoWakeupNo wakeup event0WakeupWakeup event1 WUIFWwriteClearClears flag1 ERRIF Error interrupt flag 2 1 read-write ERRIFRreadNoErrorThere was no error0ErrorAn error was detected1 ERRIFWwriteClearClears flag1 SLPWS Sleep working state 1 1 read-only SLPWSread-writeNormalCAN is not in sleep working mode0SleepingCAN is in sleep working mode1 IWS Initial working state 0 1 read-only IWSread-writeNormalCAN is not in initial working mode0InitialCAN is in initial working mode1 TSTAT TSTAT Transmit status register 0x8 0x20 0x1C000000 TMLS2 Transmit mailbox 2 last sending in transmit FIFO 31 1 read-only TMLS1 Transmit mailbox 1 last sending in transmit FIFO 30 1 read-only TMLS0 Transmit mailbox 0 last sending in transmit FIFO 29 1 read-only TMLS0read-writeNotLastThe mailbox doesn't have the last sending order0LastThe mailbox has the last sending order with at least two frames pending1 TME2 Transmit mailbox 2 empty 28 1 read-only TME1 Transmit mailbox 1 empty 27 1 read-only TME0 Transmit mailbox 0 empty 26 1 read-only TME0read-writeNotEmptyTransmit mailbox not empty0EmptyTransmit mailbox is empty1 NUM number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty 24 2 read-only 02 MST2 Mailbox 2 stop transmitting 23 1 read-write MTE2 Mailbox 2 transmit error 19 1 read-write MAL2 Mailbox 2 arbitration lost 18 1 read-write MTFNERR2 Mailbox 2 transmit finished and no error 17 1 read-write MTF2 Mailbox 2 transmit finished 16 1 read-write MST1 Mailbox 1 stop transmitting 15 1 read-write MTE1 Mailbox 1 transmit error 11 1 read-write MAL1 Mailbox 1 arbitration lost 10 1 read-write MTFNERR1 Mailbox 1 transmit finished and no error 9 1 read-write MTF1 Mailbox 1 transmit finished 8 1 read-write MST0 Mailbox 0 stop transmitting 7 1 read-write MST0RreadNotStopMailbox is not stopped, or is empty0StopStop mailbox transmitting1 MST0WwriteStopStop mailbox transmitting1 MTE0 Mailbox 0 transmit error 3 1 read-write MTE0RreadNoErrorThere was no error0ErrorAn error was detected1 MTE0WwriteClearClears error flag1 MAL0 Mailbox 0 arbitration lost 2 1 read-write MAL0RreadNoArbitrationLostArbitration was not lost0ArbitrationLostArbitration lost1 MAL0WwriteClearClears flag1 MTFNERR0 Mailbox 0 transmit finished and no error 1 1 read-write MTFNERR0RreadFinishedWithErrorMailbox transmission finished with an error0FinishedNoErrorMailbox transmission finished with no error1 MTFNERR0WwriteClearClears flag1 MTF0 Mailbox 0 transmit finished 0 1 read-write MTF0RreadInProgressMailbox transmission still in progress0FinishedMailbox transmission finished1 MTF0WwriteClearClears flag1 RFIFO0 RFIFO0 Receive message FIFO0 register 0x0C 0x20 0x00000000 RFD0 Receive FIFO0 dequeue 5 1 read-write RFD0RreadFinishedDequeuing done0InProgressDequeuing in progress1 RFD0WwriteStartStart dequeuing1 RFO0 Receive FIFO0 overfull 4 1 read-write RFO0RreadNotOverfullReceive FIFO is not overfull0OverfullReceive FIFO is overfull1 RFO0WwriteClearClears flag1 RFF0 Receive FIFO0 full 3 1 read-write RFF0RreadNotFullReceive FIFO is not full0FullReceive FIFO is full1 RFF0WwriteClearClears flag1 RFL0 Receive FIFO0 length 0 2 read-only 03 RFIFO1 RFIFO1 Receive message FIFO1 register 0x10 0x20 0x00000000 RFD1 Receive FIFO1 dequeue 5 1 read-write RFD1RreadFinishedDequeuing done0InProgressDequeuing in progress1 RFD1WwriteStartStart dequeuing1 RFO1 Receive FIFO1 overfull 4 1 read-write RFO1RreadNotOverfullReceive FIFO is not overfull0OverfullReceive FIFO is overfull1 RFO1WwriteClearClears flag1 RFF1 Receive FIFO1 full 3 1 read-write RFF1RreadNotFullReceive FIFO is not full0FullReceive FIFO is full1 RFF1WwriteClearClears flag1 RFL1 Receive FIFO1 length 0 2 read-only 03 INTEN INTEN Interrupt enable register 0x14 0x20 read-write 0x00000000 SLPWIE Sleep working interrupt enable 17 1 SLPWIEread-writeDisabledSleep working interrupt is disabled0EnabledSleep working interrupt is enabled1 WIE Wakeup interrupt enable 16 1 WIEread-writeDisabledWakeup interrupt is disabled0EnabledWakeup interrupt is enabled1 ERRIE Error interrupt enable 15 1 ERRIEread-writeDisabledError interrupt is disabled0EnabledError interrupt is enabled1 ERRNIE Error number interrupt enable 11 1 ERRNIEread-writeDisabledError number interrupt is disabled0EnabledError number interrupt is enabled1 BOIE Bus-off interrupt enable 10 1 BOIEread-writeDisabledBus-off interrupt is disabled0EnabledBus-off interrupt is enabled1 PERRIE Passive error interrupt enable 9 1 PERRIEread-writeDisabledPassive error interrupt is disabled0EnabledPassive error interrupt is enabled1 WERRIE Warning error interrupt enable 8 1 WERRIEread-writeDisabledWarning error interrupt is disabled0EnabledWarning error interrupt is enabled1 RFOIE1 Receive FIFO1 overfull interrupt enable 6 1 RFFIE1 Receive FIFO1 full interrupt enable 5 1 RFNEIE1 Receive FIFO1 not empty interrupt enable 4 1 RFOIE0 Receive FIFO0 overfull interrupt enable 3 1 RFOIE0read-writeDisabledReceive FIFO overfull interrupt is disabled0EnabledReceive FIFO overfull interrupt is enabled1 RFFIE0 Receive FIFO0 full interrupt enable 2 1 RFFIE0read-writeDisabledReceive FIFO full interrupt is disabled0EnabledReceive FIFO full interrupt is enabled1 RFNEIE0 Receive FIFO0 not empty interrupt enable 1 1 RFNEIE0read-writeDisabledReceive FIFO not empty interrupt is disabled0EnabledReceive FIFO not empty interrupt is enabled1 TMEIE Transmit mailbox empty interrupt enable 0 1 TMEIEread-writeDisabledTransmit mailbox empty interrupt is disabled0EnabledTransmit mailbox empty interrupt is enabled1 ERR ERR Error register 0x18 0x20 0x00000000 RECNT Receive Error Count defined by the CAN standard 24 8 read-only 0255 TECNT Transmit Error Count defined by the CAN standard 16 8 read-only 0255 ERRN Error number 4 3 read-write ERRNread-writeNoErrorNo Error0StuffStuff Error1FormForm Error2AckAcknowledgment Error3BitRecessiveBit recessive Error4BitDominantBit dominant Error5CrcCRC Error6CustomSet by software7 BOERR Bus-off error 2 1 read-only BOERRread-writeNoErrorNo bus-off error0ErrorBus-off error1 PERR Passive error 1 1 read-only PERRread-writeNoErrorNo passive error0ErrorPassive error1 WERR Warning error 0 1 read-only WERRread-writeNoErrorNo warning error0ErrorWarning error1 BT BT Bit timing register 0x1C 0x20 read-write 0x01230000 SCMOD Silent communication mode 31 1 SCMODread-writeNormalNormal operation0SilentSilent Mode1 LCMOD Loopback communication mode 30 1 LCMODread-writeDisabledLoop Back Mode disabled0EnabledLoop Back Mode enabled1 SJW Resynchronization jump width 24 2 03 BS2 Bit segment 2 20 3 03 BS1 Bit segment 1 16 4 03 BAUDPSC Baud rate prescaler 0 10 01023 TMI0 TMI0 Transmit mailbox identifier register 0 0x180 0x20 read-write 0x00000000 SFID_EFID The frame identifier 21 11 EFID The frame identifier 3 18 FF Frame format 2 1 FFread-writeStandardStandard format frame0ExtendedExtended format frame1 FT Frame type 1 1 FTread-writeDataData frame0RemoteRemote frame1 TEN Transmit enable 0 1 TENread-writeDisabledTransmit disabled0EnabledTransmit enabled1 TMP0 TMP0 Transmit mailbox property register 0 0x184 0x20 read-write 0x00000000 TS Time stamp 16 16 065535 TSEN Time stamp enable 8 1 TSENread-writeDisabledTimestamp disabled0EnabledTimestamp enabled1 DLENC Data length code 0 4 015 TMDATA00 TMDATA00 Transmit mailbox data0 register 0x188 0x20 read-write 0x00000000 DB3 Data byte 3 24 8 0255 DB2 Data byte 2 16 8 0255 DB1 Data byte 1 8 8 0255 DB0 Data byte 0 0 8 0255 TMDATA10 TMDATA10 Transmit mailbox data1 register 0x18C 0x20 read-write 0x00000000 DB7 Data byte 7 24 8 0255 DB6 Data byte 6 16 8 0255 DB5 Data byte 5 8 8 0255 DB4 Data byte 4 0 8 0255 TMI1 TMI1 Transmit mailbox identifier register 1 0x190 0x20 read-write 0x00000000 SFID_EFID The frame identifier 21 11 EFID The frame identifier 3 18 FF Frame format 2 1 FFread-writeStandardStandard format frame0ExtendedExtended format frame1 FT Frame type 1 1 FTread-writeDataData frame0RemoteRemote frame1 TEN Transmit enable 0 1 TENread-writeDisabledTransmit disabled0EnabledTransmit enabled1 TMP1 TMP1 Transmit mailbox property register 1 0x194 0x20 read-write 0x00000000 TS Time stamp 16 16 065535 TSEN Time stamp enable 8 1 TSENread-writeDisabledTimestamp disabled0EnabledTimestamp enabled1 DLENC Data length code 0 4 015 TMDATA01 TMDATA01 Transmit mailbox data0 register 0x198 0x20 read-write 0x00000000 DB3 Data byte 3 24 8 0255 DB2 Data byte 2 16 8 0255 DB1 Data byte 1 8 8 0255 DB0 Data byte 0 0 8 0255 TMDATA11 TMDATA11 Transmit mailbox data1 register 0x19C 0x20 read-write 0x00000000 DB7 Data byte 7 24 8 0255 DB6 Data byte 6 16 8 0255 DB5 Data byte 5 8 8 0255 DB4 Data byte 4 0 8 0255 TMI2 TMI2 Transmit mailbox identifier register 2 0x1A0 0x20 read-write 0x00000000 SFID_EFID The frame identifier 21 11 EFID The frame identifier 3 18 FF Frame format 2 1 FFread-writeStandardStandard format frame0ExtendedExtended format frame1 FT Frame type 1 1 FTread-writeDataData frame0RemoteRemote frame1 TEN Transmit enable 0 1 TENread-writeDisabledTransmit disabled0EnabledTransmit enabled1 TMP2 TMP2 Transmit mailbox property register 2 0x1A4 0x20 read-write 0x00000000 TS Time stamp 16 16 065535 TSEN Time stamp enable 8 1 TSENread-writeDisabledTimestamp disabled0EnabledTimestamp enabled1 DLENC Data length code 0 4 015 TMDATA02 TMDATA02 Transmit mailbox data0 register 0x1A8 0x20 read-write 0x00000000 DB3 Data byte 3 24 8 0255 DB2 Data byte 2 16 8 0255 DB1 Data byte 1 8 8 0255 DB0 Data byte 0 0 8 0255 TMDATA12 TMDATA12 Transmit mailbox data1 register 0x1AC 0x20 read-write 0x00000000 DB7 Data byte 7 24 8 0255 DB6 Data byte 6 16 8 0255 DB5 Data byte 5 8 8 0255 DB4 Data byte 4 0 8 0255 RFIFOMI0 RFIFOMI0 Receive FIFO mailbox identifier register 0x1B0 0x20 read-only 0x00000000 SFID_EFID The frame identifier 21 11 EFID The frame identifier 3 18 FF Frame format 2 1 FFread-writeStandardStandard format frame0ExtendedExtended format frame1 FT Frame type 1 1 FTread-writeDataData frame0RemoteRemote frame1 RFIFOMP0 RFIFOMP0 Receive FIFO0 mailbox property register 0x1B4 0x20 read-only 0x00000000 TS Time stamp 16 16 065535 FI Filtering index 8 8 0255 DLENC Data length code 0 4 015 RFIFOMDATA00 RFIFOMDATA00 Receive FIFO0 mailbox data0 register 0x1B8 0x20 read-only 0x00000000 DB3 Data byte 3 24 8 0255 DB2 Data byte 2 16 8 0255 DB1 Data byte 1 8 8 0255 DB0 Data byte 0 0 8 0255 RFIFOMDATA10 RFIFOMDATA10 Receive FIFO0 mailbox data1 register 0x1BC 0x20 read-only 0x00000000 DB7 Data byte 7 24 8 0255 DB6 Data byte 6 16 8 0255 DB5 Data byte 5 8 8 0255 DB4 Data byte 4 0 8 0255 RFIFOMI1 RFIFOMI1 Receive FIFO1 mailbox identifier register 0x1C0 0x20 read-only 0x00000000 SFID_EFID The frame identifier 21 11 EFID The frame identifier 3 18 FF Frame format 2 1 FFread-writeStandardStandard format frame0ExtendedExtended format frame1 FT Frame type 1 1 FTread-writeDataData frame0RemoteRemote frame1 RFIFOMP1 RFIFOMP1 Receive FIFO1 mailbox property register 0x1C4 0x20 read-only 0x00000000 TS Time stamp 16 16 065535 FI Filtering index 8 8 0255 DLENC Data length code 0 4 015 RFIFOMDATA01 RFIFOMDATA01 Receive FIFO1 mailbox data0 register 0x1C8 0x20 read-only 0x00000000 DB3 Data byte 3 24 8 0255 DB2 Data byte 2 16 8 0255 DB1 Data byte 1 8 8 0255 DB0 Data byte 0 0 8 0255 RFIFOMDATA11 RFIFOMDATA11 Receive FIFO1 mailbox data1 register 0x1CC 0x20 read-only 0x00000000 DB7 Data byte 7 24 8 0255 DB6 Data byte 6 16 8 0255 DB5 Data byte 5 8 8 0255 DB4 Data byte 4 0 8 0255 FCTL FCTL Filter control register 0x200 0x20 read-write 0x2A1C0E01 HBC1F Header bank of CAN1 filter 8 6 028 FLD Filter lock disable 0 1 FLDread-writeDisabledFilter lock disabled0EnabledFilter lock enabled1 FMCFG FMCFG Filter mode configuration register 0x204 0x20 read-write 0x00000000 FMOD27 Filter mode 27 1 FMOD26 Filter mode 26 1 FMOD25 Filter mode 25 1 FMOD24 Filter mode 24 1 FMOD23 Filter mode 23 1 FMOD22 Filter mode 22 1 FMOD21 Filter mode 21 1 FMOD20 Filter mode 20 1 FMOD19 Filter mode 19 1 FMOD18 Filter mode 18 1 FMOD17 Filter mode 17 1 FMOD16 Filter mode 16 1 FMOD15 Filter mode 15 1 FMOD14 Filter mode 14 1 FMOD13 Filter mode 13 1 FMOD12 Filter mode 12 1 FMOD11 Filter mode 11 1 FMOD10 Filter mode 10 1 FMOD9 Filter mode 9 1 FMOD8 Filter mode 8 1 FMOD7 Filter mode 7 1 FMOD6 Filter mode 6 1 FMOD5 Filter mode 5 1 FMOD4 Filter mode 4 1 FMOD3 Filter mode 3 1 FMOD2 Filter mode 2 1 FMOD1 Filter mode 1 1 FMOD0 Filter mode 0 1 FMOD0read-writeMaskMask mode0ListList mode1 FSCFG FSCFG Filter scale configuration register 0x20C 0x20 read-write 0x00000000 FS0 Filter scale configuration 0 1 FS0read-writeScale16Filter with 16-bit scale0Scale32Filter with 32-bit scale1 FS1 Filter scale configuration 1 1 FS2 Filter scale configuration 2 1 FS3 Filter scale configuration 3 1 FS4 Filter scale configuration 4 1 FS5 Filter scale configuration 5 1 FS6 Filter scale configuration 6 1 FS7 Filter scale configuration 7 1 FS8 Filter scale configuration 8 1 FS9 Filter scale configuration 9 1 FS10 Filter scale configuration 10 1 FS11 Filter scale configuration 11 1 FS12 Filter scale configuration 12 1 FS13 Filter scale configuration 13 1 FS14 Filter scale configuration 14 1 FS15 Filter scale configuration 15 1 FS16 Filter scale configuration 16 1 FS17 Filter scale configuration 17 1 FS18 Filter scale configuration 18 1 FS19 Filter scale configuration 19 1 FS20 Filter scale configuration 20 1 FS21 Filter scale configuration 21 1 FS22 Filter scale configuration 22 1 FS23 Filter scale configuration 23 1 FS24 Filter scale configuration 24 1 FS25 Filter scale configuration 25 1 FS26 Filter scale configuration 26 1 FS27 Filter scale configuration 27 1 FAFIFO FAFIFO Filter associated FIFO register 0x214 0x20 read-write 0x00000000 FAF0 Filter 0 associated with FIFO 0 1 FAF0read-writeFIFO0Filter associated with FIFO00FIFO1Filter associated with FIFO11 FAF1 Filter 1 associated with FIFO 1 1 FAF2 Filter 2 associated with FIFO 2 1 FAF3 Filter 3 associated with FIFO 3 1 FAF4 Filter 4 associated with FIFO 4 1 FAF5 Filter 5 associated with FIFO 5 1 FAF6 Filter 6 associated with FIFO 6 1 FAF7 Filter 7 associated with FIFO 7 1 FAF8 Filter 8 associated with FIFO 8 1 FAF9 Filter 9 associated with FIFO 9 1 FAF10 Filter 10 associated with FIFO 10 1 FAF11 Filter 11 associated with FIFO 11 1 FAF12 Filter 12 associated with FIFO 12 1 FAF13 Filter 13 associated with FIFO 13 1 FAF14 Filter 14 associated with FIFO 14 1 FAF15 Filter 15 associated with FIFO 15 1 FAF16 Filter 16 associated with FIFO 16 1 FAF17 Filter 17 associated with FIFO 17 1 FAF18 Filter 18 associated with FIFO 18 1 FAF19 Filter 19 associated with FIFO 19 1 FAF20 Filter 20 associated with FIFO 20 1 FAF21 Filter 21 associated with FIFO 21 1 FAF22 Filter 22 associated with FIFO 22 1 FAF23 Filter 23 associated with FIFO 23 1 FAF24 Filter 24 associated with FIFO 24 1 FAF25 Filter 25 associated with FIFO 25 1 FAF26 Filter 26 associated with FIFO 26 1 FAF27 Filter 27 associated with FIFO 27 1 FW FW Filter working register 0x21C 0x20 read-write 0x00000000 FW0 Filter working 0 1 FW0read-writeDisabledFilter working disabled0EnabledFilter working enabled1 FW1 Filter working 1 1 FW2 Filter working 2 1 FW3 Filter working 3 1 FW4 Filter working 4 1 FW5 Filter working 5 1 FW6 Filter working 6 1 FW7 Filter working 7 1 FW8 Filter working 8 1 FW9 Filter working 9 1 FW10 Filter working 10 1 FW11 Filter working 11 1 FW12 Filter working 12 1 FW13 Filter working 13 1 FW14 Filter working 14 1 FW15 Filter working 15 1 FW16 Filter working 16 1 FW17 Filter working 17 1 FW18 Filter working 18 1 FW19 Filter working 19 1 FW20 Filter working 20 1 FW21 Filter working 21 1 FW22 Filter working 22 1 FW23 Filter working 23 1 FW24 Filter working 24 1 FW25 Filter working 25 1 FW26 Filter working 26 1 FW27 Filter working 27 1 F0DATA0 F0DATA0 Filter 0 data 0 register 0x240 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F0DATA1 F0DATA1 Filter 0 data 1 register 0x244 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F1DATA0 F1DATA0 Filter 1 data 0 register 0x248 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F1DATA1 F1DATA1 Filter 1 data 1 register 0x24C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F2DATA0 F2DATA0 Filter 2 data 0 register 0x250 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F2DATA1 F2DATA1 Filter 2 data 1 register 0x254 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F3DATA0 F3DATA0 Filter 3 data 0 register 0x258 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F3DATA1 F3DATA1 Filter 3 data 1 register 0x25C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F4DATA0 F4DATA0 Filter 4 data 0 register 0x260 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F4DATA1 F4DATA1 Filter 4 data 1 register 0x264 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F5DATA0 F5DATA0 Filter 5 data 0 register 0x268 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F5DATA1 F5DATA1 Filter 5 data 1 register 0x26C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F6DATA0 F6DATA0 Filter 6 data 0 register 0x270 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F6DATA1 F6DATA1 Filter 6 data 1 register 0x274 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F7DATA0 F7DATA0 Filter 7 data 0 register 0x278 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F7DATA1 F7DATA1 Filter 7 data 1 register 0x27C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F8DATA0 F8DATA0 Filter 8 data 0 register 0x280 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F8DATA1 F8DATA1 Filter 8 data 1 register 0x284 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F9DATA0 F9DATA0 Filter 9 data 0 register 0x288 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F9DATA1 F9DATA1 Filter 9 data 1 register 0x28C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F10DATA0 F10DATA0 Filter 10 data 0 register 0x290 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F10DATA1 F10DATA1 Filter 10 data 1 register 0x294 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F11DATA0 F11DATA0 Filter 11 data 0 register 0x298 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F11DATA1 F11DATA1 Filter 11 data 1 register 0x29C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F12DATA0 F12DATA0 Filter 12 data 0 register 0x2A0 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F12DATA1 F12DATA1 Filter 12 data 1 register 0x2A4 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F13DATA0 F13DATA0 Filter 13 data 0 register 0x2A8 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F13DATA1 F13DATA1 Filter 13 data 1 register 0x2AC 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F14DATA0 F14DATA0 Filter 14 data 0 register 0x2B0 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F14DATA1 F14DATA1 Filter 14 data 1 register 0x2B4 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F15DATA0 F15DATA0 Filter 15 data 0 register 0x2B8 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F15DATA1 F15DATA1 Filter 15 data 1 register 0x2BC 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F16DATA0 F16DATA0 Filter 16 data 0 register 0x2C0 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F16DATA1 F16DATA1 Filter 16 data 1 register 0x2C4 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F17DATA0 F17DATA0 Filter 17 data 0 register 0x2C8 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F17DATA1 F17DATA1 Filter 17 data 1 register 0x2CC 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F18DATA0 F18DATA0 Filter 18 data 0 register 0x2D0 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F18DATA1 F18DATA1 Filter 18 data 1 register 0x2D4 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F19DATA0 F19DATA0 Filter 19 data 0 register 0x2D8 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F19DATA1 F19DATA1 Filter 19 data 1 register 0x2DC 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F20DATA0 F20DATA0 Filter 20 data 0 register 0x2E0 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F20DATA1 F20DATA1 Filter 20 data 1 register 0x2E4 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F21DATA0 F21DATA0 Filter 21 data 0 register 0x2E8 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F21DATA1 F21DATA1 Filter 21 data 1 register 0x2EC 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F22DATA0 F22DATA0 Filter 22 data 0 register 0x2F0 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F22DATA1 F22DATA1 Filter 22 data 1 register 0x2F4 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F23DATA0 F23DATA0 Filter 23 data 0 register 0x2F8 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F23DATA1 F23DATA1 Filter 23 data 1 register 0x2FC 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F24DATA0 F24DATA0 Filter 24 data 0 register 0x300 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F24DATA1 F24DATA1 Filter 24 data 1 register 0x304 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F25DATA0 F25DATA0 Filter 25 data 0 register 0x308 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F25DATA1 F25DATA1 Filter 25 data 1 register 0x30C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F26DATA0 F26DATA0 Filter 26 data 0 register 0x310 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F26DATA1 F26DATA1 Filter 26 data 1 register 0x314 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F27DATA0 F27DATA0 Filter 27 data 0 register 0x318 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 F27DATA1 F27DATA1 Filter 27 data 1 register 0x31C 0x20 read-write 0x00000000 FD0 Filter bits 0 1 FD1 Filter bits 1 1 FD2 Filter bits 2 1 FD3 Filter bits 3 1 FD4 Filter bits 4 1 FD5 Filter bits 5 1 FD6 Filter bits 6 1 FD7 Filter bits 7 1 FD8 Filter bits 8 1 FD9 Filter bits 9 1 FD10 Filter bits 10 1 FD11 Filter bits 11 1 FD12 Filter bits 12 1 FD13 Filter bits 13 1 FD14 Filter bits 14 1 FD15 Filter bits 15 1 FD16 Filter bits 16 1 FD17 Filter bits 17 1 FD18 Filter bits 18 1 FD19 Filter bits 19 1 FD20 Filter bits 20 1 FD21 Filter bits 21 1 FD22 Filter bits 22 1 FD23 Filter bits 23 1 FD24 Filter bits 24 1 FD25 Filter bits 25 1 FD26 Filter bits 26 1 FD27 Filter bits 27 1 FD28 Filter bits 28 1 FD29 Filter bits 29 1 FD30 Filter bits 30 1 FD31 Filter bits 31 1 CAN1 0x40006800 CAN1_TX 63 CAN1_RX0 64 CAN1_RX1 65 CAN1_EWMC 66 CRC cyclic redundancy check calculation unit CRC 0x40023000 0x0 0x400 registers DATA DATA Data register 0x0 0x20 read-write 0xFFFFFFFF DATA CRC calculation result bits 0 32 04294967295 FDATA FDATA Free data register 0x04 0x20 read-write 0x00000000 FDATA Free Data Register bits 0 8 0255 CTL CTL Control register 0x08 0x20 read-write 0x00000000 RST reset bit 0 1 RSTWwriteResetResets the DATA register to IDATA, with no effect on FDATA1 CTC Clock trim controller CTC 0x4000C800 0x0 0x400 registers RCU_CTC 5 CTL0 CTL0 Control register 0 0x0 0x20 read-write 0x00002000 CKOKIE Clock trim ok interrupt enable 0 1 CKWARNIE Clock trim warning interrupt enable 1 1 ERRIE Error interrupt enable 2 1 EREFIE EREFIF interrupt enable 3 1 CNTEN CTC counter enable 5 1 AUTOTRIM Hardware automatically trim mode 6 1 SWREFPUL Software reference source sync pulse 7 1 TRIMVALUE IRC48M trim value 8 6 CTL1 CTL1 Control register 1 0x04 0x20 read-write 0x2022BB7F REFPOL Reference signal source polarity 31 1 REFSEL Reference signal source selection 28 2 REFPSC Reference signal source prescaler 24 3 CKLIM Clock trim base limit value 16 8 RLVALUE CTC counter reload value 0 16 STAT STAT Status register 0x08 0x20 read-only 0x00000000 CKOKIF Clock trim OK interrupt flag 0 1 CKWARNIF Clock trim warning interrupt flag 1 1 ERRIF Error interrupt flag 2 1 EREFIF Expect reference interrupt flag 3 1 CKERR Clock trim error bit 8 1 REFMISS Reference sync pulse miss 9 1 TRIMERR Trim value error bit 10 1 REFDIR CTC trim counter direction when reference sync pulse 15 1 REFCAP CTC counter capture when reference sync pulse 16 16 INTC INTC Interrupt clear register 0x0c 0x20 write-only 0x00000000 CKOKIC CKOKIF interrupt clear bit 0 1 CKWARNIC CKWARNIF interrupt clear bit 1 1 ERRIC ERRIF interrupt clear bit 2 1 EREFIC EREFIF interrupt clear bit 3 1 DAC Digital-to-analog converter DAC 0x40007400 0x0 0x400 registers CTL CTL control register 0x0 0x20 read-write 0x00000000 DEN0 DAC0 enable 0 1 DEN0read-writeDisabledDAC channel disabled0EnabledDAC channel enabled1 DBOFF0 DAC0 output buffer turn off 1 1 DBOFF0read-writeEnabledDAC X output buffer enabled0DisabledDAC X output buffer disabled1 DTEN0 DAC0 trigger enable 2 1 DTEN0read-writeDisabledDAC trigger disabled0EnabledDAC trigger enabled1 DTSEL0 DAC0 trigger selection 3 3 DTSEL0read-writeTIMER5_TRGOTimer 5 TRGO event0TIMER2_TRGOTimer 2 TRGO event1TIMER14_TRGOTimer 14 TRGO event3TIMER1_TRGOTimer 1 TRGO event4EXTERNAL9External line96SOFTWARESoftware trigger7 DWM0 DAC0 noise wave mode 6 2 DWBW0 DAC0 noise wave bit width 8 4 DDMAEN0 DAC0 DMA enable 12 1 DDMAEN0read-writeDisabledDAC DMA mode disabled0EnabledDAC DMA mode enabled1 DEN1 DAC1 enable 16 1 DBOFF1 DAC1 output buffer turn off 17 1 DTEN1 DAC1 trigger enable 18 1 DTSEL1 DAC1 trigger selection 19 3 DWM1 DAC1 noise wave mode 22 2 DWBW1 DAC1 noise wave bit width 24 4 DDMAEN1 DAC1 DMA enable 28 1 SWT SWT software trigger register 0x04 0x20 write-only 0x00000000 SWTR0 DAC0 software trigger 0 1 SWTR0read-writeDisabledDAC channel X software trigger disabled0EnabledDAC channel X software trigger enabled1 SWTR1 DAC1 software trigger 1 1 DAC0_R12DH DAC0_R12DH DAC0 12-bit right-aligned data holding register 0x08 0x20 read-write 0x00000000 DAC0_DH DAC0 12-bit right-aligned data 0 12 04095 DAC0_L12DH DAC0_L12DH DAC0 12-bit left-aligned data holding register 0x0C 0x20 read-write 0x00000000 DAC0_DH DAC0 12-bit left-aligned data 4 12 04095 DAC0_R8DH DAC0_R8DH DAC0 8-bit right aligned data holding register 0x10 0x20 read-write 0x00000000 DAC0_DH DAC0 8-bit right-aligned data 0 8 0255 DAC1_R12DH DAC1_R12DH DAC1 12-bit right-aligned data holding register 0x14 0x20 read-write 0x00000000 DAC1_DH DAC1 12-bit right-aligned data 0 12 04095 DAC1_L12DH DAC1_L12DH DAC1 12-bit left aligned data holding register 0x18 0x20 read-write 0x00000000 DAC1_DH DAC1 12-bit left-aligned data 4 12 04095 DAC1_R8DH DAC1_R8DH DAC1 8-bit right aligned data holding register 0x1C 0x20 read-write 0x00000000 DAC1_DH DAC1 8-bit right-aligned data 0 8 0255 DACC_R12DH DACC_R12DH DAC concurrent mode 12-bit right-aligned data holding register 0x20 0x20 read-write 0x00000000 DAC0_DH DAC0 12-bit right-aligned data 0 12 04095 DAC1_DH DAC1 12-bit right-aligned data 16 12 04095 DACC_L12DH DACC_L12DH DAC concurrent mode 12-bit left aligned data holding register 0x24 0x20 read-write 0x00000000 DAC0_DH DAC0 12-bit left-aligned data 4 12 04095 DAC1_DH DAC1 12-bit left-aligned data 20 12 04095 DACC_R8DH DACC_R8DH DAC concurrent mode 8-bit right aligned data holding register 0x28 0x20 read-write 0x00000000 DAC0_DH DAC0 8-bit right-aligned data 0 8 0255 DAC1_DH DAC1 8-bit right-aligned data 8 8 0255 DAC0_DO DAC0_DO DAC0 data output register 0x2C 0x20 read-only 0x00000000 DAC0_DO DAC0 data output 0 12 04095 DAC1_DO DAC1_DO DAC1 data output register 0x30 0x20 read-only 0x00000000 DAC1_DO DAC1 data output 0 12 04095 DBG Debug support DBG 0xE0042000 0x0 0x400 registers ID ID ID code register 0x0 0x20 read-only 0x00000000 ID_CODE DBG ID code register 0 32 04294967295 CTL0 CTL0 Control register 0 0x4 0x20 read-write 0x00000000 SLP_HOLD Sleep mode hold register 0 1 SLP_HOLDread-writeDisabledNo effect0EnabledIn sleep mode the AHB clock is on1 DSLP_HOLD Deep-sleep mode hold register 1 1 DSLP_HOLDread-writeDisabledNo effect0EnabledIn deep-sleep mode the AHB clock and system clock are provided by IRC8M1 STB_HOLD Standby mode hold register 2 1 STB_HOLDread-writeDisabledNo effect0EnabledIn standby mode the AHB clock and system clock are provided by IRC8M1 TRACE_IOEN Trace pin allocation enable 5 1 TRACE_MODE Trace pin allocation mode 6 2 WWDGT_HOLD WWDGT hold bit 8 1 WWDGT_HOLDread-writeContinueContinue running the watchdog timer as usual0StopHold the watchdog timer for debug when the core is halted1 FWDGT_HOLD FWDGT hold bit 9 1 TIMER0_HOLD TIMER 0 hold bit 10 1 TIMER0_HOLDread-writeContinueContinue running the timer as usual0StopHold the timer counter for debug when the core is halted1 TIMER1_HOLD TIMER 1 hold bit 11 1 TIMER2_HOLD TIMER 2 hold bit 12 1 TIMER3_HOLD TIMER 23 hold bit 13 1 CAN0_HOLD CAN0 hold bit 14 1 CAN0_HOLDread-writeContinueContinue running CAN as usual0StopHold the CAN for debug when the core is halted1 I2C0_HOLD I2C0 hold bit 15 1 I2C0_HOLDread-writeContinueContinue running I2C as usual0StopHold the I2C timeout for debug when the core is halted1 I2C1_HOLD I2C1 hold bit 16 1 TIMER4_HOLD TIMER4_HOLD 17 1 TIMER5_HOLD TIMER 5 hold bit 18 1 TIMER6_HOLD TIMER 6 hold bit 19 1 TIMER7_HOLD TIMER 7 hold bit 20 1 CAN1_HOLD CAN1 hold bit 21 1 TIMER11_HOLD TIMER 11 hold bit 25 1 TIMER12_HOLD TIMER 12 hold bit 26 1 TIMER13_HOLD TIMER 13 hold bit 27 1 TIMER8_HOLD TIMER 8 hold bit 28 1 TIMER9_HOLD TIMER 9 hold bit 29 1 TIMER10_HOLD TIMER 10 hold bit 30 1 DMA0 DMA controller DMA 0x40020000 0x0 0x400 registers DMA0_Channel0 11 DMA0_Channel1 12 DMA0_Channel2 13 DMA0_Channel3 14 DMA0_Channel4 15 DMA0_Channel5 16 DMA0_Channel6 17 INTF INTF Interrupt flag register 0x0 0x20 read-only 0x00000000 GIF0 Global interrupt flag of channel 0 0 1 GIF0read-writeNoEventNo transfer error, half event, complete event0EventA transfer error, half event or complete event has occured1 FTFIF0 Full Transfer finish flag of channe 0 1 1 FTFIF0read-writeNotCompleteNo transfer complete event0CompleteA transfer complete event has occured1 HTFIF0 Half transfer finish flag of channel 0 2 1 HTFIF0read-writeNotHalfNo half transfer event0HalfA half transfer event has occured1 ERRIF0 Error flag of channel 0 3 1 ERRIF0read-writeNoErrorNo transfer error0ErrorA transfer error has occured1 GIF1 Global interrupt flag of channel 1 4 1 FTFIF1 Full Transfer finish flag of channe 1 5 1 HTFIF1 Half transfer finish flag of channel 1 6 1 ERRIF1 Error flag of channel 1 7 1 GIF2 Global interrupt flag of channel 2 8 1 FTFIF2 Full Transfer finish flag of channe 2 9 1 HTFIF2 Half transfer finish flag of channel 2 10 1 ERRIF2 Error flag of channel 2 11 1 GIF3 Global interrupt flag of channel 3 12 1 FTFIF3 Full Transfer finish flag of channe 3 13 1 HTFIF3 Half transfer finish flag of channel 3 14 1 ERRIF3 Error flag of channel 3 15 1 GIF4 Global interrupt flag of channel 4 16 1 FTFIF4 Full Transfer finish flag of channe 4 17 1 HTFIF4 Half transfer finish flag of channel 4 18 1 ERRIF4 Error flag of channel 4 19 1 GIF5 Global interrupt flag of channel 5 20 1 FTFIF5 Full Transfer finish flag of channe 5 21 1 HTFIF5 Half transfer finish flag of channel 5 22 1 ERRIF5 Error flag of channel 5 23 1 GIF6 Global interrupt flag of channel 6 24 1 FTFIF6 Full Transfer finish flag of channe 6 25 1 HTFIF6 Half transfer finish flag of channel 6 26 1 ERRIF6 Error flag of channel 6 27 1 INTC INTC Interrupt flag clear register 0x04 0x20 write-only 0x00000000 GIFC0 Clear global interrupt flag of channel 0 0 1 GIFC0read-writeClearClears the GIF flag in INTF1 FTFIFC0 Clear bit for full transfer finish flag of channel 0 1 1 FTFIFC0read-writeClearClears the FDFIF flag in INTF1 HTFIFC0 Clear bit for half transfer finish flag of channel 0 2 1 HTFIFC0read-writeClearClears the HTFIF flag in INTF1 ERRIFC0 Clear bit for error flag of channel 0 3 1 ERRIFC0read-writeClearClears the ERRIF flag in INTF1 GIFC1 Clear global interrupt flag of channel 1 4 1 FTFIFC1 Clear bit for full transfer finish flag of channel 1 5 1 HTFIFC1 Clear bit for half transfer finish flag of channel 1 6 1 ERRIFC1 Clear bit for error flag of channel 1 7 1 GIFC2 Clear global interrupt flag of channel 2 8 1 FTFIFC2 Clear bit for full transfer finish flag of channel 2 9 1 HTFIFC2 Clear bit for half transfer finish flag of channel 2 10 1 ERRIFC2 Clear bit for error flag of channel 2 11 1 GIFC3 Clear global interrupt flag of channel 3 12 1 FTFIFC3 Clear bit for full transfer finish flag of channel 3 13 1 HTFIFC3 Clear bit for half transfer finish flag of channel 3 14 1 ERRIFC3 Clear bit for error flag of channel 3 15 1 GIFC4 Clear global interrupt flag of channel 4 16 1 FTFIFC4 Clear bit for full transfer finish flag of channel 4 17 1 HTFIFC4 Clear bit for half transfer finish flag of channel 4 18 1 ERRIFC4 Clear bit for error flag of channel 4 19 1 GIFC5 Clear global interrupt flag of channel 5 20 1 FTFIFC5 Clear bit for full transfer finish flag of channel 5 21 1 HTFIFC5 Clear bit for half transfer finish flag of channel 5 22 1 ERRIFC5 Clear bit for error flag of channel 5 23 1 GIFC6 Clear global interrupt flag of channel 6 24 1 FTFIFC6 Clear bit for full transfer finish flag of channel 6 25 1 HTFIFC6 Clear bit for half transfer finish flag of channel 6 26 1 ERRIFC6 Clear bit for error flag of channel 6 27 1 CH0CTL CH0CTL Channel 0 control register 0x08 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for channel full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for channel half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for channel error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer direction 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority level 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to Memory Mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH0CNT CH0CNT Channel 0 counter register 0x0C 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH0PADDR CH0PADDR Channel 0 peripheral base address register 0x10 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH0MADDR CH0MADDR Channel 0 memory base address register 0x14 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH1CTL CH1CTL Channel 1 control register 0x1C 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for channel full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for channel half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for channel error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer direction 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority level 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to Memory Mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH1CNT CH1CNT Channel 1 counter register 0x20 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH1PADDR CH1PADDR Channel 1 peripheral base address register 0x24 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH1MADDR CH1MADDR Channel 1 memory base address register 0x28 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH2CTL CH2CTL Channel 2 control register 0x30 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for channel full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for channel half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for channel error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer direction 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority level 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to Memory Mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH2CNT CH2CNT Channel 2 counter register 0x34 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH2PADDR CH2PADDR Channel 2 peripheral base address register 0x38 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH2MADDR CH2MADDR Channel 2 memory base address register 0x3C 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH3CTL CH3CTL Channel 3 control register 0x44 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for channel full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for channel half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for channel error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer direction 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority level 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to Memory Mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH3CNT CH3CNT Channel 3 counter register 0x48 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH3PADDR CH3PADDR Channel 3 peripheral base address register 0x4C 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH3MADDR CH3MADDR Channel 3 memory base address register 0x50 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH4CTL CH4CTL Channel 4 control register 0x58 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for channel full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for channel half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for channel error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer direction 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority level 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to Memory Mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH4CNT CH4CNT Channel 4 counter register 0x5C 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH4PADDR CH4PADDR Channel 4 peripheral base address register 0x60 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH4MADDR CH4MADDR Channel 4 memory base address register 0x64 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH5CTL CH5CTL Channel 5 control register 0x6C 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for channel full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for channel half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for channel error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer direction 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority level 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to Memory Mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH5CNT CH5CNT Channel 5 counter register 0x70 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH5PADDR CH5PADDR Channel 5 peripheral base address register 0x74 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH5MADDR CH5MADDR Channel 5 memory base address register 0x78 0x20 read-write 0x00000000 MADDR Memory base address 0 32 CH6CTL CH6CTL Channel 6 control register 0x80 0x20 read-write 0x00000000 CHEN Channel enable 0 1 CHENread-writeDisabledChannel disabled0EnabledChannel enabled1 FTFIE Enable bit for channel full transfer finish interrupt 1 1 FTFIEread-writeDisabledFull transfer interrupt disabled0EnabledFull transfer interrupt enabled1 HTFIE Enable bit for channel half transfer finish interrupt 2 1 HTFIEread-writeDisabledHalf transfer interrupt disabled0EnabledHalf transfer interrupt enabled1 ERRIE Enable bit for channel error interrupt 3 1 ERRIEread-writeDisabledTransfer error interrupt disabled0EnabledTransfer error interrupt enabled1 DIR Transfer direction 4 1 DIRread-writeFromPeripheralRead from peripheral0FromMemoryRead from memory1 CMEN Circular mode enable 5 1 CMENread-writeDisabledCircular buffer disabled0EnabledCircular buffer enabled1 PNAGA Next address generation algorithm of peripheral 6 1 PNAGAread-writeFixedFixed address mode0IncrementIncrement address mode1 MNAGA Next address generation algorithm of memory 7 1 PWIDTH Transfer data size of peripheral 8 2 PWIDTHread-writeBits88-bit size0Bits1616-bit size1Bits3232-bit size2 MWIDTH Transfer data size of memory 10 2 PRIO Priority level 12 2 PRIOread-writeLowLow priority0MediumMedium priority1HighHigh priority2VeryHighVery high priority3 M2M Memory to Memory Mode 14 1 M2Mread-writeDisabledMemory to memory mode disabled0EnabledMemory to memory mode enabled1 CH6CNT CH6CNT Channel 6 counter register 0x84 0x20 read-write 0x00000000 CNT Transfer counter 0 16 065535 CH6PADDR CH6PADDR Channel 6 peripheral base address register 0x88 0x20 read-write 0x00000000 PADDR Peripheral base address 0 32 CH6MADDR CH6MADDR Channel 6 memory base address register 0x8C 0x20 read-write 0x00000000 MADDR Memory base address 0 32 DMA1 0x40020400 DMA1_Channel0 56 DMA1_Channel1 57 DMA1_Channel2 58 DMA1_Channel3 59 DMA1_Channel4 60 ENET_DMA Ethernet: DMA controller operation ENET 0x40029000 0x0 0x60 registers DMA_BCTL DMA_BCTL Ethernet DMA bus control register 0x0 0x20 read-write 0x00020101 SWR Software reset 0 1 DAB DMA Arbitration 1 1 DPSL Descriptor skip length 2 5 DFM Descriptor format mode 7 1 PGBL Programmable burst length 8 6 RTPR RxDMA and TxDMA transfer priority ratio 14 2 FB Fixed burst 16 1 RXDP Rx DMA PGBL 17 6 UIP Use independent PGBL 23 1 FPBL Four times PGBL mode 24 1 AA Address-aligned 25 1 MB Mixed burst 26 1 DMA_TPEN DMA_TPEN Ethernet DMA transmit poll enable register 0x4 0x20 read-write 0x00000000 TPE Transmit poll enable 0 32 DMA_RPEN DMA_RPEN Ethernet DMA receive poll enable register 0x8 0x20 read-write 0x00000000 RPE Receive poll enable 0 32 DMA_RDTADDR DMA_RDTADDR Ethernet DMA receive descriptor table address register 0xC 0x20 read-write 0x00000000 SRT Start address of receive table 0 32 DMA_TDTADDR DMA_TDTADDR Ethernet DMA transmit descriptor table address register 0x10 0x20 read-write 0x00000000 STT Start address of transmit table 0 32 DMA_STAT DMA_STAT Ethernet DMA status register 0x14 0x20 0x00000000 TS Transmit status 0 1 read-write TPS Transmit process stopped status 1 1 read-write TBU Transmit buffer unavailable status 2 1 read-write TJT Transmit jabber timeout status 3 1 read-write RO Receive overflow status 4 1 read-write TU Transmit underflow status 5 1 read-write RS Receive status 6 1 read-write RBU Receive buffer unavailable status 7 1 read-write RPS Receive process stopped status 8 1 read-write RWT Receive watchdog timeout status 9 1 read-write ET Early transmit status 10 1 read-write FBE Fatal bus error status 13 1 read-write ER Early receive status 14 1 read-write AI Abnormal interrupt summary 15 1 read-write NI Normal interrupt summary 16 1 read-write RP Receive process state 17 3 read-only TP Transmit process state 20 3 read-only EB Error bits status 23 3 read-only MSC MSC status 27 1 read-only WUM WUM status 28 1 read-only TST Time stamp trigger status 29 1 read-only DMA_CTL DMA_CTL Ethernet DMA control register 0x18 0x20 read-write 0x00000000 SRE Start/stop receive enable 1 1 OSF Operate on second frame 2 1 RTHC Receive threshold control 3 2 FUF Forward undersized good frames 6 1 FERF Forward error frames 7 1 STE Start/stop transmission enable 13 1 TTHC Transmit threshold control 14 3 FTF Flush transmit FIFO 20 1 TSFD Transmit Store-and-Forward 21 1 DAFRF Disable flushing of received frames 24 1 RSFD Receive Store-and-Forward 25 1 DTCERFD Dropping of TCP/IP checksum error frames disable 26 1 DMA_INTEN DMA_INTEN Ethernet DMA interrupt enable register 0x1C 0x20 read-write 0x00000000 TIE Transmit interrupt enable 0 1 TPSIE Transmit process stopped interrupt enable 1 1 TBUIE Transmit buffer unavailable interrupt enable 2 1 TJTIE Transmit jabber timeout interrupt enable 3 1 ROIE Receive overflow interrupt enable 4 1 TUIE Transmit underflow interrupt enable 5 1 RIE Receive interrupt enable 6 1 RBUIE Receive buffer unavailable interrupt enable 7 1 RPSIE Receive process stopped interrupt enable 8 1 RWTIE receive watchdog timeout interrupt enable 9 1 ETIE Early transmit interrupt enable 10 1 FBEIE Fatal bus error interrupt enable 13 1 ERIE Early receive interrupt enable 14 1 AIE Abnormal interrupt summary enable 15 1 NIE Normal interrupt summary enable 16 1 DMA_MFBOCNT DMA_MFBOCNT Ethernet DMA missed frame and buffer overflow counter register 0x20 0x20 read-only 0x00000000 MSFC Missed frames by the controller 0 16 MSFA Missed frames by the application 17 11 DMA_RSWDC DMA_RSWDC Ethernet DMA receive state watchdog counter register 0x24 0x20 read-write 0x00000000 WDCFRS Watchdog counter for receive status (RS) 0 8 DMA_CTDADDR DMA_CTDADDR DMA current transmit descriptor address register 0x48 0x20 read-only 0x00000000 TDAP transmit descriptor address pointer 0 32 DMA_CRDADDR DMA_CRDADDR Ethernet DMA current receive descriptor address register 0x4C 0x20 read-only 0x00000000 RDAP Receive descriptor address pointer 0 32 DMA_CTBADDR DMA_CTBADDR Ethernet DMA current transmit buffer address register 0x50 0x20 read-only 0x00000000 TBAP Transmit buffer address pointer 0 32 DMA_CRBADDR DMA_CRBADDR Ethernet DMA current receive buffer address register 0x54 0x20 read-only 0x00000000 RBAP receive buffer address pointer 0 32 ENET_MAC_FCTH MAC flow control threshold register ENET 0x40029080 0x00 0x20 registers MAC_FCTH MAC_FCTH Ethernet MAC flow control threshold register 0x00 0x20 read-write 0x00000015 RFA Threshold of active flow control 0 3 RFD Threshold of deactive flow control 4 3 ENET_MAC Ethernet: media access control ENET 0x40028000 0x0 0x100 registers ENET 61 ENET_WKUP 62 MAC_CFG MAC_CFG Ethernet MAC configuration register (MAC_CFG) 0x0 0x20 read-write 0x00008000 REN Receiver enable 2 1 TEN Transmitter enable 3 1 DFC Deferral check 4 1 BOL Back-off limit 5 2 APCD Automatic pad/CRC drop 7 1 RTD Retry disable 9 1 IPFCO IP frame checksum offload 10 1 DPM Duplex mode 11 1 LBM Loopback mode 12 1 ROD Receive own disable 13 1 SPD Fast Ethernet speed 14 1 CSD Carrier sense disable 16 1 IGBS Inter frame gap bit selection 17 3 JBD Jabber disable 22 1 WDD Watchdog disable 23 1 TFCD Type Frame CRC Dropping 25 1 MAC_FRMF MAC_FRMF Ethernet MAC frame filter register (MAC_FRMF) 0x4 0x20 read-write 0x00000000 PM Promiscuous mode 0 1 HUF Hash unicast filter 1 1 HMF Hash multicast filter 2 1 DAIFLT Destination address inverse filtering 3 1 MFD multicast filter disable 4 1 BFRMD Broadcast frames disable 5 1 PCFRM Pass control frames 6 2 SAIFLT Source address inverse filtering 8 1 SAFLT Source address filter 9 1 HPFLT Hash or perfect filter 10 1 FAR Frames all receive 31 1 MAC_HLH MAC_HLH Ethernet MAC hash list high register 0x8 0x20 read-write 0x00000000 HLH Hash list high 0 32 MAC_HLL MAC_HLL Ethernet MAC hash list low register 0xC 0x20 read-write 0x00000000 HLL Hash list low 0 32 MAC_PHY_CTL MAC_PHY_CTL Ethernet MAC PHY control register (MAC_PHY_CTL) 0x10 0x20 read-write 0x00000000 PB PHY busy 0 1 PW PHY write 1 1 CLR Clock range 2 3 PR PHY register 6 5 PA PHY address 11 5 MAC_PHY_DATA MAC_PHY_DATA Ethernet MAC MII data register (MAC_PHY_DATA) 0x14 0x20 read-write 0x00000000 PD PHY data 0 16 MAC_FCTL MAC_FCTL Ethernet MAC flow control register (MAC_FCTL) 0x18 0x20 read-write 0x00000000 FLCB_BKPA Flow control busy/back pressure activate 0 1 TFCEN Transmit flow control enable 1 1 RFCEN Receive flow control enable 2 1 UPFDT Unicast pause frame detect 3 1 PLTS Pause low threshold 4 2 DZQP Disable Zero-quanta pause 7 1 PTM Pause time 16 16 MAC_VLT MAC_VLT Ethernet MAC VLAN tag register (MAC_VLT) 0x1C 0x20 read-write 0x00000000 VLTI VLAN tag identifier (for receive frames) 0 16 VLTC 12-bit VLAN tag comparison 16 1 MAC_RWFF MAC_RWFF Ethernet MAC remote wakeup frame filter register (MAC_RWFF) 0x28 0x20 read-write 0x00000000 MAC_WUM MAC_WUM Ethernet MAC wakeup management register (MAC_WUM) 0x2C 0x20 read-write 0x00000000 PWD Power down 0 1 MPEN Magic Packet enable 1 1 WFEN Wakeup frame enable 2 1 MPKR Magic packet received 5 1 WUFR Wakeup frame received 6 1 GU Global unicast 9 1 WUFFRPR Wakeup frame filter register pointer reset 31 1 MAC_DBG MAC_DBG Ethernet MAC debug register (MAC_DBG) 0x34 0x20 read-only 0x00000000 MRNI MAC receive state not idle 0 1 RXAFS Rx asynchronous FIFO status 1 2 RXFW RxFIFO is writing 4 1 RXFRS RxFIFO read operation status 5 2 RXFS RxFIFO state 8 2 MTNI MAC transmit state not idle 16 1 SOMT Status of MAC transmitter 17 2 PCS Pause condition status 19 1 TXFRS TxFIFO read operation status 20 2 TXFW TxFIFO is writing 22 1 TXFNE TxFIFO not empty flag 24 1 TXFF TxFIFO Full flag 25 1 MAC_INTF MAC_INTF Ethernet MAC interrupt flag register (MAC_INTF) 0x38 0x20 read-only 0x00000000 WUM WUM status 3 1 MSC MSC status 4 1 MSCR MSC receive status 5 1 MSCT MSC transmit status 6 1 TMST Time stamp trigger status 9 1 MAC_INTMSK MAC_INTMSK Ethernet MAC interrupt mask register (MAC_INTMSK) 0x3C 0x20 read-write 0x00000000 WUMIM WUM interrupt mask 3 1 TMSTIM Time stamp trigger interrupt mask 9 1 MAC_ADDR0H MAC_ADDR0H Ethernet MAC address 0 high register (MAC_ADDR0H) 0x40 0x20 0x8000FFFF ADDR0H MAC address0 high 0 16 read-write MO Always 1 31 1 read-write MAC_ADDR0L MAC_ADDR0L Ethernet MAC address 0 low register 0x44 0x20 read-write 0xFFFFFFFF ADDR0L MAC address0 low 0 32 MAC_ADDR1H MAC_ADDR1H Ethernet MAC address 1 high register (MAC_ADDR1H) 0x48 0x20 read-write 0x0000FFFF ADDR1H MAC address1 high 0 16 MB Mask byte 24 6 SAF Source address filter 30 1 AFE Address filter enable 31 1 MAC_ADDR1L MAC_ADDR1L Ethernet MAC address1 low register 0x4C 0x20 read-write 0xFFFFFFFF ADDR1L MAC address1 low 0 32 MAC_ADDR2H MAC_ADDR2H Ethernet MAC address 2 high register (MAC_ADDR2H) 0x50 0x20 read-write 0x0000FFFF ADDR2H Ethernet MAC address 2 high register 0 16 MB Mask byte 24 6 SAF Source address filter 30 1 AFE Address filter enable 31 1 MAC_ADDR2L MAC_ADDR2L Ethernet MAC address 2 low register 0x54 0x20 read-write 0xFFFFFFFF ADDR2L MAC address2 low 0 32 MAC_ADDR3H MAC_ADDR3H Ethernet MAC address 3 high register (MAC_ADDR3H) 0x58 0x20 read-write 0x0000FFFF ADDR3H MAC address3 high 0 16 MB Mask byte 24 6 SAF Source address filter 30 1 AFE Address filter enable 31 1 MAC_ADDR3L MAC_ADDR3L Ethernet MAC address 3 low register 0x5C 0x20 read-write 0xFFFFFFFF ADDR3L MAC address3 low 0 32 ENET_MSC Ethernet: MAC statistics counters ENET 0x40028100 0x0 0x400 registers MSC_CTL MSC_CTL Ethernet MSC control register (MSC_CTL) 0x0 0x20 read-write 0x00000000 CTR Counter reset 0 1 CTSR Counter stop rollover 1 1 RTOR Reset on read 2 1 MCFZ MSC counter freeze 3 1 PMC Preset MSC counter 4 1 write-only AFHPM Almost full or half preset mode 5 1 MSC_RINTF MSC_RINTF Ethernet MSC receive interrupt flag register (MSC_RINTF) 0x4 0x20 read-only 0x00000000 RFCE Received frames CRC error 5 1 RFAE Received frames alignment error 6 1 RGUF Received Good Unicast Frames 17 1 MSC_TINTF MSC_TINTF Ethernet MSC transmit interrupt flag register (MSC_TINTF) 0x8 0x20 read-only 0x00000000 TGFSC Transmitted good frames single collision 14 1 TGFMSC Transmitted good frames more single collision 15 1 TGF Transmitted good frames 21 1 MSC_RINTMSK MSC_RINTMSK Ethernet MSC receive interrupt mask register (MSC_RINTMSK) 0xC 0x20 read-write 0x00000000 RFCEIM Received frame CRC error interrupt mask 5 1 RFAEIM Received frames alignment error interrupt mask 6 1 RGUFIM Received good unicast frames interrupt mask 17 1 MSC_TINTMSK MSC_TINTMSK Ethernet MSC transmit interrupt mask register (MSC_TINTMSK) 0x10 0x20 read-write 0x00000000 TGFSCIM Transmitted good frames single collision interrupt mask 14 1 TGFMSCIM Transmitted good frames more single interrupt collision mask 15 1 TGFIM Transmitted good frames interrupt mask 21 1 MSC_SCCNT MSC_SCCNT Ethernet MSC transmitted good frames after a single collision counter 0x4C 0x20 read-only 0x00000000 SCC Transmitted good frames after a single collision counter 0 32 MSC_MSCCNT MSC_MSCCNT Ethernet MSC transmitted good frames after more than a single collision 0x50 0x20 read-only 0x00000000 MSCC Transmitted good frames after more than a single collision counter 0 32 MSC_TGFCNT MSC_TGFCNT Ethernet MSC transmitted good frames counter register 0x68 0x20 read-only 0x00000000 TGF Transmitted good frames counter 0 32 MSC_RFCECNT MSC_RFCECNT Ethernet MSC received frames with CRC error counter register 0x94 0x20 read-only 0x00000000 RFCER Received frames with CRC error counter 0 32 MSC_RFAECNT MSC_RFAECNT Ethernet MSC received frames with alignment error counter register 0x98 0x20 read-only 0x00000000 RFAER Received frames with alignment error counter 0 32 MSC_RGUFCNT MSC_RGUFCNT MSC received good unicast frames counter register 0xC4 0x20 read-only 0x00000000 RGUF Received good unicast frames counter 0 32 ENET_PTP Ethernet: Precision time protocol ENET 0x40028700 0x0 0x400 registers PTP_TSCTL PTP_TSCTL Ethernet PTP time stamp control register (PTP_TSCTL) 0x0 0x20 read-write 0x00000000 TMSEN Time stamp enable 0 1 TMSFCU Time stamp fine or coarse update 1 1 TMSSTI Time stamp system time initialize 2 1 TMSSTU Time stamp system time update 3 1 TMSITEN Time stamp interrupt trigger enable 4 1 TMSARU Time stamp addend register update 5 1 ARFSEN All received frames snapshot enable 8 1 SCROM Subsecond counter rollover mode 9 1 PFSV PTP frame snooping version 10 1 ESEN Received Ethernet snapshot enable 11 1 IP6SEN Received IPv6 snapshot enable 12 1 IP4SEN Received IPv4 snapshot enable 13 1 ETMSEN Received event type message snapshot enable 14 1 MNMSEN Received master node message snapshot enable 15 1 CKNT Clock node type for time stamp 16 2 MAFEN MAC address filter enable for PTP frame 18 1 PTP_SSINC PTP_SSINC Ethernet PTP subsecond increment register 0x4 0x20 read-write 0x00000000 STMSSI System time subsecond increment 0 8 PTP_TSH PTP_TSH Ethernet PTP time stamp high register 0x8 0x20 read-only 0x00000000 STMS System time second 0 32 PTP_TSL PTP_TSL Ethernet PTP time stamp low register (PTP_TSL) 0xC 0x20 read-only 0x00000000 STMSS System time subseconds 0 31 STS System time sign 31 1 PTP_TSUH PTP_TSUH Ethernet PTP time stamp high update register 0x10 0x20 read-write 0x00000000 TMSUS Time stamp update second 0 32 PTP_TSUL PTP_TSUL Ethernet PTP time stamp low update register (PTP_TSUL) 0x14 0x20 read-write 0x00000000 TMSUSS Time stamp update subseconds 0 31 TMSUPNS Time stamp update positive or negative sign 31 1 PTP_TSADDEND PTP_TSADDEND Ethernet PTP time stamp addend register 0x18 0x20 read-write 0x00000000 TMSA Time stamp addend 0 32 PTP_ETH PTP_ETH Ethernet PTP expected time high register 0x1C 0x20 read-write 0x00000000 ETSH Expected time stamp high 0 32 PTP_ETL PTP_ETL Ethernet PTP expected time low register 0x20 0x20 read-write 0x00000000 ETSL Expected time stamp low 0 32 PTP_TSF PTP_TSF Ethernet PTP time stamp flag register 0x28 0x20 read-only 0x00000000 TSSCO Timestamp second counter overflow 0 1 TTM Target time match 1 1 PTP_PPSCTL PTP_PPSCTL Ethernet PTP PPS control register 0x2C 0x20 read-write 0x00000000 PPSOFC PPS output frequency configure 0 4 EXMC External memory controller EXMC 0xA0000000 0x0 0x1000 registers EXMC 48 SNCTL0 SNCTL0 SRAM/NOR flash control register 0 0x0 0x20 read-write 0x000030DB SYNCWR Synchronous write 19 1 CPS CRAM page size 16 3 ASYNCWAIT Asynchronous wait 15 1 EXMODEN Extended mode enable 14 1 NRWTEN NWAIT signal enable 13 1 WREN Write enable 12 1 NRWTCFG NWAIT signal configuration, only work in synchronous mode 11 1 WRAPEN Wrapped burst mode enable 10 1 NRWTPOL NWAIT signal polarity 9 1 SBRSTEN Synchronous burst enable 8 1 NREN NOR Flash access enable 6 1 NRW NOR bank memory data bus width 4 2 NRTP NOR bank memory type 2 2 NRMUX NOR bank memory address/data multiplexing 1 1 NRBKEN NOR bank enable 0 1 SNTCFG0 SNTCFG0 SRAM/NOR flash timing configuration register 0 0x4 0x20 read-write 0x0FFFFFFF ASYNCMOD Asynchronous access mode 28 2 DLAT Data latency for NOR Flash 24 4 CKDIV Synchronous clock divide ratio 20 4 BUSLAT Bus latency 16 4 DSET Data setup time 8 8 AHLD Address hold time 4 4 ASET Address setup time 0 4 SNCTL1 SNCTL1 SRAM/NOR flash control register 1 0x8 0x20 read-write 0x000030D2 SYNCWR Synchronous write 19 1 CPS CRAM page size 16 3 ASYNCWAIT Asynchronous wait 15 1 EXMODEN Extended mode enable 14 1 NRWTEN NWAIT signal enable 13 1 WREN Write enable 12 1 NRWTCFG NWAIT signal configuration, only work in synchronous mode 11 1 WRAPEN Wrapped burst mode enable 10 1 NRWTPOL NWAIT signal polarity 9 1 SBRSTEN Synchronous burst enable 8 1 NREN NOR Flash access enable 6 1 NRW NOR bank memory data bus width 4 2 NRTP NOR bank memory type 2 2 NRMUX NOR bank memory address/data multiplexing 1 1 NRBKEN NOR bank enable 0 1 SNTCFG1 SNTCFG1 SRAM/NOR flash timing configuration register 1 0xC 0x20 read-write 0x0FFFFFFF ASYNCMOD Asynchronous access mode 28 2 DLAT Data latency for NOR Flash 24 4 CKDIV Synchronous clock divide ratio 20 4 BUSLAT Bus latency 16 4 DSET Data setup time 8 8 AHLD Address hold time 4 4 ASET Address setup time 0 4 SNCTL2 SNCTL2 SRAM/NOR flash control register 2 0x10 0x20 read-write 0x000030D2 SYNCWR Synchronous write 19 1 CPS CRAM page size 16 3 ASYNCWAIT Asynchronous wait 15 1 EXMODEN Extended mode enable 14 1 NRWTEN NWAIT signal enable 13 1 WREN Write enable 12 1 NRWTCFG NWAIT signal configuration, only work in synchronous mode 11 1 WRAPEN Wrapped burst mode enable 10 1 NRWTPOL NWAIT signal polarity 9 1 SBRSTEN Synchronous burst enable 8 1 NREN NOR Flash access enable 6 1 NRW NOR bank memory data bus width 4 2 NRTP NOR bank memory type 2 2 NRMUX NOR bank memory address/data multiplexing 1 1 NRBKEN NOR bank enable 0 1 SNTCFG2 SNTCFG2 SRAM/NOR flash timing configuration register 2 0x14 0x20 read-write 0x0FFFFFFF ASYNCMOD Asynchronous access mode 28 2 DLAT Data latency for NOR Flash 24 4 CKDIV Synchronous clock divide ratio 20 4 BUSLAT Bus latency 16 4 DSET Data setup time 8 8 AHLD Address hold time 4 4 ASET Address setup time 0 4 SNCTL3 SNCTL3 SRAM/NOR flash control register 3 0x18 0x20 read-write 0x000030D2 SYNCWR Synchronous write 19 1 CPS CRAM page size 16 3 ASYNCWAIT Asynchronous wait 15 1 EXMODEN Extended mode enable 14 1 NRWTEN NWAIT signal enable 13 1 WREN Write enable 12 1 NRWTCFG NWAIT signal configuration, only work in synchronous mode 11 1 WRAPEN Wrapped burst mode enable 10 1 NRWTPOL NWAIT signal polarity 9 1 SBRSTEN Synchronous burst enable 8 1 NREN NOR Flash access enable 6 1 NRW NOR bank memory data bus width 4 2 NRTP NOR bank memory type 2 2 NRMUX NOR bank memory address/data multiplexing 1 1 NRBKEN NOR bank enable 0 1 SNTCFG3 SNTCFG3 SRAM/NOR flash timing configuration register 3 0x1C 0x20 read-write 0x0FFFFFFF ASYNCMOD Asynchronous access mode 28 2 DLAT Data latency for NOR Flash 24 4 CKDIV Synchronous clock divide ratio 20 4 BUSLAT Bus latency 16 4 DSET Data setup time 8 8 AHLD Address hold time 4 4 ASET Address setup time 0 4 SNWTCFG0 SNWTCFG0 SRAM/NOR flash write timing configuration register 0 0x104 0x20 read-write 0x0FFFFFFF WASYNCMOD Asynchronous access mode 28 2 WBUSLAT Bus latency 16 4 WDSET Data setup time 8 8 WAHLD Address hold time 4 4 WASET Address setup time 0 4 SNWTCFG1 SNWTCFG1 SRAM/NOR flash write timing configuration register 1 0x10C 0x20 read-write 0x0FFFFFFF WASYNCMOD Asynchronous access mode 28 2 WBUSLAT Bus latency 16 4 WDSET Data setup time 8 8 WAHLD Address hold time 4 4 WASET Address setup time 0 4 SNWTCFG2 SNWTCFG2 SRAM/NOR flash write timing configuration register 2 0x114 0x20 read-write 0x0FFFFFFF WASYNCMOD Asynchronous access mode 28 2 WBUSLAT Bus latency 16 4 WDSET Data setup time 8 8 WAHLD Address hold time 4 4 WASET Address setup time 0 4 SNWTCFG3 SNWTCFG3 SRAM/NOR flash write timing configuration register 3 0x11C 0x20 read-write 0x0FFFFFFF WASYNCMOD Asynchronous access mode 28 2 WBUSLAT Bus latency 16 4 WDSET Data setup time 8 8 WAHLD Address hold time 4 4 WASET Address setup time 0 4 NPCTL1 NPCTL1 NAND flash/PC card control register 1 0x60 0x20 read-write 0x00000018 ECCSZ ECC size 17 3 ATR ALE to RE delay 13 4 CTR CLE to RE delay 9 4 ECCEN ECC enable 6 1 NDW NAND bank memory data bus width 4 2 NDTP NAND bank memory type 3 1 NDBKEN NAND bank enable 2 1 NDWTEN Wait feature enable 1 1 NPCTL2 NPCTL2 NAND flash/PC card control register 2 0x80 0x20 read-write 0x00000018 ECCSZ ECC size 17 3 ATR ALE to RE delay 13 4 CTR CLE to RE delay 9 4 ECCEN ECC enable 6 1 NDW NAND bank memory data bus width 4 2 NDTP NAND bank memory type 3 1 NDBKEN NAND bank enable 2 1 NDWTEN Wait feature enable 1 1 NPCTL3 NPCTL3 NAND flash/PC card control register 3 0xA0 0x20 read-write 0x00000018 ECCSZ ECC size 17 3 ATR ALE to RE delay 13 4 CTR CLE to RE delay 9 4 ECCEN ECC enable 6 1 NDW NAND bank memory data bus width 4 2 NDTP NAND bank memory type 3 1 NDBKEN NAND bank enable 2 1 NDWTEN Wait feature enable 1 1 NPINTEN1 NPINTEN1 NAND flash/PC card interrupt enable register 1 0x64 0x20 read-write 0x00000040 FFEPT FIFO empty flag 6 1 INTFEN Interrupt falling edge detection enable 5 1 INTHEN Interrupt high-level detection enable 4 1 INTREN Interrupt rising edge detection enable bit 3 1 INTFS Interrupt falling edge status 2 1 INTHS Interrupt high-level status 1 1 INTRS Interrupt rising edge status 0 1 NPINTEN2 NPINTEN2 NAND flash/PC card interrupt enable register 2 0x84 0x20 read-write 0x00000040 FFEPT FIFO empty flag 6 1 INTFEN Interrupt falling edge detection enable 5 1 INTHEN Interrupt high-level detection enable 4 1 INTREN Interrupt rising edge detection enable bit 3 1 INTFS Interrupt falling edge status 2 1 INTHS Interrupt high-level status 1 1 INTRS Interrupt rising edge status 0 1 NPINTEN3 NPINTEN3 NAND flash/PC card interrupt enable register 3 0xA4 0x20 read-write 0x00000040 FFEPT FIFO empty flag 6 1 INTFEN Interrupt falling edge detection enable 5 1 INTHEN Interrupt high-level detection enable 4 1 INTREN Interrupt rising edge detection enable bit 3 1 INTFS Interrupt falling edge status 2 1 INTHS Interrupt high-level status 1 1 INTRS Interrupt rising edge status 0 1 NPCTCFG1 NPCTCFG1 NAND flash/PC card common space timing configuration register 1 0x68 0x20 read-write 0xFCFCFCFC COMHIZ Common memory data bus HiZ time 24 8 COMHLD Common memory hold time 16 8 COMWAIT Common memory wait time 8 8 COMSET Common memory setup time 0 8 NPCTCFG2 NPCTCFG2 NAND flash/PC card common space timing configuration register 2 0x88 0x20 read-write 0xFCFCFCFC COMHIZ Common memory data bus HiZ time 24 8 COMHLD Common memory hold time 16 8 COMWAIT Common memory wait time 8 8 COMSET Common memory setup time 0 8 NPCTCFG3 NPCTCFG3 NAND flash/PC card common space timing configuration register 3 0xA8 0x20 read-write 0xFCFCFCFC COMHIZ Common memory data bus HiZ time 24 8 COMHLD Common memory hold time 16 8 COMWAIT Common memory wait time 8 8 COMSET Common memory setup time 0 8 NPATCFG1 NPATCFG1 NAND flash/PC card attribute space timing configuration register 1 0x6C 0x20 read-write 0xFCFCFCFC ATTHIZ Attribute memory data bus HiZ time 24 8 ATTHLD Attribute memory hold time 16 8 ATTWAIT Attribute memory wait time 8 8 ATTSET Attribute memory setup time 0 8 NPATCFG2 NPATCFG2 NAND flash/PC card attribute space timing configuration register 2 0x8C 0x20 read-write 0xFCFCFCFC ATTHIZ Attribute memory data bus HiZ time 24 8 ATTHLD Attribute memory hold time 16 8 ATTWAIT Attribute memory wait time 8 8 ATTSET Attribute memory setup time 0 8 NPATCFG3 NPATCFG3 NAND flash/PC card attribute space timing configuration register 3 0xAC 0x20 read-write 0xFCFCFCFC ATTHIZ Attribute memory data bus HiZ time 24 8 ATTHLD Attribute memory hold time 16 8 ATTWAIT Attribute memory wait time 8 8 ATTSET Attribute memory setup time 0 8 PIOTCFG3 PIOTCFG3 PC card I/O space timing configuration register 0xB0 0x20 read-write 0xFCFCFCFC IOHIZ IO space data bus HiZ time 24 8 IOHLD IO space hold time 16 8 IOWAIT IO space wait time 8 8 IOSET IO space setup time 0 8 NECC1 NECC1 NAND flash ECC register 1 0x74 0x20 0x00000000 ECC ECC result 0 32 read-only NECC2 NECC2 NAND flash ECC register 2 0x94 0x20 0x00000000 ECC ECC result 0 32 read-only EXTI External interrupt/event controller EXTI 0x40010400 0x0 0x400 registers EXTI_Line0 6 EXTI_Line1 7 EXTI_Line2 8 EXTI_Line3 9 EXTI_Line4 10 EXTI_line9_5 23 EXTI_line15_10 40 INTEN INTEN Interrupt enable register (EXTI_INTEN) 0x0 0x20 read-write 0x00000000 INTEN0 Enable Interrupt on line 0 0 1 INTEN0read-writeMaskedInterrupt from line is disabled0UnmaskedInterrupt from line is enabled1 INTEN1 Enable Interrupt on line 1 1 1 INTEN2 Enable Interrupt on line 2 2 1 INTEN3 Enable Interrupt on line 3 3 1 INTEN4 Enable Interrupt on line 4 4 1 INTEN5 Enable Interrupt on line 5 5 1 INTEN6 Enable Interrupt on line 6 6 1 INTEN7 Enable Interrupt on line 7 7 1 INTEN8 Enable Interrupt on line 8 8 1 INTEN9 Enable Interrupt on line 9 9 1 INTEN10 Enable Interrupt on line 10 10 1 INTEN11 Enable Interrupt on line 11 11 1 INTEN12 Enable Interrupt on line 12 12 1 INTEN13 Enable Interrupt on line 13 13 1 INTEN14 Enable Interrupt on line 14 14 1 INTEN15 Enable Interrupt on line 15 15 1 INTEN16 Enable Interrupt on line 16 16 1 INTEN17 Enable Interrupt on line 17 17 1 INTEN18 Enable Interrupt on line 18 18 1 INTEN19 Enable Interrupt on line 19 19 1 EVEN EVEN Event enable register (EXTI_EVEN) 0x04 0x20 read-write 0x00000000 EVEN0 Enable Event on line 0 0 1 EVEN0read-writeMaskedEvent from line is disabled0UnmaskedEvent from line is enabled1 EVEN1 Enable Event on line 1 1 1 EVEN2 Enable Event on line 2 2 1 EVEN3 Enable Event on line 3 3 1 EVEN4 Enable Event on line 4 4 1 EVEN5 Enable Event on line 5 5 1 EVEN6 Enable Event on line 6 6 1 EVEN7 Enable Event on line 7 7 1 EVEN8 Enable Event on line 8 8 1 EVEN9 Enable Event on line 9 9 1 EVEN10 Enable Event on line 10 10 1 EVEN11 Enable Event on line 11 11 1 EVEN12 Enable Event on line 12 12 1 EVEN13 Enable Event on line 13 13 1 EVEN14 Enable Event on line 14 14 1 EVEN15 Enable Event on line 15 15 1 EVEN16 Enable Event on line 16 16 1 EVEN17 Enable Event on line 17 17 1 EVEN18 Enable Event on line 18 18 1 EVEN19 Enable Event on line 19 19 1 RTEN RTEN Rising Edge Trigger Enable register (EXTI_RTEN) 0x08 0x20 read-write 0x00000000 RTEN0 Rising edge trigger enable of line 0 0 1 RTEN0read-writeDisabledRising edge trigger is disabled0EnabledRising edge trigger is enabled1 RTEN1 Rising edge trigger enable of line 1 1 1 RTEN2 Rising edge trigger enable of line 2 2 1 RTEN3 Rising edge trigger enable of line 3 3 1 RTEN4 Rising edge trigger enable of line 4 4 1 RTEN5 Rising edge trigger enable of line 5 5 1 RTEN6 Rising edge trigger enable of line 6 6 1 RTEN7 Rising edge trigger enable of line 7 7 1 RTEN8 Rising edge trigger enable of line 8 8 1 RTEN9 Rising edge trigger enable of line 9 9 1 RTEN10 Rising edge trigger enable of line 10 10 1 RTEN11 Rising edge trigger enable of line 11 11 1 RTEN12 Rising edge trigger enable of line 12 12 1 RTEN13 Rising edge trigger enable of line 13 13 1 RTEN14 Rising edge trigger enable of line 14 14 1 RTEN15 Rising edge trigger enable of line 15 15 1 RTEN16 Rising edge trigger enable of line 16 16 1 RTEN17 Rising edge trigger enable of line 17 17 1 RTEN18 Rising edge trigger enable of line 18 18 1 RTEN19 Rising edge trigger enable of line 19 19 1 FTEN FTEN Falling Egde Trigger Enable register (EXTI_FTEN) 0x0C 0x20 read-write 0x00000000 FTEN0 Falling edge trigger enable of line 0 0 1 FTEN0read-writeDisabledFalling edge trigger is disabled0EnabledFalling edge trigger is enabled1 FTEN1 Falling edge trigger enable of line 1 1 1 FTEN2 Falling edge trigger enable of line 2 2 1 FTEN3 Falling edge trigger enable of line 3 3 1 FTEN4 Falling edge trigger enable of line 4 4 1 FTEN5 Falling edge trigger enable of line 5 5 1 FTEN6 Falling edge trigger enable of line 6 6 1 FTEN7 Falling edge trigger enable of line 7 7 1 FTEN8 Falling edge trigger enable of line 8 8 1 FTEN9 Falling edge trigger enable of line 9 9 1 FTEN10 Falling edge trigger enable of line 10 10 1 FTEN11 Falling edge trigger enable of line 11 11 1 FTEN12 Falling edge trigger enable of line 12 12 1 FTEN13 Falling edge trigger enable of line 13 13 1 FTEN14 Falling edge trigger enable of line 14 14 1 FTEN15 Falling edge trigger enable of line 15 15 1 FTEN16 Falling edge trigger enable of line 16 16 1 FTEN17 Falling edge trigger enable of line 17 17 1 FTEN18 Falling edge trigger enable of line 18 18 1 FTEN19 Falling edge trigger enable of line 19 19 1 SWIEV SWIEV Software interrupt event register (EXTI_SWIEV) 0x10 0x20 read-write 0x00000000 SWIEV0 Interrupt/Event software trigger on line 0 0 1 SWIEV0WwritePendGenerates an interrupt request1 SWIEV1 Interrupt/Event software trigger on line 1 1 1 SWIEV2 Interrupt/Event software trigger on line 2 2 1 SWIEV3 Interrupt/Event software trigger on line 3 3 1 SWIEV4 Interrupt/Event software trigger on line 4 4 1 SWIEV5 Interrupt/Event software trigger on line 5 5 1 SWIEV6 Interrupt/Event software trigger on line 6 6 1 SWIEV7 Interrupt/Event software trigger on line 7 7 1 SWIEV8 Interrupt/Event software trigger on line 8 8 1 SWIEV9 Interrupt/Event software trigger on line 9 9 1 SWIEV10 Interrupt/Event software trigger on line 10 10 1 SWIEV11 Interrupt/Event software trigger on line 11 11 1 SWIEV12 Interrupt/Event software trigger on line 12 12 1 SWIEV13 Interrupt/Event software trigger on line 13 13 1 SWIEV14 Interrupt/Event software trigger on line 14 14 1 SWIEV15 Interrupt/Event software trigger on line 15 15 1 SWIEV16 Interrupt/Event software trigger on line 16 16 1 SWIEV17 Interrupt/Event software trigger on line 17 17 1 SWIEV18 Interrupt/Event software trigger on line 18 18 1 SWIEV19 Interrupt/Event software trigger on line 19 19 1 PD PD Pending register (EXTI_PD) 0x14 0x20 read-write 0x00000000 PD0 Interrupt pending status of line 0 0 1 PD0RreadNotPendingNo trigger request occurred0PendingSelected trigger request occurred1 PD0WwriteClearClears pending bit1 PD1 Interrupt pending status of line 1 1 1 PD2 Interrupt pending status of line 2 2 1 PD3 Interrupt pending status of line 3 3 1 PD4 Interrupt pending status of line 4 4 1 PD5 Interrupt pending status of line 5 5 1 PD6 Interrupt pending status of line 6 6 1 PD7 Interrupt pending status of line 7 7 1 PD8 Interrupt pending status of line 8 8 1 PD9 Interrupt pending status of line 9 9 1 PD10 Interrupt pending status of line 10 10 1 PD11 Interrupt pending status of line 11 11 1 PD12 Interrupt pending status of line 12 12 1 PD13 Interrupt pending status of line 13 13 1 PD14 Interrupt pending status of line 14 14 1 PD15 Interrupt pending status of line 15 15 1 PD16 Interrupt pending status of line 16 16 1 PD17 Interrupt pending status of line 17 17 1 PD18 Interrupt pending status of line 18 18 1 PD19 Interrupt pending status of line 19 19 1 FMC FMC FMC 0x40022000 0x0 0x400 registers FMC 4 WS WS wait state counter register 0x0 0x20 read-write 0x00000000 WSCNT wait state counter register 0 3 WSCNTread-writeWS00 wait states added0WS11 wait state added1WS22 wait states added2 KEY KEY Unlock key register 0x04 0x20 write-only 0x00000000 KEY FMC_CTL unlock register 0 32 04294967295 OBKEY OBKEY Option byte unlock key register 0x08 0x20 write-only 0x00000000 OBKEY FMC_ OBCTL0 option byte operation unlock register 0 32 04294967295 STAT0 STAT0 Status register 0 0x0C 0x20 0x00000000 ENDF End of operation flag bit 5 1 read-write ENDFRreadNoEventNo end of operation occurred0EventAn end of operation event occurred1 ENDFWwriteClearClears flag1 WPERR Erase/Program protection error flag bit 4 1 read-write WPERRRreadNoErrorThere was no error0ErrorThere was an error erasing/programming protected pages1 WPERRWwriteClearClears flag1 PGERR Program error flag bit 2 1 read-write PGERRRreadNoErrorThere was no error0ErrorThere was an error programming flash1 PGERRWwriteClearClears flag1 BUSY The flash is busy bit 0 1 read-only BUSYRreadInactiveNo operation is in progress0ActiveAn operation is in progress1 CTL0 CTL0 Control register 0 0x10 0x20 read-write 0x00000080 ENDIE End of operation interrupt enable bit 12 1 ENDIEread-writeDisabledEnd of operation interrupt disabled0EnabledEnd of operation interrupt enabled1 ERRIE Error interrupt enable bit 10 1 ERRIEread-writeDisabledError interrupt generation disabled0EnabledError interrupt generation enabled1 OBWEN Option byte erase/program enable bit 9 1 OBWENRreadDisabledOption byte write disabled0EnabledOption byte write enabled1 OBWENWwriteDisableDisable option byte write0 LK FMC_CTL0 lock bit 7 1 LKRreadUnlockedCTL register is unlocked0LockedCTL register is locked1 LKWwriteLockLock CTL register1 START Send erase command to FMC bit 6 1 STARTWwriteStartTrigger an erase operation1 OBER Option bytes erase command bit 5 1 OBERread-writeOptionByteEraseErase option byte activated1 OBPG Option bytes program command bit 4 1 OBPGread-writeOptionByteProgrammingProgram option byte activated1 MER Main flash mass erase for bank0 command bit 2 1 MERread-writeMassEraseErase activated for all user sectors1 PER Main flash page erase for bank0 command bit 1 1 PERread-writePageEraseErase activated for selected page1 PG Main flash program for bank0 command bit 0 1 PGread-writeProgramFlash programming activated1 ADDR0 ADDR0 Address register 0 0x14 0x20 write-only 0x00000000 ADDR Flash erase/program command address bits 0 32 04294967295 OBCTL OBCTL Option byte control register 0x1C 0x20 read-only 0x00000000 RERR Option bytes read error bit 0 1 SPC Option bytes security protection code 1 1 USER Store USER of option bytes block after system reset 2 8 DATA Store DATA[15:0] of option bytes block after system reset 10 16 WP WPR Erase/Program Protection register 0x20 0x20 read-only 0x00000000 WP Store WP[31:0] of option bytes block after system reset 0 32 KEY1 KEY1 Unlock key register 1 0x44 0x20 write-only 0x00000000 KEY FMC_CTL unlock register 0 32 04294967295 STAT1 STAT1 Status register 1 0x4C 0x20 0x00000000 ENDF End of operation flag bit 5 1 read-write ENDFRreadNoEventNo end of operation occurred0EventAn end of operation event occurred1 ENDFWwriteClearClears flag1 WPERR Erase/Program protection error flag bit 4 1 read-write WPERRRreadNoErrorThere was no error0ErrorThere was an error erasing/programming protected pages1 WPERRWwriteClearClears flag1 PGERR Program error flag bit 2 1 read-write PGERRRreadNoErrorThere was no error0ErrorThere was an error programming flash1 PGERRWwriteClearClears flag1 BUSY The flash is busy bit 0 1 read-only BUSYRreadInactiveNo operation is in progress0ActiveAn operation is in progress1 CTL1 CTL1 Control register 1 0x50 0x20 read-write 0x00000080 ENDIE End of operation interrupt enable bit 12 1 ENDIEread-writeDisabledEnd of operation interrupt disabled0EnabledEnd of operation interrupt enabled1 ERRIE Error interrupt enable bit 10 1 ERRIEread-writeDisabledError interrupt generation disabled0EnabledError interrupt generation enabled1 LK FMC_CTL0 lock bit 7 1 LKRreadUnlockedCTL register is unlocked0LockedCTL register is locked1 LKWwriteLockLock CTL register1 START Send erase command to FMC bit 6 1 STARTWwriteStartTrigger an erase operation1 MER Main flash mass erase for bank0 command bit 2 1 MERread-writeMassEraseErase activated for all user sectors1 PER Main flash page erase for bank0 command bit 1 1 PERread-writePageEraseErase activated for selected page1 PG Main flash program for bank0 command bit 0 1 PGread-writeProgramFlash programming activated1 ADDR1 ADDR1 Address register 1 0x54 0x20 write-only 0x00000000 ADDR Flash erase/program command address bits 0 32 04294967295 WSEN WSEN Wait state enable register 0xFC 0x20 read-write 0x00000000 WSEN FMC wait state enable register 0 1 WSENread-writeNoWaitStateNo wait state added0WaitStateWait state added1 PID PID Product ID register 0x100 0x20 read-only 0x00000000 PID Product reserved ID code register 0 32 04294967295 FWDGT free watchdog timer FWDGT 0x40003000 0x0 0x400 registers CTL CTL Control register 0x00 0x20 write-only 0x00000000 CMD Key value 0 16 CMDread-writeEnableEnable access to PR, RLR and WINR registers (0x5555)21845ResetReset the watchdog value (0xAAAA)43690StartStart the watchdog (0xCCCC)52428 PSC PSC Prescaler register 0x04 0x20 read-write 0x00000000 PSC Free watchdog timer prescaler selection 0 3 PSCread-writeDivideBy4Divider /40DivideBy8Divider /81DivideBy16Divider /162DivideBy32Divider /323DivideBy64Divider /644DivideBy128Divider /1285DivideBy256Divider /2566DivideBy256bisDivider /2567 RLD RLD Reload register 0x08 0x20 read-write 0x00000FFF RLD Free watchdog timer counter reload value 0 12 04095 STAT STAT Status register 0x0C 0x20 read-only 0x00000000 PUD Free watchdog timer prescaler value update 0 1 PUDread-writeValidThe value read from the PSC register is valid0OngoingA write operation to to the PSC register is ongoing, so the value read is invalid1 RUD Free watchdog timer counter reload value update 1 1 RUDread-writeValidThe value read from the RLD register is valid0OngoingA write operation to to the RLD register is ongoing, so the value read is invalid1 GPIOA General-purpose I/Os GPIO 0x40010800 0x0 0x400 registers CTL0 CTL0 port control register 0 0x0 0x20 read-write 0x44444444 CTL7 Port x configuration bits (x = 7) 30 2 MD7 Port x mode bits (x = 7) 28 2 CTL6 Port x configuration bits (x = 6) 26 2 MD6 Port x mode bits (x = 6) 24 2 CTL5 Port x configuration bits (x = 5) 22 2 MD5 Port x mode bits (x = 5) 20 2 CTL4 Port x configuration bits (x = 4) 18 2 MD4 Port x mode bits (x = 4) 16 2 CTL3 Port x configuration bits (x = 3) 14 2 MD3 Port x mode bits (x = 3 ) 12 2 CTL2 Port x configuration bits (x = 2) 10 2 MD2 Port x mode bits (x = 2 ) 8 2 CTL1 Port x configuration bits (x = 1) 6 2 MD1 Port x mode bits (x = 1) 4 2 CTL0 Port x configuration bits (x = 0) 2 2 CTL0read-writeAnalogOrPushPullAnalog mode/GPIO output with push-pull0FloatingOrOpenDrainFloating input/GPIO output with open-drain1InputOrAfioPPInput with pull-up pull-down/AFIO output with push-pull2RSVDOrAfioODReserved/AFIO output with open-drain3 MD0 Port x mode bits (x = 0) 0 2 MD0read-writeInputInput mode (reset state)0Speed10MOutput mode ,max speed 10MHz1Speed2MOutput mode ,max speed 2MHz2Speed50MOutput mode ,max speed 50MHz3 CTL1 CTL1 port control register 1 0x04 0x20 read-write 0x44444444 CTL15 Port x configuration bits (x = 15) 30 2 MD15 Port x mode bits (x = 15) 28 2 CTL14 Port x configuration bits (x = 14) 26 2 MD14 Port x mode bits (x = 14) 24 2 CTL13 Port x configuration bits (x = 13) 22 2 MD13 Port x mode bits (x = 13) 20 2 CTL12 Port x configuration bits (x = 12) 18 2 MD12 Port x mode bits (x = 12) 16 2 CTL11 Port x configuration bits (x = 11) 14 2 MD11 Port x mode bits (x = 11 ) 12 2 CTL10 Port x configuration bits (x = 10) 10 2 MD10 Port x mode bits (x = 10 ) 8 2 CTL9 Port x configuration bits (x = 9) 6 2 MD9 Port x mode bits (x = 9) 4 2 CTL8 Port x configuration bits (x = 8) 2 2 CTL8read-writeAnalogOrPushPullAnalog mode/GPIO output with push-pull0FloatingOrOpenDrainFloating input/GPIO output with open-drain1InputOrAfioPPInput with pull-up pull-down/AFIO output with push-pull2RSVDOrAfioODReserved/AFIO output with open-drain3 MD8 Port x mode bits (x = 8) 0 2 MD8read-writeInputInput mode (reset state)0Speed10MOutput mode ,max speed 10MHz1Speed2MOutput mode ,max speed 2MHz2Speed50MOutput mode ,max speed 50MHz3 ISTAT ISTAT Port input status register 0x08 0x20 read-only 0x00000000 ISTAT15 Port input status 15 1 ISTAT14 Port input status 14 1 ISTAT13 Port input status 13 1 ISTAT12 Port input status 12 1 ISTAT11 Port input status 11 1 ISTAT10 Port input status 10 1 ISTAT9 Port input status 9 1 ISTAT8 Port input status 8 1 ISTAT7 Port input status 7 1 ISTAT6 Port input status 6 1 ISTAT5 Port input status 5 1 ISTAT4 Port input status 4 1 ISTAT3 Port input status 3 1 ISTAT2 Port input status 2 1 ISTAT1 Port input status 1 1 ISTAT0 Port input status 0 1 ISTAT0read-writeLowInput is logic low0HighInput is logic high1 OCTL OCTL Port output control register 0x0C 0x20 read-write 0x00000000 OCTL15 Port output control 15 1 OCTL14 Port output control 14 1 OCTL13 Port output control 13 1 OCTL12 Port output control 12 1 OCTL11 Port output control 11 1 OCTL10 Port output control 10 1 OCTL9 Port output control 9 1 OCTL8 Port output control 8 1 OCTL7 Port output control 7 1 OCTL6 Port output control 6 1 OCTL5 Port output control 5 1 OCTL4 Port output control 4 1 OCTL3 Port output control 3 1 OCTL2 Port output control 2 1 OCTL1 Port output control 1 1 OCTL0 Port output control 0 1 OCTL0read-writeLowSet output to logic low0HighSet output to logic high1 BOP BOP Port bit operate register 0x10 0x20 write-only 0x00000000 CR15 Port 15 Clear bit 31 1 CR14 Port 14 Clear bit 30 1 CR13 Port 13 Clear bit 29 1 CR12 Port 12 Clear bit 28 1 CR11 Port 11 Clear bit 27 1 CR10 Port 10 Clear bit 26 1 CR9 Port 9 Clear bit 25 1 CR8 Port 8 Clear bit 24 1 CR7 Port 7 Clear bit 23 1 CR6 Port 6 Clear bit 22 1 CR5 Port 5 Clear bit 21 1 CR4 Port 4 Clear bit 20 1 CR3 Port 3 Clear bit 19 1 CR2 Port 2 Clear bit 18 1 CR1 Port 1 Clear bit 17 1 CR0 Port 0 Clear bit 16 1 CR0WwriteResetResets the corresponding OCTLx bit1 BOP15 Port 15 Set bit 15 1 BOP14 Port 14 Set bit 14 1 BOP13 Port 13 Set bit 13 1 BOP12 Port 12 Set bit 12 1 BOP11 Port 11 Set bit 11 1 BOP10 Port 10 Set bit 10 1 BOP9 Port 9 Set bit 9 1 BOP8 Port 8 Set bit 8 1 BOP7 Port 7 Set bit 7 1 BOP6 Port 6 Set bit 6 1 BOP5 Port 5 Set bit 5 1 BOP4 Port 4 Set bit 4 1 BOP3 Port 3 Set bit 3 1 BOP2 Port 2 Set bit 2 1 BOP1 Port 1 Set bit 1 1 BOP0 Port 0 Set bit 0 1 BOP0WwriteSetSets the corresponding OCTLx bit1 BC BC Port bit clear register 0x14 0x20 write-only 0x00000000 CR15 Port 15 Clear bit 15 1 CR14 Port 14 Clear bit 14 1 CR13 Port 13 Clear bit 13 1 CR12 Port 12 Clear bit 12 1 CR11 Port 11 Clear bit 11 1 CR10 Port 10 Clear bit 10 1 CR9 Port 9 Clear bit 9 1 CR8 Port 8 Clear bit 8 1 CR7 Port 7 Clear bit 7 1 CR6 Port 6 Clear bit 6 1 CR5 Port 5 Clear bit 5 1 CR4 Port 4 Clear bit 4 1 CR3 Port 3 Clear bit 3 1 CR2 Port 2 Clear bit 2 1 CR1 Port 1 Clear bit 1 1 CR0 Port 0 Clear bit 0 1 CR0WwriteResetResets the corresponding OCTLx bit1 LOCK LOCK GPIO port configuration lock register 0x18 0x20 read-write 0x00000000 LKK Lock sequence key 16 1 LKKread-writeNotActivePort configuration lock key not active0ActivePort configuration lock key active1 LK15 Port Lock bit 15 15 1 LK14 Port Lock bit 14 14 1 LK13 Port Lock bit 13 13 1 LK12 Port Lock bit 12 12 1 LK11 Port Lock bit 11 11 1 LK10 Port Lock bit 10 10 1 LK9 Port Lock bit 9 9 1 LK8 Port Lock bit 8 8 1 LK7 Port Lock bit 7 7 1 LK6 Port Lock bit 6 6 1 LK5 Port Lock bit 5 5 1 LK4 Port Lock bit 4 4 1 LK3 Port Lock bit 3 3 1 LK2 Port Lock bit 2 2 1 LK1 Port Lock bit 1 1 1 LK0 Port Lock bit 0 0 1 LK0read-writeUnlockedPort configuration not locked0LockedPort configuration locked1 SPD SPD Port bit speed register 0x3C 0x20 read-write 0x00000000 SPD15 Port 15 output max speed bits 15 1 SPD14 Port 14 output max speed bits 14 1 SPD13 Port 13 output max speed bits 13 1 SPD12 Port 12 output max speed bits 12 1 SPD11 Port 11 output max speed bits 11 1 SPD10 Port 10 output max speed bits 10 1 SPD9 Port 9 output max speed bits 9 1 SPD8 Port 8 output max speed bits 8 1 SPD7 Port 7 output max speed bits 7 1 SPD6 Port 6 output max speed bits 6 1 SPD5 Port 5 output max speed bits 5 1 SPD4 Port 4 output max speed bits 4 1 SPD3 Port 3 output max speed bits 3 1 SPD2 Port 2 output max speed bits 2 1 SPD1 Port 1 output max speed bits 1 1 SPD0 Port 0 output max speed bits 0 1 GPIOB 0x40010C00 GPIOC 0x40011000 GPIOD 0x40011400 GPIOE 0x40011800 GPIOF 0x40011C00 GPIOG 0x40012000 I2C0 Inter integrated circuit I2C 0x40005400 0x0 0x400 registers I2C0_EV 31 I2C0_ER 32 CTL0 CTL0 Control register 0 0x0 0x20 read-write 0x0000 SRESET Software reset 15 1 SRESETread-writeNotResetI2C peripheral not under reset0ResetI2C peripheral under reset1 SALT SMBus alert 13 1 SALTread-writeReleaseSMBA pin released high0DriveSMBA pin driven low1 PECTRANS PEC Transfer 12 1 PECTRANSread-writeDisabledNo PEC transfer0EnabledPEC transfer1 POAP Position of ACK and PEC when receiving 11 1 POAPread-writeCurrentACK bit controls the (N)ACK of the current byte being received0NextACK bit controls the (N)ACK of the next byte to be received1 ACKEN Whether or not to send an ACK 10 1 ACKENread-writeNAKNo acknowledge returned0ACKAcknowledge returned after a byte is received1 STOP Generate a STOP condition on I2C bus 9 1 STOPread-writeNoStopSTOP will not be sent0StopSTOP will be sent1 START Generate a START condition on I2C bus 8 1 STARTread-writeNoStartSTART will not be sent0StartSTART will be sent1 SS Whether to stretch SCL low when data is not ready in slave mode 7 1 SSread-writeEnabledClock stretching enabled0DisabledClock stretching disabled1 GCEN Whether or not to response to a General Call (0x00) 6 1 GCENread-writeNotRespondSlave won't respond to General Call0RespondSlave will respond to General Call1 PECEN PEC Calculation Switch 5 1 PECENread-writeDisabledPEC calculation disabled0EnabledPEC calculation enabled1 ARPEN ARP protocol in SMBus switch 4 1 ARPENread-writeDisabledARP disabled0EnabledARP enabled1 SMBSEL SMBusType Selection 3 1 SMBSELread-writeDeviceSMBus Device0HostSMBus Host1 SMBEN SMBus/I2C mode switch 1 1 SMBENread-writeI2CI2C Mode0SMBusSMBus1 I2CEN I2C peripheral enable 0 1 I2CENread-writeDisabledPeripheral disabled0EnabledPeripheral enabled1 CTL1 CTL1 Control register 1 0x04 0x20 read-write 0x0000 DMALST Flag indicating DMA last transfer 12 1 DMALSTread-writeNotLastNext DMA EOT is not the last transfer0LastNext DMA EOT is the last transfer1 DMAON DMA mode switch 11 1 DMAONread-writeDisabledDMA requests disabled0EnabledDMA requests enabled1 BUFIE Buffer interrupt enable 10 1 BUFIEread-writeDisabledTBE=1 or RBNE=1 does not generate any interrupt0EnabledTBE=1 or RBNE=1 generates Event interrupt1 EVIE Event interrupt enable 9 1 EVIEread-writeDisabledEvent interrupt disabled0EnabledEvent interrupt enabled1 ERRIE Error interrupt enable 8 1 ERRIEread-writeDisabledError interrupt disabled0EnabledError interrupt enabled1 I2CCLK I2C Peripheral clock frequency 0 7 272 SADDR0 SADDR0 Slave address register 0 0x08 0x20 read-write 0x0000 ADDFORMAT Address mode for the I2C slave 15 1 ADDFORMATread-writeAdd77-bit slave address (note that you'll need to shift the address by 1b)0Add1010-bit slave address1 ADDRESSBit 0 of a 10-bit address01001023 SADDR1 SADDR1 Slave address register 1 0x0C 0x20 read-write 0x0000 ADDRESS2 Second I2C address for the slave in Dual-Address mode 1 7 0127 DUADEN Dual-Address mode switch 0 1 DUADENread-writeSingleSingle addressing mode0DualDual addressing mode1 DATA DATA Transfer buffer register 0x10 0x20 read-write 0x0000 TRB Transmission or reception data buffer register 0 8 0255 STAT0 STAT0 Transfer status register 0 0x14 0x20 0x0000 SMBALT SMBus Alert status 15 1 read-write SMBALTread-writeNoAlertSMBA not pulled down or no alert occured0AlertSMBA pulled down or alert occurred1 SMBTO Timeout signal in SMBus mode 14 1 read-write SMBTOread-writeNoTimeoutNo Timeout error0TimeoutSCL remained low for 25 ms1 PECERR PEC error when receiving data 12 1 read-write PECERRread-writeNoErrorNo PEC error0ErrorPEC error1 OUERR Over-run or under-run situation occurs in slave mode 11 1 read-write OUERRread-writeNoOverrunNo overrun/underrun occured0OverrunOverrun/underrun occured1 AERR Acknowledge error 10 1 read-write AERRread-writeNoErrorNo acknowledge error0ErrorAcknowledge error1 LOSTARB Arbitration Lost in master mode 9 1 read-write LOSTARBread-writeNoLostNo Arbitration Lost detected0LostArbitration Lost detected1 BERR A bus error occurs indication a unexpected START or STOP condition on I2C bus 8 1 read-write BERRread-writeNoErrorNo misplaced Start or Stop condition0ErrorMisplaced Start or Stop condition1 TBE I2C_DATA is Empty during transmitting 7 1 read-only TBEread-writeNotEmptyData register not empty0EmptyData register empty, software can write1 RBNE I2C_DATA is not Empty during receiving 6 1 read-only RBNEread-writeEmptyData register empty0NotEmptyData register not empty, software can read1 STPDET STOP condition detected in slave mode 4 1 read-only STPDETread-writeNoStopNo Stop condition detected0StopStop condition detected1 ADD10SEND Header of 10-bit address is sent in master mode 3 1 read-only ADD10SENDread-writeNoHeaderNo header of 10-bit address is sent0HeaderHeader of 10-bit address is sent1 BTC Byte transmission completed 2 1 read-only BTCread-writeNotFinishedData byte transfer not done0FinishedData byte transfer successful1 ADDSEND Address is sent in master mode or received and matches in slave mode 1 1 read-only ADDSENDread-writeNotMatchAdress mismatched or not received0MatchReceived slave address matched with one of the enabled slave addresses1 SBSEND START condition sent out in master mode 0 1 read-only SBSENDread-writeNoStartNo Start condition0StartStart condition generated1 STAT1 STAT1 Transfer status register 1 0x18 0x20 read-only 0x0000 PECV Packet Error Checking Value that calculated by hardware when PEC is enabled 8 8 0127 DUMODF Dual Flag in slave mode 7 1 DUMODFread-writeSADDR0The address matches SADDR00SADDR1The address matches SADDR11 HSTSMB SMBus Host Header detected in slave mode 6 1 HSTSMBread-writeNoHeaderNo SMBus host header detected0HeaderSMBus host header detected1 DEFSMB Default address of SMBusDevice 5 1 DEFSMBread-writeNotReceivedDefault address has not been received0ReceivedDefault address has been received1 RXGC General call address (00h) received 4 1 RXGCread-writeNotReceivedNo general call address received0ReceivedGeneral call address received1 TR Whether the I2C is a transmitter or a receiver 2 1 TRread-writeReceiverReceiver0TransmitterTransmitter1 I2CBSY Busy flag 1 1 I2CBSYread-writeNotBusyNo I2C communication0BusyI2C communication active1 MASTER A flag indicating whether I2C block is in master or slave mode 0 1 MASTERread-writeSlaveSlave mode0MasterMaster mode1 CKCFG CKCFG Clock configure register 0x1C 0x20 read-write 0x0000 FAST I2C speed selection in master mode 15 1 FASTread-writeStandardStandard mode I2C0FastFast mode I2C1 DTCY Duty cycle in fast mode 14 1 DTCYread-writeDuty2Duty cycle t_low/t_high = 20Duty16_9Duty cycle t_low/t_high = 16/91 CLKC I2C Clock control in master mode 0 12 04095 RT RT Rise time register 0x20 0x20 read-write 0x0002 RISETIME Maximum rise time in master mode 0 7 0127 FMPCFG FMPCFG Fast-mode-plus configure register 0x90 0x20 read-write 0x0000 FMPEN Fast-mode-plus enable 0 1 I2C1 0x40005800 I2C1_EV 33 I2C1_ER 34 NVIC Nested Vectored Interrupt Controller NVIC 0xE000E100 0x0 0xF00 registers 0x33D 0xC3 reserved ISER ISER Interrupt Set Enable Register 0x0 0x20 read-write 0x00000000 SETENA SETENA 0 32 ICER ICER Interrupt Clear Enable Register 0x80 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ISPR ISPR Interrupt Set-Pending Register 0x100 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ICPR ICPR Interrupt Clear-Pending Register 0x180 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 IABR IABR Interrupt Active bit Register 0x200 0x20 read-write 0x00000000 IABR IABR 0 32 IPR0 IPR0 Interrupt Priority Register 0 0x300 0x08 read-write 0x00 PRI_00 PRI_00 0 8 IPR1 IPR1 Interrupt Priority Register 1 0x301 0x08 read-write 0x00 PRI_01 PRI_01 0 8 IPR2 IPR2 Interrupt Priority Register 2 0x302 0x08 read-write 0x00 PRI_02 PRI_02 0 8 IPR3 IPR3 Interrupt Priority Register 3 0x303 0x08 read-write 0x00 PRI_03 PRI_03 0 8 IPR4 IPR4 Interrupt Priority Register 4 0x304 0x08 read-write 0x00 PRI_04 PRI_04 0 8 IPR5 IPR5 Interrupt Priority Register 5 0x305 0x08 read-write 0x00 PRI_05 PRI_05 0 8 IPR6 IPR6 Interrupt Priority Register 6 0x306 0x08 read-write 0x00 PRI_06 PRI_06 0 8 IPR7 IPR7 Interrupt Priority Register 7 0x307 0x08 read-write 0x00 PRI_07 PRI_07 0 8 IPR8 IPR8 Interrupt Priority Register 8 0x308 0x08 read-write 0x00 PRI_08 PRI_08 0 8 IPR9 IPR9 Interrupt Priority Register 9 0x309 0x08 read-write 0x00 PRI_09 PRI_09 0 8 IPR10 IPR10 Interrupt Priority Register 10 0x30A 0x08 read-write 0x00 PRI_10 PRI_10 0 8 IPR11 IPR11 Interrupt Priority Register 11 0x30B 0x08 read-write 0x00 PRI_11 PRI_11 0 8 IPR12 IPR12 Interrupt Priority Register 12 0x30C 0x08 read-write 0x00 PRI_12 PRI_12 0 8 IPR13 IPR13 Interrupt Priority Register 13 0x30D 0x08 read-write 0x00 PRI_13 PRI_13 0 8 IPR14 IPR14 Interrupt Priority Register 14 0x30E 0x08 read-write 0x00 PRI_14 PRI_14 0 8 IPR15 IPR15 Interrupt Priority Register 15 0x30F 0x08 read-write 0x00 PRI_15 PRI_15 0 8 IPR16 IPR16 Interrupt Priority Register 16 0x310 0x08 read-write 0x00 PRI_16 PRI_16 0 8 IPR17 IPR17 Interrupt Priority Register 17 0x311 0x08 read-write 0x00 PRI_17 PRI_17 0 8 IPR18 IPR18 Interrupt Priority Register 18 0x312 0x08 read-write 0x00 PRI_18 PRI_18 0 8 IPR19 IPR19 Interrupt Priority Register 19 0x313 0x08 read-write 0x00 PRI_19 PRI_19 0 8 IPR20 IPR20 Interrupt Priority Register 20 0x314 0x08 read-write 0x00 PRI_20 PRI_20 0 8 IPR21 IPR21 Interrupt Priority Register 21 0x315 0x08 read-write 0x00 PRI_21 PRI_21 0 8 IPR22 IPR22 Interrupt Priority Register 22 0x316 0x08 read-write 0x00 PRI_22 PRI_22 0 8 IPR23 IPR23 Interrupt Priority Register 23 0x317 0x08 read-write 0x00 PRI_23 PRI_23 0 8 IPR24 IPR24 Interrupt Priority Register 24 0x318 0x08 read-write 0x00 PRI_24 PRI_24 0 8 IPR25 IPR25 Interrupt Priority Register 25 0x319 0x08 read-write 0x00 PRI_25 PRI_25 0 8 IPR26 IPR26 Interrupt Priority Register 26 0x31A 0x08 read-write 0x00 PRI_26 PRI_26 0 8 IPR27 IPR27 Interrupt Priority Register 27 0x31B 0x08 read-write 0x00 PRI_27 PRI_27 0 8 IPR28 IPR28 Interrupt Priority Register 28 0x31C 0x08 read-write 0x00 PRI_28 PRI_28 0 8 IPR29 IPR29 Interrupt Priority Register 29 0x31D 0x08 read-write 0x00 PRI_29 PRI_29 0 8 IPR30 IPR30 Interrupt Priority Register 30 0x31E 0x08 read-write 0x00 PRI_30 PRI_30 0 8 IPR31 IPR31 Interrupt Priority Register 31 0x31F 0x08 read-write 0x00 PRI_31 PRI_31 0 8 IPR32 IPR32 Interrupt Priority Register 32 0x320 0x08 read-write 0x00 PRI_32 PRI_32 0 8 IPR33 IPR33 Interrupt Priority Register 33 0x321 0x08 read-write 0x00 PRI_33 PRI_33 0 8 IPR34 IPR34 Interrupt Priority Register 34 0x322 0x08 read-write 0x00 PRI_34 PRI_34 0 8 IPR35 IPR35 Interrupt Priority Register 35 0x323 0x08 read-write 0x00 PRI_35 PRI_35 0 8 IPR36 IPR36 Interrupt Priority Register 36 0x324 0x08 read-write 0x00 PRI_36 PRI_36 0 8 IPR37 IPR37 Interrupt Priority Register 37 0x325 0x08 read-write 0x00 PRI_37 PRI_37 0 8 IPR38 IPR38 Interrupt Priority Register 38 0x326 0x08 read-write 0x00 PRI_38 PRI_38 0 8 IPR39 IPR39 Interrupt Priority Register 39 0x327 0x08 read-write 0x00 PRI_39 PRI_39 0 8 IPR40 IPR40 Interrupt Priority Register 40 0x328 0x08 read-write 0x00 PRI_40 PRI_40 0 8 IPR41 IPR41 Interrupt Priority Register 41 0x329 0x08 read-write 0x00 PRI_41 PRI_41 0 8 IPR42 IPR42 Interrupt Priority Register 42 0x32A 0x08 read-write 0x00 PRI_42 PRI_42 0 8 IPR43 IPR43 Interrupt Priority Register 43 0x32B 0x08 read-write 0x00 PRI_43 PRI_43 0 8 IPR44 IPR44 Interrupt Priority Register 44 0x32C 0x08 read-write 0x00 PRI_44 PRI_44 0 8 IPR45 IPR45 Interrupt Priority Register 45 0x32D 0x08 read-write 0x00 PRI_45 PRI_45 0 8 IPR46 IPR46 Interrupt Priority Register 46 0x32E 0x08 read-write 0x00 PRI_46 PRI_46 0 8 IPR47 IPR47 Interrupt Priority Register 47 0x32F 0x08 read-write 0x00 PRI_47 PRI_47 0 8 IPR48 IPR48 Interrupt Priority Register 48 0x330 0x08 read-write 0x00 PRI_48 PRI_48 0 8 IPR49 IPR49 Interrupt Priority Register 49 0x331 0x08 read-write 0x00 PRI_49 PRI_49 0 8 IPR50 IPR50 Interrupt Priority Register 50 0x332 0x08 read-write 0x00 PRI_50 PRI_50 0 8 IPR51 IPR51 Interrupt Priority Register 51 0x333 0x08 read-write 0x00 PRI_51 PRI_51 0 8 IPR52 IPR52 Interrupt Priority Register 52 0x334 0x08 read-write 0x00 PRI_52 PRI_52 0 8 IPR53 IPR53 Interrupt Priority Register 53 0x335 0x08 read-write 0x00 PRI_53 PRI_53 0 8 IPR54 IPR54 Interrupt Priority Register 54 0x336 0x08 read-write 0x00 PRI_54 PRI_54 0 8 IPR55 IPR55 Interrupt Priority Register 55 0x337 0x08 read-write 0x00 PRI_55 PRI_55 0 8 IPR56 IPR56 Interrupt Priority Register 56 0x338 0x08 read-write 0x00 PRI_56 PRI_56 0 8 IPR57 IPR57 Interrupt Priority Register 57 0x339 0x08 read-write 0x00 PRI_57 PRI_57 0 8 IPR58 IPR58 Interrupt Priority Register 58 0x33A 0x08 read-write 0x00 PRI_58 PRI_58 0 8 IPR59 IPR59 Interrupt Priority Register 59 0x33B 0x08 read-write 0x00 PRI_59 PRI_59 0 8 IPR60 IPR60 Interrupt Priority Register 60 0x33C 0x08 read-write 0x00 PRI_60 PRI_60 0 8 IPR61 IPR61 Interrupt Priority Register 61 0x33D 0x08 read-write 0x00 PRI_61 PRI_61 0 8 IPR62 IPR62 Interrupt Priority Register 62 0x33E 0x08 read-write 0x00 PRI_62 PRI_62 0 8 IPR63 IPR63 Interrupt Priority Register 63 0x33F 0x08 read-write 0x00 PRI_63 PRI_63 0 8 IPR64 IPR64 Interrupt Priority Register 64 0x340 0x08 read-write 0x00 PRI_64 PRI_64 0 8 IPR65 IPR65 Interrupt Priority Register 65 0x341 0x08 read-write 0x00 PRI_65 PRI_65 0 8 IPR66 IPR66 Interrupt Priority Register 66 0x342 0x08 read-write 0x00 PRI_66 PRI_66 0 8 IPR67 IPR67 Interrupt Priority Register 67 0x343 0x08 read-write 0x00 PRI_67 PRI_67 0 8 STIR STIR Software Trigger Interrupt Register 0xE00 0x20 write-only 0x00000000 STIR STIR 0 32 PMU Power management unit PMU 0x40007000 0x0 0x400 registers CTL CTL power control register 0x00 0x20 read-write 0x0000C000 LDEN Low-driver mode enable in Deep-sleep mode 18 2 HDS High-driver mode switch 17 1 HDEN High-driver mode enable 16 1 LDOVS LDO output voltage select 14 2 LDNP Low-driver mode when use normal power LDO 11 1 LDLP Low-driver mode when use low power LDO. 10 1 BKPWEN Backup Domain Write Enable 8 1 BKPWENread-writeDisabledAccess to backup domain registers disabled0EnabledAccess to backup domain registers enabled1 LVDT Low Voltage Detector Threshold 5 3 LVDTread-writeV2_22.2 V0V2_32.3 V1V2_42.4 V2V2_52.5 V3V2_62.6 V4V2_72.7 V5V2_82.8 V6V2_92.9 V7 LVDEN Low Voltage Detector Enable 4 1 LVDENread-writeDisabledLow voltage detector disabled0EnabledLow voltage detector enabled1 STBRST Standby Flag Reset 3 1 STBRSTWwriteClearClear the standby flag1 WURST Wakeup Flag Reset 2 1 WURSTWwriteClearClear the wakeup flag1 STBMOD Standby Mode 1 1 STBMODread-writeDeepSleepEnter Deep-sleep mode when the CPU enters deepsleep0StandbyEnter Standby mode when the CPU enters deepsleep1 LDOLP LDO Low Power Mode 0 1 LDOLPread-writeNormalLDO operates normally during Deepsleep mode0LowPowerLDO in low-power mode during Deepsleep mode1 CS CS power control/status register 0x04 0x20 0x00000000 LDRF Low-driver mode ready flag 18 2 read-write HDSRF High-driver switch ready flag 17 1 read-only HDRF High-driver ready flag 16 1 read-only LDOVSRF LDO voltage select ready flag 14 1 read-only WUPEN0 Enable WKUP pin 8 1 read-write WUPEN0read-writeDisabledWKUP pin 0 is used for general purpose I/Os. An event on the WKUP pin 0 does not wakeup the device from Standby mode0EnabledWKUP pin 0 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 0 wakes-up the system from Standby mode)1 LVDF Low Voltage Detector Status Flag 2 1 read-only LVDFRreadAboveThresholdVDD is higher than the LVD threshold0BelowThresholdVDD is lower than or equal to the LVD threshold1 STBF Standby flag 1 1 read-only STBFRreadNoStandbyEventDevice has not been in Standby mode0StandbyEventDevice has been in Standby mode1 WUF Wakeup flag 0 1 read-only WUFRreadNoWakeupEventNo wakeup event occurred0WakeupEventA wakeup event was received from the WKUP pin or from the RTC wakeup event (RTC Tamper event, RTC TimeStamp event or RTC alarm)1 RCU Reset and clock unit RCU 0x40021000 0x0 0x400 registers RCU_CTC 5 CTL0 CTL Control register 0x0 0x20 0x00000083 IRC8MEN Internal 8MHz RC oscillator Enable 0 1 read-write IRC8MSTB IRC8M Internal 8MHz RC Oscillator stabilization Flag 1 1 read-only IRC8MADJ Internal 8MHz RC Oscillator clock trim adjust value 3 5 read-write IRC8MCALIB Internal 8MHz RC Oscillator calibration value register 8 8 read-only HXTALEN External High Speed oscillator Enable 16 1 read-write HXTALSTB External crystal oscillator (HXTAL) clock stabilization flag 17 1 read-only HXTALBPS External crystal oscillator (HXTAL) clock bypass mode enable 18 1 read-write CKMEN HXTAL Clock Monitor Enable 19 1 read-write PLLEN PLL enable 24 1 read-write PLLSTB PLL Clock Stabilization Flag 25 1 read-only PLL1EN PLL1 enable 26 1 read-write PLL1STB PLL1 Clock Stabilization Flag 27 1 read-only PLL2EN PLL2 enable 28 1 read-write PLL2STB PLL2 Clock Stabilization Flag 29 1 read-only CFG0 CFG0 Clock configuration register 0 (RCU_CFG0) 0x04 0x20 0x00000000 SCS System clock switch 0 2 read-write SCSS System clock switch status 2 2 read-only AHBPSC AHB prescaler selection 4 4 read-write APB1PSC APB1 prescaler selection 8 3 read-write APB2PSC APB2 prescaler selection 11 3 read-write ADCPSC_1_0 ADC clock prescaler selection 14 2 read-write PLLSEL PLL Clock Source Selection 16 1 read-write PREDV0_LSB The LSB of PREDV0 division factor 17 1 read-write PLLMF_3_0 The PLL clock multiplication factor 18 4 read-write USBFSPSC_1_0 USBFS clock prescaler selection 22 2 read-write CKOUT0SEL CKOUT0 Clock Source Selection 24 4 read-write ADCPSC_2 Bit 2 of ADCPSC 28 1 read-write PLLMF_5_4 Bit 5 and Bit 4 of PLLMF 29 2 read-write USBFSPSC Bit 2 of USBFSPSC 31 1 read-write INT INT Clock interrupt register (RCU_INT) 0x08 0x20 0x00000000 IRC40KSTBIF IRC40K stabilization interrupt flag 0 1 read-only LXTALSTBIF LXTAL stabilization interrupt flag 1 1 read-only IRC8MSTBIF IRC8M stabilization interrupt flag 2 1 read-only HXTALSTBIF HXTAL stabilization interrupt flag 3 1 read-only PLLSTBIF PLL stabilization interrupt flag 4 1 read-only PLL1STBIF PLL1 stabilization interrupt flag 5 1 read-only PLL2STBIF PLL2 stabilization interrupt flag 6 1 read-only CKMIF HXTAL Clock Stuck Interrupt Flag 7 1 read-only IRC40KSTBIE IRC40K Stabilization interrupt enable 8 1 read-write LXTALSTBIE LXTAL Stabilization Interrupt Enable 9 1 read-write IRC8MSTBIE IRC8M Stabilization Interrupt Enable 10 1 read-write HXTALSTBIE HXTAL Stabilization Interrupt Enable 11 1 read-write PLLSTBIE PLL Stabilization Interrupt Enable 12 1 read-write PLL1STBIE PLL1 Stabilization Interrupt Enable 13 1 read-write PLL2STBIE PLL2 Stabilization Interrupt Enable 14 1 read-write IRC40KSTBIC IRC40K Stabilization Interrupt Clear 16 1 write-only LXTALSTBIC LXTAL Stabilization Interrupt Clear 17 1 write-only IRC8MSTBIC IRC8M Stabilization Interrupt Clear 18 1 write-only HXTALSTBIC HXTAL Stabilization Interrupt Clear 19 1 write-only PLLSTBIC PLL stabilization Interrupt Clear 20 1 write-only PLL1STBIC PLL1 stabilization Interrupt Clear 21 1 write-only PLL2STBIC PLL2 stabilization Interrupt Clear 22 1 write-only CKMIC HXTAL Clock Stuck Interrupt Clear 23 1 write-only APB2RST APB2RST APB2 reset register (RCU_APB2RST) 0x0C 0x20 read-write 0x00000000 AFRST Alternate function I/O reset 0 1 PARST GPIO port A reset 2 1 PBRST GPIO port B reset 3 1 PCRST GPIO port C reset 4 1 PDRST GPIO port D reset 5 1 PERST GPIO port E reset 6 1 PFRST GPIO portF reset 7 1 PGRST GPIO port G reset 8 1 ADC0RST ADC0 reset 9 1 ADC1RST ADC1 reset 10 1 TIMER0RST Timer 0 reset 11 1 SPI0RST SPI0 reset 12 1 TIMER7RST Timer 7 reset 13 1 USART0RST USART0 Reset 14 1 ADC2RST ADC2 reset 15 1 TIMER8RST Timer 8 reset 19 1 TIMER9RST Timer 9 reset 20 1 TIMER10RST Timer 10 reset 21 1 APB1RST APB1RST APB1 reset register (RCU_APB1RST) 0x10 0x20 read-write 0x00000000 TIMER1RST TIMER1 timer reset 0 1 TIMER2RST TIMER2 timer reset 1 1 TIMER3RST TIMER3 timer reset 2 1 TIMER4RST TIMER4 timer reset 3 1 TIMER5RST TIMER5 timer reset 4 1 TIMER6RST TIMER6 timer reset 5 1 TIMER11RST TIMER11 timer reset 6 1 TIMER12RST TIMER12 timer reset 7 1 TIMER13RST TIMER13 timer reset 8 1 WWDGTRST Window watchdog timer reset 11 1 SPI1RST SPI1 reset 14 1 SPI2RST SPI2 reset 15 1 USART1RST USART1 reset 17 1 USART2RST USART2 reset 18 1 UART3RST UART3 reset 19 1 UART4RST UART4 reset 20 1 I2C0RST I2C0 reset 21 1 I2C1RST I2C1 reset 22 1 CAN0RST CAN0 reset 25 1 CAN1RST CAN1 reset 26 1 BKPIRST Backup interface reset 27 1 PMURST Power control reset 28 1 DACRST DAC reset 29 1 AHBEN AHBEN AHB enable register 0x14 0x20 read-write 0x00000014 DMA0EN DMA0 clock enable 0 1 DMA1EN DMA1 clock enable 1 1 SRAMSPEN SRAM interface clock enable when sleep mode 2 1 FMCSPEN FMC clock enable when sleep mode 4 1 CRCEN CRC clock enable 6 1 EXMCEN EXMC clock enable 8 1 USBFSEN USBFS clock enable 12 1 ENETEN Ethernet clock enable 14 1 ENETTXEN Ethernet TX clock enable 15 1 ENETRXEN Ethernet RX clock enable 16 1 APB2EN APB2EN APB2 clock enable register (RCU_APB2EN) 0x18 0x20 read-write 0x00000000 AFEN Alternate function IO clock enable 0 1 PAEN GPIO port A clock enable 2 1 PBEN GPIO port B clock enable 3 1 PCEN GPIO port C clock enable 4 1 PDEN GPIO port D clock enable 5 1 PEEN GPIO port E clock enable 6 1 PFEN GPIO port F clock enable 7 1 PGEN GPIO port G clock enable 8 1 ADC0EN ADC0 clock enable 9 1 ADC1EN ADC1 clock enable 10 1 TIMER0EN TIMER0 clock enable 11 1 SPI0EN SPI0 clock enable 12 1 TIMER7EN TIMER7 clock enable 13 1 USART0EN USART0 clock enable 14 1 ADC2EN ADC2 clock enable 15 1 TIMER8EN TIMER8 clock enable 19 1 TIMER9EN TIMER9 clock enable 20 1 TIMER10EN TIMER10 clock enable 21 1 APB1EN APB1EN APB1 clock enable register (RCU_APB1EN) 0x1C 0x20 read-write 0x00000000 TIMER1EN TIMER1 timer clock enable 0 1 TIMER2EN TIMER2 timer clock enable 1 1 TIMER3EN TIMER3 timer clock enable 2 1 TIMER4EN TIMER4 timer clock enable 3 1 TIMER5EN TIMER5 timer clock enable 4 1 TIMER6EN TIMER6 timer clock enable 5 1 TIMER11EN TIMER11 timer clock enable 6 1 TIMER12EN TIMER12 timer clock enable 7 1 TIMER13EN TIMER13 timer clock enable 8 1 WWDGTEN Window watchdog timer clock enable 11 1 SPI1EN SPI1 clock enable 14 1 SPI2EN SPI2 clock enable 15 1 USART1EN USART1 clock enable 17 1 USART2EN USART2 clock enable 18 1 UART3EN UART3 clock enable 19 1 UART4EN UART4 clock enable 20 1 I2C0EN I2C0 clock enable 21 1 I2C1EN I2C1 clock enable 22 1 CAN0EN CAN0 clock enable 25 1 CAN1EN CAN1 clock enable 26 1 BKPIEN Backup interface clock enable 27 1 PMUEN Power control clock enable 28 1 DACEN DAC clock enable 29 1 BDCTL BDCTL Backup domain control register (RCU_BDCTL) 0x20 0x20 0x00000018 LXTALEN LXTAL enable 0 1 read-write LXTALSTB External low-speed oscillator stabilization 1 1 read-only LXTALBPS LXTAL bypass mode enable 2 1 read-write LXTALDRI LXTAL drive capability 3 2 read-write RTCSRC RTC clock entry selection 8 2 read-write RTCEN RTC clock enable 15 1 read-write BKPRST Backup domain reset 16 1 read-write RSTSCK RSTSCK Reset source /clock register (RCU_RSTSCK) 0x24 0x20 0x0C000000 IRC40KEN IRC40K enable 0 1 read-write IRC40KSTB IRC40K stabilization 1 1 read-only RSTFC Reset flag clear 24 1 read-write EPRSTF External PIN reset flag 26 1 read-only PORRSTF Power reset flag 27 1 read-only SWRSTF Software reset flag 28 1 read-only FWDGTRSTF Free Watchdog timer reset flag 29 1 read-only WWDGTRSTF Window watchdog timer reset flag 30 1 read-only LPRSTF Low-power reset flag 31 1 read-only AHBRST AHBRST AHB reset register 0x28 0x20 read-write 0x00000000 USBFSRST USBFS reset 12 1 ENETRST ENET reset 14 1 CFG1 CFG1 Clock Configuration register 1 0x2C 0x20 read-write 0x00000000 PREDV0 PREDV0 division factor 0 4 PREDV1 PREDV1 division factor 4 4 PLL1MF The PLL1 clock multiplication factor 8 4 PLL2MF The PLL2 clock multiplication factor 12 4 PREDV0SEL PREDV0 input Clock Source Selection 16 1 I2S1SEL I2S1 Clock Source Selection 17 1 I2S2SEL I2S2 Clock Source Selection 18 1 ADCPSC_3 Bit 4 of ADCPSC 29 1 PLLPRESEL PLL Clock Source Selection 30 1 PLL2MF_4 Bit 5 of PLL2MF 31 1 DSV DSV Deep sleep mode Voltage register 0x34 0x20 0x00000000 DSLPVS Deep-sleep mode voltage select 0 3 read-write ADDCTL ADDCTL Additional clock control register 0xC0 0x20 0x80000000 CK48MSEL 48MHz clock selection 0 1 read-write IRC48MEN Internal 48MHz RC oscillator enable 16 1 read-write IRC48MSTB Internal 48MHz RC oscillator clock stabilization Flag 17 1 read-only IRC48MCALIB Internal 48MHz RC oscillator calibration value register 24 8 read-only ADDINT ADDINT Additional clock interrupt register 0xCC 0x20 0x00000000 IRC48MSTBIF IRC48M stabilization interrupt flag 6 1 read-only IRC48MSTBIE Internal 48 MHz RC oscillator Stabilization Interrupt Enable 14 1 read-write IRC48MSTBIC Internal 48 MHz RC oscillator Stabilization Interrupt Clear 22 1 write-only ADDAPB1RST ADDAPB1RST APB1 additional reset register 0xE0 0x20 0x00000000 CTCRST CTC reset 27 1 read-write ADDAPB1EN ADDAPB1EN APB1 additional enable register 0xE4 0x20 0x00000000 CTCEN CTC clock enable 27 1 read-write RTC Real-time clock RTC 0x40002800 0x0 0x400 registers RTC 3 RTC_Alarm 41 INTEN INTEN RTC interrupt enable register 0x0 0x20 read-write 0x00000000 OVIE Overflow interrupt enable 2 1 ALRMIE Alarm interrupt enable 1 1 SCIE Second interrupt 0 1 CTL CTL control register 0x04 0x20 read-write 0x00000020 LWOFF Last write operation finished flag 5 1 CMF Configuration mode flag 4 1 RSYNF Registers synchronized flag 3 1 OVIF Overflow interrupt flag 2 1 ALRMIF Alarm interrupt flag 1 1 SCIF Sencond interrupt flag 0 1 PSCH PSCH RTC prescaler high register 0x08 0x20 0x00000000 PSC RTC prescaler value high 0 4 write-only PSCL PSCL RTC prescaler low register 0x0C 0x20 0x00008000 PSC RTC prescaler value low 0 16 write-only DIVH DIVH RTC divider high register 0x10 0x20 read-only 0x00000000 DIV RTC divider value high 0 4 DIVL DIVL RTC divider low register 0x14 0x20 read-only 0x00008000 DIV RTC divider value low 0 16 CNTH CNTH RTC counter high register 0x18 0x20 read-write 0x00000000 CNT RTC counter value high 0 16 CNTL CNTL RTC counter low register 0x1C 0x20 read-write 0x00000000 CNT RTC conuter value low 0 16 ALRMH ALRMH Alarm high register 0x20 0x20 write-only 0x0000FFFF ALRM Alarm value high 0 16 ALRML ALRML RTC alarm low register 0x24 0x20 write-only 0x0000FFFF ALRM alarm value low 0 16 SPI0 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI0 35 CTL0 CTL0 control register 0 0x0 0x20 read-write 0x0000 BDEN Bidirectional enable 15 1 BDENread-writeUnidirectional2-line unidirectional data mode selected0Bidirectional1-line bidirectional data mode selected1 BDOEN Bidirectional Transmit output enable 14 1 BDOENread-writeReceiveOnlyReceive-only mode0TransmitOnlyTransmit-only mode1 CRCEN CRC Calculation Enable 13 1 CRCENread-writeDisabledCRC calculation disabled0EnabledCRC calculation enabled1 CRCNT CRC Next Transfer 12 1 CRCNTread-writeDataNext transmit value is data from Tx buffer0CRCNext transmit value is CRC value from TCRC1 FF16 Data frame format 11 1 FF16read-writeEightBit8-bit data frame format is selected for transmission/reception0SixteenBit16-bit data frame format is selected for transmission/reception1 RO Receive only 10 1 ROread-writeFullDuplexFull duplex (Transmit and receive)0ReceiveOnlyOutput disabled (Receive-only mode)1 SWNSSEN NSS Software Mode Selection 9 1 SWNSSENread-writeHardwareSoftware slave management disabled0SoftwareSoftware slave management enabled1 SWNSS NSS Pin Selection In NSS Software Mode 8 1 SWNSSread-writeSlaveSelectedNSS is pulled low0SlaveNotSelectedNSS is pulled high1 LF LSB First Mode 7 1 LFread-writeMSBFirstData is transmitted/received with the MSB first0LSBFirstData is transmitted/received with the LSB first1 SPIEN SPI enable 6 1 SPIENread-writeDisabledPeripheral disabled0EnabledPeripheral enabled1 PSC Master Clock Prescaler Selection 3 3 PSCread-writeDiv2PCLK / 20Div4PCLK / 41Div8PCLK / 82Div16PCLK / 163Div32PCLK / 324Div64PCLK / 645Div128PCLK / 1286Div256PCLK / 2567 MSTMOD Master Mode Enable 2 1 MSTMODread-writeSlaveSlave configuration0MasterMaster configuration1 CKPL Clock polarity Selection 1 1 CKPLread-writeIdleLowCLK pulled low when idle0IdleHighCLK pulled high when idle1 CKPH Clock Phase Selection 0 1 CKPHread-writeFirstEdgeThe first clock transition is the first data capture edge0SecondEdgeThe second clock transition is the first data capture edge1 CTL1 CTL1 control register 1 0x04 0x20 read-write 0x0000 TBEIE Tx buffer empty interrupt enable 7 1 TBEIEread-writeDisabledTBE interrupt disabled0EnabledTBE interrupt enabled1 RBNEIE RX buffer not empty interrupt enable 6 1 RBNEIEread-writeDisabledRBNE interrupt disabled0EnabledRBNE interrupt enabled1 ERRIE Error interrupt enable 5 1 ERRIEread-writeDisabledError interrupt disabled0EnabledError interrupt enabled1 TMOD SPI TI Mode Enable 4 1 NSSP SPI NSS pulse mode Enable 3 1 NSSDRV Drive NSS Output 2 1 NSSDRVread-writeDisabledNSS output is disabled in master mode0EnabledNSS output is enabled in master mode1 DMATEN Transmit Buffer DMA Enable 1 1 DMATENread-writeDisabledTx buffer DMA disabled0EnabledTx buffer DMA enabled1 DMAREN Rx buffer DMA enable 0 1 DMARENread-writeDisabledRx buffer DMA disabled0EnabledRx buffer DMA enabled1 STAT STAT status register 0x08 0x20 0x0002 FERR Format Error 8 1 read-write TRANS Transmitting On-going Bit 7 1 read-only TRANSread-writeIdleSPI or I2S is idle0BusySPI or I2S is currently transmitting or receiving1 RXORERR Reception Overrun Error Bit 6 1 read-only RXORERRread-writeNoOverrunNo overrun occurred0OverrunOverrun occurred1 CONFERR SPI Configuration error 5 1 read-only CONFERRread-writeNoFaultNo configuration fault occurred0FaultConfiguration fault occurred1 CRCERR SPI CRC Error Bit 4 1 read-write CRCERRRreadMatchCRC value received matches the SPIx_RXCRCR value0NoMatchCRC value received does not match the SPIx_RXCRCR value1 CRCERRWwriteClearClear CRC error0 TXURERR Transmission underrun error bit 3 1 read-only TXURERRread-writeNoUnderrunNo underrun occurred0UnderrunUnderrun occurred1 I2SCH I2S channel side 2 1 read-only I2SCHread-writeLeftChannel left has to be transmitted or has been received0RightChannel right has to be transmitted or has been received1 TBE Transmit Buffer Empty 1 1 read-only TBEread-writeNotEmptyTx buffer not empty0EmptyTx buffer empty1 RBNE Receive Buffer Not Empty 0 1 read-only RBNEread-writeEmptyRx buffer empty0NotEmptyRx buffer not empty1 DATA DATA data register 0x0C 0x20 read-write 0x0000 DATA Data transfer register 0 16 065535 CRCPOLY CRCPOLY CRC polynomial register 0x10 0x20 read-write 0x0007 CRCPOLY CRC polynomial register 0 16 065535 RCRC RCRC RX CRC register 0x14 0x20 read-only 0x0000 RCRC RX CRC register 0 16 065535 TCRC TCRC TX CRC register 0x18 0x20 read-only 0x0000 TCRC Tx CRC register 0 16 065535 I2SCTL I2SCTL I2S control register 0x1C 0x20 read-write 0x0000 I2SSEL I2S mode selection 11 1 I2SSELread-writeSPIModeSPI mode is selected0I2SModeI2S mode is selected1 I2SEN I2S Enable 10 1 I2SENread-writeDisabledI2S peripheral is disabled0EnabledI2S peripheral is enabled1 I2SOPMOD I2S operation mode 8 2 I2SOPMODread-writeSlaveTxSlave - transmit0SlaveRxSlave - receive1MasterTxMaster - transmit2MasterRxMaster - receive3 PCMSMOD PCM frame synchronization mode 7 1 PCMSMODread-writeShortShort frame synchronisation0LongLong frame synchronisation1 I2SSTD I2S standard selection 4 2 I2SSTDread-writePhilipsI2S Philips standard0MSBMSB justified standard1LSBLSB justified standard2PCMPCM standard3 CKPL Idle state clock polarity 3 1 CKPLread-writeIdleLowI2S clock inactive state is low level0IdleHighI2S clock inactive state is high level1 DTLEN Data length 1 2 DTLENread-writeSixteenBit16-bit data length0TwentyFourBit24-bit data length1ThirtyTwoBit32-bit data length2 CHLEN Channel length (number of bits per audio channel) 0 1 CHLENread-writeSixteenBit16-bit wide0ThirtyTwoBit32-bit wide1 I2SPSC I2SPSC I2S prescaler register 0x20 0x20 read-write 0x0002 MCKOEN I2S_MCK output enable 9 1 MCKOENread-writeDisabledMaster clock output is disabled0EnabledMaster clock output is enabled1 OF Odd factor for the prescaler 8 1 OFread-writeEvenReal divider value is DIV * 20OddReal divider value is (DIV * 2) + 11 DIV Dividing factor for the prescaler 0 8 1255 QCTL QCTL Quad-SPI mode control register 0x80 0x20 read-write 0x0000 IO23_DRV Drive IO2 and IO3 enable 2 1 QRD Quad-SPI mode read select 1 1 QMOD Quad-SPI mode enable 0 1 SPI1 0x40003800 SPI1 36 SPI2 0x40003C00 SPI2 51 TIMER0 Advanced-timers TIMER 0x40012c00 0x0 0x400 registers TIMER0_BRK_TIMER8 24 TIMER0_UP_TIMER9 25 TIMER0_TRG_CMT_TIMER10 26 TIMER0_CC 27 CTL0 CTL0 control register 0 0x0 0x20 read-write 0x0000 CKDIV Clock division 8 2 ARSE Auto-reload shadow enable 7 1 CAM Counter aligns mode selection 5 2 DIR Direction 4 1 SPM Single pulse mode 3 1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 CTL1 CTL1 control register 1 0x04 0x20 read-write 0x0000 ISO3 Idle state of channel 3 output 14 1 ISO2N Idle state of channel 2 complementary output 13 1 ISO2 Idle state of channel 2 output 12 1 ISO1N Idle state of channel 1 complementary output 11 1 ISO1 Idle state of channel 1 output 10 1 ISO0N Idle state of channel 0 complementary output 9 1 ISO0 Idle state of channel 0 output 8 1 TI0S Channel 0 trigger input selection 7 1 MMC Master mode control 4 3 DMAS DMA request source selection 3 1 CCUC Commutation control shadow register update control 2 1 CCSE Commutation control shadow enable 0 1 SMCFG SMCFG slave mode configuration register 0x08 0x20 read-write 0x0000 ETP External trigger polarity 15 1 SMC1 Part of SMC for enable External clock mode1 14 1 ETPSC External trigger prescaler 12 2 ETFC External trigger filter control 8 4 MSM Master/Slave mode 7 1 TRGS Trigger selection 4 3 SMC Slave mode selection 0 3 DMAINTEN DMAINTEN DMA/Interrupt enable register 0x0C 0x20 read-write 0x0000 TRGDEN Trigger DMA request enable 14 1 CMTDEN Commutation DMA request enable 13 1 CH3DEN Channel 3 capture/compare DMA request enable 12 1 CH2DEN Channel 2 capture/compare DMA request enable 11 1 CH1DEN Channel 1 capture/compare DMA request enable 10 1 CH0DEN Channel 0 capture/compare DMA request enable 9 1 UPDEN Update DMA request enable 8 1 BRKIE Break interrupt enable 7 1 TRGIE Trigger interrupt enable 6 1 CMTIE commutation interrupt enable 5 1 CH3IE Channel 3 capture/compare interrupt enable 4 1 CH2IE Channel 2 capture/compare interrupt enable 3 1 CH1IE Channel 1 capture/compare interrupt enable 2 1 CH0IE Channel 0 capture/compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF Interrupt flag register 0x10 0x20 read-write 0x0000 CH3OF Channel 3 over capture flag 12 1 CH2OF Channel 2 over capture flag 11 1 CH1OF Channel 1 over capture flag 10 1 CH0OF Channel 0 over capture flag 9 1 BRKIF Break interrupt flag 7 1 TRGIF Trigger interrupt flag 6 1 CMTIF Channel commutation interrupt flag 5 1 CH3IF Channel 3 capture/compare interrupt flag 4 1 CH2IF Channel 2 capture/compare interrupt flag 3 1 CH1IF Channel 1 capture/compare interrupt flag 2 1 CH0IF Channel 0 capture/compare interrupt flag 1 1 UPIF Update interrupt flag 0 1 SWEVG SWEVG Software event generation register 0x14 0x20 write-only 0x0000 BRKG Break event generation 7 1 TRGG Trigger event generation 6 1 CMTG Channel commutation event generation 5 1 CH3G Channel 3 capture or compare event generation 4 1 CH2G Channel 2 capture or compare event generation 3 1 CH1G Channel 1 capture or compare event generation 2 1 CH0G Channel 0 capture or compare event generation 1 1 UPG Update event generation 0 1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x20 read-write 0x0000 CH1COMCEN Channel 1 output compare clear enable 15 1 CH1COMCTL Channel 1 compare output control 12 3 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1MS Channel 1 mode selection 8 2 CH0COMCEN Channel 0 output compare clear enable 7 1 CH0COMCTL Channel 0 compare output control 4 3 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0MS Channel 0 I/O mode selection 0 2 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 0x20 read-write 0x0000 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL1_Output CHCTL1_Output Channel control register 1 (output mode) 0x1C 0x20 read-write 0x0000 CH3COMCEN Channel 3 output compare clear enable 15 1 CH3COMCTL Channel 3 compare output control 12 3 CH3COMSEN Channel 3 output compare shadow enable 11 1 CH3COMFEN Channel 3 output compare fast enable 10 1 CH3MS Channel 3 mode selection 8 2 CH2COMCEN Channel 2 output compare clear enable 7 1 CH2COMCTL Channel 2 compare output control 4 3 CH2COMSEN Channel 2 compare output shadow enable 3 1 CH2COMFEN Channel 2 output compare fast enable 2 1 CH2MS Channel 2 I/O mode selection 0 2 CHCTL1_Input CHCTL1_Input Channel control register 1 (input mode) CHCTL1_Output 0x1C 0x20 read-write 0x0000 CH3CAPFLT Channel 3 input capture filter control 12 4 CH3CAPPSC Channel 3 input capture prescaler 10 2 CH3MS Channel 3 mode selection 8 2 CH2CAPFLT Channel 2 input capture filter control 4 4 CH2CAPPSC Channel 2 input capture prescaler 2 2 CH2MS Channel 2 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x20 read-write 0x0000 CH3P Channel 3 capture/compare function polarity 13 1 CH3EN Channel 3 capture/compare function enable 12 1 CH2NP Channel 2 complementary output polarity 11 1 CH2NEN Channel 2 complementary output enable 10 1 CH2P Channel 2 capture/compare function polarity 9 1 CH2EN Channel 2 capture/compare function enable 8 1 CH1NP Channel 1 complementary output polarity 7 1 CH1NEN Channel 1 complementary output enable 6 1 CH1P Channel 1 capture/compare function polarity 5 1 CH1EN Channel 1 capture/compare function enable 4 1 CH0NP Channel 0 complementary output polarity 3 1 CH0NEN Channel 0 complementary output enable 2 1 CH0P Channel 0 capture/compare function polarity 1 1 CH0EN Channel 0 capture/compare function enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x0000 CNT current counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value of the counter clock 0 16 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x0000 CAR Counter auto reload value 0 16 CREP CREP Counter repetition register 0x30 0x20 read-write 0x0000 CREP Counter repetition value 0 8 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x20 read-write 0x0000 CH0VAL Capture or compare value of channel0 0 16 CH1CV CH1CV Channel 1 capture/compare value register 0x38 0x20 read-write 0x0000 CH1VAL Capture or compare value of channel1 0 16 CH2CV CH2CV Channel 2 capture/compare value register 0x3C 0x20 read-write 0x0000 CH2VAL Capture or compare value of channel 2 0 16 CH3CV CH3CV Channel 3 capture/compare value register 0x40 0x20 read-write 0x0000 CH3VAL Capture or compare value of channel 3 0 16 CCHP CCHP channel complementary protection register 0x44 0x20 read-write 0x0000 POEN Primary output enable 15 1 OAEN Output automatic enable 14 1 BRKP Break polarity 13 1 BRKEN Break enable 12 1 ROS Run mode off-state configure 11 1 IOS Idle mode off-state configure 10 1 PROT Complementary register protect control 8 2 DTCFG Dead time configure 0 8 DMACFG DMACFG DMA configuration register 0x48 0x20 read-write 0x0000 DMATC DMA transfer count 8 5 DMATA DMA transfer access start address 0 5 DMATB DMATB DMA transfer buffer register 0x4C 0x20 read-write 0x0000 DMATB DMA transfer buffer 0 16 CFG CFG Configuration register 0xFC 0x20 read-write 0x0000 OUTSEL The output value selection 0 1 CHVSEL Write CHxVAL register selection 1 1 TIMER1 General-purpose-timers TIMER 0x40000000 0x0 0x400 registers TIMER1 28 CTL0 CTL0 control register 0 0x0 0x20 read-write 0x0000 CKDIV Clock division 8 2 ARSE Auto-reload shadow enable 7 1 CAM Counter aligns mode selection 5 2 DIR Direction 4 1 SPM Single pulse mode 3 1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 CTL1 CTL1 control register 1 0x04 0x20 read-write 0x0000 TI0S Channel 0 trigger input selection 7 1 MMC Master mode control 4 3 DMAS DMA request source selection 3 1 SMCFG SMCFG slave mode control register 0x08 0x20 read-write 0x0000 ETP External trigger polarity 15 1 SMC1 Part of SMC for enable External clock mode1 14 1 ETPSC External trigger prescaler 12 2 ETFC External trigger filter control 8 4 MSM Master-slave mode 7 1 TRGS Trigger selection 4 3 SMC Slave mode control 0 3 DMAINTEN DMAINTEN DMA/Interrupt enable register 0x0C 0x20 read-write 0x0000 TRGDEN Trigger DMA request enable 14 1 CH3DEN Channel 3 capture/compare DMA request enable 12 1 CH2DEN Channel 2 capture/compare DMA request enable 11 1 CH1DEN Channel 1 capture/compare DMA request enable 10 1 CH0DEN Channel 0 capture/compare DMA request enable 9 1 UPDEN Update DMA request enable 8 1 TRGIE Trigger interrupt enable 6 1 CH3IE Channel 3 capture/compare interrupt enable 4 1 CH2IE Channel 2 capture/compare interrupt enable 3 1 CH1IE Channel 1 capture/compare interrupt enable 2 1 CH0IE Channel 0 capture/compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 0x20 read-write 0x0000 CH3OF Channel 3 over capture flag 12 1 CH2OF Channel 2 over capture flag 11 1 CH1OF Channel 1 over capture flag 10 1 CH0OF Channel 0 over capture flag 9 1 TRGIF Trigger interrupt flag 6 1 CH3IF Channel 3 capture/compare interrupt enable 4 1 CH2IF Channel 2 capture/compare interrupt enable 3 1 CH1IF Channel 1 capture/compare interrupt flag 2 1 CH0IF Channel 0 capture/compare interrupt flag 1 1 UPIF Update interrupt flag 0 1 SWEVG SWEVG event generation register 0x14 0x20 write-only 0x0000 TRGG Trigger event generation 6 1 CH3G Channel 3 capture or compare event generation 4 1 CH2G Channel 2 capture or compare event generation 3 1 CH1G Channel 1 capture or compare event generation 2 1 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x20 read-write 0x0000 CH1COMCEN Channel 1 output compare clear enable 15 1 CH1COMCTL Channel 1 compare output control 12 3 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1MS Channel 1 mode selection 8 2 CH0COMCEN Channel 0 output compare clear enable 7 1 CH0COMCTL Channel 0 compare output control 4 3 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0MS Channel 0 I/O mode selection 0 2 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 0x20 read-write 0x00000000 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL1_Output CHCTL1_Output Channel control register 1 (output mode) 0x1C 0x20 read-write 0x0000 CH3COMCEN Channel 3 output compare clear enable 15 1 CH3COMCTL Channel 3 compare output control 12 3 CH3COMSEN Channel 3 output compare shadow enable 11 1 CH3COMFEN Channel 3 output compare fast enable 10 1 CH3MS Channel 3 mode selection 8 2 CH2COMCEN Channel 2 output compare clear enable 7 1 CH2COMCTL Channel 2 compare output control 4 3 CH2COMSEN Channel 2 compare output shadow enable 3 1 CH2COMFEN Channel 2 output compare fast enable 2 1 CH2MS Channel 2 I/O mode selection 0 2 CHCTL1_Input CHCTL1_Input Channel control register 1 (input mode) CHCTL1_Output 0x1C 0x20 read-write 0x0000 CH3CAPFLT Channel 3 input capture filter control 12 4 CH3CAPPSC Channel 3 input capture prescaler 10 2 CH3MS Channel 3 mode selection 8 2 CH2CAPFLT Channel 2 input capture filter control 4 4 CH2CAPPSC Channel 2 input capture prescaler 2 2 CH2MS Channel 2 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x20 read-write 0x0000 CH3P Channel 3 capture/compare function polarity 13 1 CH3EN Channel 3 capture/compare function enable 12 1 CH2NP Channel 2 complementary output polarity 11 1 CH2P Channel 2 capture/compare function polarity 9 1 CH2EN Channel 2 capture/compare function enable 8 1 CH1P Channel 1 capture/compare function polarity 5 1 CH1EN Channel 1 capture/compare function enable 4 1 CH0P Channel 0 capture/compare function polarity 1 1 CH0EN Channel 0 capture/compare function enable 0 1 CNT CNT Counter register 0x24 0x20 read-write 0x00000000 CNT counter value 0 32 PSC PSC Prescaler register 0x28 0x20 read-write 0x0000 PSC Prescaler value of the counter clock 0 16 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x0000 CAR Counter auto reload value 0 32 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x20 read-write 0x00000000 CH0VAL Capture or compare value of channel 0 0 16 CH1CV CH1CV Channel 1 capture/compare value register 0x38 0x20 read-write 0x00000000 CH1VAL Capture or compare value of channel1 0 16 CH2CV CH2CV Channel 2 capture/compare value register 0x3C 0x20 read-write 0x00000000 CH2VAL Capture or compare value of channel 2 0 16 CH3CV CH3CV Channel 3 capture/compare value register 0x40 0x20 read-write 0x00000000 CH3VAL Capture or compare value of channel 3 0 16 DMACFG DMACFG DMA configuration register 0x48 0x20 read-write 0x0000 DMATC DMA transfer count 8 5 DMATA DMA transfer access start address 0 5 DMATB DMATB DMA transfer buffer register 0x4C 0x20 read-write 0x0000 DMATB DMA transfer buffer 0 16 CFG CFG Configuration 0xFC 0x20 read-write 0x0000 CHVSEL Write CHxVAL register selection 1 1 TIMER2 TIMER 0x40000400 TIMER2 29 TIMER3 TIMER 0x40000800 TIMER3 30 TIMER4 TIMER 0x40000C00 TIMER4 50 TIMER5 Basic-timers TIMER 0x40001000 0x0 0x400 registers TIMER5 54 CTL0 CTL0 control register 0 0x0 0x20 read-write 0x0000 ARSE Auto-reload shadow enable 7 1 SPM Single pulse mode 3 1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 CTL1 CTL1 control register 1 0x04 0x20 read-write 0x0000 MMC Master mode control 4 3 DMAINTEN DMAINTEN DMA/Interrupt enable register 0x0C 0x20 read-write 0x0000 UPDEN Update DMA request enable 8 1 UPIE Update interrupt enable 0 1 INTF INTF Interrupt flag register 0x10 0x20 read-write 0x0000 UPIF Update interrupt flag 0 1 SWEVG SWEVG event generation register 0x14 0x20 write-only 0x0000 UPG Update generation 0 1 CNT CNT Counter register 0x24 0x20 read-write 0x00000000 CNT Low counter value 0 16 PSC PSC Prescaler register 0x28 0x20 read-write 0x0000 PSC Prescaler value of the counter clock 0 16 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x00000000 CAR Counter auto reload value 0 16 TIMER6 TIMER 0x40001400 TIMER6 55 TIMER7 TIMER 0x40013400 TIMER7_BRK_TIMER11 43 TIMER7_UP_TIMER12 44 TIMER7_TRG_CMT_TIMER13 45 TIMER7_CC 46 TIMER8 General-purpose-timers TIMER 0x40014c00 0x0 0x400 registers TIMER0_BRK_TIMER8 24 CTL0 CTL0 control register 0 0x0 0x20 read-write 0x0000 CKDIV Clock division 8 2 ARSE Auto-reload shadow enable 7 1 SPM Single pulse mode 3 1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 SMCFG SMCFG slave mode configuration register 0x08 0x20 read-write 0x0000 MSM Master-slave mode 7 1 TRGS Trigger selection 4 3 SMC Slave mode control 0 3 DMAINTEN DMAINTEN DMA and interrupt enable register 0x0C 0x20 read-write 0x0000 TRGIE Trigger interrupt enable 6 1 CH1IE Channel 1 capture/compare interrupt enable 2 1 CH0IE Channel 0 capture/compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 0x20 read-write 0x0000 CH1OF Channel 1 over capture flag 10 1 CH0OF Channel 0 over capture flag 9 1 TRGIF Trigger interrupt flag 6 1 CH1IF Channel 1 capture/compare interrupt flag 2 1 CH0IF Channel 0 capture/compare interrupt flag 1 1 UPIF Update interrupt flag 0 1 SWEVG SWEVG event generation register 0x14 0x20 write-only 0x0000 TRGG Trigger event generation 6 1 CH1G Channel 1 capture or compare event generation 2 1 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x20 read-write 0x00000000 CH1COMCTL Channel 1 compare output control 12 3 CH1COMSEN Channel 1 output compare shadow enable 11 1 CH1COMFEN Channel 1 output compare fast enable 10 1 CH1MS Channel 1 mode selection 8 2 CH0COMCTL Channel 0 compare output control 4 3 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0MS Channel 0 I/O mode selection 0 2 CHCTL0_Input CHCTL0_Input Channel control register 0 (input mode) CHCTL0_Output 0x18 0x20 read-write 0x00000000 CH1CAPFLT Channel 1 input capture filter control 12 4 CH1CAPPSC Channel 1 input capture prescaler 10 2 CH1MS Channel 1 mode selection 8 2 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x20 read-write 0x0000 CH1NP Channel 1 complementary output polarity 7 1 CH1P Channel 1 capture/compare function polarity 5 1 CH1EN Channel 1 capture/compare function enable 4 1 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare function polarity 1 1 CH0EN Channel 0 capture/compare function enable 0 1 CNT CNT Counter register 0x24 0x20 read-write 0x0000 CNT current counter value 0 16 PSC PSC Prescaler register 0x28 0x20 read-write 0x0000 PSC Prescaler value of the counter clock 0 16 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x00000000 CAR Counter auto reload value 0 16 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x20 read-write 0x00000000 CH0VAL Capture or compare value of channel0 0 16 CH1CV CH1CV Channel 1 capture/compare value register 0x38 0x20 read-write 0x00000000 CH1VAL Capture or compare value of channel1 0 16 CFG CFG configuration register 0xFC 0x20 read-write 0x0000 CHVSEL Write CHxVAL register selection 1 1 TIMER9 General-purpose-timers TIMER 0x40015000 0x0 0x400 registers TIMER0_UP_TIMER9 25 CTL0 CTL0 control register 1 0x00 0x20 read-write 0x0000 CKDIV Clock division 8 2 ARSE Auto-reload shadow enable 7 1 UPS Update source 2 1 UPDIS Update disable 1 1 CEN Counter enable 0 1 DMAINTEN DMAINTEN DMA/Interrupt enable register 0x0C 0x20 read-write 0x0000 CH0IE Channel 0 capture/compare interrupt enable 1 1 UPIE Update interrupt enable 0 1 INTF INTF interrupt flag register 0x10 0x20 read-write 0x0000 CH0OF Channel 0 over capture flag 9 1 CH0IF Channel 0 capture/compare interrupt flag 1 1 UPIF Update interrupt flag 0 1 SWEVG SWEVG event generation register 0x14 0x20 write-only 0x0000 CH0G Channel 0 capture or compare event generation 1 1 UPG Update generation 0 1 CHCTL0_Output CHCTL0_Output Channel control register 0 (output mode) 0x18 0x20 read-write 0x0000 CH0MS Channel 0 I/O mode selection 0 2 CH0COMFEN Channel 0 output compare fast enable 2 1 CH0COMSEN Channel 0 compare output shadow enable 3 1 CH0COMCTL Channel 0 compare output control 4 3 CHCTL0_Input CHCTL0_Input Channel control register 0 ( (input mode) CHCTL0_Output 0x18 0x20 read-write 0x0000 CH0CAPFLT Channel 0 input capture filter control 4 4 CH0CAPPSC Channel 0 input capture prescaler 2 2 CH0MS Channel 0 mode selection 0 2 CHCTL2 CHCTL2 Channel control register 2 0x20 0x20 read-write 0x0000 CH0NP Channel 0 complementary output polarity 3 1 CH0P Channel 0 capture/compare polarity 1 1 CH0EN Channel 0 capture/compare function enable 0 1 CNT CNT Counter register 0x24 0x20 read-write 0x0000 CNT current counter value 0 16 PSC PSC Prescaler register 0x28 0x20 read-write 0x0000 PSC Prescaler value of the counter clock 0 16 CAR CAR Counter auto reload register 0x2C 0x20 read-write 0x0000 CAR Counter auto reload value 0 16 CH0CV CH0CV Channel 0 capture/compare value register 0x34 0x20 read-write 0x0000 CH0VAL Capture or compare value of channel 0 0 16 IRMP IRMP channel input remap register 0x50 0x20 read-write 0x0000 ITI1_RMP Internal trigger input1 remap 10 2 CFG CFG configuration register 0xFC 0x20 read-write 0x0000 CHVSEL Write CHxVAL register selection 1 1 TIMER10 TIMER 0x40015400 TIMER0_TRG_CMT_TIMER10 26 TIMER11 TIMER 0x40001800 TIMER7_BRK_TIMER11 43 TIMER12 TIMER 0x40001C00 TIMER7_UP_TIMER12 44 TIMER13 TIMER 0x40002000 TIMER7_TRG_CMT_TIMER13 45 USART0 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART0 37 STAT0 STAT0 Status register 0 0x00 0x20 read-only 0x000000C0 CTSF CTS change flag 9 1 LBDF LIN break detection flag 8 1 TBE Transmit data buffer empty 7 1 TC Transmission complete 6 1 RBNE Read data buffer not empty 5 1 IDLEF IDLE frame detected flag 4 1 ORERR Overrun error 3 1 NERR Noise error flag 2 1 FERR Frame error flag 1 1 PERR Parity error flag 0 1 DATA DATA Data register 0x04 0x20 read-write 0x00000000 DATA Transmit or read data value 0 9 0255 BAUD BAUD Baud rate register 0x08 0x20 read-write 0x00000000 INTDIV Integer part of baud-rate divider 4 12 04095 FRADIV Fraction part of baud-rate divider 0 4 015 CTL0 CTL0 Control register 0 0x0C 0x20 read-write 0x00000000 UEN USART enable 13 1 UENread-writeDisabledUSART prescaler and outputs disabled0EnabledUSART prescaler and outputs enabled1 WL Word length 12 1 WLread-writeBit88 data bits0Bit99 data bits1 WM Wakeup method in mute mode 11 1 WMread-writeIdleIdle line0AddressAddress mask1 PCEN Parity check function enable 10 1 PCENread-writeDisabledParity control disabled0EnabledParity control enabled1 PM Parity mode 9 1 PMread-writeEvenEven parity0OddOdd parity1 PERRIE Parity error interrupt enable 8 1 PERRIEread-writeDisabledParity error interrupt is disabled0EnabledInterrupt is generated whenever PERR=1 in the STAT register1 TBEIE Transmitter buffer empty interrupt enable 7 1 TBEIEread-writeDisabledTransmission register empty interrupt is disabled0EnabledInterrupt is generated whenever TBE=1 in the STAT register1 TCIE Transmission complete interrupt enable 6 1 TCIEread-writeDisabledTransmission complete interrupt is disabled0EnabledInterrupt is generated whenever TC=1 in the STAT register1 RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable 5 1 RBNEIEread-writeDisabledRead data buffer not empty and overrrun error interrupts are disabled0EnabledInterrupt is generated whenever ORERR=1 or RBNE=1 in the STAT register1 IDLEIE IDLE line detected interrupt enable 4 1 IDLEIEread-writeDisabledIdle line detected interrupt is disabled0EnabledInterrupt is generated whenever IDLEF=1 in the STAT register1 TEN Transmitter enable 3 1 TENread-writeDisabledTransmitter is disabled0EnabledTransmitter is enabled1 REN Receiver enable 2 1 RENread-writeDisabledReceiver is disabled0EnabledReceiver is enabled1 RWU Receiver wakeup from mute mode 1 1 RWUread-writeDisabledReceiver wakeup from mute mode0Enabled Receiver in mute mode1 SBKCMD Send break command 0 1 SBKCMDread-writeDisabledDo not transmit a break frame0Enabled Do not transmit a break frame1 CTL1 CTL1 Control register 1 0x10 0x20 read-write 0x00000000 LMEN LIN mode enable 14 1 LMENread-writeDisabledLIN mode disabled0EnabledLIN mode enabled1 STB STOP bits length 12 2 STBread-writeStop11 stop bit0Stop0p50.5 stop bit1Stop22 stop bit2Stop1p51.5 stop bit3 CKEN CK pin enable 11 1 CKENread-writeDisabledCK pin disabled0EnabledCK pin enabled1 CPL Clock polarity 10 1 CPLread-writeNotInvertedSteady low value on CK pin outside tranmission window0InvertedSteady high value on CK pin outside tranmission window1 CPH Clock phase 9 1 CPHread-writeFirstThe first clock transition is the first data capture edge0SecondThe second clock transition is the first data capture edge1 CLEN CK Length 8 1 CLENread-writeNotOutputThe clock pulse of the last data bit is not output to the CK pin0OutputThe clock pulse of the last data bit is output to the CK pin1 LBDIE LIN break detection interrupt enable 6 1 LBDIEread-writeDisabledInterrupt is disabled0EnabledAn interrupt is generated whenever LBDF=1 in the STAT register1 LBLEN LIN break frame length 5 1 LBLENread-writeBit1010-bit break detection0Bit1111-bit break detection1 ADDR Address of the USART 0 4 ADDRread-writeBit44-bit address detection0FullFull-bit address detection1 CTL2 CTL2 Control register 2 0x14 0x20 read-write 0x00000000 CTSIE CTS interrupt enable 10 1 CTSIEread-writeDisabledInterrupt is disabled0EnabledAn interrupt is generated whenever CTS=1 in the STAT register1 CTSEN CTS enable 9 1 CTSENread-writeDisabledCTS hardware flow control disabled0EnabledCTS mode enabled, data is only transmitted when the CTS input is asserted1 RTSEN RTS enable 8 1 RTSENread-writeDisabledRTS hardware flow control disabled0EnabledRTS output enabled, data is only requested when there is space in the receive buffer1 DENT DMA request enable for transmission 7 1 DENTread-writeDisabledDMA mode is disabled for transmission0EnabledDMA mode is enabled for transmission1 DENR DMA request enable for reception 6 1 DENRread-writeDisabledDMA mode is disabled for reception0EnabledDMA mode is enabled for reception1 SCEN Smartcard mode enable 5 1 SCENread-writeDisabledSmartcard Mode disabled0EnabledSmartcard Mode enabled1 NKEN Smartcard NACK enable 4 1 NKENread-writeDisabledNACK transmission in case of parity error is disabled0EnabledNACK transmission during parity error is enabled1 HDEN Half-duplex selection 3 1 HDENread-writeNotSelectedHalf duplex mode is not selected0SelectedHalf duplex mode is selected1 IRLP IrDA low-power 2 1 IRLPread-writeNormalNormal mode0LowPowerLow-power mode1 IREN IrDA mode enable 1 1 IRENread-writeDisabledIrDA disabled0EnabledIrDA enabled1 ERRIE Error interrupt enable 0 1 ERRIEread-writeDisabledError interrupt is disabled0EnabledAn interrupt is generated when FERR=1 or ORERR=1 or NERR=1 in the STAT register1 GP GP Guard time and prescaler register 0x1C 0x20 read-write 0x00000000 GUAT Guard time value in Smartcard mode 8 8 0255 PSC Prescaler value 0 8 0255 CTL3 CTL3 Control register 3 0x80 0x20 read-write 0x00000000 MSBF Most significant bit first 11 1 DINV Data bit level inversion 10 1 TINV TX pin level inversion 9 1 RINV RX pin level inversion 8 1 EBIE Interrupt enable bit of end of block event 5 1 RTIE Interrupt enable bit of receive timeout event 4 1 SCRTNUM Smartcard auto-retry number 1 3 RTEN Receiver timeout enable 0 1 RT RT Receiver timeout register 0x84 0x20 read-write 0x00000000 BL Block Length 24 8 0255 RT Receiver timeout threshold 0 24 016777215 STAT1 STAT1 Status register 1 0x88 0x20 0x000000C0 BSY Busy flag 16 1 read-only EBF End of block flag 12 1 write-only RTF Receiver timeout flag 11 1 write-only USART1 0x40004400 USART1 38 USART2 0x40004800 USART2 39 UART3 Universal asynchronous receiver transmitter UART 0x40004C00 0x0 0x400 registers UART3 52 STAT0 STAT0 Status register 0 0x00 0x20 read-only 0x000000C0 CTSF CTS change flag 9 1 LBDF LIN break detection flag 8 1 TBE Transmit data buffer empty 7 1 TC Transmission complete 6 1 RBNE Read data buffer not empty 5 1 IDLEF IDLE frame detected flag 4 1 ORERR Overrun error 3 1 NERR Noise error flag 2 1 FERR Frame error flag 1 1 PERR Parity error flag 0 1 DATA DATA Data register 0x04 0x20 read-write 0x00000000 DATA Transmit or read data value 0 9 BAUD BAUD Baud rate register 0x08 0x20 read-write 0x00000000 INTDIV Integer part of baud-rate divider 4 12 FRADIV Fraction part of baud-rate divider 0 4 CTL0 CTL0 Control register 0 0x0C 0x20 read-write 0x00000000 UEN USART enable 13 1 WL Word length 12 1 WM Wakeup method in mute mode 11 1 PCEN Parity check function enable 10 1 PM Parity mode 9 1 PERRIE Parity error interrupt enable 8 1 TBEIE Transmitter buffer empty interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RBNEIE Read data buffer not empty interrupt and overrun error interrupt enable 5 1 IDLEIE IDLE line detected interrupt enable 4 1 TEN Transmitter enable 3 1 REN Receiver enable 2 1 RWU Receiver wakeup from mute mode 1 1 SBKCMD Send break command 0 1 CTL1 CTL1 Control register 1 0x10 0x20 read-write 0x00000000 LMEN LIN mode enable 14 1 STB STOP bits length 12 2 CKEN CK pin enable 11 1 CPL Clock polarity 10 1 CPH Clock phase 9 1 CLEN CK Length 8 1 LBDIE LIN break detection interrupt enable 6 1 LBLEN LIN break frame length 5 1 ADDR Address of the USART 0 4 CTL2 CTL2 Control register 2 0x14 0x20 read-write 0x00000000 OSB One sample bit method enable 11 1 CTSIE CTS interrupt enable 10 1 CTSEN CTS enable 9 1 RTSEN RTS enable 8 1 DENT DMA request enable for transmission 7 1 DENR DMA request enable for reception 6 1 SCEN Smartcard mode enable 5 1 NKEN Smartcard NACK enable 4 1 HDEN Half-duplex selection 3 1 IRLP IrDA low-power 2 1 IREN IrDA mode enable 1 1 ERRIE Error interrupt enable 0 1 GP GP Guard time and prescaler register 0x1C 0x20 read-write 0x00000000 GUAT Guard time value in Smartcard mode 8 8 PSC Prescaler value 0 8 UART4 0x40005000 UART4 53 USBFS_GLOBAL USB full speed global registers USBFS 0x50000000 0x0 0x400 registers USBFS_WKUP 42 USBFS 67 GOTGCS GOTGCS Global OTG control and status register (USBFS_GOTGCS) 0x0 0x20 0x00000800 SRPS SRP success 0 1 read-only SRPREQ SRP request 1 1 read-write HNPS Host success 8 1 read-only HNPREQ HNP request 9 1 read-write HHNPEN Host HNP enable 10 1 read-write DHNPEN Device HNP enabled 11 1 read-write IDPS ID pin status 16 1 read-only DI Debounce interval 17 1 read-only ASV A-session valid 18 1 read-only BSV B-session valid 19 1 read-only GOTGINTF GOTGINTF Global OTG interrupt flag register (USBFS_GOTGINTF) 0x04 0x20 read-write 0x00000000 SESEND Session end 2 1 SRPEND Session request success status change 8 1 HNPEND HNP end 9 1 HNPDET Host negotiation request detected 17 1 ADTO A-device timeout 18 1 DF Debounce finish 19 1 GAHBCS GAHBCS Global AHB control and status register (USBFS_GAHBCS) 0x08 0x20 read-write 0x00000000 GINTEN Global interrupt enable 0 1 TXFTH Tx FIFO threshold 7 1 PTXFTH Periodic Tx FIFO threshold 8 1 GUSBCS GUSBCS Global USB control and status register (OTG_FS_GUSBCSR) 0x0C 0x20 0x00000A80 TOC Timeout calibration 0 3 read-write SRPCEN SRP capability enable 8 1 read-write HNPCEN HNP capability enable 9 1 read-write UTT USB turnaround time 10 4 read-write FHM Force host mode 29 1 read-write FDM Force device mode 30 1 read-write GRSTCTL GRSTCTL Global reset control register (USBFS_GRSTCTL) 0x10 0x20 0x80000000 CSRST Core soft reset 0 1 read-write HCSRST HCLK soft reset 1 1 read-write HFCRST Host frame counter reset 2 1 read-write RXFF RxFIFO flush 4 1 read-write TXFF TxFIFO flush 5 1 read-write TXFNUM TxFIFO number 6 5 read-write GINTF GINTF Global interrupt flag register (USBFS_GINTF) 0x14 0x20 0x04000021 COPM Current operation mode 0 1 read-only MFIF Mode fault interrupt flag 1 1 read-write OTGIF OTG interrupt flag 2 1 read-only SOF Start of frame 3 1 read-write RXFNEIF RxFIFO non-empty interrupt flag 4 1 read-only NPTXFEIF Non-periodic TxFIFO empty interrupt flag 5 1 read-only GNPINAK Global Non-Periodic IN NAK effective 6 1 read-only GONAK Global OUT NAK effective 7 1 read-only ESP Early suspend 10 1 read-write SP USB suspend 11 1 read-write RST USB reset 12 1 read-write ENUMF Enumeration finished 13 1 read-write ISOOPDIF Isochronous OUT packet dropped interrupt 14 1 read-write EOPFIF End of periodic frame interrupt flag 15 1 read-write IEPIF IN endpoint interrupt flag 18 1 read-only OEPIF OUT endpoint interrupt flag 19 1 read-only ISOINCIF Isochronous IN transfer Not Complete Interrupt Flag 20 1 read-write PXNCIF_ISOONCIF periodic transfer not complete interrupt flag(Host mode)/isochronous OUT transfer not complete interrupt flag(Device mode) 21 1 read-write HPIF Host port interrupt flag 24 1 read-only HCIF Host channels interrupt flag 25 1 read-only PTXFEIF Periodic TxFIFO empty interrupt flag 26 1 read-only IDPSC ID pin status change 28 1 read-write DISCIF Disconnect interrupt flag 29 1 read-write SESIF Session interrupt flag 30 1 read-write WKUPIF Wakeup interrupt flag 31 1 read-write GINTEN GINTEN Global interrupt enable register (USBFS_GINTEN) 0x18 0x20 0x00000000 MFIE Mode fault interrupt enable 1 1 read-write OTGIE OTG interrupt enable 2 1 read-write SOFIE Start of frame interrupt enable 3 1 read-write RXFNEIE Receive FIFO non-empty interrupt enable 4 1 read-write NPTXFEIE Non-periodic TxFIFO empty interrupt enable 5 1 read-write GNPINAKIE Global non-periodic IN NAK effective interrupt enable 6 1 read-write GONAKIE Global OUT NAK effective interrupt enable 7 1 read-write ESPIE Early suspend interrupt enable 10 1 read-write SPIE USB suspend interrupt enable 11 1 read-write RSTIE USB reset interrupt enable 12 1 read-write ENUMFIE Enumeration finish interrupt enable 13 1 read-write ISOOPDIE Isochronous OUT packet dropped interrupt enable 14 1 read-write EOPFIE End of periodic frame interrupt enable 15 1 read-write IEPIE IN endpoints interrupt enable 18 1 read-write OEPIE OUT endpoints interrupt enable 19 1 read-write ISOINCIE isochronous IN transfer not complete interrupt enable 20 1 read-write PXNCIE_ISOONCIE periodic transfer not compelete Interrupt enable(Host mode)/isochronous OUT transfer not complete interrupt enable(Device mode) 21 1 read-write HPIE Host port interrupt enable 24 1 read-only HCIE Host channels interrupt enable 25 1 read-write PTXFEIE Periodic TxFIFO empty interrupt enable 26 1 read-write IDPSCIE ID pin status change interrupt enable 28 1 read-write DISCIE Disconnect interrupt enable 29 1 read-write SESIE Session interrupt enable 30 1 read-write WKUPIE Wakeup interrupt enable 31 1 read-write GRSTATR_Device GRSTATR_Device Global Receive status read(Device mode) 0x1C 0x20 read-only 0x00000000 EPNUM Endpoint number 0 4 BCOUNT Byte count 4 11 DPID Data PID 15 2 RPCKST Recieve packet status 17 4 GRSTATR_Host GRSTATR_Host Global Receive status read(Host mode) GRSTATR_Device 0x1C 0x20 read-only 0x00000000 CNUM Channel number 0 4 BCOUNT Byte count 4 11 DPID Data PID 15 2 RPCKST Reivece packet status 17 4 GRSTATP_Device GRSTATP_Device Global Receive status pop(Device mode) 0x20 0x20 read-only 0x00000000 EPNUM Endpoint number 0 4 BCOUNT Byte count 4 11 DPID Data PID 15 2 RPCKST Recieve packet status 17 4 GRSTATP_Host GRSTATP_Host Global Receive status pop(Host mode) GRSTATP_Device 0x20 0x20 read-only 0x00000000 CNUM Channel number 0 4 BCOUNT Byte count 4 11 DPID Data PID 15 2 RPCKST Reivece packet status 17 4 GRFLEN GRFLEN Global Receive FIFO size register (USBFS_GRFLEN) 0x24 0x20 read-write 0x00000200 RXFD Rx FIFO depth 0 16 HNPTFLEN HNPTFLEN Host non-periodic transmit FIFO length register (Host mode) 0x28 0x20 read-write 0x02000200 HNPTXRSAR host non-periodic transmit Tx RAM start address 0 16 HNPTXFD host non-periodic TxFIFO depth 16 16 DIEP0TFLEN DIEP0TFLEN Device IN endpoint 0 transmit FIFO length (Device mode) HNPTFLEN 0x28 0x20 read-write 0x02000200 IEP0TXFD in endpoint 0 Tx FIFO depth 0 16 IEP0TXRSAR in endpoint 0 Tx RAM start address 16 16 HNPTFQSTAT HNPTFQSTAT Host non-periodic transmit FIFO/queue status register (HNPTFQSTAT) 0x2C 0x20 read-only 0x00080200 NPTXFS Non-periodic TxFIFO space 0 16 NPTXRQS Non-periodic transmit request queue space 16 8 NPTXRQTOP Top of the non-periodic transmit request queue 24 7 GCCFG GCCFG Global core configuration register (USBFS_GCCFG) 0x38 0x20 read-write 0x00000000 PWRON Power on 16 1 VBUSACEN The VBUS A-device Comparer enable 18 1 VBUSBCEN The VBUS B-device Comparer enable 19 1 SOFOEN SOF output enable 20 1 VBUSIG VBUS ignored 21 1 CID CID core ID register 0x3C 0x20 read-write 0x00001000 CID Core ID 0 32 HPTFLEN HPTFLEN Host periodic transmit FIFO length register (HPTFLEN) 0x100 0x20 read-write 0x02000600 HPTXFSAR Host periodic TxFIFO start address 0 16 HPTXFD Host periodic TxFIFO depth 16 16 DIEP1TFLEN DIEP1TFLEN device IN endpoint transmit FIFO size register (DIEP1TFLEN) 0x104 0x20 read-write 0x02000400 IEPTXRSAR IN endpoint FIFO transmit RAM start address 0 16 IEPTXFD IN endpoint TxFIFO depth 16 16 DIEP2TFLEN DIEP2TFLEN device IN endpoint transmit FIFO size register (DIEP2TFLEN) 0x108 0x20 read-write 0x02000400 IEPTXRSAR IN endpoint FIFO transmit RAM start address 0 16 IEPTXFD IN endpoint TxFIFO depth 16 16 DIEP3TFLEN DIEP3TFLEN device IN endpoint transmit FIFO size register (FS_DIEP3TXFLEN) 0x10C 0x20 read-write 0x02000400 IEPTXRSAR IN endpoint FIFO4 transmit RAM start address 0 16 IEPTXFD IN endpoint TxFIFO depth 16 16 USBFS_HOST USB on the go full speed host USBFS 0x50000400 0x0 0x400 registers HCTL HCTL host configuration register (HCTL) 0x00 0x20 0x00000000 CLKSEL clock select for USB clock 0 2 read-write HFT HFT Host frame interval register 0x04 0x20 read-write 0x0000BB80 FRI Frame interval 0 16 HFINFR HFINFR OTG_FS host frame number/frame time remaining register (HFINFR) 0x08 0x20 read-only 0xBB800000 FRNUM Frame number 0 16 FRT Frame remaining time 16 16 HPTFQSTAT HPTFQSTAT Host periodic transmit FIFO/queue status register (HPTFQSTAT) 0x10 0x20 0x00080200 PTXFS Periodic transmit data FIFO space available 0 16 read-only PTXREQS Periodic transmit request queue space available 16 8 read-only PTXREQT Top of the periodic transmit request queue 24 8 read-only HACHINT HACHINT Host all channels interrupt register 0x14 0x20 read-only 0x00000000 HACHINT Host all channel interrupts 0 8 HACHINTEN HACHINTEN host all channels interrupt mask register 0x18 0x20 read-write 0x00000000 CINTEN Channel interrupt enable 0 8 HPCS HPCS Host port control and status register (USBFS_HPCS) 0x40 0x20 0x00000000 PCST Port connect status 0 1 read-only PCD Port connect detected 1 1 read-write PE Port enable 2 1 read-write PEDC Port enable/disable change 3 1 read-write PREM Port resume 6 1 read-write PSP Port suspend 7 1 read-write PRST Port reset 8 1 read-write PLST Port line status 10 2 read-only PP Port power 12 1 read-write PS Port speed 17 2 read-only HCH0CTL HCH0CTL host channel-0 characteristics register (HCH0CTL) 0x100 0x20 read-write 0x00000000 MPL Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSD Low-speed device 17 1 EPTYPE Endpoint type 18 2 DAR Device address 22 7 ODDFRM Odd frame 29 1 CDIS Channel disable 30 1 CEN Channel enable 31 1 HCH1CTL HCH1CTL host channel-1 characteristics register (HCH1CTL) 0x120 0x20 read-write 0x00000000 MPL Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSD Low-speed device 17 1 EPTYPE Endpoint type 18 2 DAR Device address 22 7 ODDFRM Odd frame 29 1 CDIS Channel disable 30 1 CEN Channel enable 31 1 HCH2CTL HCH2CTL host channel-2 characteristics register (HCH2CTL) 0x140 0x20 read-write 0x00000000 MPL Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSD Low-speed device 17 1 EPTYPE Endpoint type 18 2 DAR Device address 22 7 ODDFRM Odd frame 29 1 CDIS Channel disable 30 1 CEN Channel enable 31 1 HCH3CTL HCH3CTL host channel-3 characteristics register (HCH3CTL) 0x160 0x20 read-write 0x00000000 MPL Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSD Low-speed device 17 1 EPTYPE Endpoint type 18 2 DAR Device address 22 7 ODDFRM Odd frame 29 1 CDIS Channel disable 30 1 CEN Channel enable 31 1 HCH4CTL HCH4CTL host channel-4 characteristics register (HCH4CTL) 0x180 0x20 read-write 0x00000000 MPL Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSD Low-speed device 17 1 EPTYPE Endpoint type 18 2 DAR Device address 22 7 ODDFRM Odd frame 29 1 CDIS Channel disable 30 1 CEN Channel enable 31 1 HCH5CTL HCH5CTL host channel-5 characteristics register (HCH5CTL) 0x1A0 0x20 read-write 0x00000000 MPL Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSD Low-speed device 17 1 EPTYPE Endpoint type 18 2 DAR Device address 22 7 ODDFRM Odd frame 29 1 CDIS Channel disable 30 1 CEN Channel enable 31 1 HCH6CTL HCH6CTL host channel-6 characteristics register (HCH6CTL) 0x1C0 0x20 read-write 0x00000000 MPL Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSD Low-speed device 17 1 EPTYPE Endpoint type 18 2 DAR Device address 22 7 ODDFRM Odd frame 29 1 CDIS Channel disable 30 1 CEN Channel enable 31 1 HCH7CTL HCH7CTL host channel-7 characteristics register (HCH7CTL) 0x1E0 0x20 read-write 0x00000000 MPL Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSD Low-speed device 17 1 EPTYPE Endpoint type 18 2 DAR Device address 22 7 ODDFRM Odd frame 29 1 CDIS Channel disable 30 1 CEN Channel enable 31 1 HCH0INTF HCH0INTF host channel-0 interrupt register (USBFS_HCHxINTF) 0x108 0x20 read-write 0x00000000 TF Transfer finished 0 1 CH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 USBER USB bus error 7 1 BBER Babble error 8 1 REQOVR Request queue overrun 9 1 DTER Data toggle error 10 1 HCH1INTF HCH1INTF host channel-1 interrupt register (HCH1INTF) 0x128 0x20 read-write 0x00000000 TF Transfer finished 0 1 CH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 USBER USB bus error 7 1 BBER Babble error 8 1 REQOVR Request queue overrun 9 1 DTER Data toggle error 10 1 HCH2INTF HCH2INTF host channel-2 interrupt register (HCH2INTF) 0x148 0x20 read-write 0x00000000 TF Transfer finished 0 1 CH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 USBER USB bus error 7 1 BBER Babble error 8 1 REQOVR Request queue overrun 9 1 DTER Data toggle error 10 1 HCH3INTF HCH3INTF host channel-3 interrupt register (HCH3INTF) 0x168 0x20 read-write 0x00000000 TF Transfer finished 0 1 CH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 USBER USB bus error 7 1 BBER Babble error 8 1 REQOVR Request queue overrun 9 1 DTER Data toggle error 10 1 HCH4INTF HCH4INTF host channel-4 interrupt register (HCH4INTF) 0x188 0x20 read-write 0x00000000 TF Transfer finished 0 1 CH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 USBER USB bus error 7 1 BBER Babble error 8 1 REQOVR Request queue overrun 9 1 DTER Data toggle error 10 1 HCH5INTF HCH5INTF host channel-5 interrupt register (HCH5INTF) 0x1A8 0x20 read-write 0x00000000 TF Transfer finished 0 1 CH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 USBER USB bus error 7 1 BBER Babble error 8 1 REQOVR Request queue overrun 9 1 DTER Data toggle error 10 1 HCH6INTF HCH6INTF host channel-6 interrupt register (HCH6INTF) 0x1C8 0x20 read-write 0x00000000 TF Transfer finished 0 1 CH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 USBER USB bus error 7 1 BBER Babble error 8 1 REQOVR Request queue overrun 9 1 DTER Data toggle error 10 1 HCH7INTF HCH7INTF host channel-7 interrupt register (HCH7INTF) 0x1E8 0x20 read-write 0x00000000 TF Transfer finished 0 1 CH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 USBER USB bus error 7 1 BBER Babble error 8 1 REQOVR Request queue overrun 9 1 DTER Data toggle error 10 1 HCH0INTEN HCH0INTEN host channel-0 interrupt enable register (HCH0INTEN) 0x10C 0x20 read-write 0x00000000 TFIE Transfer completed interrupt enable 0 1 CHIE Channel halted interrupt enable 1 1 STALLIE STALL interrupt enable 3 1 NAKIE NAK interrupt enable 4 1 ACKIE ACK interrupt enable 5 1 USBERIE USB bus error interrupt enable 7 1 BBERIE Babble error interrupt enable 8 1 REQOVRIE request queue overrun interrupt enable 9 1 DTERIE Data toggle error interrupt enable 10 1 HCH1INTEN HCH1INTEN host channel-1 interrupt enable register (HCH1INTEN) 0x12C 0x20 read-write 0x00000000 TFIE Transfer completed interrupt enable 0 1 CHIE Channel halted interrupt enable 1 1 STALLIE STALL interrupt enable 3 1 NAKIE NAK interrupt enable 4 1 ACKIE ACK interrupt enable 5 1 USBERIE USB bus error interrupt enable 7 1 BBERIE Babble error interrupt enable 8 1 REQOVRIE request queue overrun interrupt enable 9 1 DTERIE Data toggle error interrupt enable 10 1 HCH2INTEN HCH2INTEN host channel-2 interrupt enable register (HCH2INTEN) 0x14C 0x20 read-write 0x00000000 TFIE Transfer completed interrupt enable 0 1 CHIE Channel halted interrupt enable 1 1 STALLIE STALL interrupt enable 3 1 NAKIE NAK interrupt enable 4 1 ACKIE ACK interrupt enable 5 1 USBERIE USB bus error interrupt enable 7 1 BBERIE Babble error interrupt enable 8 1 REQOVRIE request queue overrun interrupt enable 9 1 DTERIE Data toggle error interrupt enable 10 1 HCH3INTEN HCH3INTEN host channel-3 interrupt enable register (HCH3INTEN) 0x16C 0x20 read-write 0x00000000 TFIE Transfer completed interrupt enable 0 1 CHIE Channel halted interrupt enable 1 1 STALLIE STALL interrupt enable 3 1 NAKIE NAK interrupt enable 4 1 ACKIE ACK interrupt enable 5 1 USBERIE USB bus error interrupt enable 7 1 BBERIE Babble error interrupt enable 8 1 REQOVRIE request queue overrun interrupt enable 9 1 DTERIE Data toggle error interrupt enable 10 1 HCH4INTEN HCH4INTEN host channel-4 interrupt enable register (HCH4INTEN) 0x18C 0x20 read-write 0x00000000 TFIE Transfer completed interrupt enable 0 1 CHIE Channel halted interrupt enable 1 1 STALLIE STALL interrupt enable 3 1 NAKIE NAK interrupt enable 4 1 ACKIE ACK interrupt enable 5 1 USBERIE USB bus error interrupt enable 7 1 BBERIE Babble error interrupt enable 8 1 REQOVRIE request queue overrun interrupt enable 9 1 DTERIE Data toggle error interrupt enable 10 1 HCH5INTEN HCH5INTEN host channel-5 interrupt enable register (HCH5INTEN) 0x1AC 0x20 read-write 0x00000000 TFIE Transfer completed interrupt enable 0 1 CHIE Channel halted interrupt enable 1 1 STALLIE STALL interrupt enable 3 1 NAKIE NAK interrupt enable 4 1 ACKIE ACK interrupt enable 5 1 USBERIE USB bus error interrupt enable 7 1 BBERIE Babble error interrupt enable 8 1 REQOVRIE request queue overrun interrupt enable 9 1 DTERIE Data toggle error interrupt enable 10 1 HCH6INTEN HCH6INTEN host channel-6 interrupt enable register (HCH6INTEN) 0x1CC 0x20 read-write 0x00000000 TFIE Transfer completed interrupt enable 0 1 CHIE Channel halted interrupt enable 1 1 STALLIE STALL interrupt enable 3 1 NAKIE NAK interrupt enable 4 1 ACKIE ACK interrupt enable 5 1 USBERIE USB bus error interrupt enable 7 1 BBERIE Babble error interrupt enable 8 1 REQOVRIE request queue overrun interrupt enable 9 1 DTERIE Data toggle error interrupt enable 10 1 HCH7INTEN HCH7INTEN host channel-7 interrupt enable register (HCH7INTEN) 0x1EC 0x20 read-write 0x00000000 TFIE Transfer completed interrupt enable 0 1 CHIE Channel halted interrupt enable 1 1 STALLIE STALL interrupt enable 3 1 NAKIE NAK interrupt enable 4 1 ACKIE ACK interrupt enable 5 1 USBERIE USB bus error interrupt enable 7 1 BBERIE Babble error interrupt enable 8 1 REQOVRIE request queue overrun interrupt enable 9 1 DTERIE Data toggle error interrupt enable 10 1 HCH0LEN HCH0LEN host channel-0 transfer length register 0x110 0x20 read-write 0x00000000 TLEN Transfer length 0 19 PCNT Packet count 19 10 DPID Data PID 29 2 HCH1LEN HCH1LEN host channel-1 transfer length register 0x130 0x20 read-write 0x00000000 TLEN Transfer length 0 19 PCNT Packet count 19 10 DPID Data PID 29 2 HCH2LEN HCH2LEN host channel-2 transfer length register 0x150 0x20 read-write 0x00000000 TLEN Transfer length 0 19 PCNT Packet count 19 10 DPID Data PID 29 2 HCH3LEN HCH3LEN host channel-3 transfer length register 0x170 0x20 read-write 0x00000000 TLEN Transfer length 0 19 PCNT Packet count 19 10 DPID Data PID 29 2 HCH4LEN HCH4LEN host channel-4 transfer length register 0x190 0x20 read-write 0x00000000 TLEN Transfer length 0 19 PCNT Packet count 19 10 DPID Data PID 29 2 HCH5LEN HCH5LEN host channel-5 transfer length register 0x1B0 0x20 read-write 0x00000000 TLEN Transfer length 0 19 PCNT Packet count 19 10 DPID Data PID 29 2 HCH6LEN HCH6LEN host channel-6 transfer length register 0x1D0 0x20 read-write 0x00000000 TLEN Transfer length 0 19 PCNT Packet count 19 10 DPID Data PID 29 2 HCH7LEN HCH7LEN host channel-7 transfer length register 0x1F0 0x20 read-write 0x00000000 TLEN Transfer length 0 19 PCNT Packet count 19 10 DPID Data PID 29 2 USBFS_DEVICE USB on the go full speed device USBFS 0x50000800 0x00 0x400 registers DCFG DCFG device configuration register (DCFG) 0x0 0x20 read-write 0x00000000 DS Device speed 0 2 NZLSOH Non-zero-length status OUT handshake 2 1 DAR Device address 4 7 EOPFT end of periodic frame time 11 2 DCTL DCTL device control register (DCTL) 0x04 0x20 0x00000000 RWKUP Remote wakeup 0 1 read-write SD Soft disconnect 1 1 read-write GINS Global IN NAK status 2 1 read-only GONS Global OUT NAK status 3 1 read-only SGINAK Set global IN NAK 7 1 write-only CGINAK Clear global IN NAK 8 1 write-only SGONAK Set global OUT NAK 9 1 write-only CGONAK Clear global OUT NAK 10 1 write-only POIF Power-on initialization flag 11 1 read-write DSTAT DSTAT device status register (DSTAT) 0x08 0x20 read-only 0x00000000 SPST Suspend status 0 1 ES Enumerated speed 1 2 FNRSOF Frame number of the received SOF 8 14 DIEPINTEN DIEPINTEN device IN endpoint common interrupt mask register (DIEPINTEN) 0x10 0x20 read-write 0x00000000 TFEN Transfer finished interrupt enable 0 1 EPDISEN Endpoint disabled interrupt enable 1 1 CITOEN Control IN timeout condition interrupt enable (Non-isochronous endpoints) 3 1 EPTXFUDEN Endpoint Tx FIFO underrun interrupt enable bit 4 1 IEPNEEN IN endpoint NAK effective interrupt enable 6 1 TXFEEN Trabsmit FIFO empty interrupt enable 7 1 DOEPINTEN DOEPINTEN device OUT endpoint common interrupt enable register (DOEPINTEN) 0x14 0x20 read-write 0x00000000 TFEN Transfer finished interrupt enable 0 1 EPDISEN Endpoint disabled interrupt enable 1 1 STPFEN SETUP phase finished interrupt enable 3 1 EPRXFOVREN Endpoint Rx FIFO overrun interrupt enable 4 1 BTBSTPEN Back-to-back SETUP packets interrupt enable 6 1 DAEPINT DAEPINT device all endpoints interrupt register (DAEPINT) 0x18 0x20 read-only 0x00000000 IEPITB Device all IN endpoint interrupt bits 0 4 OEPITB Device all OUT endpoint interrupt bits 16 4 DAEPINTEN DAEPINTEN Device all endpoints interrupt enable register (DAEPINTEN) 0x1C 0x20 read-write 0x00000000 IEPIE IN EP interrupt interrupt enable bits 0 4 OEPIE OUT endpoint interrupt enable bits 16 4 DVBUSDT DVBUSDT device VBUS discharge time register 0x28 0x20 read-write 0x000017D7 DVBUSDT Device VBUS discharge time 0 16 DVBUSPT DVBUSPT device VBUS pulsing time register 0x2C 0x20 read-write 0x000005B8 DVBUSPT Device VBUS pulsing time 0 12 DIEPFEINTEN DIEPFEINTEN device IN endpoint FIFO empty interrupt enable register 0x34 0x20 read-write 0x00000000 IEPTXFEIE IN EP Tx FIFO empty interrupt enable bits 0 4 DIEP0CTL DIEP0CTL device IN endpoint 0 control register (DIEP0CTL) 0x100 0x20 0x00008000 MPL Maximum packet length 0 2 read-write EPACT endpoint active 15 1 read-only NAKS NAK status 17 1 read-only EPTYPE Endpoint type 18 2 read-only STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only EPD Endpoint disable 30 1 read-write EPEN Endpoint enable 31 1 read-write DIEP1CTL DIEP1CTL device in endpoint-1 control register 0x120 0x20 0x00000000 EPEN Endpoint enable 31 1 read-write EPD Endpoint disable 30 1 read-write SD1PID_SODDFRM Set DATA1 PID/Set odd frame 29 1 write-only SD0PID_SEVENFRM SD0PID/SEVNFRM 28 1 write-only SNAK Set NAK 27 1 write-only CNAK Clear NAK 26 1 write-only TXFNUM Tx FIFO number 22 4 read-write STALL STALL handshake 21 1 read-write EPTYPE Endpoint type 18 2 read-write NAKS NAK status 17 1 read-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write MPL maximum packet length 0 11 read-write DIEP2CTL DIEP2CTL device endpoint-2 control register 0x140 0x20 0x00000000 EPEN Endpoint enable 31 1 read-write EPD Endpoint disable 30 1 read-write SD1PID_SODDFRM Set DATA1 PID/Set odd frame 29 1 write-only SD0PID_SEVENFRM SD0PID/SEVNFRM 28 1 write-only SNAK Set NAK 27 1 write-only CNAK Clear NAK 26 1 write-only TXFNUM Tx FIFO number 22 4 read-write STALL STALL handshake 21 1 read-write EPTYPE Endpoint type 18 2 read-write NAKS NAK status 17 1 read-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write MPL maximum packet length 0 11 read-write DIEP3CTL DIEP3CTL device endpoint-3 control register 0x160 0x20 0x00000000 EPEN Endpoint enable 31 1 read-write EPD Endpoint disable 30 1 read-write SD1PID_SODDFRM Set DATA1 PID/Set odd frame 29 1 write-only SD0PID_SEVENFRM SD0PID/SEVNFRM 28 1 write-only SNAK Set NAK 27 1 write-only CNAK Clear NAK 26 1 write-only TXFNUM Tx FIFO number 22 4 read-write STALL STALL handshake 21 1 read-write EPTYPE Endpoint type 18 2 read-write NAKS NAK status 17 1 read-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write MPL maximum packet length 0 11 read-write DOEP0CTL DOEP0CTL device endpoint-0 control register 0x300 0x20 0x00008000 EPEN Endpoint enable 31 1 write-only EPD Endpoint disable 30 1 read-only SNAK Set NAK 27 1 write-only CNAK Clear NAK 26 1 write-only STALL STALL handshake 21 1 read-write SNOOP Snoop mode 20 1 read-write EPTYPE Endpoint type 18 2 read-only NAKS NAK status 17 1 read-only EPACT Endpoint active 15 1 read-only MPL Maximum packet length 0 2 read-only DOEP1CTL DOEP1CTL device endpoint-1 control register 0x320 0x20 0x00000000 EPEN Endpoint enable 31 1 read-write EPD Endpoint disable 30 1 read-write SD1PID_SODDFRM SD1PID/SODDFRM 29 1 write-only SD0PID_SEVENFRM SD0PID/SEVENFRM 28 1 write-only SNAK Set NAK 27 1 write-only CNAK Clear NAK 26 1 write-only STALL STALL handshake 21 1 read-write SNOOP Snoop mode 20 1 read-write EPTYPE Endpoint type 18 2 read-write NAKS NAK status 17 1 read-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write MPL maximum packet length 0 11 read-write DOEP2CTL DOEP2CTL device endpoint-2 control register 0x340 0x20 0x00000000 EPEN Endpoint enable 31 1 read-write EPD Endpoint disable 30 1 read-write SD1PID_SODDFRM SD1PID/SODDFRM 29 1 write-only SD0PID_SEVENFRM SD0PID/SEVENFRM 28 1 write-only SNAK Set NAK 27 1 write-only CNAK Clear NAK 26 1 write-only STALL STALL handshake 21 1 read-write SNOOP Snoop mode 20 1 read-write EPTYPE Endpoint type 18 2 read-write NAKS NAK status 17 1 read-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write MPL maximum packet length 0 11 read-write DOEP3CTL DOEP3CTL device endpoint-3 control register 0x360 0x20 0x00000000 EPEN Endpoint enable 31 1 read-write EPD Endpoint disable 30 1 read-write SD1PID_SODDFRM SD1PID/SODDFRM 29 1 write-only SD0PID_SEVENFRM SD0PID/SEVENFRM 28 1 write-only SNAK Set NAK 27 1 write-only CNAK Clear NAK 26 1 write-only STALL STALL handshake 21 1 read-write SNOOP Snoop mode 20 1 read-write EPTYPE Endpoint type 18 2 read-write NAKS NAK status 17 1 read-only EOFRM_DPID EOFRM/DPID 16 1 read-only EPACT Endpoint active 15 1 read-write MPL maximum packet length 0 11 read-write DIEP0INTF DIEP0INTF device endpoint-0 interrupt register 0x108 0x20 0x00000080 TXFE Transmit FIFO empty 7 1 read-only IEPNE IN endpoint NAK effective 6 1 read-write EPTXFUD Endpoint Tx FIFO underrun 4 1 read-write CITO Control in timeout interrupt 3 1 read-write EPDIS Endpoint finished 1 1 read-write TF Transfer finished 0 1 read-write DIEP1INTF DIEP1INTF device endpoint-1 interrupt register 0x128 0x20 0x00000080 TXFE Transmit FIFO empty 7 1 read-only IEPNE IN endpoint NAK effective 6 1 read-write EPTXFUD Endpoint Tx FIFO underrun 4 1 read-write CITO Control in timeout interrupt 3 1 read-write EPDIS Endpoint finished 1 1 read-write TF Transfer finished 0 1 read-write DIEP2INTF DIEP2INTF device endpoint-2 interrupt register 0x148 0x20 0x00000080 TXFE Transmit FIFO empty 7 1 read-only IEPNE IN endpoint NAK effective 6 1 read-write EPTXFUD Endpoint Tx FIFO underrun 4 1 read-write CITO Control in timeout interrupt 3 1 read-write EPDIS Endpoint finished 1 1 read-write TF Transfer finished 0 1 read-write DIEP3INTF DIEP3INTF device endpoint-3 interrupt register 0x168 0x20 0x00000080 TXFE Transmit FIFO empty 7 1 read-only IEPNE IN endpoint NAK effective 6 1 read-write EPTXFUD Endpoint Tx FIFO underrun 4 1 read-write CITO Control in timeout interrupt 3 1 read-write EPDIS Endpoint finished 1 1 read-write TF Transfer finished 0 1 read-write DOEP0INTF DOEP0INTF device out endpoint-0 interrupt flag register 0x308 0x20 read-write 0x00000000 BTBSTP Back-to-back SETUP packets 6 1 EPRXFOVR Endpoint Rx FIFO overrun 4 1 STPF Setup phase finished 3 1 EPDIS Endpoint disabled 1 1 TF Transfer finished 0 1 DOEP1INTF DOEP1INTF device out endpoint-1 interrupt flag register 0x328 0x20 read-write 0x00000000 BTBSTP Back-to-back SETUP packets 6 1 EPRXFOVR Endpoint Rx FIFO overrun 4 1 STPF Setup phase finished 3 1 EPDIS Endpoint disabled 1 1 TF Transfer finished 0 1 DOEP2INTF DOEP2INTF device out endpoint-2 interrupt flag register 0x348 0x20 read-write 0x00000000 BTBSTP Back-to-back SETUP packets 6 1 EPRXFOVR Endpoint Rx FIFO overrun 4 1 STPF Setup phase finished 3 1 EPDIS Endpoint disabled 1 1 TF Transfer finished 0 1 DOEP3INTF DOEP3INTF device out endpoint-3 interrupt flag register 0x368 0x20 read-write 0x00000000 BTBSTP Back-to-back SETUP packets 6 1 EPRXFOVR Endpoint Rx FIFO overrun 4 1 STPF Setup phase finished 3 1 EPDIS Endpoint disabled 1 1 TF Transfer finished 0 1 DIEP0LEN DIEP0LEN device IN endpoint-0 transfer length register 0x110 0x20 read-write 0x00000000 PCNT Packet count 19 2 TLEN Transfer length 0 7 DOEP0LEN DOEP0LEN device OUT endpoint-0 transfer length register 0x310 0x20 read-write 0x00000000 STPCNT SETUP packet count 29 2 PCNT Packet count 19 1 TLEN Transfer length 0 7 DIEP1LEN DIEP1LEN device IN endpoint-1 transfer length register 0x130 0x20 read-write 0x00000000 PCNT Packet count 19 10 TLEN Transfer length 0 19 DIEP2LEN DIEP2LEN device IN endpoint-2 transfer length register 0x150 0x20 read-write 0x00000000 PCNT Packet count 19 10 TLEN Transfer length 0 19 DIEP3LEN DIEP3LEN device IN endpoint-3 transfer length register 0x170 0x20 read-write 0x00000000 PCNT Packet count 19 10 TLEN Transfer length 0 19 DOEP1LEN DOEP1LEN device OUT endpoint-1 transfer length register 0x330 0x20 read-write 0x00000000 STPCNT_RXDPID SETUP packet count/Received data PID 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 DOEP2LEN DOEP2LEN device OUT endpoint-2 transfer length register 0x350 0x20 read-write 0x00000000 STPCNT_RXDPID SETUP packet count/Received data PID 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 DOEP3LEN DOEP3LEN device OUT endpoint-3 transfer length register 0x370 0x20 read-write 0x00000000 STPCNT_RXDPID SETUP packet count/Received data PID 29 2 PCNT Packet count 19 10 TLEN Transfer length 0 19 DIEP0TFSTAT DIEP0TFSTAT device IN endpoint 0 transmit FIFO status register 0x118 0x20 read-only 0x00000200 IEPTFS IN endpoint TxFIFO space remaining 0 16 DIEP1TFSTAT DIEP1TFSTAT device IN endpoint 1 transmit FIFO status register 0x138 0x20 read-only 0x00000200 IEPTFS IN endpoint TxFIFO space remaining 0 16 DIEP2TFSTAT DIEP2TFSTAT device IN endpoint 2 transmit FIFO status register 0x158 0x20 read-only 0x00000200 IEPTFS IN endpoint TxFIFO space remaining 0 16 DIEP3TFSTAT DIEP3TFSTAT device IN endpoint 3 transmit FIFO status register 0x178 0x20 read-only 0x00000200 IEPTFS IN endpoint TxFIFO space remaining 0 16 USBFS_PWRCLK USB on the go full speed USBFS 0x50000E00 0x0 0x100 registers PWRCLKCTL PWRCLKCTL power and clock gating control register (PWRCLKCTL) 0x00 0x20 read-write 0x00000000 SUCLK Stop the USB clock 0 1 SHCLK Stop HCLK 1 1 WWDGT Window watchdog timer WWDGT 0x40002C00 0x0 0x400 registers WWDGT 0 CTL CTL Control register 0x0 0x20 read-write 0x0000007F WDGTEN Activation bit 7 1 WDGTENread-writeDisabledWatchdog disabled0EnabledWatchdog enabled1 CNT 7-bit counter 0 7 0127 CFG CFG Configuration register 0x04 0x20 read-write 0x0000007F EWIE Early wakeup interrupt 9 1 EWIEWwriteEnableinterrupt occurs whenever the counter reaches the value 0x401 PSC Prescaler 7 2 PSCread-writeDiv1Counter clock (PCLK1 div 4096) div 10Div2Counter clock (PCLK1 div 4096) div 21Div4Counter clock (PCLK1 div 4096) div 42Div8Counter clock (PCLK1 div 4096) div 83 WIN 7-bit window value 0 7 0127 STAT STAT Status register 0x08 0x20 read-write 0x00000000 EWIF Early wakeup interrupt flag 0 1 EWIFRreadPendingThe EWI Interrupt Service Routine has been triggered1FinishedThe EWI Interrupt Service Routine has been serviced0 EWIFWwriteFinishedThe EWI Interrupt Service Routine has been serviced0